SPC564A74L7, SPC564A80B4, SPC564A80L7 Introduction
GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.
The reset controller performs reset monitoring of internal and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z4 CPU core is via the crossbar switch. The SIU provides the following features:
● System configuration
– MCU reset configuration via external pins
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– Pad configuration control for each pad
– Pad configuration control for virtual I/O via DSPI serialization
System reset monitoring and generation
– Power-on reset support
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– Reset status register provides last reset source to software
– Glitch detection on reset input
– Software controlled reset assertion
External interrupt
– Rising or falling edge event detection
– Programmable digital filter for glitch rejection
– Critical Interrupt request
– Non-Maskable Interrupt request
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GPIO
– Centralized control of I/O and bus pins
– Virtual GPIO via DSPI serialization (requires external deserialization device)
– Dedicated input and output registers for setting each GPIO and Virtual GPIO pin
Internal multiplexing
– Allows serial and parallel chaining of DSPIs
– Allows flexible selection of eQADC trigger inputs
– Allows selection of interrupt requests between external pins and DSPI
The SPC564A80 provides up to 4 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used to store instructions or data, or both. The flash module includes a Fetch Accelerator that optimizes the performance of the flash array to match the CPU architecture. The flash module interfaces the system bus to a dedicated flash memory array controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and 128- and 256-bit read data interfaces to flash memory. The module contains a prefetch controller which prefetches sequential lines of data from the flash array into the buffers. Prefetch buffer hits allow no-wait responses.
The flash memory provides the following features:
● Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword reads are supported. Only aligned word and doubleword writes are supported.
● Fetch Accelerator
– Architected to optimize the performance of the flash
– Configurable read buffering and line prefetch support
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Introduction SPC564A74L7, SPC564A80B4, SPC564A80L7
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– Four-entry 256-bit wide line read buffer
– Prefetch controller
Hardware and software configurable read and write access protections on a per-master basis
Interface to the flash array controller pipelined with a depth of one, allowing overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs
Configurable access timing usable in a wide range of system frequencies
Multiple-mapping support and mapping-based block access timing (0-31 additional cycles) usable for emulation of other memory types
Software programmable block program/erase restriction control
Erase of selected block(s)
Read page size of 128 bits (four words)
ECC with single-bit correction, double-bit detection
Program page size of 128 bits (four words) to accelerate programming
ECC single-bit error corrections are visible to software
Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC
Embedded hardware program and erase algorithm
Erase suspend, program suspend and erase-suspended program
Shadow information stored in non-volatile shadow block
Independent program/erase of the shadow block
1.5.9 BAM
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The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by
ST and is identical for all SPC564A80 MCUs. The BAM program is executed every time the
MCU is powered-on or reset in normal mode. The BAM supports different modes of booting.
They are:
Booting from internal flash memory
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Serial boot loading (A program is downloaded into RAM via eSCI or the FlexCAN and then executed)
Booting from external memory on external bus
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The BAM also reads the reset configuration half word (RCHW) from internal flash memory and configures the SPC564A80 hardware accordingly. The BAM provides the following features:
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Sets up MMU to cover all resources and mapping of all physical addresses to logical addresses with minimum address translation
Sets up MMU to allow user boot code to execute as either Power Architecture embedded category (default) or as VLE code
Location and detection of user boot code
Automatic switch to serial boot mode if internal flash is blank or invalid
Supports user programmable 64-bit password protection for serial boot mode
Supports serial bootloading via FlexCAN bus and eSCI using standard protocol
Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing
Supports serial bootloading of either Power Architecture code (default) or VLE code
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