STMicroelectronics VN7140AJ Datasheet

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VN7140AJ, VN7140AS
Datasheet
High-side driver with MultiSense analog feedback for automotive applications
Features
Max transient supply voltage
VCC
40 V
Operating voltage range
VCC
4 to 28 V
Typ. on-state resistance (per Ch)
RON
140 mΩ
Current limitation (typ)
ILIMH
12 A
Standby current (max)
ISTBY
0.5 &micro;A
•
•
•
Product status link
VN7140AJ
VN7140AS
•
AEC-Q100 qualified
General
–
Single channel smart high-side driver with MultiSense analog feedback
Very low standby current
–
–
Compatible with 3 V and 5 V CMOS outputs
MultiSense diagnostic functions
–
Multiplexed analog feedback of: load current with high precision
proportional current mirror, VCC supply voltage and TCHIP device
temperature
–
Overload and short to ground (power limitation) indication
–
Thermal shutdown indication
–
OFF-state open-load detection
–
Output short to VCC detection
–
Sense enable/disable
Protections
–
Undervoltage shutdown
–
Overvoltage clamp
–
Load current limitation
–
Self limiting of fast thermal transients
–
Configurable latch-off on overtemperature or power limitation with
dedicated fault reset pin
–
Loss of ground and loss of VCC
–
–
Reverse battery with external components
Electrostatic discharge protection
Applications
•
•
•
All types of automotive resistive, inductive and capacitive loads
Specially intended for automotive signal lamps (up to R10W or LED Rear
Combinations)
Protected supply for ADAS systems: radars and sensors
Description
The devices are single channel high-side drivers manufactured using ST proprietary
VIPower M0-7 technology and housed in PowerSSO-16 and SO-8 packages. The
DS10830 - Rev 4 - April 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
VN7140AJ, VN7140AS
devices are designed to drive 12 V automotive grounded loads through a 3 V and 5 V
CMOS-compatible interface, and to provide protection and diagnostics.
The devices integrate advanced protective functions such as load current limitation,
overload active management by power limitation and overtemperature shutdown with
configurable latch-off.
A FaultRST pin unlatches the output in case of fault or disables the latch-off
functionality.
A dedicated multifunction multiplexed analog output pin delivers sophisticated
diagnostic functions including high precision proportional load current sense, supply
voltage feedback and chip temperature sense, in addition to the detection of overload
and short circuit to ground, short to VCC and OFF-state open-load.
A sense enable pin allows OFF-state diagnosis to be disabled during the module lowpower mode as well as external sense resistor sharing among similar devices.
DS10830 - Rev 4
page 2/45
VN7140AJ, VN7140AS
Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block diagram
VCC
Internal supply
VCC – GND
Clamp
Undervoltage
shut-down
Control &amp; Diagnostic
VCC – OUT
Clamp
FaultRST
INPUT
Gate Driver
SEL1
T
VCC
VON
Limitation
SEL0
Current
Limitation
MultiSense
MUX
SEn
Power Limitation
Overtemperature
T
Short to VCC
Open-Load in OFF
Current
Sense
Fault
GND
VSENSEH
OUTPUT
GAPGCFT00328
Table 1. Pin functions
Name
VCC
OUTPUT
GND
INPUT
MultiSense
Battery connection.
Power outputs.
Ground connection. Must be reverse battery protected by an external diode / resistor network.
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. It controls output switch
state.
Multiplexed analog sense output pin; it delivers a current proportional to the selected diagnostic: load current,
supply voltage or chip temperature.
SEn
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense diagnostic pin.
SEL0,1
Active high compatible with 3 V and 5 V CMOS outputs pin; they address the MultiSense multiplexer.
FaultRST
DS10830 - Rev 4
Function
Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low, sets
the outputs in auto-restart mode.
page 3/45
VN7140AJ, VN7140AS
Block diagram and pin description
Figure 2. Configuration diagram (top view)
PowerSSO-16
INPUT
FaultRST
SEn
GND
SEL0
SEL1
MultiSense
N.C.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OUTPUT
OUTPUT
OUTPUT
OUTPUT
N.C.
N.C.
N.C.
N.C.
TAB = V CC
SO-8
INPUT
SEn
GND
MultiSense
1
2
3
4
8
7
6
5
VCC
OUTPUT
OUTPUT
VCC
GAPG2601151129CFT
Table 2. Suggested connections for unused and not connected pins
Connection / pin
MultiSense
N.C.
Output
Input
SEn, SELx, FaultRST
Floating
Not allowed
X (1)
X
X
X
To ground
Through 1 kΩ resistor
X
Not allowed
Through 15 kΩ resistor
Through 15 kΩ resistor
1. X: do not care.
DS10830 - Rev 4
page 4/45
VN7140AJ, VN7140AS
Electrical specification
2
Electrical specification
Figure 3. Current and voltage conventions
IS
VCC
FaultRST
I SEn
I OUT
OUTPUT 0,1
CS
SEL 0
VSEn
V OUT
I SENSE
SE n
I SEL
VFR
VCC
VFn
I FR
VSENSE
I IN
VSEL
INPUT 0,1
VIN
I GND
GADG2203170950PS
Note:
VF = VOUT - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3. Absolute maximum ratings may cause permanent damage
to the device. These are stress ratings only and operation of the device at these or any other conditions above
those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table
below for extended periods may affect device reliability.
Table 3. Absolute maximum ratings
Symbol Parameter
Unit
VCC
DC supply voltage
38
-VCC
Reverse DC supply voltage
0.3
VCCPK
Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40 V; RL = 4 Ω)
40
V
VCCJS
Maximum jump start voltage for single pulse short circuit protection
28
V
-IGND
DC reverse ground pin current
200
mA
IOUT
OUTPUT DC output current
Internally limited
-IOUT
Reverse DC output current
3
IIN
V
A
INPUT DC input current
ISEn
SEn DC input current
ISEL
SEL0,1 DC input current
IFR
FaultRST DC input current
VFR
ISENSE
DS10830 - Rev 4
Value
-1 to 10
mA
FaultRST DC input voltage
7.5
V
MultiSense pin DC output current (VGND = VCC and VSENSE &lt; 0 V)
10
MultiSense pin DC output current in reverse (VCC &lt; 0 V)
-20
mA
page 5/45
VN7140AJ, VN7140AS
Thermal data
Symbol Parameter
EMAX
Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150 &deg;C)
Value
Unit
10
mJ
Electrostatic discharge (JEDEC 22A-114F)
VESD
INPUT
4000
MultiSense
2000
V
SEn, SEL0,1, FaultRST
OUTPUT
4000
VCC
VESD
Tj
Tstg
2.2
Charge device model (CDM-AEC-Q100-011)
750
V
Junction operating temperature
-40 to 150
Storage temperature
-55 to 150
&deg;C
Thermal data
Table 4. Thermal data
Symbol
Parameter
Rthj-board
Typ. value
SO-8
PowerSSO-16
Thermal resistance junction-board
(JEDEC JESD 51-8) (1)
31
7.9
Rthj-amb
Thermal resistance junction-ambient
(JEDEC JESD 51-2)(2)
71
61
Rthj-amb
Thermal resistance junction-ambient
(JEDEC JESD 51-2)
48.5
26.5
Unit
&deg;C/W
1. Device mounted on four-layers 2s2p PCB
2. Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace
2.3
Main electrical characteristics
7 V &lt; VCC &lt; 28 V; -40&deg;C &lt; Tj &lt; 150&deg;C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25&deg;C, unless otherwise specified.
Table 5. Power section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
4
13
28
V
VCC
Operating supply voltage
VUSD
Undervoltage shutdown
4
V
Undervoltage shutdown reset
5
V
VUSDReset
VUSDhyst
Undervoltage shutdown
hysteresis
0.3
IOUT = 1 A; Tj = 25&deg;C
RON
Vclamp
DS10830 - Rev 4
On-state resistance
Clamp voltage
V
140
IOUT = 1 A; Tj = 150&deg;C
280
IOUT = 1 A; VCC = 4 V; Tj = 25&deg;C
210
IS = 20 mA; 25&deg;C &lt; Tj &lt; 150&deg;C
41
IS = 20 mA; Tj = -40&deg;C
38
46
52
mΩ
V
V
page 6/45
VN7140AJ, VN7140AS
Main electrical characteristics
Symbol
Parameter
Test conditions
Supply current in standby at
VCC = 13 V (1)
ISTBY
tD_STBY
IS(ON)
IGND(ON)
VF
Max.
0.5
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 85&deg;C (2)
0.5
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 125&deg;C
3
VCC = 13 V; VIN = VOUT
= VFR = VSEL0,1 = 0 V;
VSEn = 5 V to 5 V
Supply current
VCC = 13 V; VSEn = 0 V;
VSEL0,1 = VFR = 0 V; VIN = 5 V;
IOUT = 0 A
Control stage current
consumption in ON-state. All
channels active.
VCC = 13 V; VSEn = 5 V;
VFR = VSEL0,1 = 0 V; VIN = 5 V;
IOUT = 1 A
Output - VCC diode voltage
Typ.
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 25&deg;C
Standby mode blanking time
Off-state output current at
VCC = 13 V
IL(off)
Min.
60
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25&deg;C
0
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125&deg;C
0
Unit
&micro;A
300
550
&micro;s
3
5
mA
6
mA
0.01
0.5
&micro;A
3
IOUT = -1 A; Tj = 150&deg;C
0.7
V
Unit
1. PowerMOS leakage included.
2. Parameter specified by design; not subjected to production test.
Table 6. Switching
VCC = 13 V; -40&deg;C &lt; Tj &lt; 150&deg;C, unless otherwise specified
Symbol
Parameter
td(on) (1)
Turn-on delay time at Tj = 25 &deg;C
(1)
Turn-off delay time at Tj = 25 &deg;C
td(off)
Test conditions
(dVOUT/dt)on (1)
Turn-on voltage slope at Tj = 25 &deg;C
(dVOUT/dt)off (1)
Turn-off voltage slope at Tj = 25 &deg;C
RL = 13 Ω
RL = 13 Ω
Min.
Typ.
Max.
10
70
120
10
40
100
0.1
0.27
0.7
0.1
0.35
0.7
&micro;s
V/&micro;s
WON
Switching energy losses at turn-on (twon)
RL = 13 Ω
—
0.15
0.18 (2)
mJ
WOFF
Switching energy losses at turn-off (twoff)
RL = 13 Ω
—
0.1
0.18(2)
mJ
Differential Pulse skew (tPHL - tPLH)
RL = 13 Ω
-100
-50
0
&micro;s
Typ.
Max.
Unit
tSKEW (1)
1. See Figure 6. Switching time and Pulse skew.
2. Parameter guaranteed by design and characterization; not subjected to production test.
Table 7. Logic inputs
7 V &lt; VCC &lt; 28 V; -40&deg;C &lt; Tj &lt; 150&deg;C
Symbol
Parameter
Test conditions
Min.
INPUT characteristics
DS10830 - Rev 4
page 7/45
VN7140AJ, VN7140AS
Main electrical characteristics
7 V &lt; VCC &lt; 28 V; -40&deg;C &lt; Tj &lt; 150&deg;C
Symbol
Parameter
Test conditions
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
VIN = 0.9 V
Min.
Typ.
Max.
Unit
0.9
V
1
&micro;A
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
5.3
IIN = -1 mA
&micro;A
7.2
-0.7
V
FaultRST characteristics (VN7140AJ only)
VFRL
Input low level voltage
IFRL
Low level input current
VFRH
Input high level voltage
IFRH
High level input current
VFR(hyst)
Input hysteresis voltage
VFRCL
Input clamp voltage
0.9
VIN = 0.9 V
1
&micro;A
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
V
5.3
IIN = -1 mA
&micro;A
7.5
-0.7
V
SEL0,1 characteristics (7 V &lt; VCC &lt; 18 V) (VN7140AJ only)
VSELL
Input low level voltage
ISELL
Low level input current
VSELH
Input high level voltage
ISELH
High level input current
VSEL(hyst)
Input hysteresis voltage
VSELCL
Input clamp voltage
0.9
VIN = 0.9 V
1
&micro;A
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
V
5.3
IIN = -1 mA
&micro;A
7.2
-0.7
V
SEn characteristics (7 V &lt; VCC &lt; 18 V)
VSEnL
Input low level voltage
ISEnL
Low level input current
VSEnH
Input high level voltage
ISEnH
High level input current
VSEn(hyst)
Input hysteresis voltage
VSEnCL
DS10830 - Rev 4
Input clamp voltage
0.9
VIN = 0.9 V
1
&micro;A
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
IIN = -1 mA
V
&micro;A
V
5.3
7.2
-0.7
V
page 8/45
VN7140AJ, VN7140AS
Main electrical characteristics
Table 8. Protections
7 V &lt; VCC &lt; 18 V; -40&deg;C &lt; Tj &lt; 150&deg;C
Symbol
ILIMH
Parameter
DC short circuit current
ILIML
TTSD
Test conditions
4 V &lt; VCC &lt; 18 V
VCC = 13 V;
during thermal cycling
TR &lt; Tj &lt; TTSD
TRS
Thermal reset of fault
diagnostic indication
16
4
150
175
TRS + 1
TRS + 7
VFR = 0 V; VSEn = 5 V
Thermal hysteresis(TTSD TR)(1)
ΔTJ_SD
Dynamic temperature
Tj = -40&deg;C; VCC = 13 V
Fault reset time for output
unlatch (only for VN7140AJ)
VFR = 5 V to 0 V; VSEn = 5 V;
VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V
(1)
12
Unit
A
temperature(1)
THYST
tLATCH_RST
8
Max.
(1)
Shutdown temperature
Reset
Typ.
VCC = 13 V
Short circuit current
TR
Min.
200
&deg;C
135
7
60
3
IOUT = 1 A; L = 6 mH; Tj = -40&deg;C
VCC - 38
VCC - 41
VDEMAG
Turn-off output voltage clamp
IOUT = 1 A; L = 6 mH; Tj = 25&deg;C to
150&deg;C
VON
Output voltage drop limitation
IOUT = 0.07 A
K
10
20
&micro;s
V
VCC - 46
VCC - 52
20
V
mV
1. Parameter guaranteed by design and characterization; not subjected to production test.
Table 9. MultiSense
7 V &lt; VCC &lt; 18 V; -40&deg;C &lt; Tj &lt; 150&deg;C
Symbol
VSENSE_CL
Parameter
MultiSense clamp voltage
Test conditions
Min.
VSEn = 0 V; ISENSE = 1 mA
-17
VSEn = 0 V; ISENSE = -1 mA
Typ.
Max.
-12
7
Unit
V
CurrentSense characteristics
KOL
dKcal/Kcal (1) (2)
KLED
dKLED/KLED (1) (2)
K0
dK0/K0 (1) (2)
K1
DS10830 - Rev 4
IOUT/ISENSE
IOUT = 0.01 A; VSENSE = 0.5 V;
VSEn = 5 V
295
Current sense ratio drift at
calibration point
IOUT = 0.01 A to 0.025 A;
Ical = 17.5 mA; VSENSE = 0.5 V;
VSEn = 5 V
-30
IOUT/ISENSE
IOUT = 0.025 A; VSENSE = 0.5 V;
VSEn = 5 V
330
Current sense ratio drift
IOUT = 0.025 A; VSENSE = 0.5 V;
VSEn = 5 V
-25
IOUT/ISENSE
IOUT = 0.07 A; VSENSE = 0.5 V;
VSEn = 5 V
375
Current sense ratio drift
IOUT = 0.07 A; VSENSE = 0.5 V;
VSEn = 5 V
-20
IOUT/ISENSE
IOUT = 0.15 A; VSENSE = 4 V;
VSEn = 5 V
360
30
580
820
25
550
%
720
20
500
%
%
670
page 9/45
VN7140AJ, VN7140AS
Main electrical characteristics
7 V &lt; VCC &lt; 18 V; -40&deg;C &lt; Tj &lt; 150&deg;C
Symbol
dK1/K1 (1) (2)
K2
dK2/K2 (1) (2)
K3
dK3/K3 (1) (2)
Parameter
Test conditions
Min.
Current sense ratio drift
IOUT = 0.15 A; VSENSE = 4 V;
VSEn = 5 V
-15
IOUT/ISENSE
IOUT = 0.7 A; VSENSE = 4 V;
VSEn = 5 V
380
Current sense ratio drift
IOUT = 0.7 A; VSENSE = 4 V;
VSEn = 5 V
-10
IOUT/ISENSE
IOUT = 2 A; VSENSE = 4 V; VSEn = 5 V
430
Current sense ratio drift
IOUT = 2 A; VSENSE = 4 V; VSEn = 5 V
-5
5
MultiSense disabled: VSEn = 0 V
0
0.5
-0.5
0.5
MultiSense enabled: VSEn = 5 V;
Channel ON; IOUT = 0 A; Diagnostic
selected; VIN = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; IOUT = 0 A
0
2
MultiSense enabled: VSEn = 5 V;
Channel OFF; Diagnostic selected:
VIN = 0 V; VSEL0 = 0 V; VSEL1 = 0 V
0
2
MultiSense disabled:
-1 V &lt; VSENSE &lt; 5 V(1)
ISENSE0
MultiSense leakage current
Typ.
475
Max.
Unit
15
%
570
10
470
%
520
%
&micro;A
VOUT_MSD (1)
Output voltage for MultiSense
shutdown
VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; RSENSE = 2.7 kΩ; IOUT =
1A
VSENSE_SAT
Multisense saturation voltage
VCC = 7 V; RSENSE = 2.7 kΩ;
VSEn = 5 V; VIN = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; IOUT = 2 A; Tj = 150&deg;C
5
V
CS saturation current
VCC = 7 V; VSENSE = 4 V; VIN = 5 V;
VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150&deg;C
4
mA
Output saturation current
VCC = 7 V; VSENSE = 4 V; VIN = 5 V;
VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150&deg;C
2.2
A
ISENSE_SAT (1)
IOUT_SAT (1)
5
V
OFF-state diagnostic
VOL
OFF-state open-load voltage
detection threshold
VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V
IL(off2)
OFF-state output sink current
VIN = 0 V; VOUT = VOL; Tj = -40 &deg;C to
150&deg;C
-100
VIN = 5 V to 0 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A;
VOUT = 4 V
100
tDSTKON
OFF-state diagnostic delay
time from falling edge of
INPUT
(see Figure 9. TDSTKON )
tD_OL_V
tD_VOL
Settling time for valid OFFstate open load diagnostic
indication from rising edge of
SEn
VIN = 0 V; VFR = 0 V; VSEL0 = 0 V;
VSEL1 = 0 V; VOUT = 4 V;
OFF-state diagnostic delay
time from rising edge of VOUT
VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; VOUT = 0 V to 4 V
2
3
350
4
V
-15
&micro;A
700
&micro;s
60
&micro;s
30
&micro;s
VSEn = 0 V to 5 V
5
Chip temperature analog feedback (VN7140AJ only)
DS10830 - Rev 4
page 10/45
VN7140AJ, VN7140AS
Main electrical characteristics
7 V &lt; VCC &lt; 18 V; -40&deg;C &lt; Tj &lt; 150&deg;C
Symbol
Parameter
MultiSense output voltage
proportional to chip
temperature
VSENSE_TC
dVSENSE_TC/dT(1)
Temperature coefficient
Test conditions
Min.
Typ.
Max.
Unit
VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V;
VIN = 0 V; RSENSE = 1 kΩ; Tj = -40&deg;C
2.325
2.41
2.495
V
VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V;
VIN = 0 V; RSENSE = 1 kΩ; Tj = 25&deg;C
1.985
2.07
2.155
V
VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V;
VIN = 0 V; RSENSE = 1 kΩ; Tj = 125&deg;C
1.435
1.52
1.605
V
Tj = -40&deg;C to 150&deg;C
-5.5
mV/K
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
Transfer function
VCC supply voltage analog feedback (VN7140AJ only)
VSENSE_VCC
MultiSense output voltage
proportional to VCC supply
voltage
VCC = 13 V; VSEn = 5 V; VSEL0 = 5 V;
VSEL1 = 5 V; VIN = 0 V;
RSENSE = 1 kΩ
3.16
3.23
3.3
V
6.6
V
30
mA
60
&micro;s
VSENSE_VCC = VCC / 4
Transfer function (3)
Fault diagnostic feedback (see Table 10. Truth table)
VSENSEH
MultiSense output voltage in
fault condition
VCC = 13 V; VIN = 0 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A;
VOUT = 4 V; RSENSE = 1 kΩ;
5
ISENSEH
MultiSense output current in
fault condition
VCC = 13 V; VSENSE = 5 V
7
20
MultiSense timings (current sense mode - see Figure 7. MultiSense timings (current sense mode)) (4)
tDSENSE1H
Current sense settling time
from rising edge of SEn
VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 kΩ; RL = 13 Ω
tDSENSE1L
Current sense disable delay
time from falling edge of SEn
VIN = 5 V; VSEn = 5 V to 0 V;
RSENSE = 1 kΩ; RL = 13 Ω
5
20
&micro;s
tDSENSE2H
Current sense settling time
from rising edge of INPUT
VIN = 0 V to 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 13 Ω
100
250
&micro;s
ΔtDSENSE2H
Current sense settling time
from rising edge of IOUT
(dynamic response to a step
change of IOUT)
VIN = 5 V; VSEn = 5 V; RSENSE = 1 kΩ;
ISENSE = 90 % of ISENSEMAX;
RL = 13 Ω
100
&micro;s
tDSENSE2L
Current sense turn-off delay
time from falling edge of
INPUT
VIN = 5 V to 0 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 13 Ω
250
&micro;s
50
MultiSense timings (chip temperature sense mode - see Figure 8. Multisense timings (chip temperature and VCC sense mode)
(VN7140AJ only) ) (4)
tDSENSE3H
VSENSE_TC settling time from
rising edge of SEn
VSEn = 0 V to 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; RSENSE = 1 kΩ
60
&micro;s
tDSENSE3L
VSENSE_TC disable delay time
from falling edge of SEn
VSEn = 5 V to 0 V; VSEL0 = 0 V;
VSEL1 = 5 V; RSENSE = 1 kΩ
20
&micro;s
MultiSense timings (VCC voltage sense mode - see Figure 8. Multisense timings (chip temperature and VCC sense mode)
(VN7140AJ only)) (4)
DS10830 - Rev 4
tDSENSE4H
VSENSE_VCC settling time from VSEn = 0 V to 5 V; VSEL0 = 5 V;
VSEL1 = 5 V; RSENSE = 1 kΩ
rising edge of SEn
60
&micro;s
tDSENSE4L
VSENSE_VCC disable delay
time from falling edge of SEn
VSEn = 5 V to 0 V; VSEL0 = 5 V;
VSEL1 = 5 V; RSENSE = 1 kΩ
20
&micro;s
page 11/45
VN7140AJ, VN7140AS
Main electrical characteristics
7 V &lt; VCC &lt; 18 V; -40&deg;C &lt; Tj &lt; 150&deg;C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
MultiSense timings (Multiplexer transition times) (VN7140AJ only) (4)
tD_CStoTC
MultiSense transition delay
from current sense to TC
sense
VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V to 5 V; IOUT = 0.5 A;
RSENSE = 1 kΩ
60
&micro;s
tD_TCtoCS
MultiSense transition delay
from TC sense to current
sense
VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V to 0 V; IOUT = 0.5 A;
RSENSE = 1 kΩ
20
&micro;s
tD_CStoVCC
MultiSense transition delay
from current sense to VCC
sense
VIN = 5 V; VSEn = 5 V; VSEL0 = 5 V;
VSEL1 = 0 V to 5 V; IOUT = 0.5 A;
RSENSE = 1 kΩ
60
&micro;s
tD_VCCtoCS
MultiSense transition delay
from VCC sense to current
sense
VIN = 5 V; VSEn = 5 V; VSEL0 = 5 V;
VSEL1 = 5 V to 0 V; IOUT = 0.5 A;
RSENSE = 1 kΩ
20
&micro;s
tD_TCtoVCC
MultiSense transition delay
from TC sense to VCC sense
VCC = 13 V; Tj = 125&deg;C; VSEn = 5 V;
VSEL0 = 0 V to 5 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20
&micro;s
tD_VCCtoTC
MultiSense transition delay
from VCC sense to TC sense
VCC = 13 V; Tj = 125&deg;C; VSEn = 5 V;
VSEL0 = 5 V to 0 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20
&micro;s
1. Parameter specified by design; not subjected to production test.
2. All values refer to VCC = 13 V; Tj = 25&deg;C, unless otherwise specified.
3. VCC sensing and TC are referred to GND potential.
4. Transition delays are measured up to +/- 10% of final conditions.
Figure 4. IOUT/ISENSE versus IOUT
1000
800
Max
K-factor
Min
Typ
600
400
200
0
0
1
2
IOUT[A]
DS10830 - Rev 4
3
GAPGCFT01217
page 12/45
VN7140AJ, VN7140AS
Main electrical characteristics
Figure 5. Current sense accuracy versus IOUT
65
60
55
50
45
40
35
%
30
25
20
15
10
5
0
Current sense uncalibrated precision
Current sense calibrated precision
0
1
2
3
IOUT[A]
GAPGCFT01218
Figure 6. Switching time and Pulse skew
twon
VOUT
twoff
Vcc
80% Vcc
ON
OFF
dVOUT/dt
dVOUT/dt
20% Vcc
t
INPUT
td(off)
td(on)
tpLH
tpHL
t
DS10830 - Rev 4
page 13/45
VN7140AJ, VN7140AS
Main electrical characteristics
Figure 7. MultiSense timings (current sense mode)
IN1
High
SEn
Low
High
SEL0
Low
High
SEL1
Low
IOUT1
CURRENT SENSE
tDSENSE2H
tDSENSE1L
tDSENSE1H
tDSENSE2L
Figure 8. Multisense timings (chip temperature and VCC sense mode) (VN7140AJ only)
High
SEn
Low
High
SEL0
Low
High
SEL1
Low
VCC
VSENSE = VSENSE_VCC
VSENSE = VSENSE_TC
SENSE
tDSENSE4H
tDSENSE4L
VCC VOLTAGE SENSE MODE
tDSENSE3H
tDSENSE3L
CHIP TEMPERATURE SENSE MODE
GAPGCFT00319
DS10830 - Rev 4
page 14/45
VN7140AJ, VN7140AS
Main electrical characteristics
Figure 9. TDSTKON
VINPUT
VOUT
VOUT &gt; VOL
MultiSense
TDSTKON
GAPG2609141140CFT
Table 10. Truth table
Mode
Conditions
Standby
All logic inputs low
Normal
Overload
Undervoltage
OFF-state
diagnostics
Negative output
voltage
INX FR (1) SEn SELX (1) OUTX MultiSense
L
L
L
X
H
L
H
Overload or short to GND
causing:
Hi-Z
L
See (2)
H
See (2)
Outputs configured for
auto-restart
H
H
See (2)
Outputs configured for
latch-off(1)
L
X
L
See (2)
Tj &gt; TTSD or
H
L
H
See (2)
Output cycles with
temperature hysteresis
ΔTj &gt; ΔTj _SD
H
H
L
See (2)
Output latches-off(1)
VCC &lt; VUSD (falling)
X
X
L
Hi-Z
Re-start when
VCC &gt; VUSD +
L
Hi-Z
H
See (2)
H
See (2)
&lt;0V
See (2)
See (2)
Tj &lt; 150 &deg;C
Short to VCC
L
X
Open-load
L
X
Inductive loads turn-off
L
X
L
Low quiescent current
consumption
L
Nominal load connected;
L
Comments
See (2)
X
X
See (2)
See (2)
VUSDhyst (rising)
External pull-up
1. VN7140AJ only
2. Refer to Table 11. MultiSense multiplexer addressing
Table 11. MultiSense multiplexer addressing
SEn SEL1 SEL0
MUX channel
MultiSense output
Normal mode
Overload
OFF-state diag. (1)
Negative output
SO-8
DS10830 - Rev 4
page 15/45
VN7140AJ, VN7140AS
Waveforms
SEn SEL1 SEL0
MUX channel
L
N.A.
N.A.
N.A.
H
N.A.
N.A.
Channel diagnostic
MultiSense output
Normal mode
Overload
OFF-state diag. (1)
Negative output
VSENSE = VSENSEH
Hi-Z
Hi-Z
ISENSE = 1/K * IOUT
VSENSE = VSENSEH
PowerSSO-16
H
L
L
Channel diagnostic
ISENSE = 1/K * IOUT
VSENSE = VSENSEH
VSENSE = VSENSEH
Hi-Z
H
L
H
Channel diagnostic
ISENSE = 1/K * IOUT
VSENSE = VSENSEH
VSENSE = VSENSEH
Hi-Z
H
H
L
TCHIP Sense
VSENSE = VSENSE_TC
H
H
H
VCC Sense
VSENSE = VSENSE_VCC
1. In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low,
Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN = 0; OUT = L (latched); MUX
channel = channel 0 diagnostic; Mutisense = 0. Example 2: FR = 1; IN = 0; OUT = latched, VOUT &gt; VOL; MUX channel =
channel 0 diagnostic; Mutisense = VSENSEH
2.4
Waveforms
Figure 10. Latch functionality - behavior in hard short-circuit condition (TAMB &lt;&lt; TTSD)
Logic
high
Sense
enable
Logic
high
Input
Logic
high
t
t &gt; t latch RST
I limH
Fault Reset
Output
current
Junction temperature &lt;&lt; TTDS
Δ Tj
60&deg;
Logic
high
Hard
short
circuit
VsenseH
Internal
fault
detection
Vout &lt;5V
Vout &lt;5V
Output
Voltage
Multisense
voltage
GADG1703171451PS
DS10830 - Rev 4
page 16/45
VN7140AJ, VN7140AS
Waveforms
Figure 11. Latch functionality - behavior in hard short-circuit condition
Logic
high
Sense
enable
Logic
high
Input
Logic
high
t
t &gt; t latch RST
I lim H
Fault Reset
Output
current
I lim L
TTSD
TR
TAMB
Junction
temperature
Thermal shut down
cycling
in AutoRestart mode
Logic
high
Hard
short
circuit
Internal
fault
detection
Vout &lt;5V
Vout &lt;5V
VsenseH
Output
Voltage
Multisense
voltage
Figure 12. Latch functionality - behavior in hard short-circuit condition (autorestart mode + latch off)
Logic
high
Sense
enable
Logic
high
Input
Logic
high
Fault Reset
I lim H
Output
current
I lim L
TTSD
Junction
temperature
Chip
temperature
60&deg;
TAMB
Logic
high
Hard
short
circuit
VsenseH
Internal
fault
detection
Vout &lt;5V
Vout &lt;5V
Output
Voltage
Multisense
voltage
GADG2103171742PS
DS10830 - Rev 4
page 17/45
VN7140AJ, VN7140AS
Waveforms
Figure 13. Standby mode activation
INPUT0
INPUT1
SEn
SEL0
FaultRST
IS(ON)
= Standby
= t &lt; t D_STBY
= t &gt; t D_STBY
GADG1703171116PS
Figure 14. Standby state diagram
Normal Operation
t &gt; t D_STBY
INx = Low
AND
FaultRST = Low
AND
SEn = Low
AND
SELx = Low
INx = High
OR
FaultRST = High
OR
SEn = High
OR
SELx = High
Stand-by Mode
GAPGCFT00598
DS10830 - Rev 4
page 18/45
VN7140AJ, VN7140AS
Electrical characteristics curves
2.5
Electrical characteristics curves
Figure 16. Standby current
Figure 15. OFF-state output current
ISTBY [ &micro;A]
Iloff [nA]
1
160
0.9
140
Vcc = 13V
0.8
120
0.7
Off State
Vcc = 13V
Vin = Vout = 0
100
80
0.6
0.5
0.4
60
0.3
40
0.2
20
0.1
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
T [&deg;C]
T [&deg;C]
GAPGCFT01222
GAPGCFT01221
Figure 17. IGND(ON) vs. Tcase
Figure 18. Logic Input high level voltage
ViH, VFRH, VSELH, VSEnH [V]
IGND(ON) [mA]
2
3.5
1.8
3.0
1.6
2.5
1.4
Vcc = 13V
Iout0 = Iout1 = 1A
2.0
1.2
1
1.5
0.8
1.0
0.6
0.4
0.5
0.2
0
0.0
-50
-25
0
25
50
75
100
125
150
175
GAPGCFT01223
DS10830 - Rev 4
-50
-25
0
25
50
75
100
125
150
175
T [&deg;C]
T [&deg;C]
GAPGCFT01224
page 19/45
VN7140AJ, VN7140AS
Electrical characteristics curves
Figure 19. Logic Input low level voltage
Figure 20. High level logic input current
IiH, IFRH, ISELH, ISEnH [ &micro;A]
VilL VFRL, VSELL, VSEnL [V]
2
4
1.8
3.5
1.6
3
1.4
2.5
1.2
1
2
0.8
1.5
0.6
1
0.4
0.5
0.2
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
T [&deg;C]
T [&deg;C]
GAPGCFT01225
GAPGCFT01226
Figure 21. Low level logic input current
Figure 22. Logic Input hysteresis voltage
IiL, IFRL, ISELL, ISEnL [&micro;A]
Vi(hyst), VFR(hyst), VSEL(hyst), VSEn(hyst) [V]
1
4
0.9
3.5
0.8
3
0.7
2.5
0.6
2
0.5
0.4
1.5
0.3
1
0.2
0.5
0.1
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
T [&deg;C]
T [&deg;C]
GAPGCFT01227
GAPGCFT01228
Figure 23. FaultRST Input clamp voltage
Figure 24. Undervoltage shutdown
VFRCL [V]
VUSD [V]
8
8
7
7
Iin = 1mA
6
6
5
5
4
4
3
3
2
2
1
Iin = -1mA
0
1
-1
-50
-25
0
25
50
75
100
125
150
175
T [&deg;C]
-50
-25
0
25
50
75
100
125
150
175
T [&deg;C]
GAPGCFT01229
DS10830 - Rev 4
0
GAPGCFT01230
page 20/45
VN7140AJ, VN7140AS
Electrical characteristics curves
Figure 25. On-state resistance vs. Tcase
Figure 26. On-state resistance vs. VCC
Ron [mOhm]
Ron [mOhm]
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
Iout = 1A
Vcc = 13V
-50
-25
0
25
50
75
100
125
150
T = 150 &deg;C
T = 125 &deg;C
T = 25 &deg;C
T = -40 &deg;C
0
175
5
10
15
20
25
30
35
T [&deg;C]
GAPGCFT01231
GAPGCFT01232
Figure 27. Turn-on voltage slope
Figure 28. Turn-off voltage slope
(dVout/dt)On [V/&micro;s]
(dVout/dt)Off [V/ &micro;s]
1
1
0.9
0.9
0.8
0.8
Vcc = 13V
Rl = 13Ω
0.7
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
-50
-25
0
25
50
75
100
Vcc = 13V
Rl = 13Ω
0.7
0.6
0
125
150
0
175
-50
-25
0
25
50
T [&deg;C]
75
100
125
150
175
T [&deg;C]
GAPGCFT01234
GAPGCFT01233
Figure 29. Won vs. Tcase
Figure 30. Woff vs. Tcase
Woff [mJ]
Won [mJ]
1
1
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
-50
-25
0
25
50
75
100
125
150
175
T [&deg;C]
-50
-25
0
25
50
75
100
125
150
175
T [&deg;C]
GAPGCFT01235
DS10830 - Rev 4
40
Vcc [V]
GAPGCFT01236
page 21/45
VN7140AJ, VN7140AS
Electrical characteristics curves
Figure 32. OFF-state open-load voltage detection
threshold
Figure 31. ILIMH vs. Tcase
Ilimh [A]
VOL [V]
20
4
3.5
15
3
2.5
10
Vcc = 13V
2
1.5
5
1
0.5
0
-50
-25
0
25
50
75
100
125
150
175
0
-50
T [&deg;C]
-25
0
25
Figure 33. Vsense clamp vs. Tcase
75
100
125
150
175
GAPGCFT01238
Figure 34. Vsenseh vs. Tcase
VSENSEH [V]
VSENSE_CL [V]
10
10
9
9
8
8
7
Iin = 1mA
7
6
6
5
5
4
4
3
3
2
2
1
Iin = -1mA
0
1
0
-1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
T [&deg;C]
T [&deg;C]
GAPGCFT01239
DS10830 - Rev 4
50
T [&deg;C]
GAPGCFT01237
GAPGCFT01240
page 22/45
VN7140AJ, VN7140AS
Protections
3
Protections
3.1
Power limitation
The basic working principle of this protection consists of an indirect measurement of the junction temperature
swing ΔTj through the direct measurement of the spatial temperature gradient on the device surface in order to
automatically shut off the output MOSFET as soon as ΔTj exceeds the safety level of ΔTj_SD. According to the
voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis
according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermomechanical fatigue.
3.2
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175&deg;C), it
automatically switches off and the diagnostic indication is triggered. According to the voltage level on the
FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or
remains off (FaultRST = High).
3.3
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as the other
components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current
flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a
safety level, ILIMH, by operating the output power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative
voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor
energy to be dissipated without damaging the device.
DS10830 - Rev 4
page 23/45
VN7140AJ, VN7140AS
Maximum demagnetization energy (VCC = 16 V)
4
Maximum demagnetization energy (VCC = 16 V)
Figure 35. Maximum turn off current versus inductance
VN7140Ax - Maximum turn off current versus inductance
10
1
I (A)
VN7140Ax - Single Pulse
Repetitive pulse Tjstart=100&deg;C
Repetitive pulse Tjstart=125&deg;C
0.1
0.1
1
L (mH)
10
100
1000
GAPGCFT01212
Note:
Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the
temperature specified above for curves A and B.
DS10830 - Rev 4
page 24/45
VN7140AJ, VN7140AS
Package and PCB thermal data
5
Package and PCB thermal data
5.1
PowerSSO-16 thermal data
Figure 36. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 37. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 12. PCB properties
Dimension
DS10830 - Rev 4
Value
Board finish thickness
1.6 mm +/- 10%
Board dimension
77 mm x 86 mm
Board Material
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal vias separation
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
Copper thickness on vias
0.025 mm
Footprint dimension (top layer)
2.2 mm x 3.9 mm
page 25/45
VN7140AJ, VN7140AS
PowerSSO-16 thermal data
Dimension
Value
Footprint, 2 cm2 or 8 cm2
Heatsink copper area dimension (bottom layer)
Figure 38. PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition (one channel on)
RTHjamb
100
RTHjamb
90
80
70
60
50
40
30
0
2
4
6
8
10
RTHj_amb on 4Layer PCB: 26.8&deg;C/W
GAPGCFT01213
Figure 39. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
ZTH (&deg;C/W)
100
10
1
Cu=foot print
Cu=2 cm2
Cu=8 cm2
4 Layer
0.1
0.0001
0.001
0.01
0.1
Time (s)
DS10830 - Rev 4
1
10
100
1000
GAPGCFT01214
page 26/45
VN7140AJ, VN7140AS
PowerSSO-16 thermal data
Equation: pulse calculation formula
ZTHδ = RTH &middot; δ + ZTHtp (1 - δ)
where δ = tP/T
Figure 40. Thermal fitting model of a double-channel HSD in PowerSSO-16
Note:
The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections
(power limitation or thermal cycling during thermal shutdown) are not triggered.
Table 13. Thermal parameters
Area/island (cm2)
DS10830 - Rev 4
Footprint
2
8
4L
R1 (&deg;C/W)
3.2
R2 (&deg;C/W)
4.4
R3 (&deg;C/W)
8
8
8
5
R4 (&deg;C/W)
16
6
6
4
R5 (&deg;C/W)
30
20
10
3
R6 (&deg;C/W)
26
20
18
7
C1 (W.s/&deg;C)
0.00012
C2 (W.s/&deg;C)
0.005
C3 (W.s/&deg;C)
0.1
C4 (W.s/&deg;C)
0.2
0.3
0.3
0.4
C5 (W.s/&deg;C)
0.4
1
1
4
C6 (W.s/&deg;C)
3
5
7
18
page 27/45
VN7140AJ, VN7140AS
SO-8 thermal data
5.2
SO-8 thermal data
Figure 41. S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 42. SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 14. PCB properties
Dimension
Board finish thickness
1.6 mm +/- 10%
Board dimension
77 mm x 86 mm
Board Material
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal vias separation
Thermal via diameter
Copper thickness on vias
Heatsink copper area dimension (bottom layer)
DS10830 - Rev 4
Value
1.2 mm
0.3 mm +/- 0.08 mm
0.025 mm
Footprint, 2 + 2 cm2 or 8 + 8 cm2
page 28/45
VN7140AJ, VN7140AS
SO-8 thermal data
Figure 43. SO-8 Rthj-amb vs PCB copper area in open box free air condition (one channel on)
RTHjamb
110
RTHjamb
100
90
80
70
60
50
0
2
4
6
8
10
RTHj_amb on 4Layer PCB: 48.5&deg;C/W
GAPGCFT01152
Figure 44. SO-8 thermal impedance junction ambient single pulse (one channel on)
ZTH (&deg;C/W)
100
10
1
Cu=8 cm2
Cu=2 cm2
Cu=foot print
4 Layer
0.1
0.0001
0.001
0.01
0.1
Time (s)
1
10
100
1000
GAPGCFT01153
Equation: pulse calculation formula
ZTHδ = RTH &middot; δ + ZTHtp (1 - δ)
where δ = tP/T
DS10830 - Rev 4
page 29/45
VN7140AJ, VN7140AS
SO-8 thermal data
Figure 45. Thermal fitting model of a double-channel HSD in SO-8
Note:
The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections
(power limitation or thermal cycling during thermal shutdown) are not triggered.
Table 15. Thermal parameters
DS10830 - Rev 4
Area/island (cm2)
Footprint
R1 (&deg;C/W)
4.2
R2 (&deg;C/W)
4.3
R3 (&deg;C/W)
10
R4 (&deg;C/W)
2
8
4L
28
17
17
17
R5 (&deg;C/W)
24
12
9
4
R6 (&deg;C/W)
30
23
19
9
C1 (W.s/&deg;C)
0.00012
C2 (W.s/&deg;C)
0.003
C3 (W.s/&deg;C)
0.03
C4 (W.s/&deg;C)
0.1
C5 (W.s/&deg;C)
0.4
0.8
0.8
0.8
C6 (W.s/&deg;C)
3
7
11
22
page 30/45
VN7140AJ, VN7140AS
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
6.1
PowerSSO-16 package information
Figure 46. PowerSSO-16 package outline
ggg
D2
D3
Bottom view
C A-B D
ggg
C A-B D
minimum solderable area
Section A-A
E3 E2
h
θ2
h
θ1
R1
H
B
for dual gauge only
eee C
GAUGE PLANE
S
A2
A
R
B
L
θ3
ccc C
θ
e
L1
SEATING PLANE
A1
b
ddd
C
CD
2x
f f f C A-B
D
A
N
Section B-B
D
A
b
WITH PLATING
1.2
for dual gauge only
c
c1
E1 E
index area
(0.25D x 0.75E1)
b1
2x
BASE METAL
aaa C D
Top view
2x N/2 TIPS
bbb C
1
2
3
A
N/2
B
8017965_Rev_9
DS10830 - Rev 4
GAPG1605141159CFT
page 31/45
VN7140AJ, VN7140AS
PowerSSO-16 package information
Table 16. PowerSSO-16 mechanical data
Symbol
Millimeters
Min.
Typ.
Max.
Θ
0&deg;
8&deg;
Θ1
0&deg;
Θ2
5&deg;
15&deg;
Θ3
5&deg;
15&deg;
A
1.70
A1
0.00
0.10
A2
1.10
1.60
b
0.20
0.30
b1
0.20
c
0.19
c1
0.19
D
0.25
0.28
0.25
0.20
0.23
4.9 BSC
D2
2.90
D3
2.20
3.50
e
0.50 BSC
E
6.00 BSC
E1
3.90 BSC
E2
2.20
E3
1.50
h
0.25
L
0.40
2.80
0.50
0.60
L1
1.00 REF
N
16
R
0.07
R1
0.07
S
0.20
0.85
Tolerance of form and position
DS10830 - Rev 4
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.08
eee
0.10
fff
0.10
ggg
0.15
page 32/45
VN7140AJ, VN7140AS
SO-8 package information
6.2
SO-8 package information
Figure 47. SO-8 package outline
0016023_H
GAPG1605141113CFT
Table 17. SO-8 mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
1.75
A1
0.10
A2
1.25
b
0.28
0.48
c
0.17
0.23
D
4.80
4.90
5.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
e
0.25
1.27
h
0.25
0.50
L
0.40
1.27
L1
k
ccc
DS10830 - Rev 4
Max.
1.04
0&ordm;
8&ordm;
0.10
page 33/45
VN7140AJ, VN7140AS
PowerSSO-16 packing information
6.3
PowerSSO-16 packing information
Figure 48. PowerSSO-16 reel 13&quot;
Access Hole at
Slot Location
( 40 mm min.)
W2
N
D
A
C
W1
B
If present,
tape slot in core
for tape start:
2.5 mm min. width x
10.0 mm min. depth
TAPG2004151655CFT
Table 18. Reel dimensions
Description
Value(1)
Base quantity
2500
Bulk quantity
2500
A (max)
330
B (min)
1.5
C (+0.5, -0.2)
13
D (min)
20.2
N
100
W1 (+2 /-0)
12.4
W2 (max)
18.4
1. All dimensions are in mm.
DS10830 - Rev 4
page 34/45
VN7140AJ, VN7140AS
PowerSSO-16 packing information
Figure 49. PowerSSO-16 carrier tape
P0
P2
4.0 &plusmn;0.1
2.0 &plusmn;0.1
0.30 &plusmn;0.05
X
1.55 &plusmn;0.05
1.75 &plusmn;0.1
1.6 &plusmn;0.1
F
W
B0
R 0.5
Typical
Y
K1
Y
X
K0
P1
A0
SECTION X - X
REF 4.18
REF 0.6
REF 0.5
SECTION Y - Y
GAPG2204151242CFT
Table 19. PowerSSO-16 carrier tape dimensions
Description
Value(1)
A0
6.50 &plusmn; 0.1
B0
5.25 &plusmn; 0.1
K0
2.10 &plusmn; 0.1
K1
1.80 &plusmn; 0.1
F
5.50 &plusmn; 0.1
P1
8.00 &plusmn; 0.1
W
12.00 &plusmn; 0.3
1. All dimensions are in mm.
Figure 50. PowerSSO-16 schematic drawing of leader and trailer tape
Embossed carrier
Punched carrier
8 mm &amp; 12 mm only
END
Carrier tape
Round sprocket holes
START
Top cover tape
Elongated sprocket holes
(32 mm tape and wider)
Trailer
160 mm minimum
Top cover tape
Components
100 mm min.
Leader
400 mm minimum
User direction feed
GAPG2004151511CFT
DS10830 - Rev 4
page 35/45
VN7140AJ, VN7140AS
SO-8 packing information
6.4
SO-8 packing information
Figure 51. Reel for SO-8
Access Hole at
Slot Location
( 40 mm min.)
W2
A
N
D
C
W1
B
If present,
tape slot in core
for tape start:
2.5 mm min. width x
10.0 mm min. depth
TAPG2004151655CFT
Table 20. Reel dimensions
Description
Value(1)
Base quantity
2500
Bulk quantity
2500
A (max)
330
B (min)
1.5
C (+0.5, -0.2)
13
D (min)
20.2
N
100
W1 (+2/ -0)
12.4
W2 (max)
18.4
1. All dimensions are in mm.
DS10830 - Rev 4
page 36/45
VN7140AJ, VN7140AS
SO-8 packing information
Figure 52. SO-8 carrier tape
GAPG2105151447CFT
Table 21. SO-8 carrier tape dimensions
Description
Value(1)
A0
6.50 &plusmn; 0.1
B0
5.30 &plusmn; 0.1
K0
2.20 &plusmn; 0.1
K1
1.90 &plusmn; 0.1
F
5.50 &plusmn; 0.1
P1
8.00 &plusmn; 0.1
W
12.00 &plusmn; 0.3
1. All dimensions are in mm.
Figure 53. SO-8 schematic drawing of leader and trailer tape
DS10830 - Rev 4
page 37/45
VN7140AJ, VN7140AS
PowerSSO-16 marking information
6.5
PowerSSO-16 marking information
Figure 54. PowerSSO-16 marking information
Special function digit
&amp;: Engineering sample
&lt;blank&gt;: Commercial sample
PowerSSO-16 TOP VIEW
(not to scale)
GADG0310161234SMD
Parts marked as ‘&amp;’ are not yet qualified and therefore not approved for use in production. ST is not responsible
for any consequences resulting from such use. In no event will ST be liable for the customer using any of these
engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
6.6
SO-8 marking information
Figure 55. SO-8 marking information
Marking area
1
2
3
4
5
6
7
8
Special function digit
&amp;: Engineering sample
&lt;blank&gt;: Commercial sample
SO-8 TOP VIEW
(not in scale)
GAPG2705151558CFT
Note:
DS10830 - Rev 4
Engineering Samples: these samples can be clearly identified by a dedicated special symbol in the marking of
each unit. These samples are intended to be used for electrical compatibility evaluation only; usage for any other
purpose may be agreed only upon written authorization by ST. ST is not liable for any customer usage in
production and/or in reliability qualification trials.
Commercial Samples: fully qualified parts from ST standard production with no usage restrictions
page 38/45
VN7140AJ, VN7140AS
Order codes
7
Order codes
Table 22. Device summary
Package
DS10830 - Rev 4
Order codes
Tape and reel
PowerSSO-16
VN7140AJTR
SO-8
VN7140ASTR
page 39/45
VN7140AJ, VN7140AS
Revision history
Table 23. Document revision history
Date
Revision
03-Jun-2015
1
Changes
Initial release.
Updated cover image.
Updated Table 4: &quot;Thermal data&quot;
22-Jul-2015
DS10830 - Rev 4
2
Updated following sections:
•
Section 6.1: &quot;PowerSSO-16 thermal data&quot;
•
Section 6.2: &quot;SO-8 thermal data&quot;
•
Added AEC Q100 qualified in Features section
•
Updated Figure 61: &quot;PowerSSO-16 marking information&quot;
13-Oct-2016
3
28-Jun-2018
4
Minor text changes in TCASE and VCC monitor.
04-Apr-2019
5
Updated Table 16. PowerSSO-16 mechanical data
page 40/45
VN7140AJ, VN7140AS
Contents
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
2.1
Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.1
Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2
Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3
Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4
Negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4
Maximum demagnetization energy (VCC = 16 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6
7
5.1
PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2
SO-8 thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.1
PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2
SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3
PowerSSO-16 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.4
SO-8 packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.5
PowerSSO-16 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.6
SO-8 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
DS10830 - Rev 4
page 41/45
VN7140AJ, VN7140AS
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Suggested connections for unused and not connected pins .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . .
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MultiSense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MultiSense multiplexer addressing . . . . . . . . . . . . . . . . . .
PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . .
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . .
Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 carrier tape dimensions . . . . . . . . . . . . . . .
Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO-8 carrier tape dimensions . . . . . . . . . . . . . . . . . . . . .
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document revision history . . . . . . . . . . . . . . . . . . . . . . . .
DS10830 - Rev 4
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. 9
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15
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page 42/45
VN7140AJ, VN7140AS
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
DS10830 - Rev 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration diagram (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current and voltage conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current sense accuracy versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching time and Pulse skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MultiSense timings (current sense mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multisense timings (chip temperature and VCC sense mode) (VN7140AJ only) . . . . . . . . . .
TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Latch functionality - behavior in hard short-circuit condition (TAMB &lt;&lt; TTSD) . . . . . . . . . . . .
Latch functionality - behavior in hard short-circuit condition. . . . . . . . . . . . . . . . . . . . . . . .
Latch functionality - behavior in hard short-circuit condition (autorestart mode + latch off) . . .
Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IGND(ON) vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Input low level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Input hysteresis voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FaultRST Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Won vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Woff vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFF-state open-load voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vsense clamp vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vsenseh vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum turn off current versus inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition (one channel on) .
PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) . . . . . . .
Thermal fitting model of a double-channel HSD in PowerSSO-16 . . . . . . . . . . . . . . . . . . .
S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . . . . . . . .
SO-8 Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . .
SO-8 thermal impedance junction ambient single pulse (one channel on) . . . . . . . . . . . . . .
Thermal fitting model of a double-channel HSD in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO-8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 reel 13&quot; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 schematic drawing of leader and trailer tape . . . . . . . . . . . . . . . . . . . . . . .
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. 3
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. 5
12
13
13
14
14
15
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18
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19
19
19
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29
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31
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35
35
page 43/45
VN7140AJ, VN7140AS
List of figures
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
DS10830 - Rev 4
Reel for SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . .
SO-8 carrier tape . . . . . . . . . . . . . . . . . . . . . . .
SO-8 schematic drawing of leader and trailer tape.
PowerSSO-16 marking information . . . . . . . . . . .
SO-8 marking information . . . . . . . . . . . . . . . . .
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36
37
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38
page 44/45
VN7140AJ, VN7140AS
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service
names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
&copy; 2019 STMicroelectronics – All rights reserved
DS10830 - Rev 4
page 45/45
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