STMicroelectronics VND7050AJ Datasheet

VND7050AJ
Double channel high-side driver with MultiSense analog
feedback for automotive applications
Datasheet - production data
−
−
−
Loss of ground and loss of VCC
Reverse battery with external
components
Electrostatic discharge protection
Applications
•
Features
Max transient supply voltage
VCC
40 V
Operating voltage range
VCC
4 to 28 V
Typ. on-state resistance (per Ch)
RON
50 mΩ
Current limitation (typ)
ILIMH
30 A
Standby current (max)
ISTBY
0.5 µA
•
•
•
•
AEC-Q100 qualified
General
−
Double channel smart high-side driver
with MultiSense analog feedback
−
Very low standby current
−
Compatible with 3 V and 5 V CMOS
outputs
MultiSense diagnostic functions
−
Multiplexed analog feedback of: load
current with high precision proportional
current mirror, VCC supply voltage and
TCHIP device temperature
−
Overload and short to ground (power
limitation) indication
−
Thermal shutdown indication
−
OFF-state open-load detection
−
Output short to VCC detection
−
Sense enable/disable
Protections
−
Undervoltage shutdown
−
Overvoltage clamp
−
Load current limitation
−
Self limiting of fast thermal transients
−
Configurable latch-off on
overtemperature or power limitation
with dedicated fault reset pin
October 2016
•
All types of Automotive resistive, inductive
and capacitive loads
Specially intended for Automotive Signal
Lamps (up to P27W or SAE1156 or LED
Rear Combinations)
Description
The device is a double channel high-side driver
manufactured using ST proprietary VIPower® M07 technology and housed in PowerSSO-16
package. The device is designed to drive 12 V
automotive grounded loads through a 3 V and
5 V CMOS-compatible interface, providing
protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions including high precision proportional
load current sense, supply voltage feedback and
chip temperature sense, in addition to the
detection of overload and short circuit to ground,
short to VCC and OFF-state open-load.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
DocID027396 Rev 2
This is information on a product in full production.
1/47
www.st.com
Contents
VND7050AJ
Contents
1
Block diagram and pin description ................................................ 5
2
Electrical specification.................................................................... 7
3
4
2.1
Absolute maximum ratings ................................................................ 7
2.2
Thermal data ..................................................................................... 8
2.3
Main electrical characteristics ........................................................... 8
2.4
Waveforms ...................................................................................... 20
2.5
Electrical characteristics curves ...................................................... 23
Protections..................................................................................... 27
3.1
Power limitation ............................................................................... 27
3.2
Thermal shutdown........................................................................... 27
3.3
Current limitation ............................................................................. 27
3.4
Negative voltage clamp ................................................................... 27
Application information ................................................................ 28
4.1
GND protection network against reverse battery............................. 28
4.1.1
Diode (DGND) in the ground line ..................................................... 29
4.2
Immunity against transient electrical disturbances .......................... 29
4.3
MCU I/Os protection........................................................................ 30
4.4
Multisense - analog current sense .................................................. 30
4.4.1
Principle of Multisense signal generation ......................................... 32
4.4.2
TCASE and VCC monitor ................................................................. 34
4.4.3
Short to VCC and OFF-state open-load detection ........................... 35
5
Maximum demagnetization energy (VCC = 16 V) ........................ 36
6
Package and PCB thermal data .................................................... 37
6.1
7
PowerSSO-16 thermal data ............................................................ 37
Package information ..................................................................... 40
7.1
PowerSSO-16 package information ................................................ 40
7.2
PowerSSO-16 packing information ................................................. 42
7.3
PowerSSO-16 marking information ................................................. 44
8
Order codes ................................................................................... 45
9
Revision history ............................................................................ 46
2/47
DocID027396 Rev 2
VND7050AJ
List of tables
List of tables
Table 1: Pin functions ................................................................................................................................. 5
Table 2: Suggested connections for unused and not connected pins ........................................................ 6
Table 3: Absolute maximum ratings ........................................................................................................... 7
Table 4: Thermal data ................................................................................................................................. 8
Table 5: Power section ............................................................................................................................... 8
Table 6: Switching....................................................................................................................................... 9
Table 7: Logic inputs ................................................................................................................................. 10
Table 8: Protections .................................................................................................................................. 11
Table 9: MultiSense .................................................................................................................................. 12
Table 10: Truth table ................................................................................................................................. 19
Table 11: MultiSense multiplexer addressing ........................................................................................... 20
Table 12: ISO 7637-2 - electrical transient conduction along supply line................................................. 29
Table 13: MultiSense pin levels in off-state .............................................................................................. 34
Table 14: PCB properties ......................................................................................................................... 37
Table 15: Thermal parameters ................................................................................................................. 39
Table 16: PowerSSO-16 mechanical data................................................................................................ 40
Table 17: Reel dimensions ....................................................................................................................... 42
Table 18: PowerSSO-16 carrier tape dimensions .................................................................................... 43
Table 19: Device summary ....................................................................................................................... 45
Table 20: Document revision history ........................................................................................................ 46
DocID027396 Rev 2
3/47
List of figures
VND7050AJ
List of figures
Figure 1: Block diagram .............................................................................................................................. 5
Figure 2: Configuration diagram (top view)................................................................................................. 6
Figure 3: Current and voltage conventions ................................................................................................. 7
Figure 4: IOUT/ISENSE versus IOUT....................................................................................................... 16
Figure 5: Current sense accuracy versus IOUT ....................................................................................... 17
Figure 6: Switching time and Pulse skew ................................................................................................. 17
Figure 7: MultiSense timings (current sense mode) ................................................................................. 18
Figure 8: Multisense timings (chip temperature and VCC sense mode) .................................................. 18
Figure 9: TDSTKON.................................................................................................................................. 19
Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ...................... 20
Figure 11: Latch functionality - behavior in hard short circuit condition.................................................... 21
Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) .... 21
Figure 13: Standby mode activation ......................................................................................................... 22
Figure 14: Standby state diagram ............................................................................................................. 22
Figure 15: OFF-state output current ......................................................................................................... 23
Figure 16: Standby current ....................................................................................................................... 23
Figure 17: IGND(ON) vs. Iout ................................................................................................................... 23
Figure 18: Logic Input high level voltage .................................................................................................. 23
Figure 19: Logic Input low level voltage.................................................................................................... 23
Figure 20: High level logic input current ................................................................................................... 23
Figure 21: Low level logic input current .................................................................................................... 24
Figure 22: Logic Input hysteresis voltage ................................................................................................. 24
Figure 23: FaultRST Input clamp voltage ................................................................................................. 24
Figure 24: Undervoltage shutdown ........................................................................................................... 24
Figure 25: On-state resistance vs. Tcase ................................................................................................. 24
Figure 26: On-state resistance vs. VCC ................................................................................................... 24
Figure 27: Turn-on voltage slope .............................................................................................................. 25
Figure 28: Turn-off voltage slope .............................................................................................................. 25
Figure 29: Won vs. Tcase ......................................................................................................................... 25
Figure 30: Woff vs. Tcase ......................................................................................................................... 25
Figure 31: ILIMH vs. Tcase ....................................................................................................................... 25
Figure 32: OFF-state open-load voltage detection threshold ................................................................... 25
Figure 33: Vsense clamp vs. Tcase.......................................................................................................... 26
Figure 34: Vsenseh vs. Tcase .................................................................................................................. 26
Figure 35: Application diagram ................................................................................................................. 28
Figure 36: Simplified internal structure ..................................................................................................... 28
Figure 37: MultiSense and diagnostic – block diagram ............................................................................ 31
Figure 38: MultiSense block diagram ....................................................................................................... 32
Figure 39: Analogue HSD – open-load detection in off-state ................................................................... 33
Figure 40: Open-load / short to VCC condition ......................................................................................... 34
Figure 41: GND voltage shift .................................................................................................................... 35
Figure 42: Maximum turn off current versus inductance .......................................................................... 36
Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ............................................ 37
Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ........................................... 37
Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on) ..................... 38
Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) .............. 38
Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16.......................................... 39
Figure 48: PowerSSO-16 package outline ............................................................................................... 40
Figure 49: PowerSSO-16 reel 13" ............................................................................................................ 42
Figure 50: PowerSSO-16 carrier tape ...................................................................................................... 43
Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape .................................................. 43
Figure 52: PowerSSO-16 marking information ......................................................................................... 44
4/47
DocID027396 Rev 2
VND7050AJ
1
Block diagram and pin description
Block diagram and pin description
Figure 1: Block diagram
Table 1: Pin functions
Name
VCC
OUTPUT0,1
GND
INPUT0,1
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external diode / resistor
network.
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS
outputs. It controls output switch state.
MultiSense
Multiplexed analog sense output pin; it delivers a current proportional to the selected
diagnostic: load current, supply voltage or chip temperature.
SEn
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense
diagnostic pin.
SEL0,1
FaultRST
Active high compatible with 3 V and 5 V CMOS outputs pin; they address the
MultiSense multiplexer.
Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in
case of fault; If kept low, sets the outputs in auto-restart. mode
DocID027396 Rev 2
5/47
Block diagram and pin description
VND7050AJ
Figure 2: Configuration diagram (top view)
Table 2: Suggested connections for unused and not connected pins
MultiSense
N.C.
Output
Input
Floating
Not allowed
X (1)
X
X
X
To ground
Through 1 kΩ
resistor
X
Not
allowed
Through 15 kΩ
resistor
Through 15 kΩ
resistor
Notes:
(1)X:
6/47
SEn, SELx,
Connection /
pin
do not care.
DocID027396 Rev 2
FaultRST
VND7050AJ
2
Electrical specification
Electrical specification
Figure 3: Current and voltage conventions
IS
VCC
IFR
ISEn
OUTPUT0,1
MultiSense
SEL0,1
IIN
VOUT
ISENSE
SEn
VSENSE
INPUT0,1
VIN
VSEL
VSEn
VFR
ISEL
FaultRST
VCC
VFn
IOUT
IGND
GAPGCFT00315
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability.
Table 3: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage
38
-VCC
Reverse DC supply voltage
0.3
VCCPK
Maximum transient supply voltage (ISO 16750-2:2010 Test B
clamped to 40V; RL = 4 Ω)
40
V
VCCJS
Maximum jump start voltage for single pulse short circuit
protection
28
V
-IGND
DC reverse ground pin current
200
mA
IOUT
OUTPUT0,1 DC output current
Internally
limited
A
-IOUT
Reverse DC output current
IIN
INPUT0,1 DC input current
ISEn
SEn DC input current
ISEL
SEL0,1 DC input current
IFR
FaultRST DC input current
DocID027396 Rev 2
V
11
-1 to 10
mA
7/47
Electrical specification
VND7050AJ
Symbol
Parameter
Value
Unit
FaultRST DC input voltage
7.5
V
MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V)
10
MultiSense pin DC output current in reverse (VCC < 0 V)
-20
EMAX
Maximum switching energy (single pulse) (TDEMAG = 0.4 ms;
Tjstart = 150 °C)
30
mJ
VESD
Electrostatic discharge (JEDEC 22A-114F)
•
INPUT0,1
•
MultiSense
•
SEn, SEL0,1, FaultRST
•
OUTPUT0,1
•
VCC
4000
2000
4000
4000
4000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
VFR
ISENSE
Tj
Tstg
2.2
mA
Junction operating temperature
-40 to 150
Storage temperature
-55 to 150
°C
Thermal data
Table 4: Thermal data
Symbol
Parameter
Typ. value
Rthj-board
Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8)
(1)(2)
Unit
6.4
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-5)
(1)(3)
59
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-7)(1)(2)
25
°C/W
Notes:
(1)One
2.3
channel ON.
(2)Device
mounted on four-layers 2s2p PCB
(3)Device
mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace
Main electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5: Power section
Symbol
8/47
Parameter
Test conditions
Min.
Typ.
Max.
Unit
4
13
28
V
VCC
Operating supply
voltage
VUSD
Undervoltage
shutdown
4
V
VUSDReset
Undervoltage
shutdown reset
5
V
VUSDhyst
Undervoltage
shutdown
hysteresis
0.3
DocID027396 Rev 2
V
VND7050AJ
Electrical specification
Symbol
RON
Vclamp
ISTBY
Parameter
Test conditions
Max.
Unit
IOUT = 2 A; Tj = 150°C
100
mΩ
IOUT = 2 A; VCC = 4 V; Tj = 25°C
75
IOUT = 2 A; Tj = 25°C
On-state
resistance (1)
Clamp voltage
Supply current in
standby at
VCC = 13 V (2)
IS = 20 mA; 25°C < Tj < 150°C
41
IS = 20 mA; Tj = -40°C
38
0.5
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 125°C
3
Supply current
VCC = 13 V; VSEn = VFR = VSEL0,1 = 0 V;
VIN0 = 5 V; VIN1 = 5 V;
IOUT0 = 0 A; IOUT1 = 0 A
Control stage
current
consumption in ON
state. All channels
active.
VCC = 13 V; VSEn = 5 V;
VFR = VSEL0,1 = 0 V; VIN0 = 5 V;
VIN1 = 5 V; IOUT0 = 2 A; IOUT1 = 2 A
Output - VCC diode
voltage (2)
60
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25°C
0
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125°C
0
V
V
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 85°C (3)
IS(ON)
VF
52
0.5
VCC = 13 V;
VIN = VOUT = VFR = VSEL0,1 = 0 V;
VSEn = 5 V to 0 V
IL(off)
46
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 25°C
Standby mode
blanking time
Off-state output
current at
VCC = 13 V (2)
Typ.
50
tD_STBY
IGND(ON)
Min.
µA
300
550
µs
5
8
mA
12
mA
0.01
0.5
µA
3
IOUT = -2 A; Tj = 150°C
0.7
V
Notes:
(1)For
each channel
(2)PowerMOS
(3)Parameter
leakage included.
specified by design; not subject to production test.
Table 6: Switching
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
Symbol
Test
conditions
Parameter
td(on)(1)
Turn-on delay time at Tj = 25 °C
td(off)(1)
Turn-off delay time at Tj = 25 °C
(dVOUT/dt)on(1)
Turn-on voltage slope at Tj = 25 °C
(dVOUT/dt)off
Turn-off voltage slope at Tj = 25 °C
(1)
RL = 6.5 Ω
RL = 6.5 Ω
DocID027396 Rev 2
Min.
Typ.
Max.
10
60
120
10
40
100
0.1
0.3
0.7
0.1
0.32
0.7
Unit
µs
V/µs
9/47
Electrical specification
VND7050AJ
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
Test
conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
WON
Switching energy losses at turn-on
(twon)
RL = 6.5 Ω
—
0.25
0.33(2)
mJ
WOFF
Switching energy losses at turn-off
(twoff)
RL = 6.5 Ω
—
0.23
tSKEW (1)
Differential Pulse skew (tPHL - tPLH)
RL = 6.5 Ω
-80
-30
0.31
(2)
mJ
20
µs
Max.
Unit
0.9
V
Notes:
(1)See Figure 6: "Switching time and Pulse skew".
(2)Parameter
guaranteed by design and characterization; not subject to production test.
Table 7: Logic inputs
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
Typ.
INPUT0,1 characteristics
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
5.3
IIN = -1 mA
µA
7.2
-0.7
V
FaultRST characteristics
VFRL
Input low level voltage
IFRL
Low level input current
VFRH
Input high level voltage
IFRH
High level input current
VFR(hyst)
Input hysteresis voltage
VFRCL
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
V
5.3
IIN = -1 mA
µA
7.5
-0.7
V
SEL0,1 characteristics (7 V < VCC < 18 V)
VSELL
Input low level voltage
ISELL
Low level input current
VSELH
Input high level voltage
ISELH
High level input current
VSEL(hyst)
Input hysteresis voltage
VSELCL
Input clamp voltage
0.9
VIN = 0.9 V
µA
V
10
0.2
IIN = -1 mA
SEn characteristics (7 V < VCC < 18 V)
10/47
1
2.1
VIN = 2.1 V
IIN = 1 mA
DocID027396 Rev 2
V
µA
V
5.3
7.2
-0.7
V
VND7050AJ
Electrical specification
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
VSEnL
Input low level voltage
ISEnL
Low level input current
VSEnH
Input high level voltage
ISEnH
High level input current
VSEn(hyst)
Input hysteresis voltage
VSEnCL
VIN = 0.9 V
Min.
Typ.
Unit
0.9
V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
Input clamp voltage
Max.
V
5.3
IIN = -1 mA
µA
7.2
-0.7
V
Table 8: Protections
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
VCC = 13 V
ILIMH
DC short circuit
current
4 V < VCC < 18 V
ILIML
Short circuit current
during thermal
cycling
VCC = 13 V;
TR < Tj < TTSD
TTSD
Shutdown
temperature
TR
Reset temperature(1)
TRS
Thermal reset of fault
diagnostic indication
VFR = 0 V; VSEn = 5 V
Thermal hysteresis
(TTSD - TR)(1)
ΔTJ_SD
Dynamic
temperature
Tj = -40°C; VCC = 13 V
Fault reset time for
output unlatch (1)
VFR = 5 V to 0 V; VSEn = 5 V;
VIN = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V
VDEMAG
VON
Turn-off output
voltage clamp
Output voltage drop
limitation
Typ.
21
30
(1)
THYST
tLATCH_RST
Min.
Max.
Unit
42
A
10
150
175
TRS + 1
TRS + 7
200
°C
135
7
60
3
IOUT = 2 A; L = 6 mH; Tj = 40°C
VCC 38
IOUT = 2 A; L = 6 mH;
Tj = 25°C to 150°C
VCC 41
IOUT = 0.2 A
10
K
20
µs
V
VCC 46
20
VCC 52
V
mV
Notes:
(1)Parameter
guaranteed by design and characterization; not subject to production test.
DocID027396 Rev 2
11/47
Electrical specification
VND7050AJ
Table 9: MultiSense
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
VSENSE_CL
Parameter
MultiSense clamp
voltage
Test conditions
VSEn = 0 V; ISENSE = 1 mA
Min.
Typ.
-17
VSEn = 0 V; ISENSE = -1 mA
Max.
-12
7
Unit
V
Current sense characteristics
KOL
dKcal/Kcal(1)(2)
KLED
dKLED/KLED(1)(2)
K0
dK0/K0(1)(2)
K1
dK1/K1(1)(2)
K2
dK2/K2(1)(2)
K3
dK3/K3(1)(2)
ISENSE0
12/47
IOUT/ISENSE
IOUT = 0.01 A;
VSENSE = 0.5 V; VSEn = 5 V
440
Current sense ratio
drift at calibration
point
IOUT = 0.01 A to 0.05 A;
Ical = 30 mA; VSENSE = 0.5 V;
VSEn = 5 V
-30
IOUT/ISENSE
IOUT = 0.05 A;
VSENSE = 0.5 V; VSEn = 5 V
530
Current sense ratio
drift
IOUT = 0.05 A;
VSENSE = 0.5 V; VSEn = 5 V
-25
IOUT/ISENSE
IOUT = 0.2 A; VSENSE = 0.5 V;
VSEn = 5 V
830
Current sense ratio
drift
IOUT = 0.2 A; VSENSE = 0.5 V;
VSEn = 5 V
-20
IOUT/ISENSE
IOUT = 0.4 A; VSENSE = 4 V;
VSEn = 5 V
915
Current sense ratio
drift
IOUT = 0.4 A; VSENSE = 4 V;
VSEn = 5 V
-15
IOUT/ISENSE
IOUT = 1.5 A; VSENSE = 4 V;
VSEn = 5 V
980
Current sense ratio
drift
IOUT = 1.5 A; VSENSE = 4 V;
VSEn = 5 V
-10
IOUT/ISENSE
IOUT = 4.5 A; VSENSE = 4 V;
VSEn = 5 V
1095
Current sense ratio
drift
IOUT = 4.5 A; VSENSE = 4 V;
VSEn = 5 V
-5
5
MultiSense disabled:
VSEn = 0 V
0
0.5
MultiSense disabled:
-1 V < VSENSE < 5 V(1)
-0.5
0.5
MultiSense leakage
current
MultiSense enabled:
VSEn = 5 V; All channels
ON; IOUTX = 0 A; ChX
diagnostic selected;
•
E.g. Ch0:
VIN0 = 5 V; VIN1 = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT0 = 0 A; IOUT1 = 2 A
DocID027396 Rev 2
30
1450
2200
25
1400
%
1470
10
1215
%
1700
15
1230
%
1935
20
1300
%
%
1335
%
µA
0
2
VND7050AJ
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
MultiSense enabled:
VSEn = 5 V; ChX channel
OFF; ChX diagnostic
selected:
•
E.g. Ch0:
VIN0 = 0 V; VIN1 = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT1 = 2 A
0
Typ.
Max.
Unit
2
VOUT_MSD(1)
Output Voltage for
MultiSense
shutdown
VSEn = 5 V; RSENSE = 2.7 kΩ;
•
E.g. Ch0:
VIN0 = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT0 = 2 A
VSENSE_SAT
Multisense
saturation voltage
VCC = 7 V; RSENSE = 2.7 kΩ;
VSEn = 5 V; VIN0 = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT0 = 4.5 A; Tj = 150°C
5
V
ISENSE_SAT
CS saturation
current
VCC = 7 V; VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
4
mA
Output saturation
current
VCC = 7 V; VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
6
A
OFF-state openload voltage
detection threshold
VSEn = 5 V; ChX OFF;
ChX diagnostic selected
•
E.g: Ch0
VIN0 = 0 V;
VSEL0 = 0 V;
VSEL1 = 0 V
2
OFF-state output
sink current
VIN = 0 V; VOUT = VOL
-100
tDSTKON
OFF-state
diagnostic delay
time from falling
edge of INPUT (see
Figure 9:
"TDSTKON")
VSEn = 5 V; ChX ON to OFF
transition;
ChX diagnostic selected
•
E.g: Ch0
VIN0 = 5 V to 0 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT0 = 0 A; VOUT = 4 V
100
tD_OL_V
Settling time for
valid OFF-state
open load diagnostic
indication from rising
edge of SEn
VIN0 = 0 V; VIN1 = 0 V;
VFR = 0 V; VSEL0 = 0 V;
VSEL1 = 0 V; VOUT0 = 4 V;
VSEn = 0 V to 5 V
(1)
IOUT_SAT(1)
5
V
OFF-state diagnostic
VOL
IL(off2)
DocID027396 Rev 2
3
350
4
V
-15
µA
700
µs
60
µs
13/47
Electrical specification
VND7050AJ
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
tD_VOL
Parameter
OFF-state
diagnostic delay
time from rising
edge of VOUT
Test conditions
Min.
VSEn = 5 V; ChX OFF;
ChX diagnostic selected
•
E.g: Ch0
VIN0 = 0 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
VOUT = 0 V to 4 V
Typ.
Max.
Unit
5
30
µs
Chip temperature analog feedback
VSENSE_TC
dVSENSE_TC/dT
MultiSense output
voltage proportional
to chip temperature
Temperature
coefficient
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN0,1 = 0 V;
RSENSE = 1 kΩ; Tj = -40°C
2.325
2.41
2.495
V
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN0,1 = 0 V;
RSENSE = 1 kΩ; Tj = 25°C
1.985
2.07
2.155
V
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN0,1 = 0 V;
RSENSE = 1 kΩ; Tj = 125°C
1.435
1.52
1.605
V
Tj = -40°C to 150°C
Transfer function
-5.5
mV/K
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
VCC supply voltage analog feedback
VSENSE_VCC
MultiSense output
voltage proportional
to VCC supply
voltage
Transfer function (3)
VCC = 13 V; VSEn = 5 V;
VSEL0 = 5 V; VSEL1 = 5 V;
VIN0,1 = 0 V; RSENSE = 1 kΩ
3.16
3.23
3.3
V
6.6
V
30
mA
VSENSE_VCC = VCC / 4
Fault diagnostic feedback (see Table 10: "Truth table")
VSENSEH
MultiSense output
voltage in fault
condition
VCC = 13 V; RSENSE = 1 kΩ;
•
E.g: Ch0 in open load
VIN0 = 0 V; VSEn = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V;
IOUT0 = 0 A; VOUT = 4 V
ISENSEH
MultiSense output
current in fault
condition
VCC = 13 V; VSENSE = 5 V
5
7
20
MultiSense timings (current sense mode - see Figure 7: "MultiSense timings (current sense
mode)")(4)
14/47
tDSENSE1H
Current sense
settling time from
rising edge of SEn
VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 kΩ; RL = 6.5 Ω
tDSENSE1L
Current sense
disable delay time
from falling edge of
SEn
VIN = 5 V; VSEn = 5 V to 0 V;
RSENSE = 1 kΩ; RL = 6.5 Ω
DocID027396 Rev 2
5
60
µs
20
µs
VND7050AJ
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Current sense
settling time from
rising edge of
INPUT
VIN = 0 V to 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 6.5 Ω
ΔtDSENSE2H
Current sense
settling time from
rising edge of IOUT
(dynamic response
to a step change of
IOUT)
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; ISENSE
= 90 % of ISENSEMAX;
RL = 6.5 Ω
tDSENSE2L
Current sense turnoff delay time from
falling edge of
INPUT
VIN = 5 V to 0 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 6.5 Ω
tDSENSE2H
Min.
Typ.
Max.
Unit
100
250
µs
100
µs
250
µs
50
MultiSense timings (chip temperature sense mode - see Figure 8: "Multisense timings (chip
temperature and VCC sense mode)")(4)
tDSENSE3H
VSENSE_TC settling
time from rising
edge of SEn
VSEn = 0 V to 5 V;
VSEL0 = 0 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
60
µs
tDSENSE3L
VSENSE_TC disable
delay time from
falling edge of SEn
VSEn = 5 V to 0 V;
VSEL0 = 0 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20
µs
MultiSense timings (VCC voltage sense mode - see Figure 8: "Multisense timings (chip
temperature and VCC sense mode)")(4)
tDSENSE4H
VSENSE_VCC settling
time from rising
edge of SEn
VSEn = 0 V to 5 V;
VSEL0 = 5 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
60
µs
tDSENSE4L
VSENSE_VCC disable
delay time from
falling edge of SEn
VSEn = 5 V to 0 V;
VSEL0 = 5 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20
µs
MultiSense timings (Multiplexer transition times)(4)
tD_XtoY
MultiSense
transition delay from
ChX to ChY
VIN0 = 5 V; VIN1 = 5 V;
VSEn = 5 V; VSEL1 = 0 V;
VSEL0 = 0 V to 5 V;
IOUT0 = 0 A; IOUT1 = 3 A;
RSENSE = 1 kΩ
20
µs
tD_CStoTC
MultiSense
transition delay from
current sense to TC
sense
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V to
5 V; IOUT0 = 1.5 A;
RSENSE = 1 kΩ
60
µs
tD_TCtoCS
MultiSense
transition delay from
TC sense to current
sense
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 5 V to
0 V; IOUT0 = 1.5 A;
RSENSE = 1 kΩ
20
µs
tD_CStoVCC
MultiSense
transition delay from
current sense to VCC
sense
VIN1 = 5 V; VSEn = 5 V;
VSEL0 = 5 V; VSEL1 = 0 V to
5 V; IOUT1 = 1.5A;
RSENSE = 1 kΩ
60
µs
DocID027396 Rev 2
15/47
Electrical specification
VND7050AJ
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
tD_VCCtoCS
MultiSense
transition delay from
VCC sense to current
sense
Test conditions
Min.
Max.
Unit
VIN1 = 5 V; VSEn = 5 V;
VSEL0 = 5 V; VSEL1 = 5 V to
0 V; IOUT1 = 1.5 A;
RSENSE = 1 kΩ
20
µs
tD_TCtoVCC
MultiSense
transition delay from
TC sense to VCC
sense
VCC = 13 V; Tj = 125°C;
VSEn = 5 V; VSEL0 = 0 V to
5 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20
µs
tD_VCCtoTC
MultiSense
transition delay from
VCC sense to TC
sense
VCC = 13 V; Tj = 125°C;
VSEn = 5 V; VSEL0 = 5 V to
0 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20
µs
tD_CStoVSENSEH
MultiSense
transition delay from
stable current sense
on ChX to VSENSEH
on ChY
VIN0 = 5 V; VIN1 = 0 V;
VSEn = 5 V; VSEL1 = 0 V;
VSEL0 = 0 V to 5 V;
IOUT0 = 3 A; VOUT1 = 4 V;
RSENSE = 1 kΩ
20
µs
Notes:
(1)Parameter
(2)All
(3)V
guaranteed by design and characterization; not subject to production test.
values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
CC
sensing and TC sensing are referred to GND potential.
(4)Transition
delay are measured up to +/- 10% of final conditions.
Figure 4: IOUT/ISENSE versus IOUT
16/47
DocID027396 Rev 2
Typ.
VND7050AJ
Electrical specification
Figure 5: Current sense accuracy versus IOUT
Figure 6: Switching time and Pulse skew
DocID027396 Rev 2
17/47
Electrical specification
VND7050AJ
Figure 7: MultiSense timings (current sense mode)
IN1
High
SEn
Low
High
SEL0
Low
High
SEL1
Low
IOUT1
CURRENT SENSE
tDSENSE2H
tDSENSE1L
tDSENSE1H
tDSENSE2L
GAPGCFT00318
Figure 8: Multisense timings (chip temperature and VCC sense mode)
High
SEn
Low
High
SEL0
Low
High
SEL1
Low
VCC
VSENSE = VSENSE_VCC
VSENSE = VSENSE_TC
SENSE
tDSENSE4H
tDSENSE4L
VCC VOLTAGE SENSE MODE
tDSENSE3H
tDSENSE3L
CHIP TEMPERATURE SENSE MODE
GAPGCFT00319
18/47
DocID027396 Rev 2
VND7050AJ
Electrical specification
Figure 9: TDSTKON
VINPU T
VOU T
VOU T > VOL
MultiSense
TDSTKON
GAPG2609141140CFT
Table 10: Truth table
Mode
Standby
Conditions
INX
FR
SEn
SELX
OUTX
MultiSense
All logic inputs
low
L
L
L
L
L
Hi-Z
L
X
L
See (1)
H
L
H
See (1)
Outputs
configured for
auto-restart
H
H
H
See (1)
Outputs
configured for
Latch-off
L
X
L
See (1)
H
See
L
See (1)
Output latchesoff
L
L
Hi-Z
Hi-Z
Re-start when
VCC > VUSD +
VUSDhyst (rising)
H
See (1)
H
See (1)
<0V
See (1)
Nominal load
connected;
Tj < 150 °C
Normal
Overload or
short to GND
causing:
Tj > TTSD or
ΔTj > ΔTj_SD
H
L
H
H
VCC < VUSD
(falling)
X
X
OFF-state
diagnostics
Short to VCC
L
X
Open-load
L
X
Negative
output voltage
Inductive
loads turn-off
L
X
Overload
Undervoltage
See (1)
See (1)
X
X
See (1)
See (1)
(1)
Comments
Low quiescent
current
consumption
Output cycles
with
temperature
hysteresis
External pull-up
Notes:
(1)Refer
to Table 11: "MultiSense multiplexer addressing"
DocID027396 Rev 2
19/47
Electrical specification
VND7050AJ
Table 11: MultiSense multiplexer addressing
MultiSense output
SEn
SEL1
SEL0
MUX channel
L
X
X
H
L
L
Channel 0
diagnostic
ISENSE =
1/K * IOUT0
H
L
H
Channel 1
diagnostic
ISENSE =
1/K * IOUT1
H
H
L
TCHIP Sense
VSENSE = VSENSE_TC
H
H
H
VCC Sense
VSENSE = VSENSE_VCC
Normal
mode
OFF-state
diag. (1)
Negative
output
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
Overload
Hi-Z
Notes:
(1)In
case the output channel corresponding to the selected MUX channel is latched off while the relevant input is
low, Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN0 = 0; OUT0 = L
(latched); MUX channel = channel 0 diagnostic; Mutisense = 0. Example 2: FR = 1; IN0 = 0; OUT0 = latched,
VOUT0 > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH
2.4
Waveforms
Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD)
20/47
DocID027396 Rev 2
VND7050AJ
Electrical specification
Figure 11: Latch functionality - behavior in hard short circuit condition
Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode +
latch off)
DocID027396 Rev 2
21/47
Electrical specification
VND7050AJ
Figure 13: Standby mode activation
Figure 14: Standby state diagram
22/47
DocID027396 Rev 2
VND7050AJ
2.5
Electrical characteristics curves
Electrical specification
Figure 15: OFF-state output current
Figure 16: Standby current
Figure 17: IGND(ON) vs. Iout
Figure 18: Logic Input high level voltage
Figure 19: Logic Input low level voltage
Figure 20: High level logic input current
DocID027396 Rev 2
23/47
Electrical specification
VND7050AJ
Figure 21: Low level logic input current
Figure 22: Logic Input hysteresis voltage
Figure 23: FaultRST Input clamp voltage
Figure 24: Undervoltage shutdown
VFRCL [V]
8
7
Iin = 1mA
6
5
4
3
2
1
Iin = -1mA
0
-1
-50
-25
0
25
50
75
T [°C]
100
125
150
175
GAPG2110131613CFT
Figure 25: On-state resistance vs. Tcase
24/47
DocID027396 Rev 2
Figure 26: On-state resistance vs. VCC
VND7050AJ
Electrical specification
Figure 27: Turn-on voltage slope
Figure 28: Turn-off voltage slope
Figure 29: Won vs. Tcase
Figure 30: Woff vs. Tcase
Figure 31: ILIMH vs. Tcase
Figure 32: OFF-state open-load voltage
detection threshold
DocID027396 Rev 2
25/47
Electrical specification
VND7050AJ
Figure 34: Vsenseh vs. Tcase
Figure 33: Vsense clamp vs. Tcase
VSENSEH [V]
10
9
8
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
T [°C]
26/47
DocID027396 Rev 2
100
125
150
175
GAPG1905151315CFT
VND7050AJ
Protections
3
Protections
3.1
Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as
soon as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the
FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis
according to the maximum instantaneous power which can be handled (FaultRST = Low)
or remains off (FaultRST = High). The protection prevents fast thermal transient effects
and, consequently, reduces thermo-mechanical fatigue.
3.2
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered.
According to the voltage level on the FaultRST pin, the device switches on again as soon
as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High).
3.3
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well
as the other components of the system (e.g. bonding wires, wiring harness, connectors,
loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or
during load power-up, the output current is clamped to a safety level, ILIMH, by operating the
output power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a
certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the
device.
DocID027396 Rev 2
27/47
Application information
4
VND7050AJ
Application information
Figure 35: Application diagram
4.1
GND protection network against reverse battery
Figure 36: Simplified internal structure
28/47
DocID027396 Rev 2
VND7050AJ
4.1.1
Application information
Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12: "ISO 7637-2 electrical transient conduction along supply line".
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present
device only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns
automatically to normal operation after the test”.
Table 12: ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional performance
status
Minimum
number of
pulses or test
time
Burst cycle /
pulse
repetition time
min
Pulse duration and
pulse generator
internal impedance
Level
US(1)
max
1
III
-112 V
500 pulses
0.5 s
2a
III
+55 V
500 pulses
0.2 s
5s
50 µs, 2 Ω
3a
IV
-220 V
1h
90 ms
100
ms
0.1 µs, 50 Ω
3b
IV
+150 V
1h
90 ms
100
ms
0.1 µs, 50 Ω
4 (2)
IV
-7 V
1 pulse
2 ms, 10 Ω
100 ms, 0.01 Ω
Load dump according to ISO 16750-2:2010
Test B (3)
40 V
5 pulse
1 min
400 ms, 2 Ω
Notes:
(1)U
S
is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
(2)Test
pulse from ISO 7637-2:2004(E).
(3)With
40 V external suppressor referred to ground (-40°C < Tj < 150 °C).
DocID027396 Rev 2
29/47
Application information
4.3
VND7050AJ
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the HSD I/Os (Input levels compatibility) with
the latch-up limit of microcontroller I/Os.
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4
Multisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(MultiSense) delivering the following signals:
•
•
•
Current monitor: current mirror of channel output current
VCC monitor: voltage propotional to VCC
TCASE: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in MultiSense multiplexer
addressing Table.
30/47
DocID027396 Rev 2
VND7050AJ
Application information
Figure 37: MultiSense and diagnostic – block diagram
DocID027396 Rev 2
31/47
Application information
4.4.1
VND7050AJ
Principle of Multisense signal generation
Figure 38: MultiSense block diagram
Current monitor
When current mode is selected in the MultiSense, this output is capable to provide:
•
•
Current mirror proportional to the load current in normal operation, delivering current
proportional to the load according to known ratio named K
Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can
be done using simple equations
Current provided by MultiSense output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K
Where:
•
•
32/47
VSENSE is voltage measurable on RSENSE resistor
ISENSE is current provided from MultiSense pin in current output mode
DocID027396 Rev 2
VND7050AJ
Application information
•
•
IOUT is current flowing through output
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its
spread includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin
which is switched to a “current limited” voltage source, VSENSEH.
In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH.
The typical behavior in case of overload or hard short circuit is shown in Waveforms
section.
Figure 39: Analogue HSD – open-load detection in off-state
DocID027396 Rev 2
33/47
Application information
VND7050AJ
Figure 40: Open-load / short to VCC condition
Table 13: MultiSense pin levels in off-state
Condition
Output
VOUT > VOL
Open-load
VOUT < VOL
4.4.2
Short to VCC
VOUT > VOL
Nominal
VOUT < VOL
MultiSense
SEn
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
TCASE and VCC monitor
In this case, MultiSense output operates in voltage mode and output level is referred to
device GND. Care must be taken in case a GND network protection is used, because a
voltage shift is generated between the device GND and the microcontroller input GND
reference.
Figure 41: "GND voltage shift" shows the link between VMEASURED and the real VSENSE
signal.
34/47
DocID027396 Rev 2
VND7050AJ
Application information
Figure 41: GND voltage shift
VCC monitor
Battery monitoring channel provides VSENSE = VCC / 8.
Case temperature monitor
Case temperature monitor is capable of providing information about the actual device
temperature. Since a diode is used for temperature sensing, the following equation
describes the link between temperature and output VSENSE level:
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C)).
4.4.3
Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable that VPU is switched off during the module standby mode in order to avoid
the overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following
equation:
Equation
RPU <
VPU - 4
IL(off2)min @4V
DocID027396 Rev 2
35/47
Maximum demagnetization energy (VCC = 16 V)
5
VND7050AJ
Maximum demagnetization energy (VCC = 16 V)
Figure 42: Maximum turn off current versus inductance
VND7050AJ - Maximum turn off current versus inductance
100
I (A)
10
1
VND7050AJ - Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
0.1
0.1
1
10
L (mH)
100
1000
VND7050AJ - Maximum turn off Energy versus Tdemag
1000
VND7050AJ - Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
E [mJ]
100
10
1
0.01
0.1
1
Tdemag [ms]
10
100
GAPGCFT01245
Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of
every pulse must not exceed the temperature specified above for curves A and B.
36/47
DocID027396 Rev 2
VND7050AJ
Package and PCB thermal data
6
Package and PCB thermal data
6.1
PowerSSO-16 thermal data
Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 14: PCB properties
Dimension
Value
Board finish thickness
1.6 mm +/- 10%
Board dimension
77 mm x 86 mm
Board Material
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal vias separation
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
Copper thickness on vias
0.025 mm
Footprint dimension (top layer)
2.2 mm x 3.9 mm
Heatsink copper area dimension (bottom layer)
DocID027396 Rev 2
Footprint, 2 cm2 or 8 cm2
37/47
Package and PCB thermal data
VND7050AJ
Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on)
Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
Equation: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
38/47
DocID027396 Rev 2
VND7050AJ
Package and PCB thermal data
Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16
The fitting model is a simplified thermal tool and is valid for transient evolutions
where the embedded protections (power limitation or thermal cycling during
thermal shutdown) are not triggered.
Table 15: Thermal parameters
Area/island
(cm2)
Footprint
2
8
4L
R1 = R7 (°C/W)
1.8
R2 = R8 (°C/W)
3.2
R3 (°C/W)
8
8
8
6
R4 (°C/W)
14
6
6
4
R5 (°C/W)
30
20
10
3
R6 (°C/W)
26
20
18
7
C1 = C7 (W.s/°C)
0.00035
C2 = C8 (W.s/°C)
0.005
C3 (W.s/°C)
0.05
C4 (W.s/°C)
0.2
0.3
0.3
0.4
C5 (W.s/°C)
0.4
1
1
4
C6 (W.s/°C)
3
5
7
18
DocID027396 Rev 2
39/47
Package information
7
VND7050AJ
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
PowerSSO-16 package information
Figure 48: PowerSSO-16 package outline
Table 16: PowerSSO-16 mechanical data
Dimensions
Ref.
Millimeters
Min.
Θ
0°
Θ1
0°
Θ2
5°
Θ3
5°
A
40/47
Typ.
Max.
8°
15°
15°
1.70
DocID027396 Rev 2
VND7050AJ
Package information
Dimensions
Ref.
Millimeters
Min.
A1
Typ.
Max.
0.00
0.10
A2
1.10
1.60
b
0.20
0.30
b1
0.20
c
0.19
c1
0.19
D
D1
0.25
0.28
0.25
0.20
0.23
4.9 BSC
2.90
3.50
e
0.50 BSC
E
6.00 BSC
E1
3.90 BSC
E2
2.20
2.80
h
0.25
0.50
L
0.40
0.60
L1
1.00 REF
N
16
R
0.07
R1
0.07
S
0.20
0.85
Tolerance of form and position
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.08
eee
0.10
fff
0.10
ggg
0.15
DocID027396 Rev 2
41/47
Package information
7.2
VND7050AJ
PowerSSO-16 packing information
Figure 49: PowerSSO-16 reel 13"
Table 17: Reel dimensions
Description
Value(1)
Base quantity
2500
Bulk quantity
2500
A (max)
330
B (min)
1.5
C (+0.5, -0.2)
13
D (min)
20.2
N
100
W1 (+2 /-0)
12.4
W2 (max)
18.4
Notes:
(1)All
42/47
dimensions are in mm.
DocID027396 Rev 2
VND7050AJ
Package information
Figure 50: PowerSSO-16 carrier tape
P0
4.0 ±0.1
X
1.55 ±0.05
0.30 ±0.05
P2
2.0 ±0.1
1.75 ±0.1
B0
W
F
1.6±0.1
R0.5
Typical
K1
Y
Y
X
K0
P1
A0
REF 4.18
REF 0.6
SECTION X - X
REF 0.5
SECTIONY - Y
GAPG2204151242CFT
Table 18: PowerSSO-16 carrier tape dimensions
Description
Value(1)
A0
6.50 ± 0.1
B0
5.25 ± 0.1
K0
2.10 ± 0.1
K1
1.80 ± 0.1
F
5.50 ± 0.1
P1
8.00 ± 0.1
W
12.00 ± 0.3
Notes:
(1)All
dimensions are in mm.
Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape
DocID027396 Rev 2
43/47
Package information
7.3
VND7050AJ
PowerSSO-16 marking information
Figure 52: PowerSSO-16 marking information
Engineering Samples: these samples can be clearly identified by a dedicated
special symbol in the marking of each unit. These samples are intended to be
used for electrical compatibility evaluation only; usage for any other purpose may
be agreed only upon written authorization by ST. ST is not liable for any customer
usage in production and/or in reliability qualification trials.
Commercial Samples: fully qualified parts from ST standard production with no
usage restrictions.
44/47
DocID027396 Rev 2
VND7050AJ
8
Order codes
Order codes
Table 19: Device summary
Order codes
Package
Tape and reel
PowerSSO-16
VND7050AJTR
DocID027396 Rev 2
45/47
Revision history
9
VND7050AJ
Revision history
Table 20: Document revision history
Date
Revision
19-May-2015
1
Changes
Initial release.
Updated the following:
02-Oct-2016
46/47
2
•
•
Features list on the cover page
Figure 52: "PowerSSO-16 marking information"
DocID027396 Rev 2
VND7050AJ
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
DocID027396 Rev 2
47/47
">