STMicroelectronics VN9008AJ Datasheet
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Hirdetés
VN9008AJ
Datasheet
Single channel high-side driver with Current Sense analog feedback for automotive applications
PowerSSO-16
Product status link
VN9008AJ
Product summary
Order code VN9008AJTR
Package
Packing
PowerSSO-16
Tape and reel
Features
Max transient supply voltage
Operating voltage range
Typ. on-state resistance (per Ch)
Current limitation (typ)
Standby current (max)
V
CC
V
CC
R
ON
I
LIMH
I
STBY
36 V
4 to 28 V
8 mΩ
81.6 A
0.5 µA
• AEC-Q100 qualified
• Extreme low voltage operation for deep cold cranking applications (compliant with LV124, revision 2013)
• General
– Single channel smart high-side driver with current sense analog feedback
– Very low standby current
– Compatible with 3 V and 5 V CMOS outputs
• Current sense diagnostic functions
– Multiplexed analog feedback of load current with high precision proportional current mirror
– Overload and short to ground (power limitation) indication
– Thermal shutdown indication
– OFF-state open-load detection (with external pull-up)
– Output short to V
CC
detection
– Sense enable/disable
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin
– Loss of ground and loss of V
CC
– Reverse battery through self turn-on
– Electrostatic discharge protection
Applications
• Smart power distribution, automotive headlamps, heating systems, DC motors, relay replacement and high power resistive and inductive actuators
• Protected supply for ADAS systems: radars and sensors
DS12676 - Rev 3 - September 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
VN9008AJ
Description
The device is a single channel high-side driver manufactured using ST proprietary VIPower M0-9 technology and housed in a PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3
V and 5 V CMOS-compatible interface, providing protection and diagnostics.
The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off.
A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to V
CC
and OFF-state open-load.
DS12676 - Rev 3 page 2/38
VN9008AJ
Block diagram and pin description
1 Block diagram and pin description
Figure 1. Block diagram
VCC
IN0
SEn
FaultRST
CS
GND
VCC – GND clamp
Internal supply
Undervoltage shut-down
Logic
Channel 0 control & diagnostic
Gate driver
VCC – OUT
Clamp
Power limitation
Overtemperature
Open-Load in OFF
Reverse battery
Current limitation
Current
Sense
OUT0
Name
V
CC
OUTPUT
0
GND
INPUT
0
CS
SEn
FaultRST
Table 1. Pin functions
Function
Battery connection.
Power outputs.
Ground connection. Must be reverse battery protected by an external diode / resistor network.
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. It controls output switch state.
Multiplexed analog sense output pin; it delivers a current proportional to the selected load current.
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the CS diagnostic pin.
Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low, sets the outputs in auto-restart mode.
DS12676 - Rev 3 page 3/38
VN9008AJ
Block diagram and pin description
INPUT0
FaultRST
SEn
GND
N.C.
N.C.
CS
N.C.
Figure 2. Configuration diagram (top view)
PowerSSO-16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT0
N.C.
N.C.
N.C.
N.C.
Connection / pin
Floating
To ground
1. X: do not care.
Table 2. Suggested connections for unused and not connected pins
CS
Not allowed
Through 1 kΩ resistor
NC Output
X X
X Not allowed
Input
X
Through 15 kΩ resistor
SEn, FaultRST
X
Through 15 kΩ resistor
DS12676 - Rev 3 page 4/38
2
2.1
Electrical specification
V
FR
V
SEn
Figure 3. Current and voltage conventions
I
S
V
CC
I
FR
V
Fn
I
OUT
FaultRST
I
SEn
OUTPUT
0
SE n
I
SENSE
V
OUT
CS
V
SENSE
V
CC
I
IN
INPUT
0
V
IN
I
GND
Note: V
Fn
= V
OUTn
- V
CC
during reverse battery condition.
VN9008AJ
Electrical specification
Absolute maximum ratings
Stressing the device above the rating listed in Table 3. Absolute maximum ratings
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in the table below for extended periods may affect the device reliability.
Symbol
V
CC
-V
CC
V
CCJS
-I
GND
I
OUT
-I
OUT
I
IN
I
SEn
I
FR
I
SENSE
E
MAX
V
ESD
V
ESD
T j
T stg
Table 3. Absolute maximum ratings
Parameter
DC supply voltage
Reverse DC supply voltage
Maximum jump start voltage for single pulse short circuit protection
DC reverse ground pin current
OUTPUT
0
DC output current
Reverse DC output current
INPUT
0
DC input current
SEn DC input current
FaultRST DC input current
CS pin DC output current (V
GND
= V
CC
and V
SENSE
< 0 V)
CS pin DC output current in reverse (V
CC
< 0 V)
Maximum switching energy (single pulse) (T jstart
= 150 °C)
•
•
•
•
•
Electrostatic discharge (JEDEC 22A-114F)
INPUT
CS
0
SEn, FaultRST
OUTPUT
0
V
CC
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
Value
36
16
28
200
Internally limited
15
-1 to 10
-1 to 3
-1 to 10
10
-20
32
2000
2000
2000
4000
4000
750
-40 to 150
-55 to 150
Unit
V
V mA
A mA mA
°C mJ
V
V
V
V
V
V
DS12676 - Rev 3 page 5/38
2.2
2.3
VN9008AJ
Thermal data
Thermal data
Table 4. Thermal data
Symbol
R thj-board
R thj-amb
R thj-amb
Parameter
Thermal resistance junction-board (JEDEC JESD 51-8)
Thermal resistance junction-ambient (JEDEC JESD 51-2)
Thermal resistance junction-ambient (JEDEC JESD 51-2)
1. Device mounted on four-layers 2s2p PCB
2. Device mounted on two-layers 2s0p PCB with 2 cm 2 heatsink copper trace
Main electrical characteristics
7 V < V
CC
< 28 V; -40°C < T j
< 150°C, unless otherwise specified.
All typical values refer to V
CC
= 13 V; T j
= 25°C, unless otherwise specified.
Typ. value
6.8
52.5
19.9
Unit
°C/W
Symbol
V
CC
V
USD
V
USDReset
V
USDhyst
R
ON
R
ON_ReV
V clamp
I
STBY t
D_STBY
I
S(ON)
Parameter
Operating supply voltage
Undervoltage shutdown
Undervoltage shutdown reset
Undervoltage shutdown hysteresis
Table 5. Power section
Test conditions
On-state resistance
I
OUT
= 4.6 A; T j
= 25°C
I
OUT
= 4.6 A; T j
= 150°C
I
OUT
= 4.6 A; V
CC
= 4 V; T j
= 25°C
I
OUT
= 4 A; V
CC
= 2.7 V;
V
CC
decreasing
R
DSON
in reverse battery condition
V
CC
= -13 V; I
OUT
= -4.6 A; T j
= 25°C
Clamp voltage
Supply current in standby at
V
CC
Standby mode blanking time
Supply current
I
S
= 20 mA; 25°C < T j
< 150°C
I
S
= 20 mA; T j
= -40°C
V
CC
= 13 V;
V
IN
= V
OUT
= V
FR
= V
SEn
= 0 V;
T j
= 25°C
V
CC
= 13 V;
V
IN
= V
OUT
= V
FR
= V
SEn
= 0 V;
T j
V
CC
= 13 V;
V
IN
= V
OUT
= V
FR
= V
SEn
= 0 V;
T j
= 125°C
V
CC
= 13 V;
V
IN
V
= V
OUT
SEn
= V
FR
= 5 V to 0 V
= 0 V;
V
CC
= 13 V; V
SEn
V
IN0
= 5 V; I
OUT0
= 0 V = V
= 0 A
FR
= 0 V;
Min.
4
36
36
60
Typ.
13
2.1
0.15
8
8
38
260
3.5
Max.
28
2.7
4.5
Unit
V
V
V
V
17.6
13.6
48
45
0.5
0.5
3
550
4.5
mΩ
V
V
µA
µs mA
DS12676 - Rev 3 page 6/38
DS12676 - Rev 3
VN9008AJ
Main electrical characteristics
I
Symbol
GND(ON)
Parameter
Control stage current consumption in ON-state. All channels active.
V
CC
V
FR
Test conditions
= 13 V; V
SEn
= V
IN0
= 5 V;
= 5 V; I
OUT0
= 4.6 A
I
L(off)
Off-state output current at
V
CC
= 13 V
V
IN
= V
OUT
= 0 V; V
CC
= 13 V;
T j
= 25°C
V
IN
= V
OUT
= 0 V; V
CC
= 13 V;
T j
= 125°C
I
OUT
= -4.6 A; T j
= 150°C V
F
Output - V
CC
diode voltage
1. PowerMOS leakage included.
2. Parameter specified by design; not subject to production test.
Min.
Typ.
Max.
6
Unit mA
0
0
0.01
0.5
3
0.7
µA
V
Table 6. Switching
(dV
(dV t
Symbol t t d(on) d(off)
OUT
OUT
W
W
SKEW
/dt) on
/dt)
ON
OFF off
V
CC
= 13 V; -40°C < T j
< 150°C, unless otherwise specified
Parameter Test conditions Min.
Typ.
Max.
Unit
Turn-on delay time at
T j
= 25 °C
Turn-off delay time at
T j
= 25 °C
Turn-on voltage slope at
T j
= 25 °C
Turn-off voltage slope at
T j
= 25 °C
R
R
L
L
= 2.8 Ω
= 2.8 Ω
10
10
0.3
0.3
28
20
0.7
0.8
120
100
0.9
1.1
µs
V/µs
Switching energy losses at turn-on (t won
)
Switching energy losses at turn-off (t woff
)
Differential Pulse skew (t
PHL
t
PLH
)
R
R
R
L
L
L
= 2.8 Ω
= 2.8 Ω
= 2.8 Ω
—
—
-60
0.28
0.25
-10
0.7
40
mJ mJ
µs
1. See
Figure 4. Switching time and pulse skew .
2. Parameter guaranteed by design and characterization; not subject to production test.
Symbol Parameter
Table 7. Logic inputs
7 V < V
CC
< 28 V; -40°C < T j
< 150°C
Test conditions
INPUT characteristics
Min.
Typ.
Max.
Unit
V
IL
I
IL
V
IH
I
IH
V
I(hyst)
V
ICL
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
Input clamp voltage
V
IN
= 0.9 V
V
IN
= 2.1 V
I
IN
= 1 mA
I
IN
= -1 mA
FaultRST characteristics
1
2.1
0.2
6
-0.7
0.9
10
8.5
V
µA
V
µA
V
V
V
FRL
Input low level voltage 0.9
V page 7/38
DS12676 - Rev 3
VN9008AJ
Main electrical characteristics
Symbol
I
FRL
V
FRH
I
FRH
V
FR(hyst)
V
FRCL
V
SEnL
I
SEnL
V
SEnH
I
SEnH
V
SEn(hyst)
V
SEnCL
Parameter
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
7 V < V
CC
< 28 V; -40°C < T j
< 150°C
Test conditions
V
IN
= 0.9 V
V
IN
= 2.1 V
Input clamp voltage
I
IN
= 1 mA
I
IN
= -1 mA
SEn characteristics (7 V < V
CC
< 18 V)
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
V
V
IN
IN
= 0.9 V
= 2.1 V
Input clamp voltage
I
IN
= 1 mA
I
IN
= -1 mA
Table 8. Protections t t
I
Symbol
I
LIMH
LIMH2
I
LIMH
at 22 V
T
T
T
HYST
ΔT
TSD
RS
J_SD
LATCH_RST
D_Restart
V
DEMAG
Parameter
DC short-circuit current
7 V < V
CC
< 18 V; -40°C < T j
< 150°C
Test conditions
V
CC
= 16 V; T
J
= -40°C
V
CC
= 16 V; T
J
= +150°C
V
CC
= 19 V; T
J
= -40°C
V
CC
= 19 V; T
J
= +150°C
V
CC
= 22 V; T
J
= +25°C
Shutdown temperature
Shutdown temperature
(V
CC
decreasing)
Thermal reset of fault diagnostic indication
Thermal hysteresis
(T
TSD
- T
RS
)
V
V
CC
FR
= 2.7 V
= 0 V; V
SEn
= 5 V
Dynamic temperature
Fault reset time for output
V
CC
= 19 V
V
CC
= 16 V
V
FR
= 5 V to 0 V;
V
SEn
= 5 V
V
IN0
= 5 V
Latch-OFF delay time before automatic restart
Turn-off output voltage clamp
I
OUT
= 1 A; L = 6 mH; T j
= -40°C
I
OUT
= 1 A; L = 6 mH; T
150°C j
= 25°C to
Min.
1
2.1
0.2
6
Typ.
Max.
-0.7
10
8.5
Unit
µA
V
µA
V
V
1
2.1
0.2
9
150
140
135
Min.
-15%
-15%
-15%
-15%
3
-0.7
7
55
80
Typ.
88
68
67
52
25
175
10
0.9
10
12
Max.
Unit
15%
15%
15%
15%
A
210
20
V
µA
V
µA
V
V
°C
K
µs
50 75 ms
V
CC
- 36 V
V
CC
- 36 V
CC
- 38 V
CC
- 45 V page 8/38
DS12676 - Rev 3
VN9008AJ
Main electrical characteristics
1. I
LIMH
, guaranteed between 7 V and 16 V, -40°C < T
J
< 150°C
2. I
LIMH2
, guaranteed between 16 V and 19 V, -40°C < T
J
< 150°C
3. Parameter guaranteed by design and characterization; not subject to production test.
Symbol
V
SENSE_CL
K
LED dK
LED
/K
LED
K
0 dK
0
/K
0
K
1 dK
1
/K
1
K
2 dK
2
/K
2
K
3 dK
3
/K
3
I
SENSE0
V
OUT_MSD
V
SENSE_SAT
I
SENSE_SAT
I
OUT_SAT
Table 9. Current Sense
7 V < V
CC
< 18 V; -40°C < T j
< 150°C
Parameter Test conditions Min.
Typ.
Max. Unit
CS clamp voltage
V
SEn
= 0 V; I
SENSE
= 1 mA
V
SEn
= 0 V; I
SENSE
= -1 mA
CurrentSense characteristics
-9 -8
7
-7
I
I
I
I
I
OUT
/I
SENSE
Current sense ratio drift
OUT
Current sense ratio drift
OUT
/I
SENSE
Current sense ratio drift
OUT
Current sense ratio drift
OUT
/I
/I
/I
SENSE
SENSE
SENSE
Current sense ratio drift
I
V
OUT
= 100 mA; V
SEn
= 5 V
SENSE
= 0.5 V;
I
V
OUT
= 100 mA; V
SEn
= 5 V
SENSE
= 0.5 V;
I
V
OUT
= 0.5 A; V
SEn
= 5 V
SENSE
= 0.5 V;
I
V
OUT
= 0.5 A; V
SEn
= 5 V
SENSE
= 0.5 V;
I
V
OUT
= 0.9 A; V
SEn
= 5 V
SENSE
= 3.5 V;
I
V
OUT
= 0.9 A; V
SEn
= 5 V
SENSE
= 3.5 V;
I
V
OUT
= 4.6 A; V
SEn
= 5 V
SENSE
= 3.5 V;
I
V
OUT
= 4.6 A; V
SEn
= 5 V
SENSE
= 3.5 V;
I
V
OUT
= 13.8 A; V
SEn
= 5 V
SENSE
= 3.5 V;
I
V
OUT
= 13.8 A; V
SEn
= 5 V
SENSE
= 3.5 V;
CS disabled: V
SEn
= 0 V
CS disabled:
-1 V < V
SENSE
CurrentSense leakage current
CS enabled: V
SEn
= 5 V; Channel ON;
V
IN0
= 5 V; I
OUT0
= 0 A;
CS enabled: V
SEn
= 5 V; Channel
OFF; V
IN0
= 0 V; I
OUT0
= 0 A
Output voltage for CS shutdown
Current sense saturation voltage
CS saturation current
Output saturation current
V
SEn
= 5 V; R
SENSE
= 2.7 kΩ;
E.g. Ch
0
: V
IN0
= 5 V; I
OUT0
= 4.6 A
V
CC
= 7 V; R
SENSE
= 10 kΩ;
I
V
SEn
OUT0
= 5 V; V
IN0
= 5 V;
= 13.8 A; T j
= -40°C
V
CC
V
IN0
= 7 V; V
SENSE
= 5 V; V
SEn
= 3.5 V;
= 5 V; T j
= 150°C
V
CC
V
IN0
= 7 V; V
SENSE
= 5 V; V
SEn
= 3.5 V;
= 5 V; T j
= 150°C
-35% 9800 +35%
-25
4.8
2
30
5
25
-25% 9800 25%
-20
-15% 9800 15%
-10
-7% 9800
-7
-5% 9800
-5
0
-1
0
0
20
10
7%
7
5%
5
0.5
1
10
1
V
%
%
%
%
%
µA
V
V mA
A page 9/38
DS12676 - Rev 3
VN9008AJ
Main electrical characteristics t t
Symbol t
I
V
OL
L(off2)
DSTKON
D_OL_V
D_VOL
7 V < V
CC
< 18 V; -40°C < T j
< 150°C
Parameter Test conditions
OFF-state diagnostic
OFF-state open-load voltage detection threshold
OFF-state output sink current
V
SEn
= 5 V; Ch OFF;
V
IN0
= 0 V;
V
IN
= 0 V; V
OUT
= V
OL
; T j
= -40°C to
125°C
OFF-state diagnostic delay time from falling edge of
INPUT
)
Settling time for valid OFFstate open load diagnostic indication from rising edge of
SEn
I
V
V
V
V
SEn
IN0
OUT0
IN
SEn
= 5 V; Ch ON to OFF transition;
= 5 V to 0 V;
= 0 A; V
= 0 V; V
FR
OUT
= 4 V
= 0 V; V
= 0 V to 5 V
OUT0
= 4 V;
OFF-state diagnostic delay time from rising edge of V
OUT
V
SEn
= 5 V; Ch OFF;
V
IN0
= 0 V; V
OUT
= 0 V to 4 V
Fault diagnostic feedback (see
Min.
2
-150
150
Typ.
3
-40
260
5
Max. Unit
4
-5
400
60
30
V
µA
µs
µs
µs t t t
V
SENSEH
MultiSense output voltage in fault condition
13 V < V
CC
< 18 V; Ch0 in open load;
R
SENSE
= 0.7 kΩ; V
IN0
= 0 V;
V
SEn
= 5 V; I
OUT0
= 0 A; V
OUT0
= 4 V
V
CC
= 7 V; Ch0 in open load;
R
SENSE
= 0.7 kΩ; V
IN0
= 0 V;
V
SEn
= 5 V; I
OUT0
= 0 A; V
OUT0
= 4 V
5
4.3
7.5
I
SENSEH
CurrentSense output current in fault condition
13 V < V
CC
< 18 V; V
SENSE
= 5 V;
Ch0 in open load;
V
IN0
= 0 V; V
SEn
= 5 V;
I
OUT0
= 0 A; V
OUT0
= 4 V
V
CC
= 7 V; V
SENSE
= 5 V;
Ch0 in open load;
V
IN0
= 0 V; V
SEn
= 5 V;
I
OUT0
= 0 A; V
OUT0
= 4 V
7
4.4
8.6
CurrentSense timings (current sense mode - see
Figure 5. Current sense timings (current sense mode) )
12
DSENSE1H
DSENSE1L
DSENSE2H
Current sense settling time from rising edge of SEn
Current sense disable delay time from falling edge of SEn
Current sense settling time from rising edge of INPUT
V
IN
= 5 V; V
SEn
= 0 V to 5 V;
R
SENSE
= 1 kΩ; R
L
= 2.8 Ω
V
IN
= 5 V; V
SEn
= 5 V to 0 V;
R
SENSE
= 1 kΩ; R
L
= 2.8 Ω
V
IN
= 0 V to 5 V; V
SEn
R
SENSE
= 1 kΩ; R
L
= 5 V;
= 2.8 Ω
5
100
60
20
200
V mA
µs
µs
µs
Δt t
DSENSE2H
DSENSE2L
Current sense settling time from rising edge of I
OUT
(dynamic response to a step change of I
OUT
)
Current sense turn-off delay time from falling edge of
INPUT
I
V
V
IN
SENSE
R
L
IN
= 5 V; V
= 2.8 Ω
R
SENSE
SEn
= 5 V; R
SENSE
= 90 % of I
= 5 V to 0 V; V
= 1 kΩ; R
L
SENSEMAX
SEn
= 5 V;
= 2.8 Ω
;
= 1 kΩ;
70
100
250
µs
µs page 10/38
DS12676 - Rev 3
VN9008AJ
Main electrical characteristics t
Symbol
DSENSE3H
7 V < V
CC
< 18 V; -40°C < T j
< 150°C
Parameter Test conditions
Current sense latch-OFF filtering time
1. Parameter specified by design; not subject to production test.
2. All values refer to V
CC
= 13 V; T j
= 25°C, unless otherwise specified.
3. Transition delay is measured up to +/- 10% of final conditions.
Figure 4. Switching time and pulse skew twon
VOUT
Vcc twoff dV
OUT
/dt
ON
80% Vcc
OFF dV
OUT
/dt
20% Vcc
Min.
Typ.
Max. Unit
1.4
2.0
2.6
ms t
INPUT td(on) tpLH td(off) tpHL t page 11/38
Figure 5. Current sense timings (current sense mode)
VN9008AJ
Main electrical characteristics
IN
SEn
High
Low
I
OUT
CURRENT SENSE t
DSENSE2H t
DSENSE1L
Figure 6. T
DSTKON t
DSENSE1H t
DSENSE2L
GAPG1003141014CFT
V
INPUT
V
OUT
> V
OL
V
OUT
MultiSense
DS12676 - Rev 3
Standby
Mode
Normal
Overload t
DSTKON
GAPG2609141140CFT
Table 10. Truth table
T j
< 150 °C
Conditions
All logic inputs low
Nominal load connected;
Overload or short to GND causing:
T j
> T
TSD
or
ΔT j
> ΔT j _SD
IN
X
FR SEn OUT
X
L
L
H
H
L
H
H
L
X
L
H
X
L
H
L
L
L
H
H
L
H
L
CS Comments
Hi-Z
Low quiescent current consumption
See
See
Outputs configured for autorestart
See
Outputs configured for latch-
See
See
Output cycles with temperature hysteresis
See
Output latches-off
page 12/38
2.4
VN9008AJ
Waveforms
Mode
Undervoltage V
CC
< V
USD
Conditions
(falling)
Short to V
CC
OFF-state diagnostics
Open-load
Negative output voltage
Inductive loads turn-off
1. Refer to Table 11. Current Sense multiplexer addressing
IN
X
FR SEn OUT
X
X X X
L
L
L
L
X
X
H
H
CS Comments
Hi-Z
Hi-Z
Re-start when V
CC
> V
USD
+
V
USDhyst
(rising)
See
See
External pull-up
L X
< 0 V See
SEn
L
H
MUX channel
N.A.
Channel 0 diagnostic
Table 11. Current Sense multiplexer addressing
Normal mode
I
SENSE
= 1/K * I
OUT0
MultiSense output
Overload OFF-state diag.
Hi-Z
V
SENSE
= V
SENSEH
V
SENSE
= V
SENSEH
Negative output
Hi-Z
Waveforms
INPUT
Figure 7. Latch-off mode - Intermittent short circuit
Normal condition Short circuit condition
Unlatch command is t stored, but no restart until
D_Restart is elapsed.
FaultRST
I
LIMH
I
OUT
I
NOM
CS
OTDIFF
(Internal signal)
OT
(Internal signal)
OT_Fault
(Internal signal)
OT_Fault_Diag
(Internal signal)
(*) Not in scale t
D_Restart t > t
DSENSE3H
DS12676 - Rev 3 page 13/38
DS12676 - Rev 3
I
OUT
CS
OTDIFF
(Internal signal)
OT
(Internal signal)
OT_Fault
(Internal signal)
OT_Fault_Diag
(Internal signal)
(*) Not in scale
Figure 8. Auto-restart mode - Intermittent short circuit
Short circuit condition Normal condition
INPUT
FaultRST
I
LIMH
Power Limitation
I
NOM t
D_Restart t > t
DSENSE3H
INPUT
Figure 9. Auto-restart mode - Permanent short circuit
FaultRST
I
OUT
CS
OTDIFF
(Internal signal)
OT
(Internal signal)
OT_Fault
(Internal signal)
OT_Fault_Diag
(Internal signal)
(*) Not in scale
I
LIMH
Power Limitation t
D_Restart
I
LIMH
Power Limitation t < t
DSENSE3H
VN9008AJ
Waveforms page 14/38
DS12676 - Rev 3
Figure 10. Standby mode activation
VN9008AJ
Waveforms
Figure 11. Standby state diagram
Normal Operation t > t
D_STBY
INx = Low
AND
FaultRST = Low
AND
SEn = Low
Stand-by Mode
INx = High
OR
FaultRST = High
OR
SEn = High
GADG2702181047RI page 15/38
3
3.1
3.2
3.3
3.4
VN9008AJ
Protections
Protections
Power limitation
The basic working principle of this protection consists of an indirect measurement of the junction temperature swing ΔT
J
through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as ΔT
J
exceeds the safety level of ΔT
J_SD
. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermomechanical fatigue.
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the
FaultRST pin, the device switches on again as soon as its junction temperature drops to T
R
(FaultRST = Low) or remains off (FaultRST = High).
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, I
LIMH
, by operating the output power MOSFET in the active region.
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, V
DEMAG
, allowing the inductor energy to be dissipated without damaging the device.
DS12676 - Rev 3 page 16/38
4
4.1
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Application information
Application information
Figure 12. Application diagram
+5V
V
DD
OUT
V
CC
OUT
OUT
OUT
ADC in
OUT
Rprot_SEn
SEn
INPUT
Rprot
Rprot
Rprot
FaultRST
SEL
Rprot
CS
Cext
Rsense
GND GND
Current mirror
Logic
R
GND
GND
GND
GND
GND protection network against reverse battery
Figure 13. Simplified internal structure
D
GND
OUTPUT
GND GND
Dld
FaultRST
CS
DId
DS12676 - Rev 3 page 17/38
4.1.1
4.2
VN9008AJ
Immunity against transient electrical disturbances
Diode (DGND) in the ground line
A resistor (typ. R
GND
= 4.7 kΩ) should be inserted in parallel to D
GND
if the device drives an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network.
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the V
CC
pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010.
The related function performance status classification is shown in
Table 12. ISO 7637-2 - electrical transient conduction along supply line
.
Test pulses are applied directly to DUT (device under test) both in ON and OFF-state and in accordance to ISO
7637-2:2011(E), chapter 4.
The DUT is intended as the current device only, with external components as shown in
Figure 14. M0-9 application schematic .
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: “The function does not perform as designed during the test but returns automatically to normal operation after the test”.
Table 12. ISO 7637-2 - electrical transient conduction along supply line
Test Pulse
2011(E)
Test pulse severity level with Status II functional performance status
1
2a
3a
3b
Level
III
III
IV
IV
IV
U
S
-112 V
+55 V
-220 V
+150 V
-7 V
Load dump according to ISO 16750-2:2010
Test B
35 V
Minimum number of pulses or test time
500 pulses
500 pulses
1h
1h
1 pulse
5 pulse
Burst cycle / pulse repetition time min
0.5 s
0.2 s
90 ms
90 ms
1 min max
5 s
100 ms
100 ms
1. U
S
is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
2. Test pulse from ISO 7637-2:2004(E).
3. With 35 V external suppressor referred to ground (-40°C < T j
< 150 °C).
Pulse duration and pulse generator internal impedance
2 ms, 10 Ω
50 µs, 2 Ω
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
DS12676 - Rev 3 page 18/38
Note:
VN9008AJ
Immunity against transient electrical disturbances
Figure 14. M0-9 application schematic
+5V
V
DD
OUT
V
CC
OUT
OUT
OUT
ADC in
OUT
Rprot_SEn
SEn
INPUT
Rprot
Rprot
Rprot
FaultRST
SEL
Rprot
CS
Cext
Rsense
GND GND
Current mirror
Logic
OUTPUT
R
GND
GND
D
GND
Rload_nom
GND GND
GND
GND
In case of multiple channels, each OUTPUT must be connected to the resistive nominal load.
1μF
DS12676 - Rev 3 page 19/38
4.3
4.4
VN9008AJ
MCU I/Os protection
MCU I/Os protection
If a ground protection network is used and negative transients are present on the V
CC be pulled negative. ST suggests to insert a resistor (R prot
line, the control pins will
) in line both to prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.
Equation
Vccpeak
Ilatcℎup ≤ Rprot ≤
Calculation example:
For V
CCpeak
= -150 V; I latchup
≥ 20 mA; V
OHµC
≥ 4.5 V
7.5 kΩ ≤ R prot
≤ 140 kΩ.
Recommended values: R prot
= 15 kΩ
VOHμC − VIH − VGND
IIHmax
(1)
CS - analog current sense
Diagnostic information on device and load status are provided by an analog output pin (CS) delivering the following signals:
• Current monitor: current mirror of channel output current
Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and
SEn pins, according to the address map in Table 11. Current Sense multiplexer addressing .
Figure 15. Current Sense and diagnostic – block diagram
VCC
VCC – GND
Clamp
Internal Supply
Undervoltage shut-down
FaultRST
R
PROT
To µC ADC
INPUT
SEL
1
SEL
0
SE n
I
SENSE
CS
R
SENSE
GND
MUX
Fault
Diagnostic
CURRENT
MONITOR
Fault
V
SENSEH
Control & Diagnostic
Gate Driver
VCC – OUT
Clamp
Current
Limitation
Power Limitation
Overtemperature
Short to VCC
Open-Load in OFF K factor
Current
Sense
T
I
OUT
OUT
DS12676 - Rev 3 page 20/38
VN9008AJ
CS - analog current sense
4.4.1
Principle of current sense signal generation
Figure 16. Current Sense block diagram
Vcc
Sense MOS
INPUT
Main MOS
Current sense
Current sense Switch Block
OUT
Fault
To uC ADC
CS
R
PROT
R
SENSE
Current sense
The output is capable of providing:
•
•
Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to a known ratio named K
Diagnostics flag in fault conditions delivering fixed voltage V
SENSEH
The current delivered by the current sense circuit, I
SENSE
, can be easily converted to a voltage V
SENSE
by using an external sense resistor, R
SENSE
, allowing continuous load monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While the device is operating in normal conditions (no fault intervention), V
SENSE
calculation can be done using simple equations.
Current provided by MultiSense output: I
SENSE
= I
OUT
/K
Voltage on R
SENSE
: V
SENSE
= R
SENSE
· I
SENSE
= R
SENSE
· I
OUT
/K
Where:
•
•
•
•
V
SENSE
is the voltage measurable on the R
SENSE
resistor
I
SENSE
is the current provided from CurrentSense pin in current output mode
I
OUT
is the current flowing through output
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between I
OUT
and I
SENSE
.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the CurrentSense pin, which is switched to a
“current limited” voltage source, V
SENSEH
.
In any case, the current sourced by the CurrentSense in this condition is limited to I
SENSEH
.
The typical behavior in case of overload or hard short-circuit is shown in Waveforms.
DS12676 - Rev 3 page 21/38
VN9008AJ
CS - analog current sense
+5V
Microcontroller V
DD
GND
100nF
OUT
GND
GND
2.2 k
OUT
15k
OUT
15k
OUT
15k
ADC in
15k
OUT
GND
15k
CEXT
Figure 17. Analog HSD – open-load detection in off-state
Vbat
100nF/50V
GND
V
CC
SEn
INPUT
FaultRST
SEL
CS
GND
Rsense
Cu rrent mirror
Logic
R
GND
4.7k
GND
D
GND
GND
OUTPUT
Vbat
Rpull-up
External
Pull -Up switch
OUTPUT
10nF /100V
GND
GAPG1201151432CFT
Figure 18. Open-load / short to V
CC
condition
V
IN
V
SENSE
Open-load
V
SENSE
Short to V
CC t
DSTKON
V
SENSEH
V
SENSE
= 0
Pull-up connected
Pull-up disconnected
V
SENSEH
DS12676 - Rev 3 page 22/38
4.4.2
VN9008AJ
CS - analog current sense
Condition
Open-load
Short to V
CC
Nominal
Table 13. CS pin levels in off-state
Output
V
OUT
> V
OL
V
OUT
< V
OL
V
OUT
> V
OL
V
OUT
< V
OL
CS
Hi-Z
V
SENSEH
Hi-Z
0
Hi-Z
V
SENSEH
Hi-Z
0
Short to V
CC
and OFF-state open-load detection
Short to V
CC
A short circuit between V
CC and output is indicated by the relevant current sense pin set to V
SENSEH
during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short-circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor R
PU
connecting the output to a positive supply voltage V
PU
.
It is preferable that V
PU
is switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected.
R
PU must be selected in order to ensure V
OUT
> V
OLmax in accordance with the following equation:
RPU <
VPU − 4
IL off2 min@ 4V
(2)
H
L
H
L
H
L
SEn
L
H
DS12676 - Rev 3 page 23/38
5
VN9008AJ
Maximum demagnetization energy (Vcc = 16 V)
Maximum demagnetization energy (Vcc = 16 V)
Figure 19. Maximum turn off current versus inductance
100
Single Pulse Tjstart = 150°C
Repetitive pulse Tjstart = 100°C
Repetitive pulse Tjstart = 125°C
10
1
0
0.1
1000
L (mH) 1 10 100
Figure 20. Maximum turn off energy versus inductance
Single Pulse Tjstart = 150°C
Repetitive pulse Tjstart = 100°C
Repetitive pulse Tjstart = 125°C
100
1000
10
1
0.1
L (mH)
1 10 100 1000
DS12676 - Rev 3 page 24/38
6
VN9008AJ
PowerSSO-16 thermal data
PowerSSO-16 thermal data
Figure 21. PowerSSO-16 on two-layer PCB (2s0p to JEDEC JESD 51-5)
Figure 22. PowerSSO-16 on four-layer PCB (2s2p to JEDEC JESD 51-7)
DS12676 - Rev 3
Dimension
Board finish thickness
Board dimension
Board Material
Copper thickness (top and bottom layers)
Copper thickness (inner layers)
Thermal vias separation
Thermal via diameter
Copper thickness on vias
Footprint dimension (top layer)
Heatsink copper area dimension (bottom layer)
Table 14. PCB properties
Value
1.6 mm +/- 10%
77 mm x 86 mm
FR4
0.070 mm
0.035 mm
1.2 mm
0.3 mm +/- 0.08 mm
0.025 mm
2.2 mm x 3.9 mm
Footprint, 2 cm 2 or 8 cm 2 page 25/38
DS12676 - Rev 3
VN9008AJ
PowerSSO-16 thermal data
60
50
40
30
0
Figure 23. R thj-amb
vs PCB copper area in open box free air condition (one channel on)
RTHjamb
90
RTHjamb
80
RTHj_amb on 4Layer PCB: 19.9 °C/W
70
2 4 6 8 10
Figure 24. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
100
Z
TH
(°C/W)
10
1
0.1
0.0001
0.001
0.01
Equation: pulse calculation formula
Z
THδ
= R
TH
· δ + Z
THtp
(1 - δ) where δ = t
P
/T
0.1
Time (s)
1 10
Cu=foot print
Cu=2 cm2
Cu=8 cm2
4 Layer
100 1000 page 26/38
VN9008AJ
PowerSSO-16 thermal data
Figure 25. Thermal fitting model of a double-channel HSD in PowerSSO-16
Note: the fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections
(power limitation or thermal cycling during thermal shutdown) are not triggered.
Area/island (cm²)
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W·s/°C)
C2 (W·s/°C)
C3 (W·s/°C)
C4 (W·s/°C)
C5 (W·s/°C)
C6 (W·s/°C)
Table 15. Thermal parameters
FP
0.37
1.5
4.6
16
30
26
0.001
0.008
0.08
0.2
0.4
3
2
4.6
6
20
20
0.3
1
5
8
4.6
6
10
18
0.3
1
7
4L
3
7
4
4
0.4
4
18
DS12676 - Rev 3 page 27/38
7
7.1
VN9008AJ
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
PowerSSO-16 package information
Figure 26. PowerSSO-16 package outline
DS12676 - Rev 3
8017965_10_D page 28/38
DS12676 - Rev 3
Ref.
e
E
E1
E2
E3 c c1
D
D2
D3
N
R
R1
S h
L
L1
A
A1
A2 b b1
Θ
Θ1
Θ2
Θ3 aaa bbb ccc ddd eee ffff ggg
VN9008AJ
PowerSSO-16 package information
Table 16. PowerSSO-16 package mechanical data
5°
-
0.00
1.10
Min.
0°
0°
5°
0.20
0.20
0.19
0.19
3.60
2.90
2.50
1.80
0.25
0.40
0.07
0.07
0.20
Dimensions
-
0.60
1.00 REF
16
-
-
-
Tolerance of form and position
0.10
0.10
0.08
0.08
0.10
0.10
0.15
-
0.20
4.90 BSC
-
-
0.50 BSC
6.00 BSC
3.90 BSC
-
-
Millimeters
Typ.
-
-
-
-
-
-
-
-
0.25
-
-
-
3.10
-
0.50
0.85
15°
1.70
0.10
1.60
Max.
8°
-
15°
0.30
0.28
0.25
0.23
4.20
page 29/38
DS12676 - Rev 3
VN9008AJ
PowerSSO-16 package information
Figure 27. PowerSSO-16 package outline, details
8017965_10_D_details page 30/38
7.2
VN9008AJ
PowerSSO-16 packing information
PowerSSO-16 packing information
Figure 28. PowerSSO-16 reel 13"
Access Hole at
Slot Location
( 40 mm min.)
A D
Description
Base quantity
Bulk quantity
A (max)
B (min)
C (+0.5, -0.2)
D (min)
N
W1 (+2 /-0)
W2 (max)
1. All dimensions are in mm.
C
If present, tape slot in core for tape start:
2.5 mm min. width x
10.0 mm min. depth
B
Table 17. Reel dimensions
Value
2500
2500
330
1.5
13
20.2
100
12.4
18.4
W2
W1
N
TAPG2004151655CFT
DS12676 - Rev 3 page 31/38
DS12676 - Rev 3
VN9008AJ
PowerSSO-16 packing information
0.30 ±0.05
Figure 29. PowerSSO-16 carrier tape
P
2
2.0 ±0.1
P
0
4.0 ±0.1
1.55 ±0.05
X
1.75 ±0.1
1.6 ±0.1
F
W
B
0
K
1
K
0
SECTION X - X
R 0.5
Typical
Y
X
Y
P
1
REF 4.18
REF 0.6
SECTION Y - Y
REF 0.5
A
0
GAPG2204151242CFT
Table 18. PowerSSO-16 carrier tape dimensions
Description
A
0
B
0
K
0
K
1
F
P
1
W
1. All dimensions are in mm.
Value
6.50 ± 0.1
5.25 ± 0.1
2.10 ± 0.1
1.80 ± 0.1
5.50 ± 0.1
8.00 ± 0.1
12.00 ± 0.3
Figure 30. PowerSSO-16 schematic drawing of leader and trailer tape
Embossed carrier
Punched carrier
8 mm & 12 mm only
END
Carrier tape
Round sprocket holes
START
Top cover tape
Elongated sprocket holes
(32 mm tape and wider)
Trailer
160 mm minimum
Top cover tape
Components
User direction feed
100 mm min.
Leader
400 mm minimum
GAPG2004151511CFT page 32/38
7.3
PowerSSO-16 marking information
Figure 31. PowerSSO-16 marking information
VN9008AJ
PowerSSO-16 marking information
Special function digit
&: Engineering sample
<blank>: Commercial sample
PowerSSO-16 TOP VIEW
(not to scale)
GADG0310161234SMD
Parts marked as ‘&’ are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS12676 - Rev 3 page 33/38
Revision history
Date
30-Oct-2018
11-May-2021
13-Sep-2022
Revision
1
2
3
Table 19. Document revision history
Changes
Initial release.
•
•
Added:
Section 4 Application information;
Section 5 Package information.
•
•
•
•
•
•
•
•
•
Updated:
Figure 1. Block diagram;
Figure 2. Configuration diagram (top view);
Figure 3. Current and voltage conventions;
Table 3. Absolute maximum ratings;
Table 5. Power section;
Table 8. Protections;
Table 9. Current Sense;
Section Features;
Section 2.4 Waveforms.
•
•
Minor text changes in:
Table 1. Pin functions;
Table 7. Logic inputs .
•
•
•
•
•
•
•
•
•
•
•
Updated: features and applications in cover page
Table 2. Suggested connections for unused and not connected pins
Table 3. Absolute maximum ratings
Figure 11. Standby state diagram
Figure 12. Application diagram
Section 4.2 Immunity against transient electrical disturbances
Figure 17. Analog HSD – open-load detection in off-state
•
•
Inserted:
Section 5 Maximum demagnetization energy (Vcc = 16 V)
Section 6 PowerSSO-16 thermal data
VN9008AJ
DS12676 - Rev 3 page 34/38
VN9008AJ
Contents
Contents
and OFF-state open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DS12676 - Rev 3 page 35/38
VN9008AJ
List of figures
List of figures
Figure 18. Open-load / short to V
DS12676 - Rev 3 page 36/38
VN9008AJ
List of tables
List of tables
DS12676 - Rev 3 page 37/38
VN9008AJ
IMPORTANT NOTICE – READ CAREFULLY
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DS12676 - Rev 3 page 38/38
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