STMicroelectronics L99MOD50XP Datasheet

L99MOD50XP

Multi-output driver for automotive applications

Datasheet

-

production data

 Device contains temperature warning and protection

 Open-load detection for all outputs

 Over-current protection for all outputs

 PWM control of all outputs

 Charge pump output for reverse polarity protection

 ST standard serial peripheral interface

(ST-SPI 3.0)

Features

 Programmable soft start function to drive loads with higher inrush currents as current limitation value

Applications





AEC-Q100 qualified

Two half bridges for 6

(R

DSon

150 m  load

L99MOD devices are recommended for those applications that need multiple motors control with additional loads in high-side configuration, such

 Two half bridges for 3 A load (R

DSon

= 300 m  ) as bulbs/LEDs or requiring protected supply, like sensors or cameras.

 Two half bridges for 0.75 A load

(R

DSon m  )

 One high-side driver for 6 A load (R

DSon

90  )

=

Description

The L99MOD50XP is a microcontroller-driven

 Two configurable high-side drivers for up to

1.5A load (R

(R

DSon

DSon

500 m  ) m  or  0.4

multifunctional actuator driver for automotive applications.

 Two high-side drivers for 0.5

(R

DSon m  )

Up to five DC motors and five grounded resistive load high-side drivers.

The integrated SPI controls all operating modes

(forward, reverse, brake and high impedance).

 Very low current consumption in standby mode

(I

T

S j

< 6

  85

μ A typ; T

°C) j

 85 °C; I

CC

<5 μ A typ;

 Current monitor output for all high-side drivers

Also all diagnostic information is available via SPI read.

Package

PowerSSO-36

Table 1. Device summary

Order codes

L99MOD50XPTR

Packing

Tape and reel

October 2019

This is information on a product in full production.

DS12615 Rev 4 1/42 www.st.com

1

2

Contents

Contents

3

4

L99MOD50XP

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4.1

Outputs OUT1 - OUT11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5

SPI - Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1

Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2

Wake up and active mode / standby mode . . . . . . . . . . . . . . . . . . . . . . . 21

3.3

Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4

Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.5

Overvoltage and undervoltage detection at V

S . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.6

Overvoltage and undervoltage detection at V

CC . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.7

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 22

3.8

Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.9

Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.10

Over-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.11

Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.12

PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.13

Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.14

Programmable soft-start function to drive loads with higher inrush current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1.1

4.1.2

4.1.3

Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/42 DS12615 Rev 4

L99MOD50XP

5

6

7

8

Contents

4.1.4

4.1.5

Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2

Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.1

Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.3

Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.4

Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SPI - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1

Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2

Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3

Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4

Control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.5

Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.6

Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.7

Status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.8

Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.1

PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.1

ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.2

PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.3

PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DS12615 Rev 4 3/42

3

List of tables

List of tables

L99MOD50XP

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin definition and functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 9.

Current monitor output CM / PWM 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 10.

Charge pump output CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 11.

On-resistance and switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 12.

Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 13.

Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 14.

Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 15.

SDI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 16.

DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 17.

DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 18.

CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 19.

SPI frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 20.

Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 21.

Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 22.

RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 23.

ROM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 24.

Control register 0 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 25.

Control register 1 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 26.

Control register 2 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 27.

Control register 3 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 28.

Status register 0 (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 29.

Status register 1 (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 30.

Status register 2 (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 31.

Configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 32.

PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 33.

Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4/42 DS12615 Rev 4

L99MOD50XP

List of figures

List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.

SPI - Transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 4.

SPI - Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5.

SPI - DO valid data delay time and valid time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6.

SPI - DO enable and disable time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7.

SPI - driver turn on/off timing, minimum CSN HI time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8.

Example of programmable soft-start function for inductive loads . . . . . . . . . . . . . . . . . . . . 24

Figure 9.

Write and read SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10.

Global error flag definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11.

PowerSSO-36 2 layer PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 12.

PowerSSO-36 4 layer PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13.

PowerSSO-36 thermal impedance junction to ambient vs PCB copper area . . . . . . . . . . . 37

Figure 14.

PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 15.

PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DS12615 Rev 4 5/42

5

Block diagram and pin description

1 Block diagram and pin description

/30*;3

9&&

63&'

L99MOD50XP

—)

Q)

N

N

N

N

',

'2

&/.

&61

N

3:0

Figure 1. Block diagram

9

%$7

67/1)

N N

96 &3

9&&

&KDUJH

3XPS

6763,

Pȍ

Pȍ

287

Pȍ

287

287

Pȍ

Pȍ

287

287

Pȍ 287

0

0

0

0

Pȍ

287

Pȍ

287

Pȍ

:DWW

:DWW

287

287

Pȍ

287

Pȍ

0

SURJU%XOERU/('0RGH

N

&03:0 &0

08;

*1'

*$'*36

6/42 DS12615 Rev 4

L99MOD50XP

&03:0

&61

'2

9FF

&/.

9V

9V

287

287

*1'

*1'

287

287

287

287

9V

9V

',

Block diagram and pin description

Figure 2. Configuration diagram (top view)

3RZHU662

Note: All pins with the same name must be externally connected.

*1'

287

287

287

9V

287

287

9V

9V

3:0

&3

9V

9V

9V

287

287

287

*1'

*$'*36

DS12615 Rev 4 7/42

41

Block diagram and pin description L99MOD50XP

Pin

1, 18, 19, 36

2, 35

3

4

5

6, 7, 14, 15,

23, 24, 25, 28,

29, 32

8

9

10

11

12

13

16,17

20,21

22

Symbol

Table 2. Pin definition and functions

Function

GND

OUT11

OUT1,

OUT2,

OUT3

V

S

DI

CM/

PWM2

CSN

DO

VCC

CLK

OUT4,

OUT5,

OUT6

Ground: reference potential.

Important: For the capability of driving the full current at the outputs all pins of GND must be externally connected!

High-side driver output 11.

The output is built by a high-side switch and is intended for resistive loads, therefore the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present, but the energy which can be dissipated is limited. The high-side driver is a power DMOS transistor with an internal parasitic reverse diode from the output to VS (bulk-drain-diode). The output is over-current protected.

Important: for the capability of driving the full current at the outputs both pins of OUT11 must be externally connected!

Halfbridge outputs 1,2,3.

The output is built by a high-side and a low-side switch, which are internally connected.

The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output). This output is over-current protected.

Power supply voltage (external reverse protection required).

For this input a ceramic capacitor as close as possible to GND is recommended.

Important: For the capability of driving the full current at the outputs all pins of VS must be externally connected! Pins 25 and 32 can be connected to VS to maintain compatibility with other L99MOD products; otherwise they should be left Not

Connected

Serial data input.

The input requires CMOS logic levels and receives serial data from the microcontroller.

23) transferred first.

Current monitor output/PWM2 input.

Depending on the selected multiplexer bits of the control register this output sources an image of the instant current through the corresponding high-side driver with a ratio of

1/10.000 or 1/2000. This pin is bidirectional. The microcontroller can overdrive the current monitor signal to provide a second PWM input for the outputs OUT5, OUT8 and

OUT10.

Chip Select Not input

This input is low active and requires CMOS logic levels. The serial data transfer between L99MOD50XP and the microcontroller is enabled by pulling the input CSN to low level.

Serial data output.

The diagnosis data is available via the SPI and this tristate-output. The output will remain in tristate, if the chip is not selected by the input CSN (CSN

Supply voltage.

For this input a ceramic capacitor as close as possible to GND is recommended.

Serial clock input.

This input controls the internal shift register of the SPI and requires CMOS logic levels.

Half-bridge outputs 4,5,6: see OUT1 (pin 3).

Important: For the capability of driving the full current at the outputs both pins of OUT4

(OUT5, respectively) must be externally connected!

8/42 DS12615 Rev 4

L99MOD50XP

Pin

26

27

30

31

33

34

Block diagram and pin description

Symbol

Table 2. Pin definition and functions (continued)

Function

CP

PWM1

OUT7,

OUT8,

OUT9

OUT10

Charge pump output.

This output is provided to drive the gate of an external n-channel power MOS used for reverse polarity protection (see

Figure 1.

).

PWM1 input.

This input signal can be used to control the drivers OUT1-4, OUT6-7, OUT9 and

OUT11 by an external PWM signal.

High-side driver outputs 7,8: see OUT9.

By selection of one of the 2 power DMOS at same output is it possible to supply a bulb with low on-resistance or a LED with higher on-resistance in a different application.

High-side driver output 9.

The output is built by a high-side switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to

GND is present but the energy which can be dissipated is limited. The high-side driver is a power DMOS transistor with an internal parasitic reverse diode from the output to

VS (bulk-drain-diode). The output is over-current and open load protected.

High-side driver output 10: see OUT9.

Important: beside the bit10 in control register 1 this output can be switched on setting bit1 for electrocromic control mode with higher priority.

DS12615 Rev 4 9/42

41

Electrical specifications

2 Electrical specifications

2.1

L99MOD50XP

Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality document.

Symbol

Vs

Vcc

V

DI

, V

DO,

V

CLK,

V

CSN,

V

PWM

V

CM

V

CP

V

OUTn

I

OUT,2,3,9,10

I

OUT1,6,7,8

I

OUT4,5,11

Table 3. Absolute maximum ratings

Parameter

DC supply voltage

Single pulse t max

Stabilized supply voltage, logic supply

Digital input / output voltage

Current monitor output

Charge pump output

Static output voltage (n= 1 to 11)

Output current

Output current

Output current

Value

-0.3...28

40

-0.3 to 5.5

-0.3 to V

CC

+ 0.3

-0.3 to V

CC

+ 0.3

-25 to V

S

+ 11

-0.3 to V

S

+ 0.3

±1.25

±5

±10

Unit

V

V

V

V

A

A

A

V

V

V

Table 4. ESD protection

Parameter

All pins

Output pins: OUT1 - OUT6

1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.

2. HBM with all unzapped pins grounded.

Value

± 2

(1)

± 4

(2)

Unit kV kV

10/42 DS12615 Rev 4

L99MOD50XP Electrical specifications

Symbol

T j

Table 5. Operating junction temperature

Parameter

Operating junction temperature

Value

-40 to 150

Unit

°C

Symbol

T jTW ON

T jSD ON

T jSD OFF

T jSD HYS

Table 6. Temperature warning and thermal shutdown

Parameter Min.

Temperature warning threshold junction temperature

T j

130

Thermal shutdown threshold junction temperature T j

increasing

Thermal shutdown threshold junction temperature T j

decreasing 150

Thermal shutdown hysteresis

Typ.

Max.

Unit

150

170

5

°C

°C

°C

°K

V

S

= 8 to 16 V, V

CC

= 4.5 to 5.3

V, T j

= - 40 to 150 °C, unless otherwise specified.

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

Item Symbol Parameter

Table 7. Supply

Test condition

7.1

VS Operating voltage range

7.2

7.3

7.4

(1)

7.5

7.6

7.7

(2)

(1)

I

I

S

CC

V

V

S

DC supply current

CC

quiescent supply current

V

S active mode

CC

= V

OUT1 - OUT11

V

S

quiescent supply current

V

CC

DC supply current

V

S CC standby mode

0 V

OUT1 - OUT11

T test

= -40°C, 25°C

T test

= 85°C

V

S CC

= V

CSN = V

CC

, active mode

OUT1 - OUT11

V

S

V

CC

5.3

V

CSN standby mode

V

CC

OUT1 - OUT11

T test

= -40°C, 25°C

T test

= 85°C

1. This parameter is guaranteed by design.

2. CM/ PWM 2 = V

CC

or 0 V.

Min.

Typ.

Max.

Unit

7 28 V

7

4

6

1

3

5

20

12

25

3

6

10 mA

μ A mA

μ A

DS12615 Rev 4 11/42

41

Electrical specifications

Item

8.5

8.6

8.7

8.8

8.9

8.1

8.2

8.3

8.4

L99MOD50XP

Symbol

V

SUV on

V

SUV off

V

SUV hyst

V

SOV off

V

SOV on

V

SOV hyst

V

POR off

V

POR on

V

POR hyst

Table 8. Overvoltage and under voltage detection

Parameter Test condition Min.

Typ.

Max.

Unit

V

S

UV-threshold voltage

V

S

UV-threshold voltage

V

S

UV-hysteresis

V

S

OV-threshold voltage

V

S

OV-threshold voltage

V

S

OV-hysteresis

Power-on-reset threshold

Power-on-reset threshold

Power-on-reset hysteresis

V

S

increasing

V

S

decreasing

V

SUV ON

- V

SUV OFF

V

S

increasing

V

S

decreasing

V

SOV OFF

- V

SOV ON

V

CC

increasing

V

CC

decreasing

V

POR OFF

- V

POR ON

5.6

5.2

18

17.5

2.0

0.5

1

0.11

7.2

6.1

24.5

23.5

2.9

V

V

V

V

V

V

V

V

V

Item Symbol

Table 9. Current monitor output CM / PWM 2

Parameter Test condition Min.

Typ.

9.1

V

CM

Functional voltage range

9.2

9.3

9.4

9.5

I

I

CM,r

CM acc

Current monitor output ratio:

I

CM

/ I

OUT1,4,5,6,11 and 7,8

(low on-resistance)

I

CM

/ I

OUT2,3,9,10 and 7,8

(high on-resistance)

Current monitor accuracy accI

CMOUT1,4,5,6,11 and 7, 8

(low on-res.) V

CM

V

CC

= 5 V accI

CMOUT2,3,9,10, and 7, 8

(high on-res.)

0 V <= V

CM

V

CC

<= 4

=5 V

V

I

I

Out,min

I

Out4,5,11max

Out1,6 max

I

Out7,8 max

= 5.9

= 2.9

= 1.3

A

A

I

Out,min

= 100 mA

I

Out2,3 max

= 0.6 A

I

Out9,10max

= 0.4 A

I

Out8 max

= 0.3 A

A

1.

FS (full scale)= I

OUTmax *

I

CMr_typ .

0

-8% -

2%FS

(1)

10.000

0

Max Unit

V

CC

1V

-

8% +

2%FS

(

1)

V

A

Item

10.1

10.2

10.3

10.4

Symbol

V

CP

I

CP

Table 10. Charge pump output CP

Parameter Test condition

Charge pump output voltage

Charge pump output current

V

S

= 8 V, I

CP

= -60 μ A

V

S

V

S

μ A

μ A

V

CP

= V

S

V

S

=13.5

V

Min.

V

S

+6

V

S

+8

V

S

+10

95

Typ.

150

Max

V

S

+13

V

S

+13

V

S

+13

300

Unit

V

V

V

μ A

12/42 DS12615 Rev 4

L99MOD50XP Electrical specifications

2.4.1

Item

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

11.9

11.10

Outputs OUT1 - OUT11

Symbol r

ON OUT1, r

ON OUT6

Table 11. On-resistance and switching times

Parameter Test condition Min.

Typ.

Max.

Unit

On-resistance to supply or

GND

r

ON OUT2, r

ON OUT3

On-resistance to supply or

GND r

ON OUT4, r

ON OUT5

On-resistance to supply or

GND r

ON OUT9, r

ON OUT10

On-resistance to supply r

ON OUT11

On-resistance to supply

V

S

T j

I

OUT1,6

± 1.5

A

V

S

T j

I

OUT1,6

± 1.5

A

V

S

T j

I

OUT2,3

± 0.4

A

V

S

T j

I

OUT2,3

± 0.4

A

V

S

T j

I

OUT4,5

± 3.0

A

V

S

T j

I

OUT4,5

± 3.0

A

V

S

T j

I

OUT9,10

-0.4

A

V

S

T j

I

OUT9,10

-0.4

A

V

S

T j

I

OUT11

-3.0

A

V

S

T j

I

OUT11

-3.0

A

300

450

400

600

1600 2200

2500 3400

150

225

200

300

1600 2200

2500 3400

90

130

130

180 m Ω m Ω m Ω m Ω m Ω m Ω m Ω m Ω m Ω m Ω

DS12615 Rev 4 13/42

41

Electrical specifications L99MOD50XP

Item

11.11

11.12

11.13

11.14

11.15

11.16

11.17

11.18

11.19

11.20

11.21

11.22

11.23

11.24

11.25

Symbol

Table 11. On-resistance and switching times (continued)

Parameter Test condition

r

ON OUT7 r

ON OUT8

On-resistance to supply in low mode (control register 1 bits 12 to15: 0101)

V

S

T j

I

OUT7,8

- 0.8

A

V

S

T j

I

OUT7,8

- 0.8

A

On-resistance to supply in high mode (control register

1 bits 12 to15: 1010)

V

S

T j

I

OUT7,8

- 0.2

A

V

S

T j

I

OUT7,8

- 0.2

A

I

QLH

Switched-off output current high-side drivers of OUT1-6,

8-11

V

OUT standby mode

V

OUT active mode

I

QLH7,8

Switched-off output current high-side drivers of OUT7-8

V

OUT standby mode

V

OUT active mode t t

I

QLL d ON H d OFF H

Switched-off output current low-side drivers of OUT1-6

V

OUT

= V

S

, standby mode

V

OUT active mode

Output delay time, high-side driver on (OUT

X except OUT

7,8

)

Output delay time, high-side driver on (OUT

7,8 in high R

DSon mode)

Output delay time, high-side driver on (OUT

7,8 in low R

DSon mode)

Output delay time, high-side driver off (OUT

1, 4,

5, 6, 11

)

Output delay time, high-side driver off

(OUT

2,3,7, high/low R

DSon , 8 high/low R

DSon , 9, 10

)

V

S

V

CC

(1)(2)(3)

V

S

V

CC

5 V

(1)(2)(3)

Min.

Typ.

Max.

Unit

-5

-10

-5

-15

-10

20

15

10

60

40

500

700

700

950

1800 2400

2500 3400

-2

-7

-2

-10

80

-7

40

35

35

150

70

120

80

60

80

200

100 m Ω m Ω m Ω m Ω

μ A

μ A

μ A

μ A

μ A

μ A

μ s

μ s

μ s

μ s

μ s

14/42 DS12615 Rev 4

L99MOD50XP Electrical specifications

Item Symbol

Table 11. On-resistance and switching times (continued)

Parameter Test condition

11.26

t d ON L

Output delay time, low-side driver On

V

S

V, 5 V, corresponding high-side driver is not active

(1)(2)(3)

11.27

11.28

11.29

11.30

t d OFF L 1-6 t t

D HL

D LH dV

OUT off

/dt on/

Output delay time, low-side driver OUT 1-6 off

Cross current protection time

Slew rate of OUTx

V

S

V

CC

=5 V

(1)(2)(3)

t cc ONLS_OFFHS -

t d OFFH

(4) t cc ONHS_OFFLS

-t d OFFL

(4)

V

S

V

CC

= 5 V

(1)(2)(3)

1. Rload = 16 Ω at OUT1, 6 and 7,8 in low on-resistance mode.

2. Rload = 4 Ω at OUT4, 5 and 11.

3. Rload = 64 Ω at OUT2, 3, 9, 10 and 7, 8 in high On-resistance mode.

4. t cc

is the switch-on delay time if complement in half bridge has to switch-off.

Min.

Typ.

Max.

Unit

15

40

50

0.1

30

150

200

0.2

70

300

400

0.6

μ s

μ s

μ s

V/ μ s

Item Symbol

12.1

12.2

12.3

12.4

12.5

12.6

12.7

12.8

12.9

12.10

Table 12. Current monitoring

Parameter Test condition Min.

Typ.

Max.

Unit

|I

OC1

|,

|I

OC6

|

|I

|I

OC2

OC3

|,

|

Over-current threshold to supply or GND

V

S

V

CC sink and source

3

0.75

|I

OC4

|,

|I

OC5

|

6

|I

|I

|I

OC9

|,

OC10

OC11

|

Over-current threshold to supply

V

S

V

CC

5 V, source

0.5

| 6

|I

OC7

|,

|I

OC8

|

Over-current threshold to supply in low on-resistance mode

V

S

V, 5 V, source, control register 1 bits 12 to 15: 0101

1.5

Over-current threshold to supply in high on-resistance mode

V

S

V, 5 V, source, control register 1 bits 12 to 15: 1010

0.35

t f f

FOC rec0 rec1

Filter time of over-current signal

Duration of over-current condition to set the status bit

Recovery frequency for OC recovery duty cycle bit= 0

Recovery frequency for OC recovery duty cycle bit= 1

10

1

2

55

5

1.25

10

1.0

10

2.5

0.65

100

4

6

A

A

A

A

A

A

A

μ s kHz kHz

DS12615 Rev 4 15/42

41

Electrical specifications L99MOD50XP

Item Symbol

12.11

12.12

II

OLD1

I,

II

OLD6

I

II

OLD2

I,

II

OLD3

I

12.13

12.14

II

OLD4

I,

II

OLD5

I

II

OLD9

I,

II

OLD10

I

12.15

II

OLD11

I

Table 12. Current monitoring (continued)

Parameter

Under-current threshold to supply or GND

Under-current threshold to supply

Test condition

V

S

V

CC sink and source

12.16

12.17

II

OLD7

I,

II

OLD8

I

Under-current threshold to supply in low on-resistance mode

Under-current threshold to supply in high on-resistance mode

V

S

V

CC

12.18

t

FOL

Filter time of under-current

Duration of under-current condition to set the status bit

Min.

Typ.

Max.

Unit

10

10

60

5

30

15

5

0.5

30

20

150

10

150

40

10

80

30

300

15

300

60

15

3 mA mA mA mA mA mA mA ms

2.5 SPI - Electrical characteristics

V

S

= 8 to 16 V, V

CC

= 4.5 to 5.5

V, T j

= - 40 to 150°C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

Item Symbol

14.1

t set

Table 13. Delay time from standby to active mode

Parameter Test condition Min. Typ.

Max.

Unit

Delay time

Switching from standby to active mode.

Time until output drivers are enabled after

CSN going to high and set bit 0=1 of control register 0.

256 300 μ s

Item

15.1

15.2

15.3

15.4

Symbol

V inL

V inH

V in Hyst

R

CSN in

Table 14. Inputs: CSN, CLK, PWM1/2 and DI

Parameter Test condition Min. Typ.

Max.

Unit

Input low level V

CC

= 5 V

0.3*

Vcc

V

Input high level

Input hysteresis

V

CC

= 5 V

0.7*

Vcc

500

V mV

CSN pull up resistor

V

CC

V

CC

= 5 V

0 V<V

CSN

<0.7

V

CC

30 120 250 k Ω

16/42 DS12615 Rev 4

L99MOD50XP Electrical specifications

Item Symbol

Table 14. Inputs: CSN, CLK, PWM1/2 and DI (continued)

Parameter Test condition Min. Typ.

Max.

Unit

15.5

15.6

15.7

15.8

R

R

CLK in

R

PWM1 in

C

DI in in

(1)

CLK pull down resistor

DI pull down resistor

PWM1 pull down resistor

V

CC

= 5 V

V

CLK

= 1.5 V

V

CC

= 5 V

V

DI

= 1.5

V

V

CC

= 5 V

V

PWM1

= 1.5

V

Input capacitance at input CSN,

CLK, DI and PWM1/2

0 V < V

CC

< 5.3

V

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

30

30

30

60

60

60

150

150

150

10 k Ω k Ω k Ω pF

Item

16.1

16.2

Symbol t

CLK t

CLKH t

CLKL

Parameter

(1)

Clock period

Clock high time

Table 15. SDI timing

V

CC

V

CC

V

CC

Test condition Min. Typ.

Max.

Unit

115

16.3

16.4

16.5

t t set CSN set CLK

Clock low time

CSN setup time, CSN low before rising edge of CLK

CLK setup time, CLK high before rising edge of CSN

V

V

CC

CC

= 5 V

115

400

400

16.6

16.7

16.8

16.9

t t set DI hold DI t t r in f in

DI setup time

DI hold time

Rise time of input signal DI,

CLK, CSN

Fall time of input signal DI,

CLK, CSN

V

V

V

CC

V

CC

CC

CC

= 5 V

200

200

1. DI timing parameters tested in production by a passed / failed test:

Tj = -40°C / +25°C: SPI communication @ 2

Tj = +125°C: SPI communication @ 1.25 MHz.

1000

100

100 ns ns ns ns ns ns ns ns ns

Item Symbol Parameter

Table 16. DO

Test condition Min.

17.1

17.2

17.3

17.4

I

C

V

V

DOL

DOH

DOLK

DO

(1)

Output low level

Output high level

Tristate leakage current

Tristate input capacitance

I

DO

= -5 mA

I

DO

= 5 mA

V

CSN

= V

CC

,

0 V < V

DO

< V

CC

V

CSN

= V

CC

,

0 V < V

CC

< 5.3

V

0.8 V

-10

CC

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

Typ.

Max.

0.2V

CC

10

Unit

V

V

μ A

10 pF

DS12615 Rev 4 17/42

41

Item

18.1

18.2

18.3

18.4

18.5

18.6

Electrical specifications

18.7

L99MOD50XP

Symbol t r DO t f DO t en DO tri L t dis DO L tri t en DO tri H t dis DO H tri t d DO

Parameter

DO rise time

DO fall time

DO enable time from tristate to low level

DO disable time from low level to tristate

DO enable time from tristate to high level

DO disable time from high level to tristate

DO delay time

Table 17. DO timing

Test condition

C

DO

= 100 pF

C

DO

= 100 pF

C

DO

= 100 pF, I up load to V

CC load

= 1

C

DO

= 100 pF, I up load to V

CC load

= 4 mA pull-

C

DO

=100 pF, I load down load to GND

C

DO

= 100 pF, I load

mA pull-down load to GND

V

DO

< 0.3 V

V

DO

> 0.7 V

CC

,

CC

,

C

DO

= 100 pF

Min.

Typ.

Max.

Unit

80

50

140

100 ns ns

100

380

100

380

50

250

450

250

450

250 ns ns ns ns ns

Item Symbol

19.1

t

CSN_HI,stb

19.2

t

CSN_HI,min

Parameter

Table 18. CSN timing

Test condition

Minimum CSN HI time, switching from standby mode

Transfer of SPI-command to input register

Minimum CSN HI time, active mode

Transfer of SPI-command to input register

Min.

Typ.

Max.

Unit

20

2

50

4

μ s

μ s

Figure 3. SPI - Transfer timing diagram

&61KLJKWRORZ'2HQDEOHG

&61

WLPH

&/.

',

'2

,QSXW

'DWDW

5HJLVWHU

; ;

',GDWDZLOOEHDFFHSWHGRQWKHULVLQJHGJHRI&/.VLJQDO

; ;

',GDWDZLOOEHDFFHSWHGRQWKHULVLQJHGJHRI&/.VLJQDO

IDXOWELW

; ;

&61ORZKLJKDFWXDOGDWDLV

WUDQVIHUUHGWRRXWSXWSRZHUVZLWFKHV

ROGGDWD

WLPH

WLPH

WLPH

QHZGDWD

WLPH

*$'*36

18/42 DS12615 Rev 4

L99MOD50XP Electrical specifications

Figure 4. SPI - Input timing

&61

&/.

',

W

VHW&61

W

&/.+

W

VHW',

W

KROG ',

9DOLG

W

&/./

9DOLG

W

VH W&/.

9&&

9&&

9&&

9&&

9&&

9&&

*$'*36

&/.

'2

ORZWRKLJK

Figure 5. SPI - DO valid data delay time and valid time

W

I LQ

W

ULQ

W

U '2

W

G '2 W

I'2

KLJK

'2

WRORZ

9&&

9&&

9&&

9&&

9&&

9&&

9&&

*$'*36

DS12615 Rev 4 19/42

41

Electrical specifications

&61

Figure 6. SPI - DO enable and disable time

W

ILQ

W

ULQ

L99MOD50XP

9&&

9&&

'2

SXOOXSORDGWR9&&

W

HQ'2WUL/

W

GLV'2/WUL

'2

SXOOGRZQORDGWR*1'

W

HQ'2WUL+

W

GLV'2+WUL

Figure 7. SPI - driver turn on/off timing, minimum CSN HI time

20/42 DS12615 Rev 4

L99MOD50XP

3 Application information

3.1

3.2

Application information

Dual power supply: V

S

and V

CC

The power supply voltage V

S

supplies the half bridges and the high-side drivers. An internal charge-pump is used to drive the high-side switches. The logic supply voltage V for the logic part and the SPI of the device.

CC

is used

Due to the independent logic supply voltage the control and status information is not lost, if there are temporary spikes or glitches on the power supply voltage.

Wake up and active mode / standby mode

After power up of VS and Vcc the device operates in standby-mode. Pulling the signal CSN to low level wakes the device up and the analog part is activated (active mode).

After at least 10 μ s, the first SPI communication is valid and bit 0 of the Control Register 0 can be used to set the EN-mode. If bit 0 is not set to 1, the device doesn't remain in the active mode. After at least 256 μ s all latched data are cleared and the inputs and outputs are switched to high impedance. In standby mode the current at V

(5 μ A) for CSN

S

(V

CC

) is less than 6 μ A

In standby mode the charge-pump is turned off. After enabling the device by SPI command

(bit0=1 Control Register 0) the oscillator starts and the voltage begins to increase. The output drivers are enabled after at least 256 μ s after CSN went to high.

3.5

All diagnostic functions (over/under-current, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered. The condition has to be valid for at least 32 set.

μ s (open load: 1 ms) before the corresponding status bit in the status registers is

The filters are used to improve the noise immunity of the device. The under-current and temperature warning functions are intended for information purpose and don’t change the state of the output drivers. On the contrary, the over-current condition disables the corresponding driver and thermal shutdown disables all drivers. Without setting the overcurrent recovery bits in the input data register, the microcontroller has to clear the overcurrent status bits to reactivate the corresponding drivers.

Overvoltage and undervoltage detection at V

S

If the power supply voltage VS rises above the overvoltage threshold V

SOV OFF

(typical

When the voltage VS drops below the undervoltage threshold V

SUV OFF

(UV-switch-OFF voltage), the output stages are switched to high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the

DS12615 Rev 4 21/42

41

Application information L99MOD50XP supply voltage V

S

recovers (control register 3: bit 4=0) to normal operating voltage then the outputs stages return to the programmed state. If the undervoltage/overvoltage recovery disable bit is set (control register 3: bit 4=1), the automatic turn-on of the drivers is deactivated.

The microcontroller needs to clear the status bits to reactivate the drivers. It is recommended to set bit1 control register 3 to avoid a possible high current oscillation in case of a shorted output to GND and low battery voltage.

3.6

3.7

Overvoltage and undervoltage detection at V

CC

In case of power-on (VCC increases from undervoltage to V

POR OFF

2.9

V) the circuit is initialized by an internally generated power-on-reset (POR). If the voltage VCC decreases below the minimum threshold (V

POR ON

2.0

V), the outputs are switched to tristate (high impedance) and the status registers are cleared.

Temperature warning and thermal shutdown

If the junction temperature rises above T j TW

, a temperature warning flag is set after at least

32 μ s and it can be read via the SPI. If the junction temperature increases above the second threshold T j SD

, the thermal shutdown bit is set and the power DMOS transistors of all output stages are switched off to protect the device after at least 32 μ s.

The temperature warning and thermal shutdown flags are latched and the bits must be cleared by the microcontroller. This is possible only if the temperature has decreased below trigger temperature. If the thermal shutdown bit has been cleared the output stages are reactivated.

3.9

Each half bridge is built by internally connected high-side and low-side power DMOS transistors. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT6 without external free-wheeling diodes. The highside drivers OUT7 to OUT11 are intended to drive resistive loads. Therefore only a limited energy (E<1 mJ) can be dissipated by the internal ESD-diodes in freewheeling condition.

For inductive loads (L>100 μ H) an external free-wheeling diode connected between GND and the corresponding output is required.

Open load detection

The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (t dOL

) the corresponding open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without changing the mechanical/electrical state of the loads.

22/42 DS12615 Rev 4

L99MOD50XP Application information

In case of an over-current condition a flag is set in the status register in the same way as during open load detection. If the over-current signal is valid for at least t

ISC

(typ) 55 μ s, the over-current flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero, the microcontroller has to clear the status bits to reactivate the corresponding driver.

The current monitor output sources a current image at the current monitor output which has two fixed ratios of the instantaneous current of the selected high-side driver. Outputs with a resistance of 500 m Ω and higher have a ratio of 1/2000 and those with a lower resistance of

1/10000. The signal at output CM is blanked after switching on the driver until correct settlement of the circuitry (at least for 64 μ s). The bits 0 to 3 of the control register 3 define which of the outputs are multiplexed to the current monitor output CM/PWM2. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. For example it can be used to detect the motor state (starting, free-running, stalled). Moreover, it is possible to control the power of the defroster more precisely by measuring the load current. The current monitor output is bidirectional (PWM inputs).

Each driver has a corresponding PWM enable bit, which can be programmed by the SPI interface. If the PWM enable bit is set in control registers 2 or 3, the output is controlled by the logically AND-combination of the PWM signal and the output control bit in Control

Registers 0 and 1. The outputs OUT1-4, 6, 7, 9, OUT11 are controlled by the PWM1 input and the outputs OUT5, 8 and OUT10 are controlled by the bidirectional input CM/PMW2.

For example, the two PWM inputs can be used to dim two lamps independently by external

PWM signals. In case of switching off a high/low side switch in PWM mode a minimum off time of appr. (256 μ s – td on + td off

) is predefined by the state machine, to avoid switching on the high/low side again during the negative slope. For a PWM frequency of 100Hz this means the maximum duty cycle is about 98%. Larger duty cycles can be realized by applying pulse skipping.

The six half bridges of the device are cross-current protected by an internal delay time. If one driver (LS or HS) is turned off, the activation of the other driver of the same half bridge is automatically delayed by the cross-current protection time. After the cross-current protection time is expired the slew-rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior it is always guaranteed that the previously activated driver is completely turned off before the opposite driver starts to conduct.

DS12615 Rev 4 23/42

41

Application information L99MOD50XP

3.14 Programmable soft-start function to drive loads with higher inrush current

Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable softstart function (i.e. overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set, the device automatically switches the outputs on again after a programmable recovery time. The duty cycle in over-current condition can be programmed by the SPI interface to about 12% or 25%. The PWM modulated current provides sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. The PWM frequency settles at 1.7 kHz and

3 kHz. The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. For over-load detection the microcontroller can switch on the light bulbs by setting the over-current switched off, if the overload condition remains. This over-load detection procedure has to be followed in order make it possible to switch on the low-side driver of a bridge output, if the associated high-side driver has been used in recovery mode before.

Figure 8. Example of programmable soft-start function for inductive loads

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24/42 DS12615 Rev 4

L99MOD50XP

4 Functional description of the SPI

Functional description of the SPI

4.1.1

Note:

4.1.2

4.1.3

Note:

4.1.4

Standard ST-SPI Interface Version 3.0.

The SPI communication is based on a Serial Peripheral Interface structure using CSN (Chip

Select Not), DI (Serial Data In), DO (Serial Data Out/Error) and CLK (Serial Clock) signal lines.

Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) is in high impedance state. A low signal wakes up the device and a serial communication can be started. The state when CSN is going low until the rising edge of

CSN is called a communication frame.

The device includes a test mode. This mode is activated by a dedicated sequence which includes a high voltage at the CSN pin. The CSN pin must be kept at nominal voltage levels in order to avoid accidental activation of the test mode.

Serial Data In (DI)

The input pin is used to transfer data serially into the device. The data applied to the DI is sampled at the rising edge of the CLK signal.

Serial Clock (CLK)

This input signal provides the timing of the serial interface. The Data Input (DI) is latched at the rising edge of Serial Clock CLK. The SPI can be driven by a micro controller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. Data on Serial Data Out

(DO) is shifted out at the falling edge of the serial clock (CLK). The serial clock CLK must be active only during a frame (CSN low). Any other switching of CLK close to any CSN edge could generate set up/hold violations in the SPI logic of the device.

The clock monitor counts the number of clock pulses during a communication frame (while

CSN is low). If the number of CLK pulses does not correspond to the frame width indicated in the <SPI-frame-ID> (ROM address 03H) the frame is ignored and the <frame error> bit in the <Global Status Byte> is set.

Due to this safety functionality, daisy chaining the SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.

Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and goes from high impedance to a low or high level depending on the global status bit 7 (Global Error Flag).

The first rising edge of the CLK input after a high to low transition of the CSN pin transfers the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK shifts the next bit out.

DS12615 Rev 4 25/42

41

Functional description of the SPI

4.1.5

L99MOD50XP

SPI communication flow

At the beginning of each communication the master can read the contents of the

<SPI-frame-ID> register (ROM address 03H) of the slave device. This 8-bit register indicates the SPI frame length (24 bit) and the availability of additional features.

Each communication frame consists of a command byte which is followed by 2 data bytes.

The data returned on DO within the same frame always starts with the <Global Status>

Byte. It provides general status information about the device. It is followed by 2 data bytes (i.

e. ‘ In-frame-response’ ).

For Write cycles the <Global Status> Byte is followed by the previous content of the addressed register.

Figure 9. Write and read SPI

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26/42 DS12615 Rev 4

L99MOD50XP Functional description of the SPI

Table 19. SPI frame

Command byte Data byte

Bit

Name

23

OC

1

22 21 29 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OC0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Ocx: Operation code

Ax: Address

Dx: Data Bit

4.2.1

4.3

Each communication frame starts with a command byte. It consists of an operating code which specifies the type of operation ( <Read>, <Write>, <Read and Clear>, <Read Device

Information> ) and a 6 bit address. If less than 6 address bits are required, the remaining bits are unused but are reserved.

Operation code definition

OC1

0

0

1

1

OC0

0

1

0

1

Table 20. Operation code definition

Meaning

<Write Mode>

<Read Mode>

<Read and Clear Mode>

<Read Device Information>

The <Write Mode> and <Read Mode> operations allow access to the RAM of the device.

A <Read and Clear Mode> operation is used to read a status register and subsequently clear its content.

The <Read Device Information> allows access to the ROM area which contains device related information such as <ID-Header>, <Product Code>, <Silicon Version and Category> and <SPI-frame-ID>.

Global status byte

Bit 7 6

Name GL_ER CO_ER

Reset 0 0

Table 21. Global status byte

5 4 3

C_RESET

1

TSD

0

TW

0

2 1

UOV_OC OL

0 0

0

NR

0

DS12615 Rev 4 27/42

41

Functional description of the SPI L99MOD50XP

Description:

 GL_ER: Global Error Flag. Failures of Bits 0-6 are always linked to the Global Error

Flag. This flag is generated by an OR combination of all failure events of the device. It is reflected via the DO pin while CSN is held low and no clock signal is available. The flag remains as long as CSN is low. This operation does not cause the Communication

Error bit in the <Global Status> to be set. The signal TW bit3 and OL bit1can be masked.

 CO_ER: Communication Error. If the number of clock pulses within the previous frame is not 24 the frame is ignored and this bit is set.

 C_RESET: Chip RESET. If a stuck at ‘1’ on input DI during any SPI frame occurs, or if a

Power On Reset (VCC monitor) occurs. C_RESET resets (‘1’) with any SPI command.

When C_RESET is active (‘0’), the Gate drivers are switched off (resistive path to source).

After a startup of the circuit the C_RESET is active because of the POR pulse and the

Gate drivers are switched off. The Gate drivers can only be activated after the

C_RESET has been reset with a SPI command.

 TSD: Thermal shutdown due to an internal sensor. All the gate drivers and the charge pump are switched off (resistive path to source). The TSD bit has to be cleared through a software reset to reactivate the gate drivers and the charge pump.

 TW: Thermal Warning. This bit is maskable by configuration register.

 UOV_OC: Logical OR among the filtered under-/over-voltage signals and over-current signals.

 OL: Open Load. Logical OR among the filtered under-current signals. This bit is maskable by configuration register.

 NR: Not Ready. After switching the device from standby mode to active mode an internal timer is started to allow charge-pump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished.

Figure 10. Global error flag definition

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28/42 DS12615 Rev 4

L99MOD50XP Functional description of the SPI

Address

00h

01h

02h

03h

10h

11h

12h

3Fh

Name

Table 22. RAM memory map

Access Content

Control register 0

Control register 1

Control register 2

Control register 3

Status register 0

Status register 1

Read/write Enable of device and bridge control

Read/write High/low-side control and Electrocrome block set up

Read/write

Read/write

Read only

Read only

Bridge recovery mode and PWM set up and Electrocrome block set up

High-side recovery mode and PWM set up and current monitor selection

Bridge over-current diagnosis

Bridge open load (under-current) diagnosis

Status register 2 Read only

Open load (under-current) diagnosis, VS and electrocrome diagnosis

Configuration register Read/write Mask of bits in global status register and for global error bit

Address

00h

01h

02h

03h

3Eh

Name

ID header

Version

Product code 1

Product code 2

SPI-frame ID

Table 23. ROM memory map

Access

Read only

Read only

Read only

Read only

Read only

Content

4300h (ASSP ST_SPI)

0300h

4300h (67 ST_SPI)

4800h (H ST_SPI)

0200h SPI-Frame-ID register (ST_SPI)

DS12615 Rev 4 29/42

41

SPI - control and status registers

5 SPI - control and status registers

L99MOD50XP

5.1 Control register 0

Bit Name

3

2

1

5

4

7

6

15 OUT1 – HS on/off

14 OUT1 – LS on/off

13 OUT2 – HS on/off

12 OUT2 – LS on/off

9

8

11 OUT3 – HS on/off

10 OUT3 – LS on/off

OUT4 – HS on/off

OUT4 – LS on/off

OUT5 – HS on/off

OUT5 – LS on/off

OUT6 – HS on/off

OUT6 – LS on/off

0

0

0

Table 24. Control register 0 (read/write)

Comment

If a bit is set the selected output driver is switched on. If the corresponding PWM enable bit is set the driver is only activated if PWM1 (PWM2) input signal is high. The outputs of OUT1-OUT6 are half bridges. If the bits of HS- and LS-driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from Vs to

GND.

Reserved (has to be set to '0')

0 Enable bit

If enable bit is set the device will be switched in active mode. If enable bit is cleared, the device enters standby mode and all bits are cleared.

5.2

Bit

15

14

13

12

Control register 1

Name

OUT7 – HS1 on/off

OUT7/8

Table 25. Control register 1 (read/write)

Comment

OUT7 – HS2 on/off

OUT8 – HS1 on/off

OUT8 – HS2 on/off

HS1 HS2

1

1

1

0

0

0

1

0

Mode

Off

Low on-resistance

High on-resistance

Off

30/42 DS12615 Rev 4

L99MOD50XP SPI - control and status registers

Bit

11

10

9

8-1

0

Name

OUT9 – HS on/off

OUT10 – HS on/off

OUT11 – HS on/off

Reserved

0

Table 25. Control register 1 (read/write) (continued)

Comment

If a bit is set, the selected output driver is switched on. If the corresponding PWM enable bit is set the driver is only activated if PWM1 (PWM2) input signal is high. The outputs of

OUT1-OUT6 are half bridges. If the bits of HS- and LS-driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from VS to GND.

Reserved (has to be set to '0')

Reserved (has to be set to '0')

Bit

1

0

3

2

5

4

7

6

9

8

11

10

15

14

13

12

5.3 Control register 2

Name

OUT1 – OCR enable

OUT2 – OCR enable

OUT3 – OCR enable

OUT4 – OCR enable

OUT5 – OCR enable

OUT6 – OCR enable

0

0

OUT1 PWM1 enable

OUT2 PWM1 enable

OUT3 PWM1 enable

OUT4 PWM1 enable

OUT5 PWM2 enable

OUT6 PWM1 enable

Reserved

Reserved

Table 26. Control register 2 (read/write)

Comment

In case of an over-current event the over-current status bit (Status Register 0) is set and the output is switched off. If the Over-current Recovery Enable bit (OCR) is set, the output will be automatically reactivated after a delay time resulting in a

PWM modulated current with a programmable duty cycle (bit 5 of control register

3).

Depending on occurrence of over-current event and internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero.

Reserved (has to be set to '0')

Reserved (has to be set to '0')

If the PWM1/2 Enable bit is set and the output is enabled (control register 0 or 1) the output is switched on if PWM1/2 input is high and switched off if PWM1/2 input is low. OUT5, 8 and OUT10 are controlled by PWM2 input, all other outputs are controlled by PWM1 input.

Reserved

DS12615 Rev 4 31/42

41

Bit

9

8

11

10

7

6

15

14

13

12

SPI - control and status registers

5.4

5

4

3

2

1

0

Control register 3

L99MOD50XP

Name

OUT7-OCR enable

OUT8-OCR enable

OUT9-OCR enable

OUT10-OCR enable

OUT11-OCR enable

OUT7 PWM1 enable

OUT8 PWM2 enable

OUT9 PWM1 enable

OUT10 PWM2 enable

OUT11 PWM1 enable

OCR frequency

0: 1.7 kHz

1: 3 kHz

Table 27. Control register 3 (read/write)

Comment

In case of an over-current event the over-current status bit (Status register 1) is set and the output is switched off. If the Over-current Recovery Enable bit

(OCR) is set the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (bit 5).

Depending on the occurrence of the over-current event and the internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero.

If the PWM1/2 Enable bit is set and the output is enabled (control register 0 or

1) the output is switched on if PWM1/2 input is high and switched off if

PWM1/2 input is low. OUT5, 8 and OUT10 are controlled by PWM2 input all other outputs are controlled by PWM1 input.

This bit defines in combination with the over-current recovery bit (Input

Register 1) the over-current recovery frequency of an activated driver.

OV/UVR disable

If this bit is set the microcontroller has to clear the status register after undervoltage/overvoltage event to enable the outputs.

Depending on combination of bit 3 to 0 the current image of the selected high-side output OUTn will be multiplexed to the CM/PWM2 output (see table below).

Other combinations deactivate the current monitor.

CM select bit 3

CM select bit 2

CM select bit 1

CM select bit 0

Bit 3

0

0

0

0

0

0

0

1

1

0

1

Bit 2

1

1

0

1

0

0

0

0

0

1

0

Bit 1

0

1

1

0

0

0

1

0

1

1

0

Bit 0

1

0

1

0

0

1

0

1

0

1

0

Current image of

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

OUT11

32/42 DS12615 Rev 4

L99MOD50XP SPI - control and status registers

Bit

1

0

3

2

5

4

7

6

9

8

11

10

15

14

13

12

5.5 Status register 0

Name

OUT1 – HS OC

OUT1 – LS OC

OUT2 – HS OC

OUT2 – LS OC

OUT3 – HS OC

OUT3 – LS OC

OUT4 – HS OC

OUT4 – LS OC

OUT5 – HS OC

OUT5 – LS OC

OUT6 – HS OC

OUT6 – LS OC

0

0

0

0

Table 28. Status register 0 (read)

Comment

In case of an over-current event the corresponding status bit is set and the output driver is disabled. If the over-current Recovery Enable bit is set the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle.

If the over-current recovery bit is not set, the micro controller has to clear the overcurrent bit to reactivate the output driver.

Reserved

Bit

9

8

11

10

15

14

13

12

5

4

7

6

5.6 Status register 1

Name

OUT1 – HS UC

OUT1 – LS UC

OUT2 – HS UC

OUT2 – LS UC

OUT3 – HS UC

OUT3 – LS UC

OUT4 – HS UC

OUT4 – LS UC

OUT5 – HS UC

OUT5 – LS UC

OUT6 – HS UC

OUT6 – LS UC

Table 29. Status register 1 (read)

Maskable by the configuration register

Comment

The open load detection monitors the load current in each activated output stage. If the

(t dOL corresponding under-current bit UC is set. Due to mechanical/electrical inertia of

), the typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open load status without changing the mechanical/electrical state of the loads.

DS12615 Rev 4 33/42

41

SPI - control and status registers

Table 29. Status register 1 (read) (continued)

Comment Bit

1

0

3

2

Name

0

0

0

0

Reserved

L99MOD50XP

Bit

9

8

11

10

15

14

13

12

5

4

7

6

3

2

1

0

5.7 Status register 2

Table 30. Status register 2 (read)

Comment Name

OUT7 – OC

OUT7 – UC

OUT8 – OC

OUT8 – UC

OUT9 – OC

OUT9 – UC

OUT10 – OC

OUT10 – UC

OUT11 – OC

OUT11 – UC

Reserved

Reserved

VS under-voltage

VS over-voltage

0

0

In case of an over-current event the corresponding status bit OC is set and the output driver is disabled. If the over-current recovery enable bit is set the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle.

If the over-current recovery bit is not set the micro controller has to clear the overcurrent bit to reactivate the output driver.

The open load detection monitors the load current in each activated output stage. If the dOL corresponding under-current bit UC is set. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without changing the mechanical/electrical state of the loads.

In case of an over-voltage or under-voltage event the corresponding bit is set and the outputs are deactivated. If VS voltage recovers to normal operating conditions outputs are reactivated automatically (if bit 4 of control register 3 is not set).

Reserved

34/42 DS12615 Rev 4

L99MOD50XP SPI - control and status registers

3

2

1

0

Bit

9

8

11

10

7

6

15

14

13

12

5

4

Name

Table 31. Configuration register (read/write)

Comment

0

0

0

0

0

0

0

0

0

0

Mask for bit 15 of status reg. 1

Mask for bit 14 of status reg. 1

Mask for bit 3 of global status reg.

0

Mask for bit 1 of global status reg.

0

Reserved (has to be set to '0')

Open-load event (under-current status bit of OUT1 HS) is not considered in open-load bit 1 of global status register.

Open-load event (under-current status bit of OUT1 LS) is not considered in open-load bit 1 of global status register.

Temperature warning event is not considered in the 'Global Error Flag'.

Reserved (has to be set to '0')

Open-load event (under-current status bit of OUTn) is not considered in the

'Global Error Flag'.

Reserved (has to be set to '0')

DS12615 Rev 4 35/42

41

Package and PCB thermal data

6 Package and PCB thermal data

6.1 PowerSSO-36 thermal data

Figure 11. PowerSSO-36 2 layer PCB

L99MOD50XP

Figure 12. PowerSSO-36 4 layer PCB

Note: Layout condition of R th

and Z th

measurements (board finish thickness 1.6 mm ±10%, board double layer and four layers, board dimension 129 mm x 60 mm, board material FR4, Cu thickness 0.070 mm (outer layers), Cu thickness 0.035 mm (inner layers), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm ±0.08 mm, Cu thickness on vias

0.025

mm, footprint dimension 4.1 mm x 6.5 mm). 4-layer PCB: Cu on mid1 and mid2 layer:

76.45 cm 2 . Cu on bottom layer: 68.8 cm 2 . Z th contributor.

measured on the major power dissipator

36/42 DS12615 Rev 4

L99MOD50XP Package and PCB thermal data

Figure 13. PowerSSO-36 thermal impedance junction to ambient vs PCB copper area

DS12615 Rev 4 37/42

41

Package and packing information

7 Package and packing information

L99MOD50XP

7.1 ECOPACK

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK is an ST trademark.

Figure 14. PowerSSO-36 package dimensions

38/42

Symbol

A

A2 a1 b c

D

(1)

Table 32. PowerSSO-36 mechanical data

Millimeters

Min.

Typ.

-

2.15

0

0.18

0.23

10.10

-

-

-

-

-

-

DS12615 Rev 4

Max.

2.45

2.35

0.1

0.36

0.32

10.50

L99MOD50XP Package and packing information

Symbol

O

Q

M

N k

L

H h

U

X

S

T

Y

F

G

G1

E e e3

Table 32. PowerSSO-36 mechanical data (continued)

Millimeters

Min.

7.4

-

-

-

-

-

10.1

-

0°

0.55

-

-

-

-

-

-

-

4.3

6.9

Typ.

-

0.5

8.5

2.3

-

-

-

-

-

-

4.3

-

1.2

0.8

2.9

3.65

1

-

-

-

-

-

10°

10.5

0.4

8°

0.85

-

5.2

-

-

7.5

Max.

7.6

-

0.1

-

-

0.06

1.

“D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side (0.006”).

DS12615 Rev 4 39/42

41

Package and packing information L99MOD50XP

Figure 15. PowerSSO-36 tape and reel shipment (suffix “TR”)

Reel dimensions

Base Qty

Bulk Qty

A (max)

B (min)

C (±0.2)

F

G (+2 / -0)

N (min)

T (max)

1000

1000

330

1.5

13

20.2

24.4

100

30.4

Tape dimensions

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

W

P0 (±0.1)

D1 (min)

F (±0.1)

K (max)

P1 (±0.1)

24

4

P 12

D (±0.05) 1.55

1.5

11.5

2.85

2

All dimensions are in mm.

End

Top cover tape

No components Components

500mm min 500mm min

Empty components pockets sealed with cover tape.

Start

No components

User direction of feed

40/42 DS12615 Rev 4

L99MOD50XP

8 Revision history

Revision history

Date

18-Sep-2018

07-Nov-2018

17-Jun-2019

08-Oct-2019

Revision

Table 33. Document revision history

Description of changes

1

2

3

4

Initial release.

Added Section 6: Package and PCB thermal data .

Updated the maturity from target specification to production data.

Updated

Applications

on cover page.

Updated

Table 2: Pin definition and functions .

Updated Section Select

and

4.3: status byte .

Minor text changes

DS12615 Rev 4 41/42

41

L99MOD50XP

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42/42 DS12615 Rev 4