STMicroelectronics L99MOD54XP Datasheet

L99MOD54XP

Multi-output driver for automotive applications

Datasheet

-

production data

 Charge pump output for reverse polarity protection

Applications

L99MOD devices are recommended for those applications that need multiple motors control with additional loads in high-side configuration, such as bulbs/LEDs or requiring protected supply, like sensors or cameras.

Description

Features

 AEC-Q100 qualified

The L99MOD54XP is a microcontroller-driven multifunctional actuator driver for automotive applications.

 Three half bridges for

0.75

A loads (R

DSon m Ω 

 Two configurable high-side drivers for up to

1.5

(R

A load (R

DSon

DSon

500 m Ω ) m Ω  or  0.35

Up to two DC motors and three grounded resistive loads can be driven with three half bridges and three high-side drivers.

The integrated SPI controls all operating modes

 One high-side driver for 6



(R

DSon

100 m Ω )

Programmable soft start function to drive loads

Also all diagnostic information is available via SPI read.

with higher inrush currents (i.e. current current

 Very low current consumption in standby mode

(I

S

< 6 μ A typ; T j

 85 °C)

 All outputs short circuit protected

 Current monitor output for high-side OUT1,

OUT4, OUT5 and OUT6

 All outputs over temperature protected

 Open-load diagnostic for all outputs

 Overload diagnostic for all outputs

 PWM control of all outputs

Table 1. Device summary

Package Order codes Packing

PowerSSO-36 L99MOD54XPTR Tape and reel

October 2019

This is information on a product in full production.

DS12616 Rev 4

1/35

www.st.com

1

2

Contents

Contents

3

4

L99MOD54XP

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5

SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1

Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2

Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3

Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.4

Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5

Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.6

Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.7

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 20

3.8

Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9

Overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.10

Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.11

PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.12

Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.13

Programmable soft start function to drive loads with higher inrush current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2

Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3

Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4

Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5

Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.6

Input Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2/35

DS12616 Rev 4

L99MOD54XP

5

6

7

Contents

4.7

Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.8

SPI - input data and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1

PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.1

ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.2

PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.3

PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

DS12616 Rev 4

3/35

3

List of tables

List of tables

L99MOD54XP

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9.

Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10.

Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 11.

OUT1 - OUT6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 12.

Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 13.

Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 14.

DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 15.

DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 16.

DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 17.

CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 18.

SPI - input data and status registers 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 19.

SPI - input data and status registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 20.

PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 21.

Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4/35

DS12616 Rev 4

L99MOD54XP

List of figures

List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.

SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 4.

SPI - input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5.

SPI - DO valid data delay time and valid time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6.

SPI - DO enable and disable time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7.

SPI - driver turn-on / off timing, minimum CSN HI time . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8.

SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9.

Programmable soft start function for inductive loads and incandescent bulbs . . . . . . . . . . 22

Figure 10.

PowerSSO-36 2 layer PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 11.

PowerSSO-36 4 layer PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12.

PowerSSO-36 thermal impedance junction to ambient vs PCB copper area . . . . . . . . . . . 30

Figure 13.

PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 14.

PowerSSO-36

tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DS12616 Rev 4

5/35

5

Block diagram and pin description

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6/35

DS12616 Rev 4

L99MOD54XP Block diagram and pin description

Figure 2. Configuration diagram (top view)

PowerSSO-36

Pin Symbol

Table 2. Pin definitions and functions

Function

1, 18, 19, 36

2, 35

3

4

5

6, 7, 14, 25, 28,

32

8

GND

OUT6

Ground: reference potential.

Important: for the capability of driving the full current at the outputs all pins of

GND must be externally connected.

High-side driver output 6

The output is built by a high-side switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. The high-side driver is a power DMOS transistor with an internal parasitic reverse diode from the output to V

S open-load protected.

(bulk-drain-diode). The output is over-current and

Important: for the capability of driving the full current at the outputs both pins of

OUT6 must be externally connected.

OUT1 OUT2

OUT3

Half-bridge output 1,2,3

The output is built by a high-side and a low-side switch, which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to V

S

, switchs driver from GND to output). This output is over-current and open-load protected.

V

S

DI

Power supply voltage (external reverse protection required)

For this input a ceramic capacitor as close as possible to GND is recommended.

Important: for the capability of driving the full current at the outputs all pins of V

S must be externally connected.

Serial data input

The input requires CMOS logic levels and receives serial data from the microcontroller. The data is a 24bit control word and the least significant bit (LSB,

DS12616 Rev 4

7/35

34

Block diagram and pin description L99MOD54XP

Pin

9

10

11

12

13

26

27

31

33

15, 16, 17, 20,

21, 22, 23, 24,

29, 30, 34

Table 2. Pin definitions and functions (continued)

Symbol Function

CM/PWM2

CSN

DO

V

CC

CLK

CP

PWM1

OUT4,

OUT5

Current monitor output/PWM2 input

Depending on the selected multiplexer bits of input data register this output sources an image of the instant current through the corresponding high-side driver with a ratio of 1/10.000. This pin is bidirectional. The microcontroller can overdrive the current monitor signal to provide a second PWM input for the output

OUT5.

Chip select not input

This input is low active and requires CMOS logic levels. The serial data transfer between L99MOD54XP and micro controller is enabled by pulling the input CSN to low-level.

Serial data output

The diagnosis data is available via the SPI and this 3-state output. The output remains in 3-state, if the chip is not selected by the input CSN (CSN = high)

Logic supply voltage

For this input a ceramic capacitor as close as possible to GND is recommended.

Serial clock input

This input controls the internal shift register of the SPI and requires CMOS logic levels.

Charge pump output

This output is provided to drive the gate of an external n-channel power MOS used for reverse polarity protection.

PWM1 input

This input signal can be used to control the drivers OUT1-OUT4 and OUT6 by an external PWM signal.

High-side driver output 4 and 5

Each output is built by a high-side switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. Each high-side driver is a power DMOS transistor with an internal parasitic reverse diode from each output to V

S over-current and open-load protected.

(bulk-drain-diode). Each output is

NC Not connected pins.

8/35

DS12616 Rev 4

L99MOD54XP Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality document

Symbol

V

S

V

CC

V

DI

, V

DO,

V

CLK

,

V

CSN,

V pwm1

V

CM

V

CP

I

OUT1,2,3,4,5

I

OUT6

Table 3. Absolute maximum ratings

Parameter

DC supply voltage

Single pulse t max

Stabilized supply voltage, logic supply

Value

-0.3 to 28

40

-0.3 to 5.5

Digital input / output voltage

Current monitor output

Charge pump output

Output current

Output current

-0.3 to V

CC

+ 0.3

-0.3 to V

CC

+ 0.3

-25 to V

S

+ 11

±5

±10

A

A

V

V

Unit

V

V

V

V

Table 4. ESD protection

Parameter

All pins

Output pins: OUT1 - OUT6

1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.

2. HBM with all unzapped pins grounded.

Value

 2

(1)

 8

(2)

Unit kV kV

Symbol

T j

Table 5. Operating junction temperature

Parameter

Operating junction temperature

Value

-40 to 150

Unit

°C

DS12616 Rev 4

9/35

34

Electrical specifications L99MOD54XP

Symbol

T jTW On

T jSD On

T jSD Off

T jSD HYS

Table 6. Temperature warning and thermal shutdown

Parameter

Min.

Temperature warning threshold junction temperature

T j

130

Thermal shutdown threshold junction temperature T j

increasing

Thermal shutdown threshold junction temperature T j

decreasing 150

Thermal shutdown hysteresis

Typ.

Max.

Unit

150

170

5

°C

°C

°C

°K

Values specified in this section are for V

S

V, V

CC

= 4.5 to 5.3

V, T j

= - 40 to 150 °C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

Symbol

V

S

Parameter

Operating supply voltage range

Table 7. Supply

Test condition Min.

7

Typ.

Max.

Unit

28 V

I

S

I

CC

V

S

DC supply current

V

S

quiescent supply current

V

CC

DC supply current

V

CC

quiescent supply current

I

S

+ I

CC

Sum quiescent supply current

V

S active mode

OUT1 - OUT6 floating

V

V

S

V, V standby mode

OUT1 - OUT6 floating

T test

= -40

T test

= 85

V

S

V

CSN = V

CC , active mode

V

S

V

CSN = V

CC standby mode

OUT1 - OUT6 floating

V

S

CSN = V

CC standby mode

OUT1 - OUT6 floating

V

T test

°C

7

4

6

1

25

50

20

12

25

3

50

200 mA

μ A

μ A mA

μ A

μ A

1. Guaranteed by design.

Symbol

V

SUV On

V

SUV Off

Table 8. Overvoltage and under voltage detection

Parameter Test condition Min.

V

S

UV-threshold voltage

V

S

UV-threshold voltage

V

S

increasing

V

S

decreasing

5.7

5.5

Typ.

Max.

Unit

7.2

6.9

V

V

10/35

DS12616 Rev 4

L99MOD54XP Electrical specifications

Symbol

Table 8. Overvoltage and under voltage detection (continued)

Parameter

V

SUV hyst

V

SOV Off

V

SOV On

V

SOV hyst

V

POR Off

V

POR On

V

POR hyst

V

S

UV-hysteresis

V

S

OV-threshold voltage

V

S

OV-threshold voltage

V

S

OV-hysteresis

Power-on reset threshold

Power-on reset threshold

Power-on reset hysteresis

Test condition

V

SUV On

- V

SUV Off

V

S

increasing

V

S

decreasing

V

SOV Off

- V

SOV On

V

CC

increasing

V

CC

decreasing

V

POR Off

- V

POR On

Min.

18

17.5

3.1

Typ.

Max.

Unit

0.5

1

0.3

24.5

23.5

4.4

V

V

V

V

V

V

V

Symbol

V

CM

I

CM,r

I

CM acc

Table 9. Current monitor output

Parameter

Functional voltage range

Current monitor output ratio:

I

CM

/ I

OUT6

Current monitor output ratio:

I

CM

/ I

OUT1

Current monitor output ratio:

I

CM

/ I

OUT4,5 low R

DSon

mode

Current monitor output ratio:

I

CM

/ I

OUT4,5 high R

DSon

mode

Test condition

V

CC

= 5 V

0 V V

CM

 V

CC

Current monitor accuracy

Acc I

CM

/ I

OUT 8

Current monitor accuracy

Acc I

CM

/ I

OUT 1

Current monitor accuracy

Acc I

CM

/ I

OUT 4,5 high R

DSon

mode

Current monitor accuracy

Acc I

CM

/ I

OUT 4,5 low R

DSon

mode

0 V  V

CM

 3.8

V

CC

I

Out,min 8

I

Out max 8

0 V  V

CM

 3.8

V

CC

= 5V,

I

Out,min 1

I

Out max 1

0 V  V

CM

 3.8

V

CC

I

Out,min 4,5

= 30 mA,

I

Out max 4,5

= 300 mA

0 V  V

CM

 3.8

V

CC

I

Out,min 4,5

= 150 mA,

I

Out max 4,5

1.

FS (full scale)= I

OUTmax *

I

CMr_typ

.

Min.

0

-8%

-2%FS

(1)

Typ.

10000

3800

10200

2400

Max.

Unit

4 V

-

8% +

2%FS

A

DS12616 Rev 4

11/35

34

Electrical specifications L99MOD54XP

Symbol

V

CP

I

CP

Parameter

Table 10. Charge pump output

Test condition

Charge pump output voltage

V

S

= 8 V, I

CP

= -60 μ A

V

S

μ A

V

S

 12 I

CP

= -100 μ A

Charge pump output current V

CP

= V

S S

Min.

V

S

+6

V

S

+8

V

S

+10

95

Typ.

150

Max.

V

S

+13

V

S

+13

V

S

+13

300

Unit

V

μ A

V

V

Symbol Parameter

Table 11. OUT1 - OUT6

Test condition

R

R

R

DSon OUT1,

DSon OUT2

DSon OUT3

R

DSon OUT4,

R

DSon OUT5

R

DSon OUT6

On resistance to supply or

GND

On resistance to supply in low

R

DSon mode

On resistance in high R mode

DSon

On resistance to supply

V

S

= 13.5 V, T j

= 25 °C,

I

OUT1,2,3

=  0.4

A

I

V

S

= 13.5 V, T j

OUT1,2,3

= 125 °C,

=  0.4 A

V

S

= 13.5 V, T j

= 25 °C,

I

OUT4,5

= -0.8 A

V

S

= 13.5 V, T j

= 125 °C,

I

OUT4,5

= -0.8 A

T j

= 25 °C, I

OUT4,5

= - 0.2 A

T j

= 125 °C, I

OUT4,5

= - 0.2 A

I

V

S

= 13.5 V, T j

OUT6

=  3 A

= 25 °C,

I

V

S

= 13.5 V, T j

OUT6

=  3 A

= 125 °C,

I

OUT1

I

OUT2

I

OUT3

I

OUT1

I

OUT2

I

OUT3

Output current limitation to

GND

Output current limitation to supply

Source, V

Sink, V

S

S

= 13.5 V

I

I

I

OUT4

OUT5

OUT6

Output current limitation to

GND in low R

DSon mode

Output current limitation to

GND in high R

DSon mode

Output current limitation to

GND

Source, V

Source, V

S

S

= 13.5 V

= 13.5 V t d On H

Output delay time, high-side driver on

V

S

= 13.5 V, R load

=

(1) corresponding low-side driver is not active t d Off H

Output delay time, high-side driver off

V

S

= 13.5 V, R load

=

(2)

Min.

-1.25

0.75

-3.0

-0.65

-10.5

10

15

Typ.

Max.

Unit

1600 2200

2500 3400

500 700

700 950

2000 2700

3200 4300

100 150

150

40

150

200

-0.75

1.25

-1.5

-0.35

-6

80

300 m  m  m  m  m  m  m  m 

A

A

A

A

A

μ s

μ s

12/35

DS12616 Rev 4

L99MOD54XP Electrical specifications

Symbol Parameter

Table 11. OUT1 - OUT6 (continued)

Test condition

I

I t t d On L t t d Off L

I

I d HL d LH

QLH

QLL

OLD123

I

OLD45 t

OLD6 d OL

Output delay time, low-side driver on

V

S

= 13.5 V, R load

=

(2)

corresponding high-side driver is not active

Output delay time, low-side driver off

V

S

= 13.5 V, R load

=

(2)

Cross current protection time, source to sink t

CC ONLS_OFFHS

- t d Off H

(2)

Cross current protection time, sink to source t

CC ONHS_OFFLS

- t d OFF L

(2)

Switched-off output current high-side drivers of OUT1-6

Switched-off output current low-side drivers of OUT1-3

V

OUT1-6

= 0 V, standby mode

V

OUT1-2-3-6

= 0 V, active mode

V

OUT4-5

= 0 V, active mode

V

OUT1-3

= V

S

, standby mode

V

OUT1-3

= V

S

, active mode

Open-load detection current of OUT1, OUT2 and OUT3

Source and sink

Open-load detection current of OUT4 and OUT5

Open-load detection current of OUT4 and OUT5 in high

R

DSon mode

Open-load detection current of OUT6

Minimum duration of openload condition to set the status bit

Source

Source f f t

ISC rec0 rec1

Minimum duration of overcurrent condition to switch off the driver

Recovery frequency for OC recovery duty cycle bit=0

Recovery frequency for OC recovery duty cycle bit=1 dV

OUT123

/dt dV

OUT45

/dt

Slew rate of OUT

OUT

45

123 dV

OUT6

/dt Slew rate of OUT

6

and

V

S

V

S load

=

(2)

load

=

(2)

1. OUT1,2,3 32 Ω

OUT4,5 16 Ω

OUT4,5 high RDSon mode 63 Ω

OUT6 4 Ω

2. t

CC ON is the switch On delay time t d ON

if complement in half bridge has to switch off.

Min.

15

20

10

15

5

30

500

10

1

2

0.1

0.08

-3

-40

-10

0

-40

Typ.

Max.

Unit

30

150

200

200

0

-15

-8

80

-15

20

40

10

150

0.4

0.2

70

300

400

400

-3

0

0

120

0

30

60

15

300

3000

100

4

6

0.9

0.4

μ s

μ s

μ s

μ s

μ A

μ A

μ A

μ A

μ A mA mA mA mA

μ s

μ s kHz kHz

V/ μ s

V/ μ s

DS12616 Rev 4

13/35

34

Electrical specifications L99MOD54XP

2.5

Symbol t set

SPI - electrical characteristics

Values specified in this section are V

S

= 8 to 16 V, V

CC

= 4.5 to 5.3

V, T j

= - 40 to 150 °C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

Parameter

Table 12. Delay time from standby to active mode

Test condition Min. Typ.

Delay time

Switching from standby to active mode. Time until output drivers are enabled after CSN going to high.

160

Max.

300

Unit

μ s

Symbol

Table 13. Inputs: CSN, CLK, PWM1/2 and DI

Parameter Test condition Min. Typ.

V inL

V inH

V inHyst

I

CSN in

Input low-level

Input high-level

Input hysteresis

Pull up current at input CSN

V

CC

= 5 V

V

CC

= 5 V

V

CC

= 5 V

V

CSN

= 3.5 V, V

CC

= 5 V

1.5

0.5

-40

I

CLK in

I

DI in

Pull down current at input CLK

Pull down current at input DI

V

CLK

= 1.5 V

V

DI

= 1.5 V

10

10

I

PWM1 in

C in

(1)

Pull down current at input PWM1 V

PWM

= 1.5 V

Input capacitance at input CSN,

CLK, DI and PWM1/2

0 V < V

CC

< 5.3 V

10

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

2.0

3.0

10

-20

25

25

25

Max.

3.5

-5

50

50

50

15

Unit

μ A

μ A

μ A

V

V

V

μ A pF

Symbol t

CLK t

CLKH t

CLKL t set CSN t set CLK t set DI t hold DI

Parameter

(1)

Table 14. DI timing

Test condition

Clock period

Clock high time

V

CC

= 5 V

V

CC

= 5 V

Clock low time V

CC

= 5 V

CSN setup time, CSN low before rising edge of CLK

V

CC

= 5 V

CLK setup time, CLK high before rising edge of CSN

V

CC

= 5 V

DI setup time

DI hold time

V

CC

= 5 V

V

CC

= 5 V

Min. Typ.

1000

400

400 -

-

-

400 -

400

200

200 -

-

-

Max.

Unit ns ns ns ns ns ns ns

14/35

DS12616 Rev 4

L99MOD54XP Electrical specifications

Symbol Parameter

(1)

Table 14. DI timing (continued)

Test condition t r in

Rise time of input signal DI, CLK, CSN V

CC

= 5 V t f in

Fall time of input signal DI, CLK, CSN V

CC

= 5 V

1. DI timing parameters tested in production by a passed / failed test:

Tj = -40 °C / +25 °C:

Tj = +125 °C

SPI communication @ 2 MHz.

SPI communication @ 1.25 MHz.

Min. Typ.

-

-

Max.

100

100

Unit ns ns

Symbol Parameter

Table 15. DO

Test condition Min.

Typ.

I

C

V

V

DOL

DOH

DOLK

DO

(1)

Output low-level

Output high-level

3-state leakage current

3-state input capacitance

V

CC

= 5 V, I

D

V

CC

= 5 V, I

D

V

CSN

= V

CC

,

0V < V

DO

< V

CC

V

CSN

= V

CC

,

0 V < V

CC

< 5.3

V

V

CC

- 0.4

V

-10

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

0.2

CC

- 0.2

10

Max.

Unit

0.4

V

V

10 μ A

15 pF t t t

Symbol t r DO t f DO en DO tri L dis DO L tri en DO tri H t dis DO H tri t d DO

Parameter

DO rise time

DO fall time

DO enable time from 3-state to low-level

DO disable time from low-level to 3-state

DO enable time from 3-state to high-level

DO disable time from high-level to 3-state

DO delay time

Table 16. DO timing

Test condition

C

L

= 100 pF, I load

C

L

= 100 pF, I load

C

L

= 100 pF, I load pull up load to V

CC

C

L

= 100 pF, I load

= 4 mA pull up load to V

CC

C

L

=100 pF, I load pull down load to GND

C

L

= 100 pF, I load to GND load

V

DO

C

L

< 0.3 V

CC

, V

DO

> 0.7

= 100pF

V

CC

,

-

-

-

-

Min.

Typ.

Max.

Unit

-

80

50

140

100 ns ns

100 250 ns

380 450

100 250 ns ns

380

50

450

250 ns ns

Symbol t

CSN_HI,stb t

CSN_HI,min

Parameter

CSN HI time, switching from standby mode

CSN HI time, active mode

Table 17. CSN timing

Test condition

Transfer of SPI command to

Input Register

Transfer of SPI command to input register

Min.

20

4

Typ.

Max.

-

Unit

μ s

μ s

DS12616 Rev 4

15/35

34

Electrical specifications

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16/35

DS12616 Rev 4

L99MOD54XP Electrical specifications

Figure 5. SPI - DO valid data delay time and valid time

Figure 6. SPI - DO enable and disable time

DS12616 Rev 4

17/35

34

Electrical specifications L99MOD54XP

Figure 7. SPI - driver turn-on / off timing, minimum CSN HI time

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DS12616 Rev 4

L99MOD54XP Application information

3.1 Dual power supply: V

S

and V

CC

The power supply voltage V

S

supplies the half bridges and the high-side drivers. An internal charge-pump is used to drive the high-side switches. The logic supply voltage V

(stabilized 5 V) is used for the logic part and the SPI of the device.

CC

Due to the independent logic supply voltage the control and status information is not lost, if there are temporary spikes or glitches on the power supply voltage. In case of power-on

(V

CC

increases from under voltage to V minimum threshold (V

POR ON and the status registers are cleared.

POR Off

= 4.2 V) the circuit is initialized by an internally generated power-on-reset (POR). If the voltage V

CC

decreases under the

= 3.4 V), the outputs are switched to 3-state (high impedance)

The standby mode of the L99MOD54XP is activated by clearing the bit 23 of the input data register 0. All latched data is cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at V

S

CSN = high (DO in 3-state). By switching the V

CC

(V

CC

) is less than 6 μ A (50 μ A) for

voltage a very low quiescent current can be achieved. If bit 23 is set, the device is switched to active mode.

Each half bridge is built by an internally connected high-side and a low-side power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT3 without external free-wheeling diodes. The high-side drivers OUT4 to OUT6 are intended to drive resistive loads. Hence only a limited energy

(E<1mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For inductive loads (L>100  H) an external free-wheeling diode connected to GND and the corresponding output is needed.

All diagnostic functions (over/open-load, power supply over-/under voltage, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32 μ s (open-load: 1 ms, respectively) before the corresponding status bit in the status registers is set. The filters are used to improve the noise immunity of the device. Open-load and temperature warning functions are intended for information purpose and don't change the state of the output drivers. On the contrary, the overload condition disables the corresponding driver (over-current) and overtemperature switches off all drivers (thermal shutdown). Without setting the over-current recovery bits in the input data register, the microcontroller has to clear the over-current status bits to reactivate the corresponding drivers.

DS12616 Rev 4

19/35

34

Application information

3.5 Overvoltage and under voltage detection

L99MOD54XP

If the power supply voltage V

S

rises above the overvoltage threshold V

SOV Off

(typical 21 V), the outputs OUT1 to OUT6 are switched to high impedance state to protect the load. When the voltage V

S

drops below the under voltage threshold V

SUV Off

(UV-switch-off voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the supply voltage V

S

recovers (register 0: bit 20=0) to normal operating voltage the outputs stages return to the programmed state after at least 32 μ s.

If the under voltage/overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the drivers. It is strongly recommended to set bit 20 to avoid a possible high current oscillation in case of a shorted output to GND and low battery voltage.

3.7

The charge pump runs under all conditions in normal mode. In standby the charge pump is out of action.

Temperature warning and thermal shutdown

If junction temperature rises above T j TW

a temperature warning flag is set after at least 32

μ s and is detectable via the SPI. If junction temperature increases above the second threshold T j SD

, the thermal shutdown bit is set and power DMOS transistors of all output stages are switched off to protect the device after at least 32 μ s. Temperature warning flag and thermal shutdown bit are latched and must be cleared by the microcontroller. The related bit is only cleared if the temperature decreases below the trigger temperature. If the thermal shutdown bit has been cleared the output stages are reactivated.

The open-load detection monitors the load current in each activated output stage. If the load current is below the open-load detection threshold for at least 1 ms (t dOL

) the corresponding open-load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open-load status without changing the mechanical/electrical state of the loads.

In case of an over-current condition a flag is set in the status register in the same way as open-load detection. If the over-current signal is valid for at least t

ISC

= 32 μ s, the overcurrent flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.

20/35

DS12616 Rev 4

L99MOD54XP Application information

The current monitor output sources a current image at the current monitor output which has a fixed ratio (1/10000) of the instantaneous current of the selected high-side driver. Signal at output CM is blanked after switching on of driver until correct settlement of circuitry (at least for 32 μ s).

The bits 18 and 19 of the input data register 0 control which of the outputs OUT1, OUT4,

OUT5 and OUT6 is multiplexed to the current monitor output. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. For example this can be used to detect the motor state

(starting, free-running, stalled). Moreover, it is possible to regulate the power of the defroster more precisely by measuring the load current. The current monitor output is bidirectional

(c.f. PWM inputs).

Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface. If the PWM enable bit in Input data register 1 is set, the output is controlled by the logically AND-combination of the PWM signal and the output control bit in input data register 0. The outputs OUT1-OUT4 and OUT6 are controlled by the PWM1 input and the output OUT5 is controlled by the bidirectional input CM/PMW2. For example, the two PWM inputs can be used to dim two lamps independently by external PWM signals.

The three half-bridges of the device are cross-current protected by an internal delay time. If one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge is automatically delayed by the cross-current protection time. After the cross-current protection time is expired the slew-rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior it is always guaranteed that the previously activated driver is totally turned-off before the opposite driver starts to conduct.

3.13 Programmable soft start function to drive loads with higher inrush current

Loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable soft start function (i.e. overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set, the device switches-on automatically the outputs again after a programmable recovery time. The duty cycle in overcurrent condition can be programmed by the SPI interface to be about 15 %...25

%. The

PWM modulated current provides sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. The PWM frequency settles at

1.5

kHz or 3 kHz. The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example the microcontroller can switch on light bulbs by setting the over-current recovery bit for the first 50ms. After clearing the recovery bit the output is automatically disabled if the overload condition still exits.

DS12616 Rev 4

21/35

34

Application information L99MOD54XP

Figure 9. Programmable soft start function for inductive loads and incandescent bulbs

22/35

DS12616 Rev 4

L99MOD54XP

4 Functional description of the SPI

Functional description of the SPI

4.1

Note:

Serial Peripheral Interface (SPI)

This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in the following mode: CPOL = 0 and CPHA = 0.

For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.

This device is not limited to microcontroller with a built-in SPI. Only three CMOS compatible output pins and one input pin are needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO pin reflects the status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers 0 and 1. The microcontroller can poll the status of the device without the need of a full SPI communication cycle.

In contrast to the SPI standard the least significant bit (LSB) is transferred first

(see Figure 3 ).

4.2

Note:

Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) is in high impedance state. A low signal activates the output driver and a serial communication can be started. The state when CSN is going low until the rising edge of CSN is called a communication frame.

The device includes a test mode. This mode is activated by a dedicated sequence which includes a high voltage at the CSN pin. The CSN pin must be kept at nominal voltage levels in order to avoid accidental activation of the test mode.

4.3

Note:

4.4

Serial Data In (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI is sampled at the rising edge of the CLK signal and shifted into an internal 24-bit shift register.

At the rising edge of the CSN signal the contents of the shift register is transferred to data input register. The writing to the selected data input register is only enabled if exactly 24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame is ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.

Serial Data Out (DO)

The data output driver is activated by a logical low-level at the CSN input and goes from high impedance to a low or high-level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin transfers the

DS12616 Rev 4

23/35

34

Functional description of the SPI L99MOD54XP content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK shifts the next bit out.

4.5

4.6

Serial Clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input

(DI) is sampled at the rising edge of the CLK and the data output (DO) changes with the falling edge of the CLK signal.

Input Data Register

The device has two input registers. The first bit (bit 0) at the DI input is used to select one of the two input registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register is written to the selected input data register only if a frame of exact 24 data bits is detected. Depending on bit 0 the content of the selected status register is transferred to DO during the current communication frame. Bit

1-17 controls the behavior of the corresponding driver.

If bit 23 is zero, the device goes into the standby mode. The bits 18 and 19 are used to control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status registers. The bits in the status registers are cleared after the current communication frame

(rising edge of CSN).

This device uses two status registers to store and to monitor the state of the device. No error bit (bit 0) is used as a fault bit and is a logical-NOR combination of bits 1-22 in both status registers. The state of this bit can be polled by the microcontroller without the need of a full

SPI communication cycle. If one of the over-current bits is set, the corresponding driver is disabled. If the over-current recovery bit of the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers go into a high impedance state. Again the microcontroller has to clear the bit to enable the drivers.

24/35

DS12616 Rev 4

L99MOD54XP Functional description of the SPI

4.8 SPI - input data and status registers

Table 18. SPI - input data and status registers 0

Input register 0 (write) Status register 0 (read)

Bit

23

22

21

20

19

18

Name Comment Name Comment

Enable bit

Overvoltage/ undervoltage recovery disable

If enable bit is set the device switches in active mode. If enable bit is cleared the device goes into standby mode and all bits are cleared.

After power-on reset device starts in standby mode.

Reset bit

If reset bit is set both status registers are cleared after rising edge of CSN input.

OC recovery duty cycle

0: 12% 1: 25%

This bit defines in combination with the over-current recovery bit (input register 1) the duty cycle in overcurrent condition of an activated driver.

If this bit is set the microcontroller has to clear the status register after under voltage / overvoltage event to enable the outputs.

Depending on combination of bit 18 and 19 the current image (1/10.000) of the selected HS-output is multiplexed to the CM output:

V

V

S

S

Always 1

overvoltage

undervoltage

A broken V frame.

CC

-or SPI connection of the L99MOD54XP can be detected by the microcontroller, because all

24 bits low or high is not a valid

In case of an overvoltage or undervoltage event the corresponding bit is set and the outputs are deactivated. If V

S voltage recovers to normal operating conditions outputs are reactivated automatically (if bit 20 of status register 0 is not set).

Thermal shutdown

In case of a thermal shutdown all outputs are switched off.

The microcontroller has to clear the

TSD bit by setting the Reset Bit to reactivate the outputs.

Temperature warning

The TW bit can be used for thermal management by the microcontroller to avoid a thermal shutdown. The microcontroller has to clear the TW bit.

Current monitor select bits

Bit 19 Bit 18

0 0

1

0

1

0

1

1

Output

OUT6

OUT1

OUT4

OUT5

Not ready bit

After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events (e.g. measuring filter times).

DS12616 Rev 4

25/35

34

Functional description of the SPI L99MOD54XP

Table 18. SPI - input data and status registers 0 (continued)

Input register 0 (write) Status register 0 (read)

Bit

Name Comment Name

17

16

15

14

11

10

9

8

13

12

7 x (don’t care) x (don’t care) x (don’t care) x (don’t care) x (don’t care) x (don’t care)

6 OUT3 – HS on/off

5 x (don’t care)

OUT3 – LS on/off

If a bit is set the selected output driver is switched on. If the corresponding PWM enable bit is set (input register

1) the driver is only activated if

PWM1 (PWM2) input signal is high. The outputs of OUT1-

OUT3 are half bridges. If the bits of HS- and LS-driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from V

S

to GND.

4 OUT2 – HS on/off

3

2

1

OUT6 – HS on/off x (don’t care)

OUT5 – HS on/off

OUT4 – HS on/off

OUT2 – LS on/off

OUT1 – HS on/off

OUT1 – LS on/off

OUT6 – HS overcurrent

0

OUT5 – HS overcurrent

OUT4 – HS overcurrent

0

0

0

0

0

0

0

OUT3 – HS overcurrent

OUT3 – LS overcurrent

OUT2 – HS overcurrent

OUT2 – LS overcurrent

OUT1 – HS overcurrent

OUT1 – LS overcurrent

Comment

In case of an over-current event the corresponding status bit is set and the output driver is disabled. If the over-current recovery enable bit is set (input register 1) the output is automatically reactivated after a delay time resulting in a

PWM modulated current with a programmable duty cycle (bit 21).

If the over-current recovery bit is not set the microcontroller has to clear the over-current bit (reset bit) to reactivate the output driver.

0 0 No error bit

A logical NOR-combination of all bits 1 to 22 in both status registers.

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DS12616 Rev 4

L99MOD54XP Functional description of the SPI

Table 19. SPI - input data and status registers 1

Input register 1 (write) Status register 1 (read)

Bit

23

22

21

20

19

18

Name Comment Name Comment

Enable bit

OUT6 OC recovery enable x (don’t care)

OUT5 OC recovery enable

OUT4 OC recovery enable x (don’t care)

If enable bit is set the device is switched in active mode. If enable bit is cleared device goes into standby mode and all bits are cleared. After power-on reset device starts in standby mode.

V

V

S

S

Always 1

overvoltage

undervoltage

In case of an over-current event the over-current status bit (status register 0) is set and the output is switched off. If the over current recovery enable bit is set the output is automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (bit 21 of input data register 0).

Depending on occurrence of overcurrent event and internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero.

Thermal shutdown

Temperature warning

Not ready bit

A broken V

CC

or SPI connection of the

L99MOD54XP can be detected by the microcontroller, because all

24 bits low or high is not a valid frame.

In case of an overvoltage or under voltage event the corresponding bit is set and the outputs are deactivated.

If V

S

voltage recovers to normal operating conditions outputs are reactivated automatically.

In case of a thermal shutdown all outputs are switched off. The microcontroller has to clear the TSD bit by setting the reset bit to reactivate the outputs.

The TW bit can be used for thermal management by the microcontroller to avoid a thermal shutdown. The microcontroller has to clear the TW bit.

After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is only present during start up time.

Since this bit is controlled by internal clock it can be used for synchronizing testing events(e.g. measuring filter times).

DS12616 Rev 4

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34

Functional description of the SPI L99MOD54XP

Table 19. SPI - input data and status registers 1 (continued)

Input register 1 (write) Status register 1 (read)

Bit

8

7

6

17

16

Comment

15

14

13

12

11

10 x (don’t care)

OUT3 OC recovery enable

OUT2 OC recovery enable

OUT1 OC recovery enable

OUT6 PWM1 enable x (don’t care)

After 50ms the bit can be cleared. If over-current condition still exists, a wrong load can be assumed.

9

Name

Enable high

R

DSon

OUT5 x (don’t care)

5

4

3

2

1 enable

OUT4 PWM1 enable x (don’t care)

Enable high

R

DSon

OUT4 x (don’t care) x (don’t care)

If the PWM1/2 enable bit is set and the output is enabled (input register

0) the output is switched on if

PWM1/2 input is high and switched off if PWM1/2 input is low. OUT5 is controlled by PWM2 input. All other outputs are controlled by PWM1 input.

OUT3 PWM1 enable

OUT2 PWM1 enable

OUT1 PWM1 enable

Name

OUT6 – HS open-load

0

OUT5 – HS open-load

OUT4 – HS open-load

0

0

0

0

0

0

0

OUT3 – HS open-load

OUT3 – LS open-load

OUT2 –HS open-load

OUT2– LS open-load

OUT1 – HS open-load

OUT1 – LS open-load

Comment

The open-load detection monitors the load current in each activated output stage.

If the load current is below the open-load detection

(t dOL

) the corresponding open-load bit is set. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g.

3 ms) can be used to test the open-load status without changing the mechanical/electrical state of the loads.

0 1 No error bit

A logical NOR-combination of all bits 1 to 22 in both status registers.

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DS12616 Rev 4

L99MOD54XP

5 Package and PCB thermal data

Package and PCB thermal data

5.1 PowerSSO-36 thermal data

Figure 10. PowerSSO-36 2 layer PCB

Figure 11. PowerSSO-36 4 layer PCB

Note: Layout condition of R th

and Z th

measurements (board finish thickness 1.6 mm ±10%, board double layer and four layers, board dimension 129 mm x 60 mm, board material FR4, Cu thickness 0.070 mm (outer layers), Cu thickness 0.035 mm (inner layers), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm ±0.08 mm, Cu thickness on vias

0.025

mm, footprint dimension 4.1 mm x 6.5 mm). 4-layer PCB: Cu on mid1 and mid2 layer:

76.45 cm

2

. Cu on bottom layer: 68.8 cm

2

. Z th contributor.

measured on the major power dissipator

DS12616 Rev 4

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34

Package and PCB thermal data L99MOD54XP

Figure 12. PowerSSO-36 thermal impedance junction to ambient vs PCB copper area

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DS12616 Rev 4

L99MOD54XP

6

Package and packing information

Package and packing information

6.1 ECOPACK

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK is an ST trademark.

Figure 13. PowerSSO-36 package dimensions

Symbol

D

E b c e

A

A2 a1

Table 20. PowerSSO-36 mechanical data

Millimeters

Min.

2.15

2.15

0

0.18

0.23

10.10

7.4

-

Typ.

-

-

-

-

0.5

-

-

-

DS12616 Rev 4

Max.

2.47

2.40

0.075

0.36

0.32

10.50

7.6

-

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34

Package and packing information L99MOD54XP

L

N

H h e3

G

G1

X

Y

Symbol

Table 20. PowerSSO-36 mechanical data (continued)

Millimeters

Min.

10.1

-

0.55

-

4.3

6.9

-

-

-

Typ.

-

-

-

-

-

-

8.5

-

-

Max.

-

0.1

0.06

10.5

0.4

0.85

10 deg

5.2

7.5

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DS12616 Rev 4

L99MOD54XP Package and packing information

Figure 14. PowerSSO-36 tape and reel shipment (suffix “TR”)

Reel dimensions

Base Qty

Bulk Qty

A (max)

B (min)

C (±0.2)

F

G (+2 / -0)

N (min)

T (max)

1000

1000

330

1.5

13

20.2

24.4

100

30.4

Tape dimensions

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

W

P0 (±0.1)

D1 (min)

F (±0.1)

K (max)

P1 (±0.1)

24

4

P 12

D (±0.05) 1.55

1.5

11.5

2.85

2

All dimensions are in mm.

End

Top cover tape

Start

No components Components No components

500mm min 500mm min

Empty components pockets sealed with cover tape.

User direction of feed

DS12616 Rev 4

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34

Revision history L99MOD54XP

Date

24-Jul-2018

09-Nov-2018

13-Jun-2019

08-Oct-2019

Table 21. Document revision history

Revision Changes

1

2

3

4

Initial release.

Added

Section 5: Package and PCB thermal data

.

Updated the maturity from target specification to production data.

Updated Applications on cover page.

Updated Section 4.2: Chip Select Not (CSN)

.

Minor text changes

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DS12616 Rev 4

L99MOD54XP

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2019 STMicroelectronics – All rights reserved

DS12616 Rev 4

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