STMicroelectronics ISO8200BQ Datasheet

ISO8200BQ

Galvanic isolated octal high-side smart power solid state-relay

TFQFPN32

Features

 V demag

= V

CC

- 45 V (per channel)

 R

DS(on)

= 0.12  (per channel)

 I

OUT

= 0.7 A (per channel)

 V

CC

= 45 V

 Parallel input interface

 Direct and synchronous control mode

 High common mode transient immunity

 Short-circuit protection

 Channel overtemperature protection

 Thermal independence of separate channels

 Common output disable pin

 Case overtemperature protection

 Loss of GND

CC

and V

CC

protection

 Undervoltage shutdown with auto-restart and hysteresis

 Overvoltage protection (V

CC

clamping)

 Very low supply current

 Common fault open-drain output

 5 V and 3.3 V TTL/CMOS compatible I/Os

 Fast demagnetization of inductive loads

 Reset function for IC output disable

 ESD protection

 Designed to meet IEC 61000-4-2, IEC 61000-

4-4, IEC 61000-4-5 and IEC 61000-4-8

 UL1577 and UL508 certified

 Safety Limits as per VDE0884-11

Datasheet

-

production data

Applications

 Programmable logic control

 Industrial PC peripheral input/output

 Numerical control machines

 Drivers for all types of loads (resistive, capacitive, inductive)

Description

The ISO8200BQ is a galvanic isolated 8-channel driver featuring a very low supply current. It contains 2 independent galvanic isolated voltage domains (V

CC

for the power stage and V

DD

for the digital stage). Additional embedded functions are: loss of GND protection, undervoltage shutdown with hysteresis, and reset function for immediate power output shutdown.

IC is intended to drive any kind of load with one side connected to ground. Active channel current limitation combined with thermal shutdown,

(independent for each channel), and automatic restart, protect the device against overload and short-circuit. In overload conditions, if junction temperature overtakes threshold, the channel involved is turned off and on again automatically after the IC temperature decreases below a reset threshold. If this condition causes case temperature to reach TCR limit threshold, the overloaded channel is turned off and it only restarts when case and junction temperature decrease down to the reset thresholds. Non- overloaded channels continue operating normally.

An internal circuit provides an OR-wired nonlatched common FAULT indicator signaling the channel OVT. The FAULT pin is an open-drain active low fault indication pin.

May 2020

This is information on a product in full production.

DS10781 Rev 9 1/40 www.st.com

10

11

8

9

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4

1

2

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6

Contents

Contents

7

ISO8200BQ

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.1

Parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

Input signals (IN1 to IN8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Load input data (LOAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Output synchronization (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Output enable (OUT_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.2

Direct control mode (DCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3

Synchronous control mode (SCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.4

Fault indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.4.1

Junction overtemperature and case overtemperature . . . . . . . . . . . . . . 23

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.1

Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.2

Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Reverse polarity on VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Supply voltage and power output conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/40 DS10781 Rev 9

15

16

ISO8200BQ

12

13

14

Contents

Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

13.1

TFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

14.1

TFQFPN32 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

14.1.1

TFQFPN32 packing method concept . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

14.1.2

TFQFPN32 winding direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

14.1.3

TFQFPN32

leader and trailer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DS10781 Rev 9 3/40

40

List of tables

List of tables

ISO8200BQ

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Digital supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Diagnostic pin and output protection function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power switching characteristics (VCC = 24 V; -40 °C < TJ < 125 °C) . . . . . . . . . . . . . . . . 11

Logic input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 9.

Parallel interface timings (VDD = 5 V; VCC

= 24 V; -40 °C < TJ < 125 °C) . . . . . . . . . . . . 14

Table 10.

Insulation and safety-related specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 11.

Insulation characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 12.

Safety limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 13.

Interface signal operation (general) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 14.

Interface signal operation in direct control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 15.

Interface signal operation in synchronous control mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 16.

TFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 17.

Tolerance of form and position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 18.

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 19.

Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4/40 DS10781 Rev 9

ISO8200BQ

List of figures

List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

Pin connection (top through view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.

RDS(on) measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4.

dV/dT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5.

td(ON) - td(OFF) synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6.

td(ON) - td(OFF) direct control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7.

Watchdog behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8.

Output channel enable timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9.

Direct control mode IC configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10.

Direct control mode time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11.

Synchronous control mode IC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12.

Synchronous control mode time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13.

Multiple device synchronous control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 14.

Thermal status update (DCM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 15.

Thermal status update (SCM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 16.

Current limitation with different load conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 17.

Thermal protection flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 18.

Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 19.

Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 20.

Reverse polarity protection on VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 21.

Maximum demagnetization energy vs. load current, typical values Tamb = 125 °C . . . . . 30

Figure 22.

Supply voltage and power output conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 23.

Simplified thermal model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 24.

TFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 25.

TFQFPN32 package detail outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 26.

TFQFPN32 suggested footprint (measured in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 27.

TFQFPN32 packing method concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 28.

TFQFPN32 carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 29.

TFQFPN32 reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 30.

TFQFPN32 winding direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 31.

TFQFPN32 leader and trailer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DS10781 Rev 9 5/40

40

Block diagram

1 Block diagram

Figure 1. Block diagram

ISO8200BQ

6/40 DS10781 Rev 9

ISO8200BQ

2 Pin connection

Figure 2. Pin connection (top through view)

Pin connection

Pin

13

14

15

16

17

9

10

11

12

7

8

5

6

3

4

1

2

Name

OUT6

OUT5

OUT5

OUT4

OUT4

OUT3

OUT3

OUT2

OUT2

GND

DD

NC

GND

CC

OUT8

OUT8

OUT7

OUT7

OUT6

Table 1. Pin description

Description

Input logic ground, negative logic supply

Not connected

Output power ground

Channel 8 power output

Channel 7 power output

Channel 6 power output

Channel 5 power output

Channel 4 power output

Channel 3 power output

Channel 2 power output

DS10781 Rev 9 7/40

40

Pin connection ISO8200BQ

Pin Name

Table 1. Pin description (continued)

Description

18

19

20

21

22

OUT1

OUT1

Channel 1 power output

V

DD

Positive logic supply

OUT_EN Output enable

SYNC

Input-to-output synchronization signal. Active low, see

Section 6.3:

Synchronous control mode (SCM) on page 21 .

27

28

29

30

23

24

25

26

LOAD

Load input data signal. Active low, see Section 6.3

IN1 Channel 1 input

IN2

IN3

IN4

IN5

IN6

IN7

Channel 2 input

Channel 3 input

Channel 4 input

Channel 5 input

Channel 6 input

Channel 7 input

31

32

IN8

TAB(V

CC

) V

CC

TAB(GND

CC

) GND

CC

Channel 8 input

FAULT Common fault indication, active low

Exposed tab internally connected to V

CC

, positive power supply voltage

Exposed tab internally connected to GND

CC

8/40 DS10781 Rev 9

ISO8200BQ

3 Absolute maximum ratings

Absolute maximum ratings

Symbol

Table 2. Absolute maximum ratings

Parameter Min.

Max.

Unit

V

CC

V

DD

V

IN

V

FAULT

I

GND DD

I

OUT

I

GNDcc

-I

OUT

I

IN

I

FAULT

Power supply voltage

Digital supply voltage

DC input pin voltage (INx, OUT_EN, LOAD, SYNC)

Fault pin voltage

DC digital ground reverse current

Channel output current (continuous)

DC power ground reverse current

Reverse output current (single channel)

DC input pin current (INx, OUT_EN, LOAD, SYNC)

Fault pin current

-0.3

-0.3

-0.3

-0.3

-

-

-

-

-10

-10

45

6.5

+6.5

+6.5

-25

-250

-5

+ 10

+ 10

V

ESD

Electrostatic discharge with human body model

(R = 1.5 k  ; C = 100 pF)

2000

E

AS

Single pulse avalanche energy per channel not simultaneously at

Tamb

= 125 °C, I

OUT

= 0.5 A

Single pulse avalanche energy per channel, all channels driven simultaneously at

Tamb

= 125 °C, I

OUT

= 0.5 A

Power dissipation at Tc = 25 °C

-

1.8

0.35

P

TOT

T

J

T

STG

Junction operating temperature

Storage temperature

-

-

-

Internally limited

Internally limited

-55 to 150

1. Protection functions are intended to avoid IC damage in fault conditions and are not intended for continuous operation. Continuous or repetitive operations of protection functions may reduce the IC lifetime.

(1)

(1)

V

V

V

V mA

Internally limited A mA

A mA mA

V

J

W

°C

°C

4 Thermal data

Symbol

Table 3. Thermal data

Parameter Max. value

R thj-case

R thj-amb

Thermal resistance, junction-case(

(1)

Thermal resistance, junction-ambient

(2)

2

15

1. For each channel.

2. TFQFPN32 mounted on the product evaluation board (FR4, 4 layers, 8 cm

2 thickness 35 mm).

for each layer, copper

Unit

°C/W

°C/W

DS10781 Rev 9 9/40

40

Electrical characteristics

5 Electrical characteristics

ISO8200BQ

(10.5 V < V

CC

< 36 V; -40 °C < T

J

< 125 °C, unless otherwise specified)

Symbol Parameter

Table 4. Power section

Test conditions Min. Typ. Max. Unit

V

CC(THON)

V

CC

undervoltage turn-ON threshold

V

CC(THOFF)

V

CC

undervoltage turn-OFF threshold

-

-

8

9.5

9

10.5

-

V

V

V

V

R

I

CC(hys)

CCclamp

DS(on)

R

I pd

CC

LGND

V

OUT(OFF)

I

OUT(OFF)

V

CC

undervoltage hysteresis -

Clamp on V

CC

pin I clamp

= 20 mA

On-state resistance

(1)

I

OUT

= 0.5 A, T

J

= 25 °C

I

OUT

= 0.5 A T

J

= 125 °C

Output pull-down resistor

Power supply current

Ground disconnection output current

Off-state output voltage

Off-state output current

1. See

Figure 3: RDS(on) measurement .

0.25 0.5

-

0.12

All channels in OFF-state

All channels in ON-state

V

CC

= V

GND

= 0 V

V

OUT

= -24 V

Channel OFF and I

OUT

= 0 A

Channel OFF and V

OUT

= 0 V -

-

-

-

210

5

9

-

-

-

-

45 50 52

0.24

-

-

500

1

5 k

V

V



 mA

μA

V

μA

Symbol

I

DD

I

DD

supply current

Table 5. Digital supply voltage

Parameter

V

V

DD

DD(THON)

Operating voltage

V

DD undervoltage turn-ON threshold

V

DD(THOFF)

V

DD

undervoltage turn-OFF threshold

V

DD(hys)

-

-

-

V

DD undervoltage hysteresis -

Test conditions Min. Typ. Max. Unit

2.75

2.55

2.45

-

-

-

V

DD

= 5 V and input channel with a steady logic level

V

DD

= 3.3 V and input channel with a steady logic level

0.04 0.1

4.5

4.4

5.5

2.75

2.65

-

6

5.9

V

V

V

V mA mA

10/40 DS10781 Rev 9

ISO8200BQ Electrical characteristics

Symbol

Table 6. Diagnostic pin and output protection function

Parameter

I

V

LFAULT

I

FAULT

PEAK

I

LIM

H yst

T

JSD

T

JR

T

HIST

T

CSD

T

CR

T

CHYST

FAULT pin open-drain voltage output low

FAULT output leakage current

Maximum DC output current before limitation

Short-circuit current limitation

ILIM tracking limits

Junction shutdown temperature

Junction reset temperature

Junction thermal hysteresis

Case shutdown temperature

Case reset temperature

Case thermal hysteresis

V demag

Output voltage at turn-OFF

Test conditions Min.

I

FAULT

= 10 mA

-

-

-

-

-

-

-

V

FAULT

= 5 V

V

CC

= 24 V

R

LOAD

= 0 

-

I

OUT

= 0.5 A

I

LOAD

> = 1 mH

-

-

-

0.7

-

150

115

-

-

-

-

Typ.

-

-

1.6

1.3

0.3

170

150

20

130

110

20

Max.

Unit

0.4

1

-

1.9

-

-

145

-

-

-

-

V

μA

A

V

CC

-45 V

CC

-50 V

CC

-52 V

°C

°C

°C

°C

°C

A

A

°C

Table 7. Power switching characteristics (VCC = 24 V; -40 °C < TJ < 125 °C)

Symbol Parameter Test conditions Min. Typ. Max. Unit dV/dt(ON) Turn-ON voltage slope I

OUT

= 0.5 A, resistive load 48  dV/dt(OFF) Turn-OFF voltage slope I

OUT

= 0.5 A, resistive load 48  t d

(ON) Turn-ON delay time

(1)

I

OUT

= 0.5 A, resistive load 48  t d

(OFF) Turn-OFF delay time

(1) t f

Fall time

(1) t r

Rise time

(1)

I

I

I

OUT

OUT

OUT

= 0.5 A, resistive load 48

= 0.5 A, resistive load 48

= 0.5 A, resistive load 48





 -

-

-

-

-

5.6

2.81

17

22

5

5

-

-

22

40

-

-

V/μs

V/μs

1. See

Figure 3: RDS(on) measurement

,

Figure 4: dV/dT

and Figure 6: td(ON) - td(OFF) direct control mode .

μs

μs

μs

μs

DS10781 Rev 9 11/40

40

Electrical characteristics

Figure 3. R

DS(on)

measurement

ISO8200BQ

Figure 4. dV/dT

12/40 DS10781 Rev 9

ISO8200BQ Electrical characteristics

Figure 5. t d(ON)

- t d(OFF) synchronous mode

Figure 6. t d(ON)

- t d(OFF)

direct control mode

DS10781 Rev 9 13/40

40

Electrical characteristics ISO8200BQ

Symbol

Table 8. Logic input and output

Parameter Test conditions

IL

IH

V

I(HYST) t

V

V

I

IN

WM

Logic input pin low level voltage (INx, OUT_EN,

LOAD, SYNC)

Logic input pin high level voltage (INx, OUT_EN,

LOAD, SYNC)

-

-

Logic input hysteresis voltage (INx, OUT_EN,

LOAD, SYNC)

Logic input pin current (INx, OUT_EN, LOAD,

SYNC)

Power side watchdog time -

V

DD

= 5 V

V

IN

= 5 V

Min.

-0.3

0.7 x V

DD

-

10

272

Typ.

Max.

Unit

100

-

320

0.3 x V

DD

V

DD

+ 0.3

V

-

-

400

V mV

μA

μs

Symbol

Table 9. Parallel interface timings (VDD = 5 V; VCC = 24 V; -40 °C < TJ < 125 °C)

Parameter Test conditions Min.

Typ.

Max.

Unit t dis(SYNC) t dis(DCM) t w(SYNC) t su(LOAD) t h(LOAD) t w(LOAD) t su(IN) t h(IN)

SYNC disable time

SYNC, LOAD disable time

Sync. control mode

Direct control mode

SYNC negative pulse width Sync. control mode

LOAD setup time

LOAD hold time

LOAD pulse width

Input setup time -

Sync. control mode

Sync. control mode

Sync. control mode

Input hold time -

Sync. control mode t t w(IN)

INLD

Input pulse width

IN to LOAD time

Direct control mode

Direct control mode

From IN variation to LOAD falling edge t

LDIN

LOAD to IN time

Direct control mode

From LOAD falling edge to IN variation t w(OUT_EN) t p(OUT_EN) t jitter(SCM) t jitter(DCM) f refresh

OUT_EN pulse width

-

-

OUT_EN propagation delay -

Jitter on single channel

Refresh delay

Sync. mode

Direct mode

80

400

240

80

10

80

20

10

160

20

80

400

150

-

-

-

-

-

-

-

22

-

-

15

-

-

-

-

-

-

-

-

-

-

-

40

6

20

-

-

-

-

-

-

-

-

μs

ns

195 μs ns ns ns ns ns ns

μs

-

ns ns ns

μs

μs kHz

14/40 DS10781 Rev 9

ISO8200BQ Electrical characteristics

Symbol

CLR

CPG

CTI

Table 10. Insulation and safety-related specifications

Parameter Test conditions Value Unit

Clearance (minimum external air gap)

Creepage (minimum external tracking)

Measured from input terminals to output terminals, the shortest distance through air

Measured from input terminals to output terminals, the shortest distance path along body

Comparative tracking index (tracking resistance)

DIN IEC 112/VDE 0303 part 1

Isolation group Material group (DIN VDE 0110, 1/89, Table 1)

3.3

3.3

 600 V

I mm mm

-

Symbol Parameter

Table 11. Insulation characteristics

Test conditions

IEC 60747-5-5

V

V

IORM

V

PR

IOTM

Maximum working isolation

Input to output test voltage

Transient overvoltage

-

Method a, type test,

V

PR

= V

IORM

x 1.6, tm = 10s partial discharge < 5 pC

Method b, 100% production test,

V

PR

= V

IORM

x 1.875, tm = 1s partial discharge < 5 pC

Type test t ini

= 60 s

V

IOSM

R

IO

UL1577

V

ISO

V

ISO test

Maximum surge insulation voltage

Insulation resistance

Insulation withstand test

Type test

V

IO

= 500 V at t

Insulation withstand voltage 1 min. type test s

1 s 100% production

Value

937

1500

1758

4245

4245

>10

9

V

V

V

V

V

Unit

PEAK

PEAK

PEAK

PEAK

PEAK



2500/3536 V rms

/V

PEAK

3000/4245 V rms

/V

PEAK

DS10781 Rev 9 15/40

40

Electrical characteristics ISO8200BQ

Note:

Parameter

Table 12. Safety limits

Description Test Condition Limit value Unit

Input safety, Logic side

T si

Safety temperature of Logic side

P si

Safety power of Logic side

-

V

DD

≤ 6.5V,

V

LOGIC(x)

≤ 6.5V,

I

LOGIC(x)

≤ 10mA,

T

J

≤ Tsi

150

0.9

o

C

W

Output safety, Process side

T so

Safety temperature of Process side

P so

Safety power of Process side

-

V

CC

≤ 36V,

I

OUT(x)

T

J

≤ 1.5A,

≤ Tso

150

4.5

o

C

W

The above limits are measured according to VDE 0884-11. Respecting above limits prevents potential damage potential damage to the isolation barrier upon failure on logic or process side circuitry. User can use these values to protect the IC and consequently guarantee the safety of the embedded isolation barrier.

LOGIC(X) stands for "any pin of logic side".

OUT(X) stands for "any of the 8 output pins of process side".

16/40 DS10781 Rev 9

ISO8200BQ

6 Functional description

6.1

6.1.1

6.1.2

6.1.3

Functional description

Parallel interface

Smart parallel interface built-in ISO8200BQ offers three interfacing signals easily managed by a microcontroller.

The LOAD signal enables the input buffer storing the value of the channel inputs.

The SYNC signal copies the input buffer value into the transmission buffer and manages the synchronization between low voltage side and the channel outputs on the isolated side. The

OUT_EN signal enables the channel outputs.

An internal refresh signal updates the configuration of the channel outputs with a f refresh frequency. This signal can be disabled forcing low the SYNC input when LOAD is high.

SYNC and LOAD pins can be in direct control mode (DCM) or synchronous control mode

(SCM).

The operation of these two signals is described as follows:

Table 13. Interface signal operation (general)

LOAD SYNC OUT_EN

Don't care Don't care Low

(1)

Device behavior

The outputs are disabled (turned off)

High High

Low

High

Low

High

Low

Low

High The outputs are left unchanged

High

The input buffer is enabled

The outputs are left unchanged

High

The internal refresh signal is disabled

The transmission buffer is updated

The outputs are left unchanged

High

The device operates in direct control mode as described in

Section 6.2: Direct control mode (DCM)

1. The outputs are turned off on OUT_EN falling edge and they are kept disabled as long as it is low.

Input signals (IN1 to IN8)

Inputs from IN1 to IN8 are the driving signals of the corresponding OUT1 to OUT8 outputs.

Data are direct loaded on related outputs if SYNC and LOAD inputs are low (DCM operation) or stored into input buffer when LOAD is low and SYNC is high.

Load input data (LOAD)

The input is active low; it stores the data from IN1 to IN8 into the input buffer.

Output synchronization (SYNC)

The input is active low; it enables the ISO8200BQ transmission buffer loading input buffer data and manages the transmission between the two isolated sides of the device.

DS10781 Rev 9 17/40

40

Functional description

6.1.4 Watchdog

ISO8200BQ

The isolated side of the device provides a watchdog function in order to guarantee a safe condition when V

DD

supply voltage is missing.

If the logic side does not update the output status within t

WD new update request is received.

, all outputs are disabled until a

The refresh signal is also considered a valid update signal, so the isolated side watchdog does not protect the system from a failure of the host controller (MCU freezing).

Figure 7. Watchdog behavior

18/40 DS10781 Rev 9

ISO8200BQ

6.1.5

Functional description

Output enable (OUT_EN)

This pin provides a fast way to disable all outputs simultaneously. When the OUT_EN pin is driven low the outputs are disabled. To enable the output stage, the OUT_EN pin has to be raised. This timing execution is compatible with an external reset push, safety requirement, and allows, in a PLC system, the microcontroller polling to obtain all internal information during a reset procedure.

Figure 8. Output channel enable timing

6.2 Direct control mode (DCM)

When SYNC and LOAD inputs are driven by the same signal, the device operates in direct control mode (DCM).

In DCM the SYNC / LOAD signal operates as an active low input enable:

 When the signal is high, the current output configuration is kept regardless the input values

 When the signal is low, each channel input directly drives the respective output

This operation mode can also be set shorting both signals to the digital ground; in this case the channel outputs are always directly driven by the inputs except when OUT_EN is low

(outputs disabled).

SYNC / LOAD

Don't care

High

Low

Table 14. Interface signal operation in direct control mode

OUT_EN

Low

(1)

High

High

Device behavior

The outputs are disabled (turned off)

The outputs are left unchanged

The channel inputs drive the outputs

1. The outputs are turned off on OUT_EN falling edge and they are kept disabled as long as it is low.

DS10781 Rev 9 19/40

40

Functional description

Figure 9. Direct control mode IC configuration

ISO8200BQ

Figure 10. Direct control mode time diagram

20/40 DS10781 Rev 9

ISO8200BQ

6.3

Functional description

Synchronous control mode (SCM)

When SYNC and LOAD inputs are independently driven, the device can operate in synchronous control mode (SCM). The SCM is used to reduce the jittering of the outputs and to drive all outputs of different devices at the same time.

In SCM the LOAD signal is forced low to update the input buffer while the SYNC signal is high. The LOAD signal is raised and the SYNC one is forced low for at least t

SYNC(SCM)

.

During this period, the internal refresh is disabled and any pending transmission between the low voltage and the isolated side is completed. When the SYNC signal is raised the channel output configuration is changed according to the one stored in the input.

If the t

SYNC(SCM)

limit is met, the maximum jitter of the channel outputs is t jitter

(SCM).

If more devices share the same SYNC signal, all device outputs change simultaneously with a maximum jitter related to maximum delay and maximum jitter for single device.

Table 15. Interface signal operation in synchronous control mode

LOAD SYNC OUT_EN

Don't care Don't care Low

(1)

Device behavior

The outputs are disabled (turned off)

High

Low

High

High

Low

High

High

Low

Rising edge

Low

High The outputs are left unchanged

High The input buffer is enabled. The outputs are left unchanged.

High

High

The internal refresh signal is disabled. The transmission buffer is updated. The outputs are left unchanged.

The outputs are updated according to the current transmission buffer value

High Should be avoided (DCM operation only)

1. The outputs are turned off on OUT_EN falling edge and they are kept disabled as long as it is low.

Figure 11. Synchronous control mode IC configuration

DS10781 Rev 9 21/40

40

Functional description

Figure 12. Synchronous control mode time diagram

ISO8200BQ

Figure 13. Multiple device synchronous control mode

22/40 DS10781 Rev 9

ISO8200BQ

6.4

6.4.1

Functional description

Fault indication

The FAULT pin is an active low open-drain output indicating fault conditions. This pin is active when at least one of the following conditions occurs:

 Junction overtemperature of one or more channels (T

J

>T

TJSD

)

 Communication error

The communication error is intended as an internal data corruption event in the data transfer through isolation. In case of communication error the outputs are initially kept in the previous status and then reset (turned off) at the first communication error during data transfer of the refresh signal.

Junction overtemperature and case overtemperature

The thermal status of the device is updated during each transmission sequence between the two isolated sides.

In SCM operation, when the LOAD signal is high and the SYNC one is low, the communication is disabled. In this case the thermal status of the device cannot be updated and the FAULT indication can be different from the current status.

In any case, the thermal protection of the channel outputs is always operative.

Figure 14. Thermal status update (DCM)

DS10781 Rev 9 23/40

40

Functional description

Figure 15. Thermal status update (SCM)

ISO8200BQ

24/40 DS10781 Rev 9

ISO8200BQ

7 Power section

7.1

Power section

Current limitation

The current limitation process is active when the current sense connected on the output stage measures a current value, which is higher than a fixed threshold.

When this condition is verified the gate voltage is modulated to avoid the increase of the output current over the limitation value.

Figure 16

shows typical output current waveforms with different load conditions.

Figure 16. Current limitation with different load conditions

DS10781 Rev 9 25/40

40

Power section

7.2

ISO8200BQ

Thermal protection

The device is protected against overheating in case of overload conditions. During the driving period, if the output is overloaded, the device suffers two different thermal stresses, the former related to the junction, and the latter related to the case.

The two faults have different trigger thresholds: the junction protection threshold is higher than the case protection one; generally the first protection, that is active in thermal stress conditions, is the junction thermal shutdown. The output is turned off when the temperature is higher than the related threshold and turned back on when it goes below the reset threshold. This behavior continues until the fault on the output is present.

If the thermal protection is active and the temperature of the package increases over the fixed case protection threshold, the case protection is activated and the output is switched off and back on when the junction temperature of each channel in fault and case temperature is below the respective reset thresholds.

Figure 17

shows the thermal protection behavior, while

Figure 18 reports typical

temperature trends and output vs. input state.

Figure 17. Thermal protection flowchart

26/40 DS10781 Rev 9

ISO8200BQ

Figure 18. Thermal protection

Power section

DS10781 Rev 9 27/40

40

Reverse polarity protection

8 Reverse polarity protection

Note:

ISO8200BQ

Reverse polarity protection can be implemented on board using two different solutions:

1.

Placing a resistor (R

GND

) between IC GND pin and load GND

2. Placing a diode in parallel to a resistor between IC GND pin and load GND

If option 1 is selected, the minimum resistance value has to be selected according to

Equation 1 :

Equation 1

R

GND

 V

CC

/I

GNDcc where I

GNDcc

is the DC reverse ground pin current and can be found in Section 3: Absolute maximum ratings on page 9

.

Power dissipated by RGND during reverse polarity situations is:

Equation 2

P

D

= (V

CC

) 2 /R

GND

If option 2 is selected, the diode has to be chosen by taking into account VRRM > |V

CC its power dissipation capability:

| and

Equation 3

P

D

 I

S

* V

F

In normal operation (no reverse polarity), there is a voltage drop ( Δ V) between GND of the device and GND of the system. Using option 1, Δ V = Rgnd * Icc. Using option 2,

Δ

V = VF

@(IF)

.

Figure 19. Reverse polarity protection

28/40

This schematic can be used with any type of load.

DS10781 Rev 9

ISO8200BQ

9 Reverse polarity on V

DD

Note:

Reverse polarity on VDD

The reverse polarity on V

DD

GND

DD

can be implemented on board by placing a diode between

pin and GND digital ground.

The diode has to be chosen by taking into account VRRM > |V

DD capability:

| and its power dissipation

Equation 4

P

D

 I

DD

* V

F

In normal operation (no reverse polarity), there is a voltage drop ( Δ V = VF@(Idd)) between GND DD of the device and digital ground of the system .

In order to guarantee to proper triggering of the input signal, Δ V(max.) must result lower than V

IH(MIN).

Figure 20. Reverse polarity protection on V

DD

DS10781 Rev 9 29/40

40

Demagnetization energy

10 Demagnetization energy

ISO8200BQ

Figure 21. Maximum demagnetization energy vs. load current, typical values

T amb

= 125 °C

11 Conventions

Supply voltage and power output conventions

Figure 22

shows the convention used in this paper for voltage and current usage.

Figure 22. Supply voltage and power output conventions

30/40 DS10781 Rev 9

ISO8200BQ

12 Thermal information

Thermal impedance

Figure 23. Simplified thermal model

Thermal information

DS10781 Rev 9 31/40

40

Package information

13 Package information

ISO8200BQ

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK ® is an ST trademark.

13.1 TFQFPN32 package information

Figure 24. TFQFPN32 package outline

32/40 DS10781 Rev 9

ISO8200BQ

Figure 25. TFQFPN32 package detail outline

Package information

Figure 26. TFQFPN32 suggested footprint (measured in mm)

0.3

0

0.3

0

0.7

0

0.3

0

0

0.9

0

DS10781 Rev 9 33/40

40

Package information

Table 16. TFQFPN32 package mechanical data

Dimensions (mm]

Symbol

Min.

Typ.

e5 k z1 z2 e e2 e3 e4 z3 z4 z5 z6

L

(1)

D3

E3

D4

E4

D

E

(1)

D2

E2

A

A1

A2 b

(1) b1

(1)

1. Dimensions “b” and “L” are measured on terminal plating surface.

-

-

-

-

-

0

-

-

-

-

0.45

1.13

1.00

-

-

4.30

6.70

1.40

3.20

0.95

0

-

0.20

0.25

10.90

8.90

0.80

4.07

3.80

1.10

1.05

3.15

4.85

0.30

1.15

2.85

0.50

1.23

1.10

0.65

0.40

4.40

6.80

1.50

3.30

1.00

-

0.20 REF

0.25

0.30

11.0

9.00

ISO8200BQ

Max.

-

-

-

-

-

-

-

-

-

-

0.55

1.33

1.20

-

-

4.50

6.90

1.60

3.40

1.05

0.05

-

0.30

0.35

11.10

9.10

34/40 DS10781 Rev 9

ISO8200BQ Package information

Symbol aaa bbb ccc ddd eee fff

REF

Tolerance of form and position

Table 17. Tolerance of form and position

Definition

0.15

0.10

0.10

0.08

0.08

0.10

-

Notes

The bilateral profile tolerance that controls the position of the plastic body sides. The centers of the profile zones are defined by the basic dimensions D and E.

The tolerance that controls the position of the entire terminal pattern with respect to datum's A and B. The center of the tolerance zone for each terminal is defined by the basic dimension "e" as related to datum's A and

B.

The tolerance located parallel to the seating plane in which the top surface of the package must be located.

The tolerance that controls the position of the terminals to each other. The centers of the profile zones are defined by basic dimension "e".

This tolerance is normally compounded with tolerance zone defined by bbb.

The unilateral tolerance located above the seating plane where in the bottom surface of all terminals must be located.

This tolerance is commonly known as the “coplanarity” of the package terminals.

The tolerance that controls the position of the exposed metal heat feature. The center of the tolerance zone will be datum's defined by the centerlines of the package body.

No tolerance for A2

DS10781 Rev 9 35/40

40

Packing information

14 Packing information

14.1 TFQFPN32 packing information

14.1.1 TFQFPN32 packing method concept

Figure 27. TFQFPN32 packing method concept

ISO8200BQ

36/40 DS10781 Rev 9

ISO8200BQ

Figure 28. TFQFPN32 carrier tape

Packing information

Reel – 330 mm diameter x 101 mm hub x 24 mm width

Figure 29. TFQFPN32 reel

DS10781 Rev 9 37/40

40

Packing information

14.1.2 TFQFPN32 winding direction

Figure 30. TFQFPN32 winding direction

ISO8200BQ

14.1.3 TFQFPN32 leader and trailer

Figure 31. TFQFPN32 leader and trailer

Note: Leader and trailer length as per EAI-481specification.

38/40 DS10781 Rev 9

ISO8200BQ

15 Ordering information

Order code

ISO8200BQ

ISO8200BQTR

Table 18. Ordering information

Package

TFQFPN32

TFQFPN32

Ordering information

Packing

Tube

Tape and reel

16 Revision history

Date

17-Nov-2016

21-Apr-2017

05-Oct-2017

18-May-2018

24-Apr-2019

18-Oct-2019

08-May-2020

Revision

Table 19. Document revision history

Changes

3

4

5

6

7

8

9

Datasheet promoted from preliminary to production data. Updated

Table 6: Diagnostic pin and output protection function .

Updated Table 10: “ Insulation and safety-related specifications ” .

Minor text changes.

Updated Table 11: “IEC 60747-5-2 insulation characteristics” .

Updated

Section : Features on page 1

.

Replaced Vdd by V

DD

in whole document.

Updated titles of

Table 7 on page 11 and

Table 9 on page 14 .

Updated titles of

Figure 3 on page 12

, Figure 5 on page 13 , Figure 6 on page 13

, Figure 20 on page 29 and

Figure 21 on page 30 .

Added cross-reference to Section 6.2

in Table 13 on page 17 .

Updated

Figure 9 on page 20

and Figure 11 on page 21 (replaced

ISO8200B by ISO8200BQ).

Added Section on page 34

.

Minor modifications throughout document.

Added Table 12: Safety limits on page 15 ,

Updated

Table 2: Absolute maximum ratings on page 9

Updated

Section : Features on page 1

.

Minor text changes.

Updated

Section : Features on page 1

.

Table 4 ,

11 and

16 updated.

Figure 24 replaced.

Table 17 added.

DS10781 Rev 9 39/40

40

ISO8200BQ

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40/40 DS10781 Rev 9