STMicroelectronics VNI8200XP Datasheet
STMicroelectronics VNI8200XP is a smart power solid-state relay with a serial/parallel selectable interface. It features eight channels with an output current of 0.7 A each and a maximum supply voltage of 45 V. The VNI8200XP has built-in protection features such as short-circuit, overtemperature, and undervoltage shutdown. It also includes a 100 mA high-efficiency step-down switching regulator and a channel output status LED driving array.
Reklāma
Reklāma
VNI8200XP
Octal high-side smart power solid-state relay with serial/parallel selectable interface on-chip
Datasheet - production data
PowerSSO-36 package with exposed pad down (EPD)
Features
Type V
R
DS(on)
(1)
I
OUT
(1)
V
CC
VNI8200XP V
CC
-45 V 0.11 Ω 0.7 A 45 V
Notes:
(1)
Per channel
Output current: 0.7 A per channel
Serial/parallel selectable interface
Short-circuit protection
8-bit and 16-bit SPI Interface for IC command and control diagnostic
Channel overtemperature detection and protection
Thermal independence of separate channels
Drives all type of loads (resistive, capacitive, inductive load)
Loss of GND protection
Power Good diagnostic
Undervoltage shutdown with hysteresis
Overvoltage protection (V
CC
clamping)
Very low supply current
Common fault open drain output
IC warning temperature detection
Channel output enable
100 mA high efficiency step-down switching regulator with integrated boot diode
Adjustable regulator output
Switching regulator disable
5 V and 3.3 V compatible I/Os
Channel output status LED driving 4x2 multiplexed array
Fast demagnetization of inductive loads
ESD protection
Designed to meet IEC61131-2, IEC61000-4-
4, and IEC61000-4-5
Applications
Programmable logic control
Industrial PC peripheral input/output
Numerical control machines
Table 1: Device summary
Order code Package Packing
VNI8200XP
VNI8200XPTR
PowerSSO-36
Tube
Tape and reel
July 2015 DocID15234 Rev 9
This is information on a product in full production.
1/43 www.st.com
Contents
Contents
VNI8200XP
2 Block diagram .................................................................................. 7
3 Pin connection ................................................................................. 8
4 Maximum ratings ........................................................................... 10
5 Electrical characteristics .............................................................. 12
Power section .................................................................................. 12
SPI characteristics .......................................................................... 13
Protection and diagnostic ................................................................ 14
Step-down switching regulator ........................................................ 16
LED driving array ............................................................................ 16
6 Reverse polarity protection .......................................................... 17
7 Demagnetization energy ............................................................... 18
9 Pin function description................................................................ 20
SPI/parallel selection mode (SEL2) ................................................. 20
Serial data in (SDI) .......................................................................... 20
Serial data out (SDO) ...................................................................... 20
Serial data clock (CLK) ................................................................... 20
8/16-bit selection (SEL1) ................................................................. 21
Output enable (OUT_EN) ................................................................ 21
IC warning case temperature detection ........................................... 22
Fault indication ................................................................................ 22
Power Good ( PG ) ........................................................................ 23
Programmable watchdog counter reset (WD) ................................. 23
10 SPI operation (SEL2 = H) .............................................................. 25
8-bit SPI mode (SEL1 = L) .............................................................. 25
16-bit SPI mode (SEL1 = H) ............................................................ 25
11 LED driving array .......................................................................... 27
2/43 DocID15234 Rev 9
VNI8200XP Contents
12 Step-down switching regulator .................................................... 28
13 Typical circuits and conventions ................................................. 29
14 Thermal management ................................................................... 32
Thermal behavior ............................................................................ 33
15 Interface timing diagram ............................................................... 34
16 Switching parameter test conditions ........................................... 35
17 Package information ..................................................................... 36
PowerSSO-36 package information ................................................ 36
PowerSSO-36 packing information ................................................. 39
18 Revision history ............................................................................ 42
DocID15234 Rev 9 3/43
List of tables
List of tables
VNI8200XP
4/43 DocID15234 Rev 9
VNI8200XP
List of figures
List of figures
Figure 10: Typical circuit for switching regulation V
= 3.3 V .............................................................. 29
Figure 11: Typical circuit for switching regulation V
= 5 V ................................................................ 30
DocID15234 Rev 9 5/43
Description
1
VNI8200XP
Description
The VNI8200XP is a monolithic 8-channel driver featuring a very low supply current, with integrated SPI interface and high efficiency 100 mA micropower step-down switching regulator peak current control loop mode. The IC, realized in STMicroelectronics™
VI Power™ technology, is intended to drive any kind of load with one side connected to ground.
Active channel current limitation combined with thermal shutdown, independent for each channel, and automatic restart, protect the device against overload.
Additional embedded functions are: loss of GND protection that automatically turns off the device outputs in case of ground disconnection, undervoltage shutdown with hysteresis,
Power Good diagnostic for valid supply voltage range recognition, output enable function for immediate power outputs ON/OFF, and programmable watchdog function for microcontroller safe operation; case overtemperature protection to control the IC case temperature.
The device embeds a four-wire SPI serial peripheral with selectable 8 or 16-bit operations; through a select pin the device can also operate with a parallel interface.
Both the 8-bit and 16-bit SPI operations are compatible with daisy chain connection.
The SPI interface allows command of the output driver by enabling or disabling each channel featuring, in 16-bit format, a parity check control for communication robustness. It also allows the monitoring of the status of the IC signaling Power Good, overtemperature condition for each channel, IC pre-warning temperature detection.
Built-in thermal shutdown protects the chip from overtemperature and short-circuit. In overload condition, the channel turns OFF and ON again automatically after the IC temperature decreases below a threshold fixed by a temperature hysteresis so that junction temperature is controlled. If this condition makes case temperature reaching case temperature limit, T
CSD
, overloaded channels are turned OFF and restart, nonsimultaneously, when case and junction temperature decrease below their own reset threshold. If the case of thermal reset, the channels loaded are not switched on until the junction temperature reset event. Non-overloaded channels continue to operate normally.
Case temperature above T
CSD
is reported through the TWARN open drain pin.
An internal circuit provides a not latched common FAULT indicator reporting if one of the following events occurs: channel OVT (overtemperature), parity check fail. The Power
Good diagnostic warns the controller that the supply voltage is below a fixed threshold.
The watchdog function is used to detect the occurrence of a software fault of the host controller. The watchdog circuitry generates an internal reset on expiry of the internal watchdog timer. The watchdog timer reset can be achieved by applying a negative pulse on the WD pin. The watchdog function can be disabled by the WD_EN dedicated pin. This pin also allows the programming of a wide range of watchdog timings.
An internal LED matrix driver circuitry (4 rows, 2 columns) allows the detection of the status of the single outputs. An integrated step-down voltage regulator provides supply voltage to the internal LED matrix driver and logic output buffers and can be used to supply the external optocouplers if the application requires isolation. The regulator is protected against short-circuit or overload conditions thanks to pulse-by-pulse current limit with a peak current control loop.
6/43 DocID15234 Rev 9
VNI8200XP
2 Block diagram
Figure 1: Block diagram
Block diagram
FB
SEL1/IN1
WD_EN/IN2
OUT_EN/IN3
WD/IN4
SDI/IN5
CLK/IN6
SS/IN7
SDO/IN8
SEL2
V
REG
ROW0
ROW1
ROW2
ROW3
DC-DC converter
Undervoltage and
Power Good
Vcc clamp
SPI
LED drivng
Clamp power
Logic
Current limiter
Junction temp.
detection
Case temp.
detection
Pull down resistor
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
GIPG020420151244LM
DocID15234 Rev 9 7/43
Pin connection
3
8/43
VNI8200XP
Pin
1
2
3
4
5
6
7
8
9
10
11
Pin connection
12
13
14
15
Figure 2: Pin connection (top view)
16
17
18
11
12
13
14
15
1
2
3
4
5
6
7
8
SEL2
SEL1/IN1
WD_EN/IN2
OUT_EN/IN3
9
10
WD/IN4
SDI/IN5
CLK/IN6
SS/IN7
SDO/IN8
VREG
COL0
COL1
DCVDD
VREF
ROW0
ROW1
ROW2
ROW3
TAB=Vcc
36
NC
NC
35
34
OUT1
OUT2
33
OUT3
32
OUT4
31
30
OUT5
OUT6
OUT7
28
27
OUT8
26
NC
BOOT
25
PHASE
GND
FB
29
24
23
22
TWARN
21
FAULT
PG
20
19
GIPG020420151249LM
Name
Table 2: Pin description
Type Description
SEL2
SEL1/IN1
Logic input
Logic input
SPI/parallel selection mode
8/16-bit SPI selection mode/channel 1 input
WD_EN/IN2 Logic/analog input Watchdog enable_setting/channel 2 input
OUT_EN/IN3 Logic input Output enable/channel 3 input
WD/IN4 Logic input
Watchdog input. The internal watchdog counter is cleared on the falling edges/channel 4 input
SDI/IN5
CLK/IN6
Logic input
Logic input
Serial data input/channel 5 input
Serial clock/channel 6 input
SS /IN7 Logic input Slave select/channel 7 input
SDO/IN8
VREG
COL0
COL1
DCVDD
VREF
ROW0
Logic input/output Serial data output/channel 8 input
Power supply SPI/inputs/LED supply voltage
Open source output
Open source output
LED source output
LED source output
Analog output
Analog output
Internally generated DC-DC low voltage supply (to be connected to external 10 nF capacitor)
Internally generated DC-DC voltage reference (to be connected to external 10 nF capacitor)
Open drain output Status channel 1-2
DocID15234 Rev 9
VNI8200XP
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
TAB
GND
PHASE
BOOT
NC
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
NC
NC
TAB
Name
ROW1
ROW2
ROW3
PG
FAULT
TWARN
FB
Type
Open drain output Status channel 3-4
Open drain output Status channel 5-6
Open drain output Status channel 7-8
Description
Open drain output Power Good diagnostic, active low
Pin connection
Open drain output Fault indication, active low
Open drain output IC case warning temperature detection, active low
Analog input
Power output
Power output
Power output
Power output
Power output
Power output
Power output
Power output
Power output
Power output
Power supply
Step-down feedback input. The output voltage, directly connected to this pin, results in an output voltage of 3.3 V. An external resistor divider is required for higher output voltages
Ground
Step-down output
Step-down bootstrap voltage. Used to provide a drive voltage, higher than the supply voltage, to power the switch of the step-down regulator
Not connected
Channel 8 power output
Channel 7 power output
Channel 6 power output
Channel 5 power output
Channel 4 power output
Channel 3 power output
Channel 2 power output
Channel 1 power output
Not connected
Not connected
Exposed tab internally connected to V
CC
DocID15234 Rev 9 9/43
Maximum ratings
4 Maximum ratings
Symbol
V
CC
-V
CC
V
REG
V
FAULT
V
TWARN
V
PG
V
BOOT
V
ROW
V
COL
V dig
Table 3: Absolute maximum ratings
Parameter
Power supply voltage
Reverse supply voltage
Logic supply voltage
Voltage range at pins TWARN , FAULT , PG
Bootstrap peak voltage V
PHASE
= V
CC
Voltage range on ROW pins
Voltage range on COL pins
Voltage level range on logic input pins
I
OUT
Output current (continuous)
I
R
I
GND
I
REG
I
FAULT
I
TWARN,
I
PG
I
IN
Reverse output current (per channel)
DC ground reverse current
V
REG
input current
Current range on pins TWARN , FAULT , PG
I
I
V
ROW
COL
E
ESD
AS
Input current range
Current range on ROW pins (ROW in ON-state)
Current range on ROW pins (ROW in OFF-state)
Current range on COL pins (COL in ON-state)
Current range on COL pins (COL in OFF-state)
Electrostatic discharge (R = 1.5 kΩ; C = 100 pF)
Single pulse avalanche energy per channel not simultaneously @T amb
= 125 °, I
OUT
= 0.5 A
P
TOT
Power dissipation at T
C
= 25 °C
VNI8200XP
V
V
V
V
A
A mA mA mA mA mA mA mA mA
V
J
Unit
V
V
V
V
Value
45
-0.3
-0.3 to +6
-0.3 to +6
V
CC
+6
-0.3 to +6
-0.3 to +6
-0.3 to +6
Internally limited
(1)
-5
-250
-1/10
-1 to +10
-1 to +10
+20
-1 to +10
-10
-1 to +10
2000
3
Internally
Internally limited
-55 to 150
W
T
J
T
STG
Junction operating temperature
Storage temperature
°C
°C
Notes:
(1)
Protection functions are intended to avoid IC damage in fault conditions and are not intended for continuous operation. Continuous and repetitive operation of protection functions may reduce the IC lifetime.
10/43 DocID15234 Rev 9
VNI8200XP
Table 4: Thermal data
Symbol Parameter
R th(JC)
Thermal resistance junction-case
R th(JA)
Thermal resistance junction-ambient
Max.
Max.
Maximum
Value
2
15
ratings
Unit
°C/W
°C/W
Notes:
(1)
Per channel.
(2)
PowerSSO-36 mounted on the STEVAL-IFP022V1 developed on four-layer FR4, with about 8 cm
2
for each layer.
DocID15234 Rev 9 11/43
Electrical characteristics
5
5.1
Electrical characteristics
VNI8200XP
Power section
10.5 V < V
CC
< 36 V; -40 °C < T
J
< 125 °C; unless otherwise specified
Symbol Parameter
Table 5: Power section
Test conditions Min. Typ. Max. Unit
V
CC
V
CC clamp
Supply voltage
Clamp on V
CC
Current 20 mA
10.5
45 50
36
52
V
V
R
DS(on)
I
S
I
DS
On-state resistance
V
CC
supply current
V
REG
supply current
I
OUT
= 0.5 A at T
J
= 25 °C
I
OUT
= 0.5 A
All channels in OFF-state,
DC-DC in OFF-state,
V
REG
All channels in ON-state,
DC-DC in OFF-state
V
REG
All channels in ON-state,
DC-DC in ON-state
V
REG
= 5 V, SPI
DC-DC OFF V
REG
= 5 V SPI
OFF WD_EN = 0
DC/DC OFF V
REG
= 5 V SPI
ON WD_EN = V
REG
0.65
3.5
0.11
5.3
200
250
0.2
1.1
5.2
Ω mA mA
µA
µA
V
OUT(OFF)
I
I
LGND
F
CP
OUT(OFF)
Output current at
GND disconnection
OFF-state output voltage
OFF-state output current
Charge pump frequency
All pins at 0 V except
V
OUT
= 24 V
V
IN
= 0 V, I
OUT
= 0 A
V
IN
= V
OUT
= 0 V
0
1.45
0.5
1
2 mA
V
µA
MHz
Notes:
(1)
SS signal high, no communication.
(2)
SS signal low, communication ON.
(3)
To cover EN55022 class A and class B normative.
12/43 DocID15234 Rev 9
VNI8200XP
5.2 SPI characteristics
Electrical characteristics
10.5 V < V
CC
< 36 V; 2.7 V < V
REG
< 5 V; -40 <T j
<125 °C; unless otherwise specified
Symbol Parameter
Table 6: SPI characteristics
Test conditions Min. Typ. Max. Unit f
CLK t r
(CLK), t f
(CLK)
SPI clock frequency
SPI clock rise/fall time
-
-
5
20
MHz ns t su
( SS ) SS setup time 120 - ns t h
( SS ) SS hold time 120 - ns t t t w
(CLK) CLK high time t su
(SDI) Data input setup time t h
(SDI) Data input hold time a dis
(SDO)
(SDO)
Data output access time
Data output disable time t v
(SDO) Data output valid time t h
(SDO) Data output hold time
V
SDO
Voltage on serial data output
I
SDO
=15 mA
I
SDO
=-4 mA
80
100
100
0
V
REG
-0.8
-
-
-
-
-
-
-
-
-
100
200
100
0.8 ns ns ns ns ns ns ns
V
V
5.3 Switching
V
CC
= 24 V; -40 °C < T
J
< 125 °C
Symbol t d(ON)
Turn-ON delay time t r t d(OFF)
Turn-OFF delay time t f
Parameter
Rise time
Fall time dV/dt
(ON) dV/dt
(off)
Turn-ON voltage slope
Turn-OFF voltage slope
Table 7: Switching
Test conditions
I
OUT
= 0.5 A, resistive load, input rise time < 0.1 µs
I
OUT
= 0.5 A, resistive load, input rise time < 0.1 µs
I
OUT
= 0.5 A, resistive load, input rise time < 0.1 µs
I
OUT
= 0.5 A, resistive load, input rise time < 0.1 µs
I
OUT
= 0.5 A, resistive load, input rise time < 0.1 µs
I
OUT
= 0.5 A, resistive load, input rise time < 0.1 µs
Min. Typ. Max. Unit
- 5 - µs
-
-
-
-
-
5
10
5
3
4
-
-
-
-
-
µs
µs
µs
V/µs
V/µs
DocID15234 Rev 9 13/43
Electrical characteristics
5.4 Logic inputs
VNI8200XP
10.5 V < V
CC
< 36 V; -40 °C < T
J
< 125 °C; unless otherwise specified
Table 8: Logic inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
V
IH
V
I(HYST)
I
IN
Input low level voltage
Input high level voltage
Input hysteresis voltage
Input current V
IN
= 5 V
2.20
8
0.15
0.8 V
V
V
µA
5.5 Protection and diagnostic
10.5 V < V
CC
< 36 V; -40 °C < T
J
< 125 °C; unless otherwise specified
Symbol Parameter
Table 9: Protection and diagnostic
Test conditions Min. Typ.
V
PGH1
V
PGH2
V
PGHYS
V
USD
V
USDHYS
V demag
Power Good diagnostic ON threshold
Power Good diagnostic OFF threshold
Power Good diagnostic hysteresis
Undervoltage ON protection
Undervoltage OFF protection
Undervoltage hysteresis
Output voltage at turn-OFF
I
OUT
= 0.5 A;
L
LOAD
≥ 1 mH
16.5
15.2
8.4
0.4
17.5
16.5
1
9.5
9
0.5
Max.
18.4
17.4
10
V
CC
-52 V
CC
-50 V
CC
-45
V
TWARN
TWARN pin lowstate output voltage
I
TWARN
= 3 mA
(active condition)
0.6
V
FAULT
FAULT pin lowstate output voltage
I
FAULT
= 3 mA (fault condition)
0.6
V
PG
I
PEAK
PG pin low-state output voltage
Maximum DC output current before limitation
I
PG
= 3 mA (active condition)
V
REG
= 3.3 V V
CC
= 0
1.4
0.7
Unit
V
V
V
V
V
V
V
V
A
14/43 DocID15234 Rev 9
VNI8200XP
Symbol t
I
I
T t t
WD
WM
Hyst
LFAULT
TWARN
T
T
T
I
T t
I t
LIM
PG
TSD
T
R
CR res
WO
HIST
CSD
CHYST
OUT_EN
Parameter
Short-circuit current limitation per channel
Test conditions
R
LOAD
= 0
V
CC
= 24 V
T
J
= 25 °C
R
LOAD
= 0 I
LIM
tracking limits
FAULT leakage current
TWARN leakage current
V pin
= 5 V
PG leakage current
Junction shutdown temperature
Junction reset temperature
Junction thermal hysteresis
Case shutdown temperature
Case reset temperature
Case thermal hysteresis
Watchdog hold time
Watchdog time
OUT_EN pin
OUT_EN hold time
V
CC
= 24 V I
OUT
72 mA
Notes:
(1)
Time from reset active low and power out disable.
(2)
The time from t
WM elapsed to power out disable.
160
50
50
Min.
Electrical characteristics
Typ. Max. Unit
0.7 1.7 1.1
0.3
A
A
115
2 μA
10
180
160
20
130
110
20
155 t
WM
+ t d(off)
°C
°C
°C
°C
°C
°C ns us ns ms
DocID15234 Rev 9 15/43
Electrical characteristics
5.6 Step-down switching regulator
VNI8200XP
10.5 V < V
CC
< 36 V; -40 °C < T
J
< 125 °C; unless otherwise specified
Table 10: Step-down switching regulator
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
DC_out
Regulated output voltage
V
FB
R
DS(on)
I lim
I qop
I qst-by f s
D max
Ton min f sc
Voltage feedback
MOSFET on-resistance
Limitation current
Total operating quiescent current
Total standby quiescent current
Switching frequency
Maximum duty cycle
Minimum on-time
Frequency in short-circuit condition
I
REG
from 0 to 100 mA
V
REG
3.3 V
I
REG
from 0 to 100 mA
V
REG
5 V
Regulator standby
3.1
3.1
0.55
3.3 3.5
5
3.3 3.5
1.5
0.9
0.6
15.8
400
80%
150
50
V
V
Ω
A mA
µA kHz
% ns kHz
5.7 LED driving array
10.5 V < V
CC
< 36 V; -40 °C < T
J
< 125 °C; unless otherwise specified
Symbol Parameter
Table 11: LED driving array
Test conditions Min. Typ.
V
COL
V
ROW
F sw
Output source voltage on COL pins
Open drain voltage on
ROW pins
Row refresh frequency with duty=25%
Output current 0 to 7 mA
Output current 0 to 15 mA
V
REG
-0.3 V
REG
-0.2
0.2
780
Max. Unit
0.3
V
V
Hz
16/43 DocID15234 Rev 9
VNI8200XP
6
Reverse polarity protection
Reverse polarity protection
Reverse polarity protection can be implemented on board using two different solutions:
1. Placing a resistor (R
GND
) between IC GND pin and load GND
2. Placing a diode between IC GND pin and load GND
If option 1 is selected, the minimum resistance value has to be selected according to the following equation:
R
GND
≥ V
CC
/ I
GND where I
GND
is the DC reverse ground pin current and can be found in of this datasheet.
Power dissipated by R
GND
(when V
CC
< 0: during reverse polarity situations) is:
P
D
= (V
CC
)
2
/R
GND
If option 2 is selected, the diode has to be chosen by taking into account VRRM >|V
CC
| and its power dissipation capability:
P
D
≥ I
S
*V
F
In normal conditions (no reverse polarity), due to the diode, there is a voltage drop between GND of the device and GND of the system.
Figure 3: Reverse polarity protection
This schematic can be used with any type of load.
DocID15234 Rev 9 17/43
Demagnetization energy
7 Demagnetization energy
VNI8200XP
Figure 4: Maximum demagnetization energy vs. load current, typical values
18/43 DocID15234 Rev 9
VNI8200XP
8
Truth table
Truth table
Condition
Normal operation
Junction overtemperature
Case overtemperature
Undervoltage
Power Good
Input
Table 12: Truth table
Output
SPI status bit
High
Low
High
Low
High
Low
High
Low
High
Low
On
Off
Off
Off
Off
Off
Off
Off
On
Off
Reset
Reset
Set
Set
(1)
Set
(1)
Set
(1)
Reset
Reset
Set
(2)
FAULT TWARN
Power
Good
X
X
X
High
High
High
High
Low
High
X
High
High
X
X
Low
X
X
High
High
X
X
X
Low
Low
High
High
X
X
X
Notes:
(1)
This signal becomes high after the temperature falls below the reset threshold.
(2)
If fault expires, the reset condition occurs after SPI communication, otherwise it is set again.
DocID15234 Rev 9 19/43
Pin function description
9
9.1
9.2
9.3
9.4
20/43
Pin function description
VNI8200XP
SPI/parallel selection mode (SEL2)
This pin allows the selection of the IC interfacing mode. The SPI interface is selected if
SEL2 = H, while the parallel interface is selected if SEL2 = L, according to:
Pin
Table 13: Pin function description
SEL2 = H a
SPI operation
SEL2 = L parallel operation
SDO/IN8 SDO Serial data output IN8 Input to channel 8
SS /IN7 SS Slave select IN7 Input to channel 7
CLK/IN6
SDI/IN5
CLK
SDI
Serial clock
Serial data input
WD/IN4 WD Watchdog input
OUT_EN / IN3 OUT_EN IC OUTPUT enable / disable
WD_EN/IN2
SEL1/IN1
IN6 Input to channel 6
IN5 Input to channel 5
IN4 Input to channel 4
IN3 Input to channel 3
WD_EN Watchdog enable / disable and timing preset IN2 Input to channel 2
SEL1 8/16-bit SPI selection mode IN1 Input to channel 1
Serial data in (SDI)
If SEL2 = H, this pin is the input of the serial control frame. SDI is read on CLK rising edges and, therefore, the microcontroller must change SDI state during the CLK falling edges.
After the SS falling edge, the SDI is equal to the most significant bit of the control frame.
Serial data out (SDO)
If SEL2 = H, this pin is the output of the serial fault frame. SDO is updated on CLK falling edges and, therefore, the microcontroller must read SDO state during the CLK rising edges.
The SDO pin is tri-stated when SS signal is high and it is equal to the most significant bit of the fault frame after the SS falling edge.
Serial data clock (CLK)
If SEL2 = H, the CLK line is the input clock for serial data sampling. On CLK rising edge the
SDI input is sampled by the IC and the SDO output is sampled by the host microcontroller.
On CLK falling edge, both SDI and SDO lines are updated to the next bit of the frame, from the most to the less significant one. When the SS signal is high, slave not selected, the microcontroller should drive the CLK low (the settings for the MCU SPI port are CPHA = 0 and CPOL = 0). a
SEL2 has an internal weak pull-down.
DocID15234 Rev 9
VNI8200XP
9.5 Slave select
Pin function description
If SEL2 = H, the slave select ( SS ) signal is used to enable the VNI8200XP serial communication shift register; data is flushed-in through the SDI pin and flushed-out from the SDO pin only when the SS pin is low. On the SS pin falling edge the shift register
(containing the fault conditions) is frozen, so any change on the power switches status is latched until the next SS falling edge event and the SDO output is enabled. On the SS pin rising edge event the 8/16 bits present on the SPI shift register are evaluated and the outputs are driven according to this frame. If more than 8/16 bits (depending on the SPI settings) are flushed inside only the last 8/16 are evaluated; the others are flushed out from the SDO pin after fault condition bits; in this way a proper communication is possible also in a daisy chain configuration.
Figure 5: SPI mode diagram
9.6
9.7
8/16-bit selection (SEL1)
If SEL2 = H, SEL1 is used to select between two possible SPI configurations: the 8-bit SPI mode (SEL1 = L) and the 16-bit SPI mode (SEL1 = H). 8/16-bit SPI operation is described below.
Output enable (OUT_EN)
If SEL2 = H, the OUT_EN pin provides a fast way to disable all the outputs simultaneously.
When the OUT_EN pin is driven low for at least T
RES
, the outputs are disabled while fault conditions in the SPI register are latched. To enable the outputs, the OUT_EN pin should be raised and the IC should be re-programmed through the SPI interface. As fault conditions are latched inside the IC and SPI interface also works while the OUT_EN pin is driven low, the SPI can be used to detect if a fault condition occurred before than the reset event.
The device is ready to operate normally after a T
SU period. The OUT_EN pin is the fastest way to disable all outputs when a fault occurs.
DocID15234 Rev 9 21/43
Pin function description
Figure 6: Output channel enable/disable behavior
VNI8200XP
9.8
9.9
22/43
IC warning case temperature detection
The TWARN pin is an active low open drain output. This pin is activated if the IC case temperature exceeds T
CSD
. According to the PCB thermal design and R thJC
value, this function allows a warning about a PCB overheating condition to be given.
The TWARN bit is also available through SPI. This bit is not latched: the TWARN pin is low only while the case overtemperature condition is active (T
C
> T
CSD
) and is released when this condition is removed (T
C
< T
CR
).
Fault indication
The FAULT pin is an open drain active low fault indication pin. This pin is activated by one or more of the following conditions:
Channel overtemperature (OVT)
This pin is activated when at least one of the channels is in junction overtemperature.
Unlike the SPI fault detection bits, this signal is not latched: the FAULT pin is low only when the fault condition is active and is released if the input driving signal is OFF or after the OVT protection condition has been removed. This last event occurs if the channel temperature decreases below the threshold level and the case temperature has not exceeded T
CSD
or is below T
CR
. This means that the FAULT pin is low only while the junction overtemperature is active (T
J
> TTSD) and is released after this condition has been removed (T
J
< TR and TC < TCR).
Parity check fail
When SPI mode is used (SEL2 = H), if a parity check fault of the incoming SPI frame is detected or counted, CLK rising edges are different by a multiple of 8, the FAULT pin is kept low. When counted CLK rising edges are a multiple of 8 and parity check is valid, the
FAULT pin is kept high.
DocID15234 Rev 9
VNI8200XP
9.10 Power Good ( PG )
Pin function description
The PG terminal is an open drain, which indicates the status of the supply voltage. When
V
CC
supply voltage reaches the V sth1
threshold, PG goes into a high impedance state. It goes into a low impedance state when V
CC
falls below the V sth2
threshold.
In 16-bit SPI mode, a PG bit is also available. This bit is set high when the Power Good diagnostic is active, it is otherwise cleared.
Figure 7: Power Good diagnostic
PG
VPGH2 VPGH1 Vcc
GIPG030420151221LM
9.11 Programmable watchdog counter reset (WD)
If SEL2 = H, the VNI8200XP embeds a watchdog counter that must be erased, with a negative pulse on the WD pin, before it expires. If the WD counter elapses, the VNI8200XP goes into an internal reset state where all the outputs are disabled; to restart normal operation a negative pulse must be applied to the WD pin.
The watchdog enable/disable pin should be connected through an external divider to V
REG
.
The watchdog time is fixed in the following table:
V
WD_EN
Table 14: Programmable watchdog time t
WM
0.25 V
REG
> V
WD_EN
0.25 V
REG
≤ V
WD_EN
< 0.5 V
REG
0.25 V
REG
≤ V
WD_EN
< 0.75 V
REG
0.75 V
REG
≤ V
WD_EN
= V
REG
Disable
40 ± 25% ms
80 ± 25% ms
160 ± 25% ms
DocID15234 Rev 9 23/43
Pin function description
Figure 8: Watchdog reset
VNI8200XP
24/43 DocID15234 Rev 9
VNI8200XP SPI operation (SEL2 = H)
10 SPI operation (SEL2 = H)
10.1 8-bit SPI mode (SEL1 = L)
If SEL2 = H, the 8-bit SPI mode is based on an 8-bit command frame sent from the microcontroller to the IC; each bit directly drives the corresponding output where LSB drives output 0 and MSB drives output 7. Each bit, set to ‘1’, activates (closes) the corresponding output.
At the same time, the IC transfers the channel fault conditions (OVT) to the microcontroller.
These fault conditions are latched at the occurrence and cleared after each communication
(each time the SS signal has a positive transition). Each bit, set to ‘1’, indicates an OVT condition for the corresponding channel.
Table 15: Command 8-bit frame (master-to-slave)
MSB LSB
IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0
Table 16: Fault 8-bit frame (slave-to-master)
MSB LSB
F7 F6 F5 F4 F3 F2 F1 F0
10.2 16-bit SPI mode (SEL1 = H)
The 16-bit SPI mode is based on a 16-bit command frame sent from the microcontroller to the IC; the first 8 bits directly drive the output channels (each bit, set to ‘1’, activates the corresponding output), the other 8 bits contain a 4-bit parity check code where the last bit
(the inversion of the previous one) is used to detect a communication error condition
(providing at least a transition in each frame):
P0 = IN0 +IN1+ IN2 +IN3 +IN4+ IN5+ IN6 +IN7
P1 = IN1 + IN3 + IN5 + IN7
P2 = IN0 + IN2 + IN4 + IN6 nP0 = Not P0
Table 17: Command 16-bit frame (master-to-slave)
MSB
IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0 P2 P1 P0
At the same time, the IC transfers to the microcontroller a 16-bit fault frame where the first
8 bits indicate a channel fault (OVT) condition (each bit, set to ‘1’, indicates an OVT event), the following 4 bits provide general fault condition information. FB_OK: this bit is related to the DC-DC regulation: at the DC-DC turn-on, this bit is low and becomes high after FB rises above 90% of the nominal V
FB
voltage and a correct SPI communication occurred. If the FB voltage falls below 80% of the nominal V
FB
voltage, this bit is zero; TWARN (IC warning case temperature), PC (parity check fail, the bit, set to ‘1’, indicates a PC fail or the
LSB nP0
DocID15234 Rev 9 25/43
SPI operation (SEL2 = H) VNI8200XP length is not a multiple of 8) and PG (Power Good). The last 4 bits are used as parity check bits and communication error condition (see command 16-bit frame):
P0 = F0+ F1+ F2 + F3 + F4 + F5 + F6 + F7
P1 = PC+ FB_OK + F1 + F3 + F5 + F7
P2 = PG + TWARN + F0 + F2 + F4 + F6 nP0 = not P0
Table 18: Fault 16-bit frame (slave-to-master)
MSB
F7 F6 F5 F4 F3 F2 F1 F0 FB_OK TWARN PC PG P2
Channel indications are latched and cleared after a communication only.
LSB
P1 P0 nP0
26/43 DocID15234 Rev 9
VNI8200XP
11
LED driving array
LED driving array
The LED driving array carries out the status of the output channels (ON or OFF).
Figure 9: LED driving array
The following equation is an indication how to choose the R ext resistor value:
R ext
= (V
COLmin.
) - (V
ROWmax.
)- V
F(LED)
/ I
F(LED) where I
F(LED)
≤ 7 mA and (V
COL
min.) and (V
ROW
max.) can be found in and V
F(LED)
and I
F(LED) depend on the electrical characteristics of the LEDs.
DocID15234 Rev 9 27/43
Step-down switching regulator
12 Step-down switching regulator
VNI8200XP
The IC embeds a high efficiency 100 mA micropower step-down switching regulator. The regulator is protected against short-circuit or overload conditions. Pulse-by-pulse current limit regulation is obtained in normal operation through a current loop control.
A low ESR output capacitor connected to the V
REG pin
helps to limit the regulated voltage ripple; a low ESR (less than 10 mΩ) capacitor is preferable. The control loop pin FB allows
3.3 V to be regulated, connecting it directly to V
REG
, or 5 V connecting it through a voltage divider R l
/R fbl
. The DC-DC converter can be turned off by connecting the feedback pin to the DCVDD pin. In some applications it is possible to supply a 5 V or 3.3 V voltage externally or, in the case of two or more VNI8200XP inside the same board, it's possible to configure the DC-DC converter on only one device and also supply the other ICs. if the DC-DC converter is adjusted to provide 3.3 V regulation and the V
DC_out
is used to power an external load and not the device, a 33 kΩ resistor has to be connected on V
DC_out pin.
28/43 DocID15234 Rev 9
VNI8200XP
13
Typical circuits and conventions
Typical circuits and conventions
Figure 10: Typical circuit for switching regulation V
DC-out
= 3.3 V
DocID15234 Rev 9 29/43
Typical circuits and conventions
Figure 11: Typical circuit for switching regulation V
DC-out
= 5 V
VNI8200XP
30/43 DocID15234 Rev 9
VNI8200XP Typical circuits and conventions
Figure 12: SPI directional logic convention
SDI
SS
CLK
SDO
WD
OUT_EN
WD_EN
SEL1
SEL2
PG
FAULT
TWARN
VREG
TAB=Vcc
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
GIPG030420151337LM
DocID15234 Rev 9 31/43
Thermal management
14 Thermal management
VNI8200XP
The power dissipation in the IC is the main factor that sets the safe operating condition of the device in the application. Therefore, it must be taken into account very carefully.
Heatsinking can be achieved using copper on the PCB with proper area and thickness. The following image shows the junction-to-ambient thermal impedance values for the
PowerSSO-36 package.
Figure 13: PowerSSO-36 thermal impedance vs. time
For instance, three cases have been considered using a PowerSSO-36 packaged with copper slug soldered on a 1.6 mm thickness FR4 board with dissipating footprint (copper thickness of 70 µm):
single layer PCB with just IC footprint dissipating area
double layer PCB with footprint dissipating area on the top side and a 2 cm
2 dissipating layer on the bottom side through 15 via holes
double layer PCB with footprint dissipating area on the top side and an 8 cm
2 dissipating layer on the bottom side through 15 via holes
32/43 DocID15234 Rev 9
VNI8200XP
14.1 Thermal behavior
Figure 14: Thermal behavior
Thermal management
1 Thermal shutdown
2 Junction hysteresis
3 Restore to idle condition
4 Case hysteresis
DocID15234 Rev 9 33/43
Interface timing diagram
15 Interface timing diagram
Figure 15: Serial timing
VNI8200XP
34/43 DocID15234 Rev 9
VNI8200XP
16
Switching parameter test conditions
Switching parameter test conditions
Figure 16: dV/dt(ON) and dV/dt(OFF) time diagram test conditions
Figure 17: t d(ON)
and t d(OFF)
time diagram test conditions
DocID15234 Rev 9 35/43
Package information VNI8200XP
17 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
17.1 PowerSSO-36 package information
Figure 18: PowerSSO-36 package outline
36/43 DocID15234 Rev 9
7587131 rev9
VNI8200XP
Figure 19: PowerSSO-36 package outline details
Package information
Not in scale (section A-A)
Figure 20: PowerSSO-36 package outline details (section B-B)
Not in scale (section B-B)
DocID15234 Rev 9 37/43
Package information
Dim.
N
R
R1
S h
L
L1
L2
E1
E2
E3
E4
G1
G2
G3 c1
D
D1
D2
D3 e
E
A2 b b1 c ɵ ɵ1 ɵ2
A
A1
0.30
0.20
0.25
0.30
0.60
4.20
Table 19: PowerSSO-36 mechanical data mm
Min.
0°
Typ.
5°
0°
2.15
0.00
2.15
0.18
0.13
0.23
0.25
0.20 0.20
10.30 BSC
7.00
3.65
4.30
0.50 BSC
10.30 BSC
7.50 BSC
2.30
2.90
1.20
1.00
0.80
0.70
1.40 REF
0.25 BSC
36
VNI8200XP
7.40
4.200
0.40
0.85
4.60
Max.
8°
10°
2.45
0.10
2.35
0.32
0.30
0.32
0.30
38/43 DocID15234 Rev 9
VNI8200XP
17.2 PowerSSO-36 packing information
Figure 21: PowerSSO-36 tube shipment outline
Package information
Table 20: PowerSSO-36 tube shipment mechanical data
Description
Base quantity
Bulk quantity
Tube lenght (± 0.5)
A
B
C (± 0.1)
Value
49
1225
532
3.5
13.8
0.6
All dimensions are in mm
DocID15234 Rev 9 39/43
Package information
Figure 22: PowerSSO-36 tape dimension outline
VNI8200XP
40/43
Table 21: PowerSSO-36 tape dimension mechanical data
Description Dimensions
Tape width
Tape hole spacing
Component spacing
W
P0 (± 0.1)
P
Hole diameter
Hole diameter
Hole position
Compartment depth
Hole spacing
D (± 0.05)
D1 (min.)
F (± 0.1)
K (max.)
P1 (± 0.1)
Value
24
4
12
1.55
1.5
11.5
2.85
2
According to the Electronic Industries Association (EIA) standard 481 rev. A, Feb
1986
DocID15234 Rev 9
VNI8200XP
Figure 23: PowerSSO-36 reel shipment outline
Package information
Table 22: PowerSSO-36 reel dimension mechanical data
Description Value
Base quantity
Bulk quantity
1000
1000
A max.
B min.
C (± 0.2)
F
G (2 ± 0)
N min.
T min.
330
1.5
13
20.2
24.4
100
30.4
DocID15234 Rev 9 41/43
Revision history
18
VNI8200XP
Revision history
Date
Table 23: Document revision history
Revision Changes
04-Dec-2008
29-Apr-2009
19-Jun-2012
27-Jun-2012
08-Mar-2013
04-Dec-2013
20-Feb-2014
30-Apr-2015
30-Jul-2015
1
2
3
4
5
6
7
8
9
Initial release.
Updated table 5.
Updated: Features,Section 9.4, Section 9.7,Section
9.9, Section 9.10, Section 12, Table 2,Table 3,Table 5,
Table 7, Table 8, Table 9, Table 10,Table 11,Table 14,
Figure 1, Figure 2. Changed: Figure 6, Figure 7,
Figure 8, Figure 17, Figure 17. Content reworked to improve the readability.
Updated section 10.2.
Updated Table 5, Table 9, Table 10, Table 14.
Updated footnote 2. in Table 4. Updated Section 12.
Added Section 6. Changed Figure 10 and Figure 11.
Added Table 12. Changed product status to production data.
Updated EAS parameter in Table 3: Absolute maximum ratings. Updated Section 6: Reverse polarity protection. Added Section 7: Demagnetization energy.
Changed figure 4
Updated package information section.
Updated I s
parameter in power section table and protection and diagnostic table.
Updated programmable watchdog time table.
42/43 DocID15234 Rev 9
VNI8200XP
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics
– All rights reserved
DocID15234 Rev 9 43/43
Lejupielādēt
Publiskā saite ir atjaunināta
Ir atjaunināta publiskā saite uz jūsu tērzēšanu. You may view and manage your chat links after registration here.
Dokumenta publiskā saite
Reklāma