STMicroelectronics IPS8160HQ Datasheet
STMicroelectronics IPS8160HQ-1 is an advanced high-side driver designed for industrial applications. It boasts 8 channels with a steady-state operating current of up to 1A per channel, making it ideal for various high-power switching applications. With built-in protection features like overtemperature shutdown, overload and short-circuit protection, and loss of ground detection, this device ensures reliable operation in demanding conditions. The STATUS pin provides a diagnostic output for overtemperature conditions, enhancing system safety.
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Product status link
IPS8160HQ
IPS8160HQ-1
Product label
IPS8160HQ, IPS8160HQ-1
Datasheet
Octal channel high-side driver
Features
• Operating output current: 0.7 A (IPS8160HQ) or 1.0 A (IPS8160HQ-1) per channel
• CMOS compatible input
• Very low standby current
• Undervoltage shutdown
• Overload and short-circuit protection with output current limitation
• Junction overtemperature protection
• Case overtemperature protection for thermal independence of the channels
• Protection against loss of ground
• Thermal shutdown diagnostic pin
• Designed to meet IEC 61000-4-2, IEC 61000-4-4, IEC 61000-4-5
• Package: QFN48L 8x6x0.9 mm
Applications
• Programmable logic control
• Vending machines
• Industrial PC peripheral input/output
• Numerical control machines
• General high-side switch applications
Description
The IPS8160HQ and IPS8160HQ-1 are monolithic devices designed with
STMicroelectronics VIPower M0-3 technology, intended to drive any kind of load with one side connected to ground. They can be driven by using a 3.3 V logic supply.
They are suitable for applications with up to 0.7 A (IPS8160HQ) or 1 A
(IPS8160HQ-1) steady-state operating current.
Active current limitation combined with thermal shutdown and automatic restart protect the devices against overload. In overload conditions, the channel turns
OFF and ON again automatically to maintain the junction temperature between
T
JSD
and T
R
. If this condition causes the case temperature to trigger T
CSD
, then overloaded channels are turned OFF and can be turned back ON only when the case temperature decreases down to T
CR
. Non-overloaded channels continue to operate normally.
The devices automatically turn OFF in case of ground pin disconnection.
Devices are especially suitable for industrial applications conforming to IEC 61131.
DS13934 - Rev 1 - December 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
IPS8160HQ, IPS8160HQ-1
Block diagram
1
Block diagram
Figure 1. IPS8160HQ, IPS8160HQ-1 block diagram
DS13934 - Rev 1 page 2/28
2
IPS8160HQ, IPS8160HQ-1
Pin connections
Pin connections
Figure 2. Connection diagram (top through view)
DS13934 - Rev 1
Symbol
OUT1
N.C.
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
GND
STATUS
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
V
CC
Pin
18
19
20
21
33
34
35, 36
1, 2
3 to 13,
22 to 32
14
15
16
17
37, 38
39, 40
41, 42
43, 44
45, 46
47, 48
EP
Table 1. Pin functions
Description
Channel 1 power output
Not connected
Channel 1 input
Channel 2 input
Channel 3 input
Channel 4 input
Channel 5 input
Channel 6 input
Channel 7 input
Channel 8 input
Output power ground
Common open source diagnostic for overtemperature
Channel 8 power output
Channel 7 power output
Channel 6 power output
Channel 5 power output
Channel 4 power output
Channel 3 power output
Channel 2 power output
Supply voltage page 3/28
3
IPS8160HQ, IPS8160HQ-1
Maximum ratings
Maximum ratings
Symbol
V
CC
-I
GND
I
OUT
-I
OUT
I
IN
V
IN
V
ESD
P
TOT
EAS
T
J
T
C
T
STG
Table 2. Absolute maximum ratings
Parameter
DC supply voltage
DC ground reverse current
Transient ground reverse current (pulse duration < 1 ms)
DC output current
Reverse DC output current
DC input current range
Input voltage range
Electrostatic discharge (R = 1.5 KΩ; C = 100 pF)
Power dissipation at Tc = 25 °C
Single pulse Avalanche Energy per channel, all channels driven simultaneously (Tamb = 125 °C, I
OUT
= 0.6 A per channel)
Junction operating temperature
Case operating temperature
Storage temperature range
Value
45
250
6
Internally limited
2
-1, +10
-0.3, +5.5
2000
4
0.5
Internally limited
Internally limited
-40, +150
J
°C
°C
°C
A mA
V
V
W
Unit
V mA
A
A
DS13934 - Rev 1 page 4/28
4
IPS8160HQ, IPS8160HQ-1
Thermal data
Thermal data
Table 3. Thermal data
Symbol
R th(JC)
R th(JA)
Parameter
Thermal Resistance, Junction-to-case per channel
Thermal Resistance, Junction-to-ambient
1. Rth between the die and the bottom case surface measured by cold plate as per JESD51.
2. JESD51-7.
Max. Value
1.5
30
Unit
°C/W
DS13934 - Rev 1 page 5/28
5
IPS8160HQ, IPS8160HQ-1
Electrical characteristics
Electrical characteristics
10.5 V < V
CC
< 32 V; -40 °C < T
J
< 125 °C; unless otherwise specified.
Symbol
V
USD
R
ON
I
S
I
LGND
I
L(OFF)
V
OUT(OFF)
Table 4. Power section
Parameter
V
CC
undervoltage turnoff threshold
Test Condition
ON-state resistance
I
OUT
≤ 1 A; T
J
= 25 °C; V
CC
≤ 36 V
I
OUT
≤ 1 A; T
J
= 125 °C; V
CC
≤ 36 V
Supply current
OFF-state
V
CC
= 24 V; T
CASE
= 25 °C
ON-state (all channels ON)
V
CC
= 24 V; T
CASE
= 100 °C
Output current at turn-off
V
CC
= V
GND
= 24 V;
V
STAT
= V
IN
= 5 V; V
OUT
= 0 V; T
J
= 25 °C
V
CC
= V
GND
= 24 V;
V
STAT
= V
IN
= 5 V; V
OUT
= 0 V; T
J
= 125 °C
OFF-state output current V
IN
= V
OUT
= 0 V
OFF-state output voltage
V
IN
= 0 V; I
OUT
= 0 A
Min.
Typ.
Max.
Unit
7 10.5
V
160
280 mΩ mΩ
150 µA
12 mA
0.5
mA
0
0.55
mA
5
3
µA
V
Symbol t
ON t
OFF
Parameter
Turn-ON time
Turn-OFF time
Table 5. Switching (V
CC
= 24 V)
Test Condition
R
L
= 48 Ω; from 50% V
IN
to 80% V
OUT
R
L
= 48 Ω; from 50% V
IN
to 10% V
OUT
t
OFF
- t
ON
Turn-OFF, Turn-ON matching dV
OUT t
/dt
(ON) dV
OUT
/dt
(OFF) d(VCCON)
Turn-ON voltage slope
Turn-OFF voltage slope
Power on delay time from
VCC rising edge
R
L
= 48 Ω; from V
19.2 V
OUT
= 2.4 V to V
OUT
=
R
L
= 48 Ω; from V
= 2.4 V
OUT
= 21.6 V to V
OUT
Min.
20
20
-40
Typ.
30
Max.
60
Unit
µs
40
10
0.7
1.5
1
80
60
µs
μs
V/µs
V/µs ms
DS13934 - Rev 1 page 6/28
Figure 3. Turn-ON and turn-OFF
IPS8160HQ, IPS8160HQ-1
Electrical characteristics
Figure 4. V
CC
turn-ON
DS13934 - Rev 1
Symbol
V
INL
I
INL
V
INH
I
INH
V
IN(HYST)
Parameter
Input low level
Low level input current
Input high level
High level input current
Input hysteresis voltage
V
CL
Input clamp voltage
Table 6. Input pins
Test Condition
V
IN
= 1.25 V
V
IN
= 2.25 V
I
IN
= 1 mA
I
IN
= -1 mA
Min.
1
2.25
0.25
6.0
Typ.
Max.
1.25
6.8
-0.7
10
8.0
Unit
V
µA
V
µA
V
V page 7/28
DS13934 - Rev 1
IPS8160HQ, IPS8160HQ-1
Electrical characteristics
I
LIM
Table 7. Protections
Symbol
T
CSD
T
CR
T
CHYST
T
JSD
T
R
T
HYST
I
PEAK
Parameter
Case shutdown temperature
Case reset temperature
Case thermal hysteresis
Junction shutdown temperature
Junction reset temperature
Junction thermal hysteresis
Maximum DC output current before limitation
DC short-circuit current limitation per channel
Test Condition Min.
125
110
7
150
135
Typ.
130
15
175
Max.
135
200
V
CC
= 24 V; R
LOAD
= 10 mΩ
7
1.1
15
2.6
I
V
CC
= 24 V; R
LOAD
= 10 mΩ
OUT
= 0.5 A; L= 6 mH
0.7
1.7
1
V
CC
-57 V
CC
-52 V
CC
-47 V
DEMAG
Turn-OFF output clamp voltage
1. IPS8160HQ
2. IPS8160HQ-1
°C
°C
°C
Unit
°C
°C
°C
A
A
V
Symbol
I
HSTAT
I
LSTAT
Parameter
STATUS pin high level current
STATUS pin leakage current
V
CLSTAT
STATUS pin clamp voltage
Table 8. Status Pin
Test Condition
V
CC
= 18 to 32 V; R
STAT
(Fault condition)
= 1 kΩ
Normal operation; V
CC
= 32 V
I
STAT
= 1 mA
I
STAT
= -1 mA
Min.
2
6.0
Typ.
3
Max.
4
0.1
8.0
6.8
-0.7
Unit mA
μΑ
V page 8/28
6
IPS8160HQ, IPS8160HQ-1
Current, voltage conventions and truth table
Current, voltage conventions and truth table
Figure 5. Current and voltage conventions
DS13934 - Rev 1
Normal operation
Current limitation
Undervoltage
1. Pin voltage = I
OUT
* R
LOAD
Conditions
Overtemperature (see Figure 10 and
)
Table 9. Truth table
INPUTx
L
H
L
H
L
H
L
H
OUTPUTx
L
H
L
X
L
L
L
L
STATUS
X
X
L
H
L
L
L
L page 9/28
IPS8160HQ, IPS8160HQ-1
Power Section
7
Power Section
7.1
Current limitation
Current limitation process is activated when the current sense connected on the output stage measures a current value higher than a fixed threshold.
When this condition is verified, the gate voltage is modulated to prevent the output current from rising above the limitation value.
The following figures show typical output current waveforms with different load conditions.
Figure 6. Switching on resistive and on bulb lamp load
Figure 7. Switching on light and heavy inductive load
DS13934 - Rev 1 page 10/28
IPS8160HQ, IPS8160HQ-1
Thermal protection
Figure 8. Short-circuit during ON-state and switching on short-circuit
7.2
Thermal protection
The device is protected against overheating due to overload conditions. During the driving period, if the output is overloaded, the device suffers two different thermal stresses, the first is related to the junction, and the second related to the case.
The two faults have different trigger thresholds: the junction protection threshold (T
JSD
) is higher than the case protection one (T
CSD
); generally the first protection that is activated in thermal stress conditions is the junction thermal shutdown. The output is turned off when the temperature is higher than the related threshold and turned back on when it goes below the reset threshold (T
JR
). This behavior continues until the fault on the output is present.
If the thermal protection is active and the temperature of the package increases over the fixed case protection threshold, the case protection is activated and the output is switched off and back on when the junction temperature, of each channel in fault and case temperature, are below the respective reset thresholds.
DS13934 - Rev 1 page 11/28
Figure 9. Thermal protection flowchart
IPS8160HQ, IPS8160HQ-1
Status indication
Input(i) ON
Output(i) ON
Status(i) OFF
7.3
N
T J (i) > T JSD
Y
Output(i) OFF
Status(i) ON
T C >T CSD
N
Y
Y
T C >T CR
N
T JR >T JR(i)
Y
N
Status indication
The Status pin is an active high common open source output indicating fault conditions. This pin is activated in case of junction overtemperature (T
JX
>T
JSD
) of one or more output channels.
STATUS behavior when T
JSD
is triggered before T
CSD and when T
CSD
is triggered before T
JSD
respectively.
Figure 10. Thermal protection and STATUS behavior (T
JSD
triggered before T
CSD
)
DS13934 - Rev 1 page 12/28
IPS8160HQ, IPS8160HQ-1
Status indication
Figure 11. Thermal protection and STATUS behavior (T
CSD
triggered before T
JSD
)
DS13934 - Rev 1 page 13/28
8
Note:
IPS8160HQ, IPS8160HQ-1
Reverse polarity protection
Reverse polarity protection
Reverse polarity protection can be implemented on board using two different solutions:
1.
Placing a resistor (R
GND
) between IC GND pin and load GND
2.
Placing a diode between IC GND pin and load GND
If option 1 is selected, the minimum resistance value has to be selected according to the following equation:
R
GND
≥ V
CC
/ I
GND where I
GND
is the DC reverse ground pin current and can be found in
of this datasheet.
Power dissipated by R
GND
(when V
CC
< 0, reverse polarity situations) is:
P
D
= (V
CC
) 2 / R
GND
If option 2 is selected, the diode has to be chosen by taking into account VRRM > |V cc
| and its power dissipation capability:
P
D
≥ I
S
x V f
In normal operation (no reverse polarity), there is a voltage drop (ΔV) between GND of the device and GND of the system. Using option 1, ΔV = R
GND
x I
CC
; using option 2, ΔV = VF@(IF).
Figure 12. V
CC
Reverse Polarity Protection
DS13934 - Rev 1
This schematic can be used with any type of load.
page 14/28
9
IPS8160HQ, IPS8160HQ-1
Active clamp
Active clamp
Active clamp is also known as Fast Demagnetization of inductive loads or Fast Current Decay. When a high-side driver turns off an inductance, an undervoltage on the output is detected.
The OUT pin is pulled down to V
CC
-V
DEMAG
. The conduction state is modulated by an internal circuitry in order to keep the OUT pin voltage at ~V
DEMAG
until the load energy has been dissipated. The energy is dissipated in both
IC internal switch and load resistance.
Figure 13. Active clamp typical waveforms
Figure 14. Typical demagnetization energy (single pulse, all channels) at V
CC
= 24 V and T
AMB
= 125 °C
DS13934 - Rev 1 page 15/28
IPS8160HQ, IPS8160HQ-1
Thermal information
10
Thermal information
10.1
Thermal impedance
Figure 15. Simplified thermal model of the process stage
DS13934 - Rev 1 page 16/28
11
11.1
IPS8160HQ, IPS8160HQ-1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
ECOPACK is an ST trademark.
QFN48L 8x6 mm package mechanical data
Figure 16. QFN48L 8x6 mm package information
DS13934 - Rev 1 page 17/28
DS13934 - Rev 1
IPS8160HQ, IPS8160HQ-1
QFN48L 8x6 mm package mechanical data
Symbol
E2
L k
N e
E
D2
A
A1
A3 b
D
Table 10. QFN48L 8x6 mm package mechanical data
Min.
0.80
0.00
0.20
5.97
3.97
0.365
0.53
[mm]
Nom.
0.85
-
0.2 REF
0.25
8 BSC
0.50 BSC
6.00 BSC
6.02
4.02
0.40
Max.
0.90
0.05
0.30
6.07
4.07
0.435
48
Note
12
9, 12
5, 6, 7, 12, 13
4, 12
4, 12
12, 13
8
Symbol aaa bbb ccc ddd eee fff
Note
REF
Table 11. Tolerance of forms and positions
Tolerance of form and position
0.10
0.10
0.10
0.05
0.08
0.10
1,12
NOTES (to be reported on column "Note" of package mechanical data table)
1.
Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2.
All the dimensions are in mm.
3.
Terminal A1 identifier and terminal numbering convention shall conform to JEP95 SPP-002. Terminal A1 identifier must be located within the zone indicated on the outline drawing. Topside terminal A1 indicator may be molded, or metalized feature. Optional indicator on bottom surface may be a molded, marked, or metallized feature.
4.
Outlines with "D" and "E" increments less than 0.5 mm should be registered as "standalone" outlines. These outlines should use as many of the algorithms and dimensions states in the design standard as possible to ensure predictability in manufacturing.
5.
Dimension "b" applies to the metalized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension "b" should not be measured in that radius area.
6.
Inner edge of corner terminals may be chamfered or rounded in order to achieve minimum gap "k". This feature should not affect the terminal with "b", which is measured L/2 from the edge of the package body.
7.
Exact shape of the leads at the edge of the package is optional.
page 18/28
DS13934 - Rev 1
IPS8160HQ, IPS8160HQ-1
QFN48L 8x6 mm package mechanical data
8.
"N" is the maximum number of terminal positions for the specified body size. Depopulation is allowed, but only under the following conditions:
– Depopulation scheme must be consistent in each quadrant of the package
– Non-symmetric variations should be broken out as separate mechanical outline variations, including depopulation graphics.
9.
A1 is defined as the distance from the seating plane to the lowest point on the package body (standoff).
10. Dimension D2 and E2 refer to exposed pad. For exposed pad dimensions see Variation Table.
11. For tolerance of form and position see Table below.
12. Critical dimensions:
– A
– A1
– D & E
– b & L
– e
– D2 & E2
13. Dimensions "b" and "L" are measured at terminal plating surface.
14. Depending on the method of lead termination at the edge of the package, pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3 mm.
15. For Symbols, Recommended Values and Tolerances see Table below: (ACCORDING TO PACKAGE OR
JEDEC SPEC IF REGISTERED).
Symbol aaa bbb ccc ddd eee fff
Table 12. Definitions
Definition
The bilateral profile tolerance that controls the position of the plastic body sides. The centers of the profile zones are defined by the basic dimensions D and E.
The tolerance that controls the position of the entire terminal pattern with respect to Datum's A and B. The center of the tolerance zone for each terminal is defined by basic dimension "e" as related to Datum's A and B.
The tolerance located parallel to the seating plane in which the top surface of the package must be located.
The tolerance that controls the position of the terminals to each other. The centers of the profile zones are defined by basic dimension "e"
Notes
The unilateral tolerance located above the seating plane where in the bottom surface of all terminals must be located.
The tolerance that controls the position of the exposed metal heat feature. The center of the tolerance zone is the datum's defined by the centerlines of the package body.
This tolerance is normally compounded with tolerance zone defined by bbb.
This tolerance is commonly known as the "coplanarity" of the package terminals.
page 19/28
DS13934 - Rev 1
IPS8160HQ, IPS8160HQ-1
QFN48L 8x6 mm package mechanical data
Figure 17. QFN48 8x6 mm suggested footprint [mm]
STMicroelectronics is not responsible for PCB-related issues. The footprint shown in the above figure is a suggestion which may differ from the customer PCB supplier design rules.
page 20/28
12
IPS8160HQ, IPS8160HQ-1
Packing information
Packing information
Figure 18. QFN48L 8x6 mm reel shipment reference
DS13934 - Rev 1
Item
Ao
Bo
Ko
T
Table 13. Standard SPC parameters
Description
Pocket Length
Pocket Width
Pocket Depth
Tape Thickness page 21/28
DS13934 - Rev 1
IPS8160HQ, IPS8160HQ-1
Packing information
Figure 19. QFN48L 8x6 mm tape dimensions
Figure 20. QFN48L 8x6 mm tape, Pin 1 indication page 22/28
13
Ordering information
Part number
IPS8160HQ
IPS8160HQ-1
Table 14. Ordering information
Package
QFN48L 8x6 mm
IPS8160HQ, IPS8160HQ-1
Ordering information
Packaging
Tape and reel
DS13934 - Rev 1 page 23/28
IPS8160HQ, IPS8160HQ-1
Revision history
Date
23-Dec-2022
Version
1
Table 15. Document revision history
Changes
Initial release.
DS13934 - Rev 1 page 24/28
IPS8160HQ, IPS8160HQ-1
Contents
Contents
DS13934 - Rev 1 page 25/28
IPS8160HQ, IPS8160HQ-1
List of tables
List of tables
DS13934 - Rev 1 page 26/28
IPS8160HQ, IPS8160HQ-1
List of figures
List of figures
Figure 10. Thermal protection and STATUS behavior (T
). . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Thermal protection and STATUS behavior (T
). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14. Typical demagnetization energy (single pulse, all channels) at V
= 125 °C . . . . . . . . . . . . 15
DS13934 - Rev 1 page 27/28
IPS8160HQ, IPS8160HQ-1
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
DS13934 - Rev 1 page 28/28
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