STMicroelectronics SPV1050 Datasheet
Annonce
Annonce
SPV1050
Datasheet
Ultralow power energy harvester and battery charger
Product status link
SPV1050
Product label
Features
• Transformerless thermoelectric generators and PV modules energy harvester
• High efficiency for any harvesting source
• Up to 70 mA output current
• Fully integrated MOSFETs for Boost or Buck-boost configurations
• Selectable enable/disable MPPT functionality
• Programmable MPPT by external resistors
• 2.6 V to 5.3 V trimmable output overvoltage level (± 1% accuracy)
• 2.2 V to 3.6 V trimmable output undervoltage level (± 1% accuracy)
• Two fully independent LDOs (1.8 V and 3.3 V output)
• Enable/disable LDO pins
• Load disconnect function (by-pass transistor open) prior the first start-up (Cold
Start) to avoid battery lifetime shortening
• Battery Connected and DC-DC switching open drain indication pins
Application
• Internet of things
• Remote control
• Fleet and livestock tracking
• Agriculture sensors
• Toll-pay
• Electronic labels
• Smart watch and wearable.
Description
The SPV1050 is an ultra-low power and high-efficiency power manager embedding four MOSFETs for boost or buck-boost DC-DC converter and an additional transistor for the load connection/disconnection.
An internal high accuracy MPPT algorithm can be used to maximize the power extracted from PV panel or TEG.
The internal logic works to guarantee tight monitoring of both the end-of-charge voltage (V
EOC
) and the minimum battery voltage (V
UVP
) by opening the passtransistor at triggering of the V
EOC
threshold or at triggering of the V
UVP
threshold to preserve the battery life. Both the V
EOC
and V
UVP
thresholds can be trimmed by external resistors connected between the STORE rail and the EOC and UVP pins, respectively.
In boost configuration (CONF pin connected to the supply source), the IC requires
550 mV and 30 μA to Cold start; while after the first start-up the input voltage can range between 150 mV and V
EOC
. In buck-boost configuration (CONF pin connected to ground), the IC requires 2.6 V and 5 μA at Cold start; while after the first start-up input voltage can range between 150 mV up to 18 V.
The STORE pin is available as unregulated voltage output (e.g. to supply by external
LDO a micro-controller), while two fully independent LDOs (1.8 V and 3.3 V) are embedded for powering other companion ICs like MCU, sensors or RF transceivers.
Both LDOs can be independently enabled through the related pins.
DS10044 - Rev 7 - January 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
1
Block Diagram
Figure 1. Block diagram
SPV1050
Block Diagram
DS10044 - Rev 7 page 2/30
2
Pin configurations
SPV1050
Pin configurations
DS10044 - Rev 7 page 3/30
3
SPV1050
Pin description
Pin description
Pin no.
(VFQFPN
20)
1 MPP
Name
2 MPP_SET
3 MPP_REF
4
5
6
7
GND
LDO1_EN
LDO2_EN
BATT_CHG
8 BATT_CONN
9 EOC
10 UVP
11
12
13
14
LDO1
LOD2
CONF
BATT
Type Description
I
I
I
GND
I
I
O
O
O
O
I
I
I
I/O
Input voltage sense pin: to be connected to the voltage source. The connection can be direct or through a ladder resistor, depending on the maximum voltage of the source despite the AMR and operating range of the MPP pin. The switching of the DC-DC is disabled when V
MPP
<
V
EN_TH
.
MPPT enable/disable and setting voltage pin.
Connect this pin directly to STORE pin when MPPT function is not required: this configuration (V
MPP_SET
> V
STORE
-V
EN_TH
) inhibits the periodic deactivation of the embedded DC-DC.
If MPPT function is required, then connect MPP_SET and MPP pins through a ladder resistor: the MPPT algorithm periodically deactivates the
DC-DC for sampling of the open circuit voltage of the source. Typically, the
DC-DC is stopped for ~400 ms every ~16 s.
Voltage reference pin.
The switching of the DC-DC is controlled by internal logic purposing high conversion efficiency, even with low power sources. The switching remains active until V
MPP
> V
MPP_REF
. Connecting this pin to ground enables continuous switching of the DC-DC converter, provided that enough power can be supplied by the source.
When MPPT function is required, connect this pin to a 10 nF capacitor: at every sampling period (~16 s) this capacitor stores the reference voltage
(% of the open circuit voltage of the source) V
MPP_REF
.
When MPPT function is not required, connect this pin to an external voltage reference.
Signal ground pin.
If high, enables LDO1 (1.8V).
If high, enables LDO2 (3.3V).
DC-DC operation output flag pin (open drain): if low, it indicates that the
DC-DC is switching; if high, it indicates that the DC-DC is not switching.
Embedded pass transistor connection status pin (open drain): if low, it indicates that the pass transistor between the STORE and BATT pins is closed (load connected); if high, it indicates that the pass transistor between the STORE and BATT pins is open (load disconnected).
Load overvoltage/battery end of charge protection pin.
To be connected to the STORE pin through a resistor divider. Internal DC-
DC stops/restarts switching when the voltage at EOC pin is higher/lower than the internal bandgap voltage (V
BG
= 1.23 V, typical value).
Also, at start-up (internal pass transistor between STORE and BATT is still open) and while V
STORE
is increasing, the triggering of the internal bandgap voltage makes the internal pass transistor gets closed.
Load/battery undervoltage protection pin.
To be connected to the STORE pin through a resistor divider. Internal pass transistor between STORE and BATT pins opens when the voltage at UVP pin goes below the internal bandgap voltage (V
BG
= 1.23 V, typical value).
1.8 V regulated output voltage pin.
3.3 V regulated output voltage pin.
DC-DC converter configuration pin.
Boost configuration: CONF pin connected to the input supply source.
Buck-boost configuration: CONF pin connected to ground.
Load/battery connection pin.
DS10044 - Rev 7 page 4/30
Pin no.
(VFQFPN
20)
15 STORE
Name
16
17
18
19
IN_LV
NC
PGND
L_HV
20 IN_HV
EP Exposed Pad
SPV1050
Pin description
Type Description
I/O
I
Tank capacitor connection pin.
Low voltage input source.
It has to be connected to the inductor for both boost and buck-boost configuration.
Not connected.
-
PGND Power ground pin.
I
Input pin for buck-boost configuration.
Boost configuration: to be connected to ground.
Buck-boost configuration: to be connected to the inductor.
I
GND
High voltage input source.
Boost configuration: to be connected to ground.
Buck-boost configuration: to be connected to the input supply source.
Connect to ground layer of the application board. It's warmly recommended a direct connection (without any vias) between EP, GND,
PGND and the ground net of the tank capacitor on STORE pin.
DS10044 - Rev 7 page 5/30
4
Maximum ratings
Symbol
IN_LV
IN_HV
L_HV
CONF
MPP
MPP_SET
MPP_REF
BATT
STORE
UVP
EOC
BATT_CONN
BATT_CHG
LDO1_EN
LDO2_EN
LDO1
LDO2
PGND
GND
T
J
T
STORAGE
Table 1. Absolute maximum ratings
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input/output
Analog input/output
Analog input
Analog input
Digital output
Digital output
Digital input
Digital input
Analog output
Analog output
Power ground
Signal ground
Junction temperature
Storage temperature
Parameter Value
V
STORE
+ 0.3
20
IN_HV +0.3
5.5
5.5
5.5
5.5
5.5
5.5
V
STORE
+ 0.3
V
STORE
+ 0.3
5.5
5.5
V
STORE
+ 0.3
V
STORE
+ 0.3
V
STORE
+ 0.3
V
STORE
+ 0.3
0
-0.3 to 0.3
-40 to 125
150
Table 2. Thermal data
Symbol
R th(JC)
R th(JA)
Thermal resistance junction-case
Parameter
Thermal resistance junction-ambient
Value
7.5
49
1. Measured on 2-layer application board FR4, Cu thickness = 17 um with total exposed pad area = 16 mm 2
SPV1050
Maximum ratings
Unit
°C/W
°C/W
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V o C
V
V o C
DS10044 - Rev 7 page 6/30
5
SPV1050
Electrical characteristics
Electrical characteristics
V
STORE
= 4 V; -40 °C < T
J
< 85 °C, unless otherwise specified. Voltage with respect to GND, unless otherwise specified
Table 3. Electrical characteristics
I
I
I
I
Symbol Parameter
Load/battery operating range
BATT
V
R
BATT
BATT
Bandgap
Test conditions
Output current to load/ battery boost configuration buck-boost configuration
BATT pin voltage range
Pass transistor resistance BATT_CONN = low
V
BG
Internal reference voltage
Accuracy
UVP
V
STORE(UVP)
UVP
EOC
HYS
V
STORE
undervoltage protection range
UVP hysteresis
(V
V
UVP
+ UVP
STORE
rising
HYS
) < (V
EOC
- EOC
HYS
)
V
STORE(EOC)
EOC
HYS
STORE
V
STORE
end-of-charge voltage range
EOC hysteresis
(V
V
UVP
+ UVP
STORE
HYS
falling
) < (V
EOC
- EOC
HYS
)
V
STORE
STORE pin voltage operating range
Static current consumption
SD
SB
OP
Shutdown current
Standby current
Operating current in open load
Shutdown mode: before first start-up or
BATT_CONN high
T
AMB
< 60 °C
Standby mode:
BATT_CONN low, BATT_CHG high,
V
STORE
= 5.3 V, V
MPP
< V
EN_TH
and
LDO1,2_EN low
T
AMB
= 25 °C
Operating mode (LDOs in open load),
BATT_CONN low,
BATT_CHG high,
T
AMB
= 25 °C
LDO1_EN = 1 or
LDO2_EN = 1
LDO1_EN = 1 and
LDO2_EN = 1
DC-DC converter
V
IN-SU
Cold start minimum input voltage
Boost configuration, BATT_CONN high or at first start-up
Buck-boost configuration BATT_CONN high or at first start-up
Min.
-
30
2.2
6
-
-1
2.2
-
-
-
-
-
-
-
-
2.6
V
STORE(
UVP)
Typ.
1.23
-
-
-
0.8
1.7
2.6
0.55
2.6
-
7
-
-
-
5
-
-1
Max.
70
-
5.3
8
-
+1
3.6
-
5.3
-
V
STORE(
EOC)
1
-
-
-
0.58
2.8
Unit mA
V
%
V
%
V
Ω
V
%
V nA
μA
μA
V
DS10044 - Rev 7 page 7/30
DS10044 - Rev 7
SPV1050
Electrical characteristics
I
I f
I
SU
V
EN_TH
V
IN_LV
V
IN_HV
R-ON
B
SR-ON
R-ON
B
BB
SR-ON
SW
Symbol
UVLO
UVLO
L(ZC)
H
L
L(PEAK)
BB
Cold start minimum input current
Parameter Test conditions
Boost configuration
Buck-boost configuration
DC-DC switching enable threshold
Voltage checked during T
SAMPLE
Input voltage range
Boost configuration
Buck-boost configuration
Low-side MOS resistance
Synchronous rectifier MOS resistance
Low-side MOS resistance
Synchronous rectifier MOS resistance
Maximum allowed switching frequency
Undervoltage lockout activation threshold
Undervoltage lockout deactivation threshold
DC-DC input current high peak threshold
Boost configuration
Buck-boost configuration
Boost and buck-boost configurations
V
STORE
increasing
V
STORE
falling
DC-DC output current low threshold
DC-DC ON Time
DC-DC OFF Time
DC-DC active and input current rising
(T
AMB
= 25 o C)
DC-DC active and input current falling
(T
AMB
= 25 o C)
DC-DC maximum ON time
DC-DC- minimum OFF time
T
ON(MAX)
T
OFF(MIN)
MPPT
T
T
V
TRACKING
SAMPLE
MPP
MPPT tracking period
MPPT sampling time
MPP pin voltage range
BATT_CHG low
BATT_CHG high
MPPT enabled, MPPT
RATIO
= 50%,
V
MPP(MAX)
= 150mV, DC-DC switching
(see
Boost and buck-boost configurations MPP
ACC
LDO
MPP tracking accuracy
I t
V
LDO1,2
ΔV
LDO1,2
LDO
LDO1,2
V
LDO1,2_EN_H
V
LDO1,2_EN_L
Digital output
LDO1,2 adjusted output voltage
LDO1 dropout
LDO2 dropout
LDO1_EN = 1
LDO2_EN = 1
V
UVP
+ 200 mV < V
STORE
≤ 5.3 V; I
LDO1
= 100 mA
3.3 V < V
UVP
+ 200 mV < V
STORE
≤ 5.3
V; I
LDO2
= 100 mA
BATT_CONN = low; C
LDO1,2
= 100 nF LDO1,2 START-up time
I
OUT
max from LDO1
I
OUT
max from LDO2
LDO1,2 enable input HIGH
LDO1,2 enable input LOW
BATT_CONN= low
Min.
-
-
V
EN_TH
V
EN_TH
0.5
0.5
1
1
-
-
2
85
0
0.2
12
0.3
0.075
95
-
1
-
-
-
1.0
1.5
1.5
Typ.
30
5
0.1
-
-
1.0
-
2.6
2.1
1.8
3.3
-
-
-
-
-
Max.
-
-
0.15
V
EOC
18
1.5
1.5
2
2
Unit
μA
V
V
Ω
Ω
1
2.8
-
MHz
V
V
V
190
82
10
20
0.5
UVP
-0.1
0.5
0.5
1
200
200
-
0.5
mA mA
μs
μs s s
V
%
V
% ms mA mA
V
V page 8/30
SPV1050
Electrical characteristics
Symbol
V
BATT_CONN_L
V
BATT_CHG_L
Parameter
BATT_CONN voltage drop
BATT_CHG voltage drop
Test conditions
1 mA sink current; BATT_CONN = low
1 mA sink current; BATT_CHG = low
1. Guaranteed by design, not tested in production.
Min.
40
40
Typ.
70
70
Max.
150
150
Unit mV mV
DS10044 - Rev 7 page 9/30
6
6.1
SPV1050
Functional description
Functional description
The SPV1050 can be used as energy harvester or normal DC-DC converter, depending on the activation or deactivation of the embedded MPPT algorithm (by MPP_SET pin setting). Also, the IC offers both load overvoltage and under-voltage control, which fit with the most typical requirements of battery charger applications. The additional unregulated (STORE) and regulated (LDO1, LDO2) voltage rails makes the IC suitable to be used as power manager.
Independently by the activation/deactivation of the MPPT function, the DC-DC converter stage can be configured
Figure 12. Buck-boost configuration example .
If the embedded MPPT algorithm is enabled (MPP and MPP_SET pins connected to input source by a resistor partitioning), the device periodically stops the switching of the DC-DC converter to do a sampling of the input voltage and to store it on the capacitor connected at MPP_REF pin. When the sampling time elapses, the IC restarts operating: if V
MPP
> V
MPP_REF
, then the DC-DC can switch according the internal driving sequence purposing the optimization of the conversion efficiency. The selection of the resistor partitioning at the input stage, according to the electrical characteristic of the harvested source, allows the IC to maximize the power
extracted: see further details in Section 6.2 Boost configuration ,
Section 6.3 Buck-boost configuration and
Figure 19. MPPT setup circuitry .
The MPPT algorithm can be disabled by shorting the MPP_SET pin to the STORE pin. In this application case the MPP_REF pin is usually connected to a voltage reference. In case of low impedance source (e.g. USB), the
MPP_REF is normally connected to GND: the IC tries switching at highest duty cycle. In case of high impedance source (limited current capability, i.e. the source in unable to sustain the continuous switching at maximum duty cycle), the MPP_REF pin can be connected to a reference voltage (V
EXT_REF
) such that the IC stops switching when V
MPP
< V
EXT_REF
. This voltage reference can be set through a resistor ladder connected to STORE rail or to any other voltage reference available.
Battery voltage control
The IC integrates a pass transistor between the STORE and BATT pins to implement both the undervoltage and the overvoltage protection thresholds. These thresholds are respectively controlled by the pins UVP and EOC, normally connected to the STORE pin by a resistor partitioning. The respective voltages (V
UVP
and V
EOC
) are compared with the IC internal voltage reference (V
BG
= 1.23 V, typical value).
Those protection thresholds guarantee the lifetime and the safety of the battery.
DS10044 - Rev 7 page 10/30
Figure 2. Battery management section
SPV1050
Battery voltage control
DS10044 - Rev 7
Before the first startup (cold start) the pass transistor is open, so that the leakage from the output is lower than
1 nA. The pass transistor is closed once the (rising) voltage on the STORE pin triggers the overvoltage threshold
V
STORE(EOC)
(corresponding to V
EOC
> V
BG
). An internal hysteresis (EOC
HYS
) sets the restart voltage level for
DC-DC converter. The IC also offers the undervoltage protection threshold: the pass transistor is opened once the
(falling) voltage on the STORE pin decreases down to the undervoltage threshold V
STORE(UVP)
(corresponding to
V
UVP
< V
BG
).
following:
Equation 1: set the total output resistance (R
OUT(TOT)
= R4 + R5 + R6) to minimize its leakage:
• 10 MΩ ≤ R
OUT(TOT)
≤ 20 MΩ
Equation 2:
• R6 = (V
BG
/ V
EOC
) × R
OUT(TOT)
Equation 3:
• R5 = (V
BG
/ V
UVP
) × R
OUT(TOT)
- R6
In addition, the IC provides two open drain digital outputs to an external microcontroller:
• BATT_CONN
This pin is pulled down when the pass transistor is closed. It will be released once the pass transistor will be opened. If used, this pin must be pulled up to the STORE rail by resistor (10 MΩ, typically) .
• BATT_CHG
This pin is pulled down when the DC-DC converter is switching, while it's released when it is not switching, i.e. it is high after STORE triggers V
STORE(EOC)
and until it drops by EOC
HYS
, or when the UVLO
L
threshold is triggered, or during the sampling period (T
SAMPLE
) of the MPPT algorithm. If used, this pin must be pulled-up to the STORE rail by a resistor (10 MΩ, typically).
page 11/30
SPV1050
Boost configuration
For some applications (typically with battery or super-cap connected to BATT pin) it could be necessary to implement a reactivation hysteresis after undervoltage event (pass transistors status changes from closed to open): it avoids the undesired continuous system reset loop due to full discharge of the C
STORE
at every triggering of the overvoltage threshold. The application solution is simply based on a diode (or p-channel MOSFET driven by BATT_CONN) between STORE and BATT pins.
Figure 3. Implementations examples of larger UVP hysteresis
6.2
Boost configuration
Figure 4. Boost configuration example
below shows an example of boost application circuit.
Figure 4. Boost configuration example
DS10044 - Rev 7
In case of boost configuration, once the source is connected, the SPV1050 will start boosting the voltage on the
STORE rail. In the range of 0 ≤ V
STORE
< 2.6 V the voltage boost is carried on by an integrated high-efficiency charge pump, while the DC-DC converter stage remains OFF.
Figure 5. Boost start-up shows the behavior of input voltage V
IN
(voltage supplied by the source) and V
STORE
at the start-up.
page 12/30
Figure 5. Boost start-up
SPV1050
Boost configuration
DS10044 - Rev 7
In the range 2.6 V ≤ V
STORE
< V
STORE(EOC)
the voltage on STORE rail is boosted by the DC-DC converter that operates driven by internal logic until V
MPP
> V
MPP_REF
. Switching activity of the DC-DC is controlled by internal logic: ON phase stops at triggering of I
L(PEAK)
(peak current through the inductor) and can't be longer than
T
ON(MAX)
; OFF phase can't be shorter than T
OFF(MIN)
. Also, purposing highest efficiency with low power source, the first ON phase after reactivation of the DC-DC is limited a triggering of I
L(PEAK)
/ 2.
If the MPPT mode is active, then the IC stops switching for ~400 ms (T
SAMPLE
) every ~16 seconds (T
TRACKING
).
During the T
SAMPLE
, the IC goes in high impedance and the open circuit voltage V
OC
at input stage is sampled and stored by charging the C
REF
(capacitor on the MPP_REF pin) through the MPP_SET pin.
Once the T
SAMPLE
is elapsed, the DC-DC converter will start switching back: the IC impedance is set featuring the
V
IN
stays as close as possible to the V
MPP_REF
. The periodic sampling of V
OC
guarantees the best MPPT in case of source condition variations (e.g. irradiation/thermal gradient and/or temperature changes).
A resistor partitioning connected between the source and the pins MPP and MPP_SET has to be properly
selected, in order to match the source manufacturer's specs: refer to Section 6.4 MPPT setting
for further details.
shows the input voltage waveform of a PV panel supplying
V
OC
= 1.25 V and V
MP
= 1.05 V.
page 13/30
DS10044 - Rev 7
Figure 6. MPPT tracking
SPV1050
Boost configuration
Once the voltage at STORE pin triggers the V
STORE(EOC)
the switching of the DC-DC converter stops until
V
STORE
decreases below the threshold defined by the internal hysteresis.
Figure 7. Triggering of V
EOC
(BATT pin floating) page 14/30
DS10044 - Rev 7
SPV1050
Boost configuration
The following plots (
Figure 8. Efficiency vs. input current; V
= 1.0 V , Figure 9. Efficiency vs. input current; V
= 1.5 V , Figure 10. Efficiency vs. input current; V
Figure 11. Efficiency vs. input current; V
show the power efficiency of the DC-DC converter configured in boost mode at T
AMB
= 25 °C in some typical use cases at different open circuit voltages (MPPT
RATIO
= 83%):
Figure 8. Efficiency vs. input current; V
OC
= 1.0 V
0.7
0.65
0.6
0.55
0.5
0.45
0.9
0.85
0.8
0.75
0.4
0.01
0.1
10
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
1
Input current [mA]
100
AM03745
Figure 9. Efficiency vs. input current; V
OC
= 1.5 V
0.9
0.85
0.8
0.75
0.7
0.65
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.6
0.01
0.1
1
Input current [mA]
10 100
AM03746
Figure 10. Efficiency vs. input current; V
OC
= 2.0 V
1
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0.6
0.01
0.1
10 100
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
1
Input current [mA]
AM03747 page 15/30
6.3
SPV1050
Buck-boost configuration
Figure 11. Efficiency vs. input current; V
OC
= 2.5 V
1
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0.6
0.01
0.1
10 100
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
1
Input current [mA]
AM03748
Buck-boost configuration
Figure 12. Buck-boost configuration example shows an example of buck-boost application circuit.
Figure 12. Buck-boost configuration example
BATT
STORE
UVP
Input source
IN_LV
IN_HV
L_HV
+
-
+
-
EOC
MPP
MPP_SET
MPP_REF
LDO1_EN
LDO2_EN
CONF
MPPT
CONTROL
LOGIC
STORE
STORE
1.8 V
3.3 V
LDO1
TO LOAD1
C
STORE
Battery
LDO2
TO LOAD2
_____ _____
BATT_CON
_____ _____
BATT_CHG
Cin
PGND GND
AM03399
In case of buck-boost configuration, once the harvested source is connected, the IN_HV and STORE pins will be internally shorted until V
STORE
< 2.6 V. Figure 13. Buck-boost start-up (I
shows the behavior of the input voltage V
IN_HV
and V
STORE
at the start-up.
DS10044 - Rev 7 page 16/30
Figure 13. Buck-boost start-up (I
IN
= 5 μA)
SPV1050
Buck-boost configuration
DS10044 - Rev 7
In the range 2.6 V ≤ V
STORE
< V
STORE(EOC)
the integrated DC-DC switches until V
MPP
> V
MPP_REF
.
If the MPPT function is active, then the IC stops switching for ~400ms (T
SAMPLE
) every ~16 seconds (T
TRACKING
).
During the T
SAMPLE
, the open circuit voltage V
OC
of the input source is sampled and stored by charging the C
REF
(capacitor on the MPP_REF pin) through the MPP_SET pin. Once the T
SAMPLE
is elapsed, the DC-DC converter operates again driven by the internal logic and such that V
IN
(voltage supplied by the source) stays as close as possible to the maximum power point of the source. The periodic sampling of V
OC case of source condition variations (e.g. irradiation and/or temperature changes).
guarantees the best MPPT in
A resistor partitioning connected between the source and the pins MPP and MPP_SET has to be properly selected in order to match the electrical characteristics of the source given by the manufacturer. Please refer to
Section 6.4 MPPT setting for further details.
Figure 14. MPPT tracking shows the MPPT tracking form in case of V
OC
= 9.9 V and voltage at maximum power point V
MP
= 8.2 V.
page 17/30
Figure 14. MPPT tracking
SPV1050
Buck-boost configuration
DS10044 - Rev 7
The following plots (
Figure 15. Efficiency vs. input current - V
Figure 16. Efficiency vs. input current -
= 9V , Figure 17. Efficiency vs. input current - V
,
Figure 18. Efficiency vs. input current - V
15V ) show the power efficiency of the DC-DC converter configured in buck-boost mode at T
AMB typical use cases (MPPT
RATIO
= 83%):
= 25 °C in some
Figure 15. Efficiency vs. input current - V
OC
= 6V
0.85
0.8
] 0.75
0.7
0.65
0.6
0.01
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.1
1
Input current [mA]
10 100
AM03750 page 18/30
DS10044 - Rev 7
Figure 16. Efficiency vs. input current - V
OC
= 9V
0.85
0.8
0.75
0.7
0.65
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.6
0.01
0.1
1
Input current [mA]
10 100
AM03751
Figure 17. Efficiency vs. input current - V
OC
= 12V
0.85
0.8
0.75
0.7
0.65
0.6
0.01
0.8
0.75
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.7
0.65
0.6
0.01
0.1
1
Input current [mA]
10 100
AM03752
Figure 18. Efficiency vs. input current - V
OC
= 15V
0.85
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.1
1
Input current [mA]
10 100
AM03753
SPV1050
Buck-boost configuration page 19/30
6.4
SPV1050
MPPT setting
MPPT setting
When MPPT is enabled, the SPV1050 can regulate its impedance to extract the maximum power from the harvesting source. Typically, the datasheet of an harvesting source reports the main electrical characteristics: open circuit voltage (V
OC
) and voltage at maximum power (V
MP
); the MPPT
RATIO
is consequently calculated as
V
MP
/V
OC
. Referring to PV panels and TEGs, the V
MP
and V
OC
can change according to the external conditions
(light irradiation, temperature), but usually the effect on MPPT
RATIO
remains limited.
The highest MPPT accuracy of the SPV1050 can be achieved only by a proper selection of the resistors at the input stage (R1, R2, R3).
Figure 19. MPPT setup circuitry
Source
R
1
R
2
R
3
MPP
MPP_SET
MPP_REF
MPPT
Cin
C
REF
PGND GND
AM03400
To select R1, R2 and R3 it is necessary to set some application parameters and then apply the below equations from 4 to 7.
• Electrical characteristics of the harvesting source
– V
OC(MAX)
, intended as V
OC
at max operating condition of the source
– MPPT
RATIO
, intended as V
MP
/V
OC
at typical operating conditions of the source
•
•
Application constraints
– I
LEAKAGE
, intended as the acceptable leakage through the resistors at the input stage
– Usually, 0.1 μA ≤ I
LEAKAGE
≤ 1 μA fits for most of the applications.
SPV1050 constraints
– V
EN_TH (MAX)
≤ V
MPP(MAX)
≤ (V
UVP(MIN)
- 100 mV) ⇒
150 mV ≤ V
MPP(MAX)
≤ 2.1 V
– V
MPP(MAX)
< V
OC(MAX)
DS10044 - Rev 7 page 20/30
DS10044 - Rev 7
SPV1050
MPPT setting
Equation 4:
R
IN(TOT)
= R1 + R2 + R3 > (V
OC(MAX)
/ I
LEAKAGE
) × MPPT
RATIO
Equation 5:
R1 = R
IN(TOT)
Equation 6:
× [ 1 - (V
MPP(MAX)
/ V
OC(MAX)
) ]
R2 = R
IN(TOT)
Equation 7:
× (V
MPP(MAX)
/ V
OC(MAX)
) × (1 - MPPT
RATIO
)
R3 = R
IN(TOT)
× (V
MPP(MAX)
/ V
OC(MAX)
) × MPPT
RATIO
Example:
Harvesting source is a PV panel with V
MP(TYP) maximum light irradiation V
OC(MAX)
= 2.2 V.
= 1.5 V and V
OC(TYP)
= 2.0 V (
⇒
MPPT
RATIO
= 75%). At
V
MPP(MAX)
could be set between 0.15 V and 2.1 V: in this example we can assume that V
MPP(MAX)
= 0.50 V ( =
33% of V
MP(TYP)
).
In general, V
MPP(MAX)
depends on the power supplied by the PV panel at low light irradiation and on the minimum acceptable conversion efficiency of the DC-DC.
Hence set
•
•
•
V
OC(MAX)
= 2.2 V
V
MPP(MAX)
= 0.5 V
I
LEAKAGE
= 0.1 μ A
R
IN(TOT)
= (2.2 V / 0.1 uA) × 0.75 = 16.5 MΩ
R1 =16.5 MΩ × [ 1 - (0.5 V / 2.2 V) ] = 12.75 MΩ
R2 =16.5 MΩ × (0.5 V/ 2.2 V) × (1- 0.75) = 0.94 MΩ
R3 =16.5 MΩ × (0.5 V/ 2.2 V) × 0.75 = 2.81 MΩ
Also, the MPPT accuracy can be strongly affected by an improper selection of the input capacitor. The input capacitance C
IN
= 4.7 μF generally covers the most typical use cases.
The energy extracted from the source, and stored on C
IN
, is transferred to the load by the DC-DC converter through the inductor. The energy extracted by the inductor depends by the sink current: the higher input currents cause higher voltage drop on the input capacitance and this may result a problem for low voltage (< 1 V) and high energy (> 20 mA) sources. In such application cases the input capacitance has to be increased or, alternatively the L1 inductance has to be reduced.
During the T
SAMPLE
time frame the input capacitor C
IN
is charged up to V
OC
by the source with a time constant
(T1) resulting from the capacitance and the equivalent resistance R
EQ
of the source.
In case of PV source, being I
MP
the minimum operating current for MPPT, the R
EQ
can be calculated as following:
Equation 8:
• R
EQ
= (V
OC
- V
MP
) / I
MP
= V
OC
× (1 - MPP
RATIO
) / I
MP
Thus C
IN
is calculated by the following formula:
Equation 9:
• C
IN
≤ T1 /R
EQ
The following plots (
) show the effect of different C
IN
values on the time constant. If the capacitance is too high, the capacitor may not be charged within the T
SAMPLE
= 400 ms time window, thus affecting the MPPT accuracy.
page 21/30
Figure 20. Energy harvester equivalent circuit
R
EQ
I
MPP
V
EQ
C1
V
C1
AM03401V1
Figure 21. Voltage vs. time at different C values and fixed current
SPV1050
Power manager
6.5
Power manager
The SPV1050 device works as a power manager by providing two regulated voltages on the LDO1 (1.8 V) and
LDO2 (3.3 V) pins.
Each LDO can be selectively enabled or disabled by driving the related enable/disable pins LDO1_EN and
LDO2_EN. The performances of the LDOs can be optimized by selecting a proper capacitor between the LDO output pin and ground. A 100 nF for each LDO pin is suitable for the most typical use cases.
the LDOs when a 100 mA load is connected.
DS10044 - Rev 7 page 22/30
Figure 22. LDO1 turn on with 100 mA load
SPV1050
Power manager
Figure 23. LDO2 turn on with 100 mA load
DS10044 - Rev 7
Note that the internal logic inhibits both LDOs when the embedded pass transistor is open, that is when the battery is not connected. Also, the LDOs are both supplied by the STORE rail: if the input source is unable to sustain the current required by the load, then the missing energy will be supplied by the battery connected to the
BATT pin. In this case, the current from the battery causes a voltage drop between STORE and BATT pins due to the resistance of the pass transistor:
V
STORE
= V
BATT
- (R
BATT
* I
LOAD
).
If V
STORE
drops and UVP pin triggers the undevoltage threshold, then the pass transistor gets open and the load is no longer supplied until next end of charge condition is reached.
page 23/30
7
7.1
SPV1050
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
Package and packing information
Figure 24. VFQFPN20 3 x 3 x 1 mm - 20-lead pitch 0.4 package outline
DS10044 - Rev 7 page 24/30
DS10044 - Rev 7
SPV1050
Package and packing information
Table 4. VFQFPN20 3 x 3 x 1 mm - 20-lead pitch 0.4 package mechanical data
Symbol b
D
D1
D2
E
A
A1
A2
A3
E1
E2 e
L ddd
Min.
0.80
-
-
-
0.15
2.85
-
1.50
2.85
-
1.50
0.35
0.30
-
Typ.
0.20
3.00
1.60
1.60
3.00
0.90
0.02
0.65
0.20
1.60
1.60
0.40
0.40
-
1. “VFQFPN” stands for “Thermally Enhanced Very thin Fine pitch Quad Packages No lead”. Very thin: 0.80 < A ≤ 1.00 mm / fine pitch: e < 1.00 mm.
Max.
0.25
3.15
-
1.70
3.15
1.0
0.05
1.00
-
-
1.70
0.45
0.50
0.07
Figure 25. Recommended footprint of VFQFPN20 3 x 3 x 1 mm - 20-lead pitch 0.4
page 25/30
Figure 26. Tape and reel design
SPV1050
Package and packing information
DS10044 - Rev 7 page 26/30
SPV1050
Ordering information
8
Ordering information
Order code
SPV1050TTR
Op. temp. range [ o C]
-40 to 85
Package
VFQFPN 3 x 3 x 1 20L
Packing
Tape and reel
DS10044 - Rev 7 page 27/30
DS10044 - Rev 7
SPV1050
Application tips
Appendix A
Application tips
In the DC-DC converters the energy is transferred from the input to the output through the inductor. During the ON phase of the duty cycle the inductor stores energy; during the OFF phase of the duty cycle the energy is released toward the output stage.
Figure 27. Inductor current and input voltage waveforms
I
L(PEAK)
I
LH
I
L(MIN)
V
IN
L
*
T
ON
V
IN
- V
STORE
L
*
T
OFF
LOW INPUT POWER
Internal
Driving Signal
T
ON
ON
T
T
OFF
OFF
T
ON(MAX)
T
OFF(MIN)
V
IN
The SPV1050 activates the driving signal of the DC-DC when V
MPP
> V
MPP_REF
. During the ON phase of the driving signal, the inductor is loaded for T
ON
until one of the following events occurs:
•
•
•
V
STORE
triggers the overvoltage threshold
The inductor current (I
L
) triggers the internal threshold I
L(PEAK)
(= 140 mA, typ.)
T
ON(MAX)
= 10 μs elapses
In the OFF phase the energy stored in the inductor will be released to the output stage: during T
OFF
the I
L decreases to I
LZC
. According to the internal controls of the IC, T
OFF(MIN)
= 0.2 μs: in order to prevent I
L
goes negative, the application must be designed such that the energy stored in the inductor during T
ON
is always greater than, or equal to, the energy released during T
OFF
. This goal can be achieved through the proper selection of R2 + R3. Thus, in order to guarantee I
L(MIN)
> 0, it must be:
Equation 10:
• I
L(MIN)
= I
H
- (V
STORE
- V
IN
)×(T
OFF(MIN)
/L) > 0
Equation 11:
• I
L(MIN)
= (V
IN
/L) × T
ON(MAX)
- (V
STORE
- V
IN
)×(T
OFF(MIN)
/L) > 0 leading
Equation 12:
• V
IN
> V
STORE
× (T
OFF(MIN)
/(T
ON(MAX)
+ T
OFF(MIN)
) = V
STORE
/ 51
As worst case for the above equation it can be considered V
STORE
at the overvoltage level.
The resistor R1, part of the partitioning at the input stage, can be used purposing the DC-DC switch-off before
I
L(MIN)
≤ 0.
V
MPP
= V
IN
*(R2+R3)/(R1+R2+R3) < V
EN_TH page 28/30
SPV1050
Revision history
Date
25-Nov-2013
28-Aug-2014
18-Dec-2014
06-Aug-2015
17-May-2018
12-Oct-2021
26-Jan-2022
2
3
4
5
6
7
Table 5. Document revision history
Version
1
Changes
Initial release.
Document status promoted from preliminary data to production data, with comprehensive update of electrical characteristic sand graphic content throughout the document.
Document status corrected to reflect current phase of product development.
Minor text edits throughout the document. Added maximum values for R th j-c
and R th j-a
in Table 2: Thermal data, with associated footnote. Multiple changes to parameters, test conditions and values in Table 4: Electrical characteristics. Modified text in Section 6: Functional description and Section
6.4: MPPT setting. Removed order code SPV1050T from Table 7: Device summary, and modified package and packing values for order code SPV1050-
WST. Added Appendix A: Application tips
Added Figure 26 on page 32. Minor modifications throughout the document
Changed datasheet formatting. Front page: rephrased Features list and
Description; extended Application list. Block diagram: added details of the input stage with internal control thresholds. Pin Description: rephrased descriptions of input and output stage pins. Electrical characteristics: minor editing fixes; added V
EN_TH
, I
L(PEAK)
, I
L(ZC)
, T
ON(MAX)
and T
OFF(MAX) parameters. Chapter 6: minor editing; added application examples for the management of larger UVP hysteresis. Chapter 6.4: reviewed calculation of input resistor partitioning. Deleted Appendix A.
Updated cover image in the front page, pin configuration, ordering information and package information: deleted any reference to die form.
Corrected editing error in Equation 1.
DS10044 - Rev 7 page 29/30
SPV1050
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
DS10044 - Rev 7 page 30/30
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