STMicroelectronics STBLW35 Datasheet
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STBLW35
Product label
STBLW35
Datasheet
Ultra-low power and wide input range buck-boost converter
Features
• Seamless transition from Buck-Boost to Boost and vice versa working mode
• Up to 70 mA output current
• Four fully integrated MOSFETs
• Enable pin
• 2.6 V to 5.3 V trimmable overvoltage level (± 1% accuracy)
• 2.2 V to 3.6 V trimmable undervoltage level (± 1% accuracy)
• Two fully independent LDOs (1.8 V and 3.3 V output)
• Enable/disable LDO control pins
• Load disconnect function at first switch-on
• Embedded pass transistor status and DC-DC status open drain indication pins
Application
• WSN, building and home automation, industrial control, security, surveillance
• Wearable and biomedical sensors, fitness
• Battery charging
Description
The STBLW35 is an ultra-low power and high-efficiency buck-boost DC-DC converter which can work as boost or buck-boost according to the selected hardware configuration. When in buck-boost the DC-DC can seamlessly switch between the two working modes depending on operating conditions.
The IC shows very low power losses either in active or disable mode and provides an average output current between 33 mA to 70 mA, suitable to guarantee load minimum current constraints or to faster charge a battery. The device also allows the charge of any battery by tightly monitoring the end-of-charge and the minimum battery voltage in order to avoid overdischarge and to preserve battery life.
The power manager covers the input voltage range from 150 mV up to 18 V and guarantees high efficiency in both buck-boost and boost configuration.
Furthermore, the STBLW35 device shows very high flexibility thanks also to the trimming capability of the overvoltage and the undervoltage protection voltages.
In order to optimize the power consumption during system operation, the device can be driven in standby mode thanks to the high impedance Enable pin.
An unregulated voltage output is available (to supply a transceiver for instance), while two fully independent LDOs are embedded for powering sensors and other companion chips. Both LDOs (1.8 V and 3.3 V) can be independently enabled through dedicated pins.
DS13777 - Rev 1 - July 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
Block Diagram
Figure 1. Block diagram
STBLW35
Block Diagram
DS13777 - Rev 1 page 2/27
2
Pin configuration
Figure 2. Pin out (top through view)
STBLW35
Pin configuration
DS13777 - Rev 1 page 3/27
3
STBLW35
Pin description
Pin description
Pin no.
1 EN
Name
2 EXT_REF
3 EN_REF
4
5
6
7
GND
LDO1_EN
LDO2_EN
DC-DC_ON
8 OUT_CONN
9 OVP
10 UVP
11
12
13
14
15
LDO1
LOD2
CONF
OUTPUT
STORE
16
17
18
19
IN_LV
NC
PGND
L_HV
Table 1. Pin description
Type Description
GND
I
I
I
I
I
I
O
O
Enable/disable switching pin. Connected to the supply voltage (directly
or by a resistor partitioning, see Section 6 Functional description
,
Section 6.2 Boost configuration
and Section 6.3 Buck-boost configuration
).
Connect this pin (by a short or by a 1 kΩ resistor) to an external voltage reference or to STORE pin.
Connect this pin to an external voltage reference: the DC-DC switches when V
EN
> V
EN_REF
and stops switching when V
EN
≤ V
EN_REF
.
Connecting this pin to ground enables continuous switching of the DC-DC converter provided that enough power is available at the source and other protections (e.g. overvoltage) are not active.
Signal ground pin.
If high, enables LDO1.
If high, enables LDO2.
DC-DC ON output flag pin (open drain). If low, it indicates that the DC-DC is switching. If high, it indicates that the DC-DC is not switching.
Embedded pass transistor connection status pin (open drain). If high, it indicates that the pass transistor between the STORE and OUTPUT pins is open (load disconnected). If low, it indicates that the pass transistor between the STORE and OUTPUT pins is closed (load connected).
Output overvoltage protection pin.
To be connected to the STORE pin through a resistor divider. Internal DC-
DC stops/restarts switching when the voltage at OVP pin is higher/lower than the internal bandgap voltage.
Also, at startup (internal pass transistor between STORE and OUTPUT is still open) and while V
STORE
is increasing, the triggering of the internal bandgap voltage makes the internal pass transistor close.
O
O
I
I
Output undervoltage protection pin.
To be connected to the STORE pin through a resistor divider. Internal pass transistor between STORE and OUTPUT pins opens when the voltage at
UVP pin goes below the internal bandgap voltage.
1.8 V regulated output voltage pin.
3.3 V regulated output voltage pin.
DC-DC converter configuration pin.
Boost configuration: CONF pin connected to the input supply source
(see Figure 4. Boost configuration ). Buck-boost configuration: CONF pin
connected to ground (see Figure 11. Buck-boost configuration ).
Load connection pin.
I/O
I/O
I
Tank capacitor connection pin.
Low voltage input source.
It has to be connected to the inductor for both boost and buck-boost configuration. See
and
Figure 11. Buck-boost configuration
.
I Not connected.
PGND Power ground pin.
I
Input pin for buck-boost configuration.
Boost configuration: to be connected to ground.
Buck-boost configuration: to be connected to the inductor (see
Figure 11. Buck-boost configuration
).
DS13777 - Rev 1 page 4/27
Pin no.
20 IN_HV
Name
STBLW35
Pin description
Type
I
Description
High voltage input source.
Boost configuration: to be connected to ground.
Buck-boost configuration: to be connected to the voltage supply source
(see Figure 11. Buck-boost configuration ).
DS13777 - Rev 1 page 5/27
4
Maximum ratings
Symbol
IN_LV
IN_HV
L_HV
CONF
EN
EXT_REF
EN_REF
OUTPUT
STORE
UVP
OVP
OUT_CONN
DC-DC_ON
LDO1_EN
LDO2_EN
LDO1
LDO2
PGND
GND
T
J
T
STORAGE
Table 2. Absolute maximum ratings
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input/output
Analog input/output
Analog input
Analog input
Digital output
Digital output
Digital input
Digital input
Analog output
Analog output
Power ground
Signal ground
Junction temperature
Storage temperature
Parameter Value
V
STORE
+ 0.3
20
IN_HV + 0.3
5.5
5.5
5.5
5.5
5.5
5.5
V
STORE
+ 0.3
V
STORE
+ 0.3
5.5
5.5
V
STORE
+ 0.3
V
STORE
+ 0.3
V
STORE
+ 0.3
V
STORE
+ 0.3
0
-0.3 to 0.3
-40 to 125
150
Table 3. Thermal data
Symbol
R th(JC)
R th(JA)
Thermal resistance junction-case
Parameter
Thermal resistance junction-ambient
Value
7.5
49
1. Measured on 2-layer application board FR4, Cu thickness = 17 um with total exposed pad area = 16 mm 2 .
STBLW35
Maximum ratings
Unit
°C/W
°C/W
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V o C
V
V o C
DS13777 - Rev 1 page 6/27
5
STBLW35
Electrical characteristics
Electrical characteristics
V
STORE
= 4 V; -40 °C < T
J
< 85 °C, unless otherwise specified. Voltage with respect to GND, unless otherwise specified.
Table 4. Electrical characteristics
Symbol Parameter
Output operating range
Test conditions
I
OUT
Maximum output current
Boost configuration
Buck-boost configuration
V
OUT
OUTPUT pin voltage range
Pass transistor resistance R
OUT
Bandgap
V
BG
Internal reference voltage
Accuracy
UVP
V
STORE(UVP)
V
STORE
undervoltage protection range
UVP hysteresis
(V
UVP
+ UVP
HYS
) < (V
OVP
- OVP
HYS
)
UVP
HYS
OVP
V
STORE
rising
V
STORE(OVP)
V
STORE
end-of-charge voltage range
OVP hysteresis
(V
UVP
+ UVP
HYS
) < (V
OVP
- OVP
HYS
)
OVP
HYS
STORE
V
STORE
falling
V
STORE
STORE pin voltage operating range
I
I
I
Static current consumption
SD
SB
OP
Shutdown current
Standby current
Operating current in open load
Shutdown mode: before first startup or
OUT_CONN high
T
AMB
< 60 °C
Standby mode:
OUT_CONN low,
DC-DC_ON high,
V
STORE
= 5.3 V and LDO1,2_EN low
T
AMB
= 25 °C
Operating mode:
LDOs in open load
OUT_CONN low,
DC-DC_ON high
T
AMB
= 25 °C
LDO1_EN = 1 or
LDO2_EN = 1
LDO1_EN = 1 and
LDO2_EN = 1
DC-DC converter
Min.
33
2.2
6
-
-
-1
2.2
-
-
-
-
-
-
2.6
V
STOR
E(UVP)
Typ.
1.23
-
-
-1
-
-
0.8
1.7
2.6
-
35
-
7
-
5
Max.
-
+1
5.3
-
V
STOR
E(OVP)
1
-
-
-
70
-
5.3
8
3.6
-
Unit mA
V
%
V
%
V
Ω
V
%
V nA
μA
μA
DS13777 - Rev 1 page 7/27
DS13777 - Rev 1
STBLW35
Electrical characteristics
Symbol Parameter Test conditions
I
V
IN-SU
SU
Minimum input voltage to startup
Start-up input current
Boost configuration OUT_CONN high or at first startup
Buck-boost configuration OUT_CONN high or at first startup
Boost configuration
Buck-boost configuration
V
IN_LV
V
IN_HV
V
EN
R-ON
B
Operating input voltage range
EN pin voltage range
Boost configuration
Buck-boost configuration
SR-ON
B
Low-side MOS resistance
Synchronous rectifier
MOS resistance
Boost configuration f
R-ON
BB
SR-ON
SW
UVLO
UVLO
H
L
BB
Low-side MOS resistance
Synchronous rectifier
MOS resistance
Buck-boost configuration
Maximum allowed switching frequency
Undervoltage lockout activation threshold
Undervoltage lockout deactivation threshold
Boost and buck-boost configurations
V
V
STORE
STORE
rising
falling
LDO
V
LDO1,2
ΔV
LDO1,2
LDO1,2 adjusted output voltage
LDO1 dropout
LDO2 dropout
LDO1_EN = 1
LDO2_EN = 1
V
UVP
+ 200 mV < V
OUT
≤ 5.3 V; I
LDO1
= 100 mA
3.3 < V
100 mA
UVP
+ 200 mV < V
OUT
≤ 5.3 V; I
LDO2
=
I t
LDO
LDO1,2
V
V
LDO1,2_EN_H
LDO1,2_EN_L
LDO1,2 START-up time OUT_CONN = low; C
LDO1,2
= 100 nF
I
OUT
max. from LDO1
I
OUT
max. from LDO2
LDO1,2 enable input
HIGH
LDO1,2 enable input
LOW
Digital output
V
OUT_CONN_L
V
DC-DC_ON_L
V
OUT_CONN
= low
V
DC-DC_ON
= low
1 mA sink current
1 mA sink current
1. Guaranteed by design, not tested in production.
Min.
-
-
0.15
0.15
0.075
0.5
0.5
1
1
2
1
-
-
-
-
-
40
40
-
-
-
Typ.
0.55
-
2.6
2.1
1.8
3.3
-
70
70
2.6
-
-
30
5
-
-
-
-
1.0
1.0
1.5
1.5
Max.
0.58
Unit
V
2.8
-
-
V
EOC
18
V
UVP
1.5
1.5
2
2
μA
V
V
Ω
Ω
1
2.8
-
0.5
0.5
1
200
200
-
0.5
150
150
MHz
V
V
V
% ms mA mA
V
V mV mV page 8/27
6
6.1
STBLW35
Functional description
Functional description
The STBLW35 integrates a DC-DC converter stage that can be configured as boost or buck-boost by tying the CONF pin to positive rail of the supply or to ground, respectively (see
Figure 4. Boost configuration and
Figure 11. Buck-boost configuration ).
In normal operation the IC works with the EN pin connected to the input supply rail (directly or by a resistor partitioning according to voltage range of the supply source, operating range and absolute maximum rating of the
EN pin), EXT_REF pin connected to the STORE pin and by EN_REF pin connected to a voltage reference. After the first startup (see
and Section 6.3 Buck-boost configuration ) the DC-DC converter
switches until the voltage at EN pin (V
EN
) is higher than the voltage at EN_REF pin (V
EN_REF
) and until the
).
In case of low impedance source, the EN_REF is normally connected to GND: the IC switches at the highest duty cycle. In case of high impedance source (by means, with limited current capability, i.e. the source is unable to sustain the continuous switching at the maximum duty cycle), the EN_REF pin can be connected to a proper voltage reference (V
IN(MIN)
) such that the IC stops switching when V
EN
> V
IN(MIN)
. This voltage reference can be set through a resistor ladder connected to STORE rail or to any other voltage reference available in the application.
Output voltage control
In order to guarantee the lifetime and safety of the load (e.g. a battery), the IC controls an integrated pass transistor (with R
DS(ON)
= R
BATT
) between the STORE and OUTPUT pins and implements both the undervoltage and the overvoltage protection thresholds. These thresholds are respectively controlled by the pins UVP and
OVP, normally connected to the STORE pin by a resistor partitioning. The respective voltages (V
UVP
and V
OVP
) are compared with the IC internal voltage reference (V
BG(TYP)
= 1.23 V).
CONTROL
LOGIC
Figure 3. Output voltage control section
OUTPUT
PASS
TRANSISTOR
STORE
R
4
UVP
+
-
R
5
OVP
+
-
1.23 V R
6
_____ _____
OUT_CONN
_____ _____
DC-DC_ON
C
STORE
LOAD
GND
DS13777 - Rev 1 page 9/27
6.2
STBLW35
Boost configuration
Before the first startup the pass transistor is open, so that the leakage from the output is lower than 1 nA. The pass transistor is closed once the voltage on the STORE pin rises such that the overvoltage threshold is triggered
(V
OVP
> V
BG
). An internal hysteresis (OVP
HYS
) sets the restart voltage level for DC-DC converter. The IC also offers the undervoltage protection threshold: the pass transistor is opened once the voltage on the STORE pin decreases down to the undervoltage threshold (V
UVP
< V
BG
). For some applications (battery charging) it may be necessary to implement a reactivation hysteresis after undervoltage event: it can be easily implemented by a diode (or by a p-channel MOSFET driven by OUT_CONN) between STORE and OUTPUT pins. Referring to
Figure 3. Output voltage control section
, the design rules to set up the R4, R5 and R6 are the following:
Equation 1:
• V
BG
= V
UVP
× (R5 + R6) / (R4 + R5 + R6)
Equation 2:
• V
BG
= V
OVP
× R6 / (R4 + R5 + R6)
In order to minimize the leakage due to the output resistor partitioning it has to be typically:
Equation 3:
• 10MΩ ≤ R4 + R5 + R6 ≤ 20MΩ
In addition, the IC provides two open drain digital outputs to an external microcontroller:
• OUT_CONN
This pin is pulled down when the pass transistor is closed. It is released once the pass transistor is opened
(e.g. triggering of V
UVP
). If used, this pin must be pulled up to the STORE by a 10 MΩ (typical) resistor.
• DC-DC_ON
This pin is pulled down when the DC-DC converter is switching, while it's released when it is not switching, i.e. when the OVP threshold is triggered until the voltage on the STORE pin drops at V
OVP
- OVP
HYS
or when the UVLO threshold is triggered. If used, this pin must be pulled up to the STORE by a 10 MΩ (typical) resistor.
Note that the output current causes a voltage drop over the R
BATT
of the internal pass transistor, consequently, voltages at STORE (where the resistor partitioning to OVP and UVP pins are connected) and OUTPUT may slightly differ. If high precision is required for the output voltage regulation thresholds, then some application workaround may be necessary. For example, two p-channel MOSFETs in back-to-back, both driven by
OUT_CONN could be placed between STORE and OUTPUT pins.
Boost configuration
below shows an example of boost application circuit. In this example, the EN pin is shorted to input supply rail: a resistor partitioning may be required if the voltage range of the supply source goes above the limits of EN pin (see
Table 2. Absolute maximum ratings and
Table 4. Electrical characteristics ).
DS13777 - Rev 1 page 10/27
DS13777 - Rev 1
SUPPLY SOURCE
Cin to STORE
STBLW35
Boost configuration
IN_LV
IN_HV
L_HV
EN
EXT_REF
EN_REF
LDO1_EN
LDO2_EN
CONF
Figure 4. Boost configuration
-
+
CONTROL
LOGIC
STORE
STORE
1.8 V
3.3 V
-
+
+
-
OUTPUT
STORE
UVP
OVP
LDO1
TO LOAD1
C
STORE
LDO2
TO LOAD2
_____ _____
OUT_CONN
_____ _____
DC-DC_ON
LOAD
PGND GND
In case of boost configuration, once the source is connected, the IC starts boosting the voltage on the STORE pin. In the range of 0 ≤ V
STORE
< 2.6 V the voltage boost is carried on by an integrated high-efficiency charge pump, while the DC-DC converter stage remains OFF.
shows the behavior of input voltage V
IN
and V
STORE
at the startup.
Figure 5. Boost startup page 11/27
STBLW35
Boost configuration
In the range V
STORE
≥ 2.6 V and until V
OVP
< V
BG
the V voltage range DC-DC switches until V
EN
> V
EN_REF
.
STORE voltage is boosted by the DC-DC converter. In this
Once the voltage at STORE pin triggers the overvoltage threshold (V
OVP
= V
BG
) the switching of the DC-DC converter is stopped until V
STORE
decrease below the level defined by the internal hysteresis (OVP
HYS
).
Figure 6. Triggering of V
OVP
(BATT pin floating)
DS13777 - Rev 1
The following plots (
Figure 7. Efficiency vs. input current; V
Figure 8. Efficiency vs. input current; V
,
Figure 9. Efficiency vs. input current; V
,
Figure 10. Efficiency vs. input current; V
show the power efficiency of the DC-DC converter configured in boost mode at T
AMB
)
= 25 °C in some typical use cases at different input voltages:
Figure 7. Efficiency vs. input current; V
IN
= 0.85 V
0.7
0.65
0.6
0.55
0.5
0.45
0.9
0.85
0.8
0.75
0.4
0.01
0.1
10
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
1
Input current [mA]
100
AM03745 page 12/27
6.3
Figure 8. Efficiency vs. input current; V
IN
= 1.25 V
0.9
0.85
0.8
0.75
0.7
0.65
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.6
0.01
0.1
1
Input current [mA]
10 100
AM03746
Figure 9. Efficiency vs. input current; V
IN
= 1.65 V
1
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0.6
0.01
0.1
10 100
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
1
Input current [mA]
AM03747
Figure 10. Efficiency vs. input current; V
IN
= 2.05 V
0.8
0.75
0.9
0.85
1
0.95
0.7
0.65
0.6
0.01
0.1
10 100
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
1
Input current [mA]
AM03748
Buck-boost configuration
Figure 11. Buck-boost configuration shows an example of buck-boost application circuit.
STBLW35
Buck-boost configuration
DS13777 - Rev 1 page 13/27
DS13777 - Rev 1
STBLW35
Buck-boost configuration
Supply source to STORE
IN_LV
IN_HV
L_HV
EN
EXT_REF
EN_REF
LDO1_EN
LDO2_EN
CONF
Cin
Figure 11. Buck-boost configuration
+
-
CONTROL
LOGIC
STORE
STORE
1.8 V
3.3 V
-
+
+
-
OUTPUT
STORE
UVP
OVP
LDO1
TO LOAD1
C
STORE
LDO2
TO LOAD2
_____ _____
OUT_CONN
_____ _____
DC-DC_ON
LOAD
PGND GND
In case of buck-boost configuration, once the source is connected, the IN_HV and STORE pins are internally shorted until V
STORE
< 2.6 V. Figure 12. Buck-boost startup (I
shows the behavior of the input voltage
V
IN_HV
and V
STORE
at the startup.
Figure 12. Buck-boost startup (I
IN
= 5 μA) page 14/27
DS13777 - Rev 1
STBLW35
Buck-boost configuration
In the range V
STORE
≥ 2.6 V and below the overvoltage protection (V
OVP
< V
BG
) the integrated DC-DC converter starts switching until V
EN
> V
EN_REF
. For the supply sources providing voltages above the allowed range for EN and EN_REF then a resistor partitioning connected between the source and these pins is necessary.
The following plots (
Figure 13. Efficiency vs. input current - V
= 5 V , Figure 14. Efficiency vs. input current - V
Figure 15. Efficiency vs. input current - V
= 10 V , Figure 16. Efficiency vs. input current - V
) show the power efficiency of the DC-DC converter configured in buck-boost mode at T
AMB use cases:
= 25 °C in some typical
Figure 13. Efficiency vs. input current - V
IN
= 5 V
0.85
0.8
] 0.75
0.7
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.75
0.7
0.65
0.6
0.01
0.65
0.6
0.01
0.1
1
Input current [mA]
10 100
AM03750
Figure 14. Efficiency vs. input current - V
IN
= 7.5 V
0.85
0.8
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.1
1
Input current [mA]
10 100
AM03751 page 15/27
6.4
STBLW35
Power manager
0.8
0.75
0.7
0.65
0.6
0.01
Figure 15. Efficiency vs. input current - V
IN
= 10 V
0.85
0.8
0.75
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.7
0.65
0.6
0.01
0.1
1
Input current [mA]
10 100
AM03752
Figure 16. Efficiency vs. input current - V
IN
= 12.5 V
0.85
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.1
1
Input current [mA]
10 100
AM03753
Power manager
The IC works as a power manager also by providing one unregulated output voltage on the STORE pin and two regulated voltages on the LDO1 (1.8 V) and LDO2 (3.3 V) pins.
Each LDO can be selectively enabled or disabled by driving the related enable/disable pins LDO1_EN and
LDO2_EN. The performances of the LDOs can be optimized by selecting a proper capacitor between the LDO
100 mA load is connected.
DS13777 - Rev 1 page 16/27
Figure 17. LDO1 turn-on with 100 mA load
STBLW35
Power manager
Figure 18. LDO2 turn-on with 100 mA load
DS13777 - Rev 1 page 17/27
7
STBLW35
Package and packing information
Package and packing information
Figure 19. VFQFPN20 3 x 3 x 1 mm - 20-lead pitch 0.4 package outline
DS13777 - Rev 1
Symbol
A
A1
A2
Table 5. VFQFPN20 3 x 3 x 1 mm - 20-lead pitch 0.4 package mechanical data
Min.
0.80
-
-
Typ.
0.90
0.02
0.65
Max.
1.0
0.05
1.00
page 18/27
STBLW35
Package and packing information
Symbol e
L ddd
E
E1
E2
A3 b
D
D1
D2
Min.
-
0.15
2.85
-
1.50
2.85
-
1.50
0.35
0.30
-
Typ.
0.20
0.20
3.00
1.60
1.60
3.00
1.60
1.60
0.40
0.40
-
Max.
3.15
-
1.70
0.45
0.50
0.07
-
0.25
3.15
-
1.70
1. “VFQFPN” stands for “Thermally Enhanced Very thin Fine pitch Quad Packages No lead”. Very thin: 0.80 < A ≤ 1.00 mm / fine pitch: e < 1.00 mm.
Figure 20. Reccomended footprint of VFQFPN20 3 x 3 x 1 mm - 20-lead pitch 0.4
DS13777 - Rev 1 page 19/27
Figure 21. Tape and reel design
STBLW35
Package and packing information
DS13777 - Rev 1 page 20/27
STBLW35
Ordering information
8
Ordering information
Order code
STBLW35TTR
Table 6. Order code
Op. temp. range [ o C]
-40 to 85
Package
VFQFPN 3 x 3 x 1 20L
Packing
Tape and reel
DS13777 - Rev 1 page 21/27
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Application tips
Appendix A
Application tips
In DC-DC converters the energy is transferred from the input to the output through the inductor. During the ON phase of the duty cycle, the inductor stores energy while during the OFF phase of the duty cycle, the energy is released toward the output stage.
Figure 22. Inductor current and input voltage waveforms
I
L(PEAK)
I
LH
I
L(MIN)
V
IN
L
*
T
ON
V
IN
- V
STORE
L
*
T
OFF
LOW INPUT POWER
Internal
Driving Signal
T
ON
ON
T
T
OFF
OFF
T
ON(MAX)
T
OFF(MIN)
V
IN
DS13777 - Rev 1
The IC controls the duty cycle of the driving signal by comparing the voltages on the EN and EN_REF pins. When
V
EN
rises higher than V
EN_REF
, the IC switches ON and the inductor is loaded for T
ON
until one of the following events occurs:
•
•
V
STORE
triggers the overvoltage threshold
The inductor current (I
L
) triggers the internal threshold I
L(PEAK)
(= 140 mA, typ.)
• T
ON(MAX)
= 10 μs elapses
The energy stored in the inductor is released to the output stage during the OFF phase. During T
OFF
, I
L decreases to 0 mA (all energy has been released). According to the internal controls of the IC, T
OFF(MIN)
=
0.2 μs then, in order to prevent I
L
becoming negative, the application must be designed such that the energy stored in the inductor during T
ON
is always greater or equal to the energy released during T
OFF
. The application has to guarantee I
L(MIN)
> 0:
Equation 10:
• I
L(MIN)
= I
H
- (V
STORE
- V
IN
)×(T
OFF(MIN)
/L) > 0
Equation 11:
• I
L(MIN)
= (V
IN
/L) × T
ON(MAX)
- (V
STORE
- V
IN
)×(T
OFF(MIN)
/L) > 0 leading
Equation 12:
• V
IN
> V
STORE
× (T
OFF(MIN)
/(T
ON(MAX)
+ T
OFF(MIN)
)
A resistor partitioning can be used between input rail, EN and EN_REF pins purposing the IC switch-off before
I
L(MIN)
≤ 0. As worst case for the above equation it can be considered: V
STORE
at overvoltage level, V
EN
at the minimum operating voltage (V
IN(MIN)
).
page 22/27
Revision history
Date
15-Jul-2021
Version
1
Table 7. Document revision history
Changes
Initial release.
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DS13777 - Rev 1 page 23/27
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Contents
Contents
DS13777 - Rev 1 page 24/27
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List of tables
List of tables
DS13777 - Rev 1 page 25/27
STBLW35
List of figures
List of figures
Figure 7. Efficiency vs. input current; V
Figure 8. Efficiency vs. input current; V
Figure 9. Efficiency vs. input current; V
Figure 10. Efficiency vs. input current; V
Figure 12. Buck-boost startup (I
Figure 13. Efficiency vs. input current - V
Figure 14. Efficiency vs. input current - V
Figure 15. Efficiency vs. input current - V
Figure 16. Efficiency vs. input current - V
DS13777 - Rev 1 page 26/27
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DS13777 - Rev 1 page 27/27
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