STMicroelectronics STM8L151G2 Datasheet

Wait mode (WFE or WFI mode). Wait consumption: refer to Table 20

(18)

(8-bit)

(16-bit)

(2)

/41

(1)(2)

(23/28)

(3)

(10)

(18)

/41

Others

CPU frequency

Operating voltage

RTC, window watchdog, independent watchdog,

16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz external oscillator

16 MHz

1.8 to 3.6 V (down to 1.65 V at power-down) with BOR

1.65 to 3.6 V without BOR

Operating temperature

−

40 to +85 °C /

−

40 to +125 °C

Packages

TSSOP20

UFQFPN20

UFQFPN28

UFQFPN32

LQFP48

TSSOP20

UFQFPN20

UFQFPN28

UFQFPN32

LQFP48

The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as general purpose output only (PA1).

26 GPIOs in the STM8L151K3 and 40 GPIOs in the STM8L151C3.

22 channels in the STM8L151K3 and 28 channels in the STM8L151C3.

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Description

Note:

The ultra-low-power low-density STM8L151x2/3 devices are fully pin-to-pin, software and feature compatible. Besides the full compatibility within the family, the devices are part of

STMicroelectronics microcontrollers ultra-low-power strategy which also includes

STM8L101xx and STM8L15xxx. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features.

They are all based on STMicroelectronics 0.13 µm ultra-low leakage process.

The STM8L151xx and STM8L152xx are pin-to-pin compatible with STM8L101xx devices.

Performance

All families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM

Cortex

-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios.

This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.

Shared peripherals

STM8L151xx/152xx and STM8L15xxx share identical peripherals which ensure a very easy migration from one family to another:

•

Analog peripherals: ADC1 and comparators COMP1/COMP2

• Digital peripherals: RTC and some communication interfaces

Common system strategy

To offer flexibility and optimize performance, the STM8L151xx/152xx and STM8L15xxx devices use a common architecture:

•

Same power supply range from 1.8 to 3.6 V, down to 1.65 V at power down

• Architecture optimized to reach ultra-low consumption both in low power modes and

Run mode

•

Fast startup strategy from low power modes

• Flexible system clock

•

Ultra-safe reset: same reset strategy for both STM8L15x and STM32L15xxx including power-on reset, power-down reset, brownout reset and programmable voltage detector.

Features

ST ultra-low-power continuum also lies in feature compatibility:

• More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm

•

Memory density ranging from 4 to 128 Kbyte

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Functional overview STM8L151x2, STM8L151x3

IR_TIM

SCL, SDA,

SMB

SPI1_MOSI, SPI1_MISO,

SPI1_SCK, SPI1_NSS

USART1_RX, USART1_TX,

USART1_CK

DDA,

SSA

ADC1_INx

DDREF

SSREF

VREFINT out

COMP1_INP

COMP2_INP

COMP2_INM

Figure 1. Low-density STM8L151x2/3 device block diagram

OSC_IN,

OSC_OUT

OSC32_IN,

OSC32_OUT

SWIM

2 channels

1-16 MHz oscillator

16 MHz internal RC

32 kHz oscillator

38 kHz internal RC

Interrupt controller

STM8 Core

Debug module

(SWIM)

16-bit Timer 2 (2)

16-bit Timer 3

(2)

8-bit Timer 4 (2)

Infrared interface

DMA1 (4 channels)

I²C1

SPI1

USART1

SSA

12-bit ADC1

Temp sensor

Internal reference

voltage

COMP 1

COMP 2

Clock controller and CSS

VDD18

@VDD

Power

VOLT. REG.

Clocks to core and peripherals

RESET

POR/PDR

BOR

PVD up to

8-Kbyte

Program memory

256-byte

Data EEPROM

1-Kbyte RAM

Port A

Port B

Port C

Port D

Port E

Port F

Beeper

RTC

IWDG

(38 kHz clock)

WWDG

V DD =1.65 V

3.6 V

V SS to

NRST

PVD_IN

PA[7:0]

PB[7:0]

PC[7:0]

PD[7:0]

PE[7:0]

PF0

BEEP

ALARM, CALIB,

MS18275V2

Legend :

ADC: Analog-to-digital converter

BOR: Brownout reset

DMA: Direct memory access

I²C: Inter-integrated circuit multi master interface

IWDG: Independent watchdog

POR/PDR: Power on reset / power down reset

RTC: Real-time clock

SPI: Serial peripheral interface

SWIM: Single wire interface module

USART: Universal synchronous asynchronous receiver transmitter

WWDG: Window watchdog

There is no TIM1 on STM8L151x2, STM8L151x3 devices.

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Functional overview

The low-density STM8L151x2/3 devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

•

Wait mode : The CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt or a Reset can be used to exit the microcontroller from

• Low power run mode : The CPU and the selected peripherals are running. Execution is done from RAM with a low speed oscillator (LSI or LSE). Flash and data EEPROM are stopped and the voltage regulator is configured in ultra-low-power mode. The microcontroller enters Low power run mode by software and can exit from this mode by software or by a reset.

All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. Low power run mode consumption: refer to

Table 21 .

•

Low power wait mode: This mode is entered when executing a Wait for event in Low power run mode. It is similar to Low power run mode except that the CPU clock is stopped. The wakeup from this mode is triggered by a Reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, DMA controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an event, the system goes back to Low power run mode.

All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. Low power wait mode consumption: refer to

Table 22 .

• Active-halt mode : CPU and peripheral clocks are stopped, except RTC. The wakeup can be triggered by RTC interrupts, external interrupts or reset. Active-halt consumption: refer to

Table 23 and Table 24

•

Halt mode : CPU and peripheral clocks are stopped, the device remains powered on.

The RAM content is preserved. The wakeup is triggered by an external interrupt or reset. A few peripherals have also a wakeup from Halt capability. Switching off the internal reference voltage reduces power consumption. Through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 µs. Halt consumption: refer to

Table 25 .

The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline.

It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions.

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Functional overview STM8L151x2, STM8L151x3

Architecture and registers

•

Harvard architecture

• 3-stage pipeline

•

32-bit wide program memory bus - single cycle fetching most instructions

• X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations

•

8-bit accumulator

• 24-bit program counter - 16 Mbyte linear memory space

•

16-bit stack pointer - access to a 64 Kbyte level stack

• 8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

• 20 addressing modes

•

Indexed indirect addressing mode for lookup tables located anywhere in the address space

• Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

• 80 instructions with 2-byte average instruction size

•

Standard data movement and logic/arithmetic functions

• 8-bit by 8-bit multiplication

•

16-bit by 8-bit and 16-bit by 16-bit division

• Bit manipulation

•

Data transfer between stack and accumulator (push/pop) with direct stack access

• Data transfer using the X and Y registers or direct memory-to-memory transfers

The low-density STM8L151x2/3 feature a nested vectored interrupt controller:

• Nested interrupts with 3 software priority levels

• 32 interrupt vectors with hardware priority

• Up to 40 external interrupt sources on 11 vectors

• Trap and reset interrupts

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STM8L151x2, STM8L151x3

3.3

3.3.1

3.3.2

Reset and supply management

Functional overview

Power supply scheme

The device requires a 1.65 V to 3.6 V operating supply voltage (V

DD supply pins must be connected as follows:

). The external power

• V

SS1

; V

DD1

= 1.8 to 3.6 V, down to 1.65 V at power down: external power supply for

I/Os and for the internal regulator. Provided externally through V

DD1 corresponding ground pin is V

SS1

pins, the

•

SSA;

DDA

= 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for analog peripherals (minimum voltage to be applied to V

DDA used). V

DDA

is 1.8 V when the ADC1 is

and V

SSA

must be connected to V

DD1

and V

SS1

, respectively.

•

SS2

; V

DD2

= 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for

I/Os. V

DD2

and V

SS2

must be connected to V

DD1

and V

SS1

, respectively.

• V

REF+

; V

REF-

(for ADC1): external reference voltage for ADC1. Must be provided externally through V

REF+

and V

REF-

pin.

Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently (in which case, the V

min value at power down is 1.65 V).

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the BOR) in Halt mode. The device remains under reset when V

DD is below a specified threshold, V

POR/PDR or V

BOR

, without the need for any external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when V

DDA

is higher than the V

PVD

DDA

drops below the V

PVD

threshold and/or when

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

The low-density STM8L151x2/3 embeds an internal voltage regulator for generating the 1.8

V power supply for the core and peripherals.

This regulator has two different modes:

•

Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event

(WFE) modes.

•

Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and

Low power wait modes.

When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption.

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Functional overview STM8L151x2, STM8L151x3

The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.

Features

• Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

•

Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register.

• Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

•

System clock sources: 4 different clock sources can be used to drive the system clock:

– 1-16 MHz High speed external crystal (HSE)

– 16 MHz High speed internal RC oscillator (HSI)

– 32.768 kHz Low speed external crystal (LSE)

– 38 kHz Low speed internal RC (LSI)

• RTC clock sources: the above four sources can be chosen to clock the RTC whatever the system clock.

•

Startup clock: After reset, the microcontroller restarts by default with an internal

2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

• Clock security system (CSS): This feature can be enabled by software. If a HSE clock failure occurs, the system clock is automatically switched to HSI.

•

Configurable main clock output (CCO): This outputs an external clock for use by the application.

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STM8L151x2, STM8L151x3

OSC_OUT

OSC_IN

OSC32_OUT

OSC32_IN

Functional overview

Figure 2. Low-density STM8L151x2/3 clock tree diagram

HSE OSC

1-16 MHz

HSI RC

1-16 MHz

HSE

HSI

LSI

LSE

SWIM[3:0]

SYSCLK to core and memory

SYSCLK prescaler

/1;2;4;8;16;32;64

Peripheral

Clock enable (13 bits)

PCLK to peripherals

LSE

BEEP to

CLKBEEPSEL[1:0]

BEEPCLK

LSI

LSI RC

38 kHz IWDGCLK to

IWDG

LSE OSC

32.768 kHz

RTCSEL[3:0]

RTC prescaler

/1;2;4;8;16;32;64 RTCCLK

RTC to

CCO

Configurable clock output

CCO prescaler

/1;2;4;8;16;32;64

CCOSEL[3:0]

HSI

LSI

HSE

LSE

MS18281V2

3.5 Low power real-time clock

The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.

Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically.

It provides a programmable alarm and programmable periodic interrupts with wakeup from

Halt capability.

•

Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach

36 hours

• Periodic alarms based on the calendar can also be generated from every second to every year

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Functional overview STM8L151x2, STM8L151x3

3.6 Memories

The low-density STM8L151x2/3 devices have the following main features:

•

Up to 1 Kbyte of RAM

• The non-volatile memory is divided into three arrays:

– Up to 8 Kbyte of low-density embedded Flash program memory

– 256 byte of data EEPROM

– Option bytes.

The EEPROM embeds the error correction code (ECC) feature.

The option byte protects part of the Flash program memory from write and readout piracy.

3.7 DMA

A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and peripherals-from/to-memory transfer capability. The 4 channels are shared between the following IPs with DMA capability: ADC1, I2C1, SPI1, USART1, the three Timers.

Note:

•

12-bit analog-to-digital converter (ADC1) with 25 channels (including 1 fast channel), temperature sensor and internal reference voltage

• Conversion time down to 1 µs with f

SYSCLK

= 16 MHz

•

Programmable resolution

• Programmable sampling time

•

Single and continuous mode of conversion

• Scan capability: automatic conversion performed on a selected group of analog inputs

•

Analog watchdog

• Triggered by timer

ADC1 can be served by DMA1.

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The low-density STM8L151x2/3 embed two comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal or external

(coming from an I/O).

• One comparator with fixed threshold (COMP1).

•

One comparator rail to rail with fast or slow mode (COMP2). The threshold can be one of the following:

– External I/O

– Internal reference voltage or internal reference voltage sub multiple (1/4, 1/2, 3/4)

The two comparators can be used together to offer a window function. They can wake up from Halt mode.

DS7204 Rev 11

STM8L151x2, STM8L151x3 Functional overview

The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.

The highly flexible routing interface controls the routing of internal analog signals to ADC1,

COMP1, COMP2, and the internal reference voltage V

REFINT

. It also provides a set of registers for efficiently managing the charge transfer acquisition sequence (

Section 3.11:

Touch sensing

Low-density STM8L151x2/3 devices provide a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (example, glass, plastic). The capacitive variation introduced by a finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the electrode capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. In low-density STM8L15xxx devices, the acquisition sequence is managed either by software or by hardware and it involves analog I/O groups, the routing interface, and timers.Reliable touch sensing solutions can be quickly and easily implemented using the free STM8 Touch Sensing Library.

3.12 Timers

Low-density STM8L151x2/3devices contain two 16-bit general purpose timers (TIM2 and

TIM3) and one 8-bit basic timer (TIM4).

All the timers can be served by DMA1.

Table 2 compares the features of the advanced control, general-purpose and basic timers.

Timer

Counter resolution

Counter type

TIM2

TIM3

TIM4

16-bit

8-bit up/down up

Table 2. Timer feature comparison

Prescaler factor

DMA1 request generation

Capture/compare channels

Complementary outputs

Any power of 2 from 1 to 128

Any power of 2 from 1 to 32768

Yes

None

DS7204 Rev 11

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Functional overview STM8L151x2, STM8L151x3

3.12.1 16-bit general purpose timers

• 16-bit autoreload (AR) up/down-counter

•

7-bit prescaler adjustable to fixed power of 2 ratios (1…128)

• 2 individually configurable capture/compare channels

•

PWM mode

• Interrupt capability on various events (capture, compare, overflow, break, trigger)

•

Synchronization with other timers or external signals (external clock, reset, trigger and enable)

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow.

The watchdog system is based on two independent timers providing maximum security to the applications.

The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the internal LSI RC clock source, and thus stays active even in case of a

CPU clock failure.

3.14 Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Functional overview

3.15.1 SPI

Note:

The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial communication with external devices.

• Maximum speed: 8 Mbit/s (f

SYSCLK

/2) both for master and slave

• Full duplex synchronous transfers

• Simplex synchronous transfers on 2 lines with a possible bidirectional data line

•

Master or slave operation - selectable by hardware or software

• Hardware CRC calculation

• Slave/master selection input pin

SPI1 can be served by the DMA1 Controller.

3.15.2 I²C

Note:

The I

C bus interface (I

C1) provides multi-master capability, and controls all I²C busspecific sequencing, protocol, arbitration and timing.

• Master, slave and multi-master capability

•

Standard mode up to 100 kHz and fast speed modes up to 400 kHz.

•

7-bit and 10-bit addressing modes.

• SMBus 2.0 and PMBus support

• Hardware CRC calculation

C1 can be served by the DMA1 Controller.

3.15.3 USART

Note:

The USART interface (USART1) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates.

• 1 Mbit/s full duplex SCI

• SPI1 emulation

•

High precision baud rate generator

•

SmartCard emulation

• IrDA SIR encoder decoder

• Single wire half duplex mode

USART1 can be served by the DMA1 Controller.

The low-density STM8L151x2/3 devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals.

DS7204 Rev 11

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Functional overview STM8L151x2, STM8L151x3

Development tools

Development tools for the STM8 microcontrollers include:

•

The STice emulation system offering tracing and code profiling

• The STVD high-level language debugger including C compiler, assembler and integrated development environment

• The STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.

Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming.

The single-wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, CPU operation can also be monitored in realtime by means of shadow registers.

Bootloader

The low-density STM8L151x2/3 ultra-low-power devices feature a built-in bootloader (see

UM0560: STM8 bootloader user manual ).

The bootloader is used to download application software into the device memories, including RAM, program and data memory, using standard serial interfaces. It is a complementary solution to programming via the SWIM debugging interface.

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STM8L151x2, STM8L151x3

4 Pinout and pin description

Pinout and pin description

Figure 3. STM8L151Cx LQFP48 package pinout

PA0

NRST/PA1

PA2

PA3

PA4

PA5

PA6

SS1

/ V

SSA

PA7

REF-

DDA

REF+

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

PD7

PD6

PD5

PD4

PF0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

MSv60427

Figure 4. STM8L151Kx UFQFPN32 package pinout

NRST/PA1

PA2

PA3

PA4

PA5

PA6

VSS1

VDD1

32 31 30 29 28 27 26 25

9 10 11

12 13 14 15 16

PD7

PD6

PD5

PD4

PB7

PB6

PB5

PB4

MS18277V1

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Pinout and pin description STM8L151x2, STM8L151x3

Figure 5. STM8L151Gx UFQFPN28 package pinout

NRST/PA1

PA2

PA3

PA4

PA5

SS1

SSA

REF-

DD1

DDA

REF+

28 27 26 25 24 23 22

8 9 10 11 12 13 14

PC0

PD4

PB7

PB6

PB5

PB4

PB3 ai18250b

Figure 6. STM8L151Fx UFQFPN20 package pinout

NRST / PA1

PA2

PA3

VSS/VSSA/VREF-

DD/VDDA/VREF+

20 1 9 1 8 1 7 1 6

6 7 8 9 10

PC0

PB7

PB6

PB5

PB4

MS18279V1

Figure 7. STM8L151Fx TSSOP20 package pinout

PC5

PC6

PA0

NRST / PA1

PA2

PA3

VSS/VSSA/VREF-

VDD/VDDA/VREF+

PD0

PB0

PC4

PC1

PC0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

MS18280V1

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STM8L151x2, STM8L151x3 Pinout and pin description

Type

Table 3. Legend/abbreviation for table 4

I= input, O = output, S = power supply

Output HS = high sink/source (20 mA)

Level

FT Five-volt tolerant

Port and control configuration

Reset state

Input

Output float = floating, wpu = weak pull-up

T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release).

Unless otherwise specified, the pin state is the same during the reset phase (i.e.

“under reset”) and after internal reset release (i.e. at reset state).

Pin number

Table 4. Low-density STM8L151x2/3 pin description

Input Output

Pin name

Default alternate function

2 1 1 1 4 NRST/PA1

(1)

3 2 2 2 5

PA2/OSC_IN/

[USART_TX]

[SPI_MISO]

5 4 4 -

PA4/TIM2_BKIN/

[TIM2_ETR]

(2)

ADC1_IN2/

COMP1_INP

6 5 5 -

PA5/TIM3_BKIN/

[TIM3_ETR]

ADC1_IN1/

COMP1_INP

7 6 -

PA6/ADC1_TRIG/

ADC1_IN0/

COMP1_INP

8 - PA7

24 13 12 7 10

PB0

(3)

/TIM2_CH1/

ADC1_IN18/

COMP1_INP

I/O X HS X Reset

I/O X X X HS X X Port A2

4 3 3 3 6

PA3/OSC_OUT/ [USA

RT_RX]

/[SPI_MOSI

]

I/O X X X HS X X Port A3

I/O

I/O -

Port A4

Port A5

Port A6

Port A7

I/O X X X HS X X Port B0

PA1

HSE oscillator input /

[USART transmit] / [SPI master in- slave out] /

HSE oscillator output /

[USART receive]/ [SPI master out/slave in] /

Timer 2 - break input /

[Timer 2 - external trigger] /ADC1 input 2/

Comparator1 positive input

Timer 3 - break input /

[Timer 3 - external trigger] /ADC1input 1/

Comparator1 positive input

ADC1- trigger

/ADC1input 0/

Comparator1 positive input

Timer 2 - channel 1 /

ADC1_IN18/

Comparator1 positive input

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Pinout and pin description STM8L151x2, STM8L151x3

Pin number

Table 4. Low-density STM8L151x2/3 pin description (continued)

Input Output

Pin name

Default alternate function

25 14 13

26 15 14

27 16 15 10 13

28 17 16 11 14

29 18 17 12 15

30 19 18 13 16

PB1/TIM3_CH1/

ADC1_IN17/

COMP1_INP

PB2/ TIM2_CH2/

ADC1_IN16/

COMP1_INP

PB3/TIM2_ETR/

ADC1_IN15/RTC_AL

ARM

(4)

COMP1_INP

PB4

/SPI1_NSS/

ADC1_IN14/

COMP1_INP

PB5/SPI_SCK/

/ADC1_IN13/

COMP1_INP

PB6/SPI1_MOSI/

ADC1_IN12/

COMP1_INP

I/O

Port B1

Port B2

Port B3

Port B4

Port B5

Port B6

Timer 3 - channel1/

ADC1_IN17/

Comparator1 positive input

Timer 2 - channel2

ADC1_IN16/

Comparator1 positive input

Timer 2 - external trigger / ADC1_IN15 /

RTC_ALARM

/Comparator1

positive input

SPI master/slave select

/ ADC1_IN14/

Comparator1 positive input

[SPI clock] /

ADC1_IN13/

Comparator 1 positive input

SPI master out/ slave in / ADC1_IN12/

Comparator1 positive input

31 20 19 14 17

42 28 24 -

PB7/SPI1_MISO/

ADC1_IN11/

COMP1_INP

PC3/USART_TX/

ADC1_IN5/

COMP1_INP/

COMP2_INM

I/O

I/O -

Port B7

Port C3

SPI1 master in-slave out/ ADC1_IN11/

Comparator1 positive input

37 25 21 15 18 PC0/I2C_SDA I/O FT X X T

(5)

Port C0 I2C data

38 26 22 16 19 PC1/I2C_SCL

41 27 23 -

PC2/USART_RX/ADC

1_IN6/

COMP1_INP

I/O FT

I/O -

X X

X HS X X

Port C1 I2C clock

Port C2

USART receive /

ADC1_IN6/

Comparator1 positive input

USART transmit /

ADC1_IN5/

Comparator1 positive input/Comparator 2 negative input

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Pinout and pin description

Pin number

Table 4. Low-density STM8L151x2/3 pin description (continued)

Input Output

Pin name

Default alternate function

43 29 25 17 20

PC4/USART_CK]/

I2C_SMB/CCO/

ADC1_IN4/

COMP1_INP/

COMP2_INM

44 30 26 18 1

PC5/OSC32_IN

TIM2_CH1

(6)

45 31 27 19 2

PC6/OSC32_OUT/

[SPI_SCK]

[USART_RX]

TIM2_CH2

(6)

46 -

PC7/ADC1_IN3/

COMP1_INP/

COMP2_INM

20 9 8 6 9

PD0/TIM3_CH2/

[ADC1_TRIG]

ADC1_IN22/

COMP1_INP/

COMP2_INP

21 10 9 -

PD1/TIM3_ETR/

ADC1_IN21/

COMP1_INP/

COMP2_INP

22 11 10 -

PD2/ADC1_IN20/

COMP1_INP

23 12 11 -

PD3/ADC1_IN19/

RTC_CALIB

(7)

COMP1_INP

33 21 20 -

PD4/ADC1_IN10/

COMP1_INP

I/O X X X HS X X Port C4

I/O X X X HS X X Port C5

I/O X X X HS X X Port C6

I/O X X X HS X X Port C7

I/O X X X HS X X Port D0

I/O X X X HS X X Port D1

I/O X X X HS X X Port D2

I/O X X X HS X X Port D3

I/O X X X HS X X Port D4

USART synchronous clock / I2C1_SMB /

Configurable clock output / ADC1_IN4/

Comparator1 positive input/Comparator 2 negative input

LSE oscillator input /

[SPI master/slave select] / [USART transmit]/

Timer 2 -channel 1

(6)

LSE oscillator output /

[SPI clock] / [USART receive]/

Timer 2 -channel 2

(6)

ADC1_IN3/

Comparator1 positive input/Comparator 2 negative input

Timer 3 - channel 2 /

[ADC1_Trigger] /

ADC1_IN22/

Comparator1 positive input/Comparator 2 positive input

Timer 3 - external trigger / ADC1_IN21/

Comparator1 positive input/Comparator 2 positive input

ADC1_IN20/

Comparator1 positive input

ADC1_IN19/

RTC calibration

(7)

Comparator1 positive input

ADC1_IN10/

Comparator1 positive input

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Pinout and pin description STM8L151x2, STM8L151x3

Pin number

Table 4. Low-density STM8L151x2/3 pin description (continued)

Input Output

Pin name

Default alternate function

34 22 -

PD5/ ADC1_IN9/

COMP1_INP

35 23 -

PD6/ADC1_IN8/

RTC_CALIB/

COMP1_INP

36 24 -

PD7 /ADC1_IN7/

RTC_ALARM/

COMP1_INP

14 - PE0

15 - PE1

16 - PE2

17 - PE3/ADC1_IN26

18 - PE4/ADC1_IN27

19 -

PE5/ADC1_IN23/

COMP1_INP/

COMP2_INP

47 - PE6/PVD_IN

48 - PE7/ADC1_IN25

32 - PF0/ADC1_IN24

10 - V

8 7 5 8 V

DDA

/ V

REF+

9 7 6 4 7 V

/ V

REF-

/ V

SSA

11 - V

DDA

12 - V

REF+

13 - Reserved

I/O X X X HS X X Port D5

ADC1_IN9/

Comparator1 positive input

I/O

I/O -

Port D6

Port D7

ADC1_IN8 / RTC calibration/

Comparator1 positive input

ADC1_IN7/RTC alarm/

Comparator1 positive input

I/O X X X HS X X Port E0

I/O

Port E1

Port E2

I/O X X X HS X X Port E3 ADC1_IN26

I/O X X X HS X X Port E4 ADC1_IN27

I/O X X X HS X X Port E5

ADC1_IN23/

Comparator 1 positive input/Comparator 2 positive input

I/O X X X HS X X Port E6 PVD_IN

I/O X X X HS X X Port E7 ADC1_IN25

I/O X X X HS X X Port F0 ADC1_IN24

S -

Digital supply voltage

Digital supply voltage /

ADC1 positive voltage reference

Ground voltage / ADC1 negative voltage reference / Analog ground voltage

Analog supply voltage

ADC1 positive voltage reference

Pin not connected

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Pinout and pin description

Pin number

Table 4. Low-density STM8L151x2/3 pin description (continued)

Input Output

Pin name

Default alternate function

1 32 28 20 3

PA0

(8)

[USART_CK]

SWIM/BEEP/IR_TIM

(9)

I/O X X X

(9)

X X Port A0

[USART1 synchronous

clock]

Table 4: Low-density STM8L151x2/3 pin description , some alternate functions

/ SWIM input and output /

Beep output / Infrared

Timer output

40 - V

SSIO

39 - V

DDIO

S -

I/O ground voltage

I/O supply voltage

At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L15xxx and STM8L16xxx reference manual (RM0031).

[ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function).

A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.

20-pin and 28-pin packages only.

In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to V

DD implemented).

are not

20-pin packages only.

28-pin packages only

The PA0 pin is in input pull-up during the reset phase and after reset release.

High Sink LED driver capability available on PA0.

Note: The slope control of all GPIO pins, except true open drain pins, can be programmed. By default, the slope control is limited to 2 MHz.

As shown in

can be remapped on different I/O ports by programming one of the two remapping registers described in the “Routing interface (RI) and system configuration controller” section in the

STM8L15xxx and STM8L16xxx reference manual (RM0031).

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Memory and register map

5 Memory and register map

STM8L151x2, STM8L151x3

32/123

The memory map is shown in

Figure 8 .

Figure 8. Memory map

0x00 0000

0x00 9FFF

RAM including

Stack (512 bytes) 0x00 03FF

0x00 0400

0x00 1FFF

0x00 1000

Reserved

Data EEPRO M

(256 Bytes)

0x00 10FF

0x00 1100

Reserved

0x00 47FF

0x00 4800

0x00 487F

0x00 4880

Option bytes

Reserved

0x00 4909

0x00 4910

0x00 4911

0x00 4912

0x00 4925

0x00 4926

0x00 4931

0x00 4932

0x00 4FFF

0x00 5000

Reserved

0x00 5457

0x00 5458

G PIO and peripheral registers

Reserved

0x00 5FFF

0x00 6000

VREFINT_Factory_CONV

TS_Factory_CONV_V90

Reserved

Unique ID

Boot ROM

(2 Kbyt es)

0x00 67FF

0x00 6800

Reserved

0x00 7EFF

0x00 7F00

CPU/ SWIM/ Debug/I TC

Registers

0x00 7FFF

0x00 8000

0x00 80FF

0x00 8100

Reset and int errupt vectors

Low densit y

Flash program memory

0x00 5000

0x00 501E

0x00 5050

0x00 5055

0x00 5070

0x00 509D

0x00 50A0

0x00 50A6

0x00 50AA

0x00 52E0

0x00 52EA

0x00 52FF

0x00 5317

0x00 5340

0x00 53C8

0x00 5430

0x00 5440

0x00 5445

0x00 5450

0x00 5457

0x00 50A9

0x00 50B0

0x00 50B2

0x00 50B4

0x00 50C0

0x00 50D1

0x00 50D3

0x00 50D5

0x00 50E0

0x00 50E3

0x00 50F0

0x00 50F4

0x00 5040

0x00 5191

0x00 5200

0x00 5208

0x00 5210

0x00 521F

0x00 5230

0x00 523B

0x00 5250

0x00 5267

0x00 5280

0x00 5297

GPIO ports

Reserved

Flash

Reserved

DMA1

SYSCFG

ITC-EXT1

WFE

ITC-EXT1

Reserved

RST

PWR

Reserved

CLK

Reserved

WWDG

Reserved

IWDG

Reserved

BEEP

Reserved

RTC

Reserved

SPI1

Reserved

I2C1

Reserved

USART1

Reserved

TIM2

Reserved

TIM3

Reserved

TIM4

Reserved

IRTIM

Reserved

ADC1

Reserved

COMP1/COMP2

Reserved

MS18274V2

Table 5

lists the boundary addresses for each memory size. The top of the stack is at the RAM end address.

The VREFINT_Factory_CONV byte represents the LSB of the V

REFINT

12-bit ADC1 conversion result. The

DS7204 Rev 11

STM8L151x2, STM8L151x3 Memory and register map

MSB have a fixed value: 0x6.

The TS_Factory_CONV_V90 byte represents the LSB of the V

90 have a fixed value: 0x3.

12-bit ADC1 conversion result. The MSB

Refer to Table 8

for an overview of hardware register mapping, to Table 7

for details on I/O port hardware registers, and to

Table 9 for information on CPU/SWIM/debug module controller registers.

Memory area

Table 5. Flash and RAM boundary addresses

Size Start address End address

RAM 1 Kbyte 0x00 0000 0x00 03FF

Flash program memory

8 Kbyte

4 Kbyte

0x00 8000

0x00 9FFF

0x00 8FFF

Address

0x00 4910

0x00 4911

Address

0x00 5000

0x00 5001

0x00 5002

0x00 5003

0x00 5004

0x00 5005

0x00 5006

0x00 5007

0x00 5008

0x00 5009

Block

Table 6. Factory conversion registers

Register label Register name

VREFINT_Factory_

CONV

TS_Factory_CONV_

V90

Value of the internal reference voltage measured during the factory phase

Value of the temperature sensor output voltage measured during the factory phase

Reset status

0xXX

Block

Table 7. I/O port hardware register map

Register label Register name

Port A

Port B

PA_ODR

PA_IDR

PA_DDR

PA_CR1

PA_CR2

PB_ODR

PB_IDR

PB_DDR

PB_CR1

PB_CR2

Port A data output latch register

Port A input pin value register

Port A data direction register

Port A control register 1

Port A control register 2

Port B data output latch register

Port B input pin value register

Port B data direction register

Port B control register 1

Port B control register 2

Reset status

0x00

0xXX

0x00

0xXX

0x00

0x01

0x00

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Address

0x00 500A

0x00 500B

0x00 500C

0x00 500D

0x00 500E

0x00 500F

0x00 5010

0x00 5011

0x00 5012

0x00 5013

0x00 5014

0x00 5015

0x00 5016

0x00 5017

0x00 5018

0x00 5019

0x00 501A

0x00 501B

0x00 501C

0x00 501D

Memory and register map STM8L151x2, STM8L151x3

Table 7. I/O port hardware register map (continued)

Block Register label Register name

Port C

Port D

Port E

Port F

PC_ODR

PC_IDR

PC_DDR

PC_CR1

PC_CR2

PD_ODR

PD_IDR

PD_DDR

PD_CR1

PD_CR2

PE_ODR

PE_IDR

PE_DDR

PE_CR1

PE_CR2

PF_ODR

PF_IDR

PF_DDR

PF_CR1

PF_CR2

Port C data output latch register

Port C input pin value register

Port C data direction register

Port C control register 1

Port C control register 2

Port D data output latch register

Port D input pin value register

Port D data direction register

Port D control register 1

Port D control register 2

Port E data output latch register

Port E input pin value register

Port E data direction register

Port E control register 1

Port E control register 2

Port F data output latch register

Port F input pin value register

Port F data direction register

Port F control register 1

Port F control register 2

Reset status

0x00

0xXX

0x00

0xXX

0x00

0xXX

0x00

0xXX

0x00

Address

0x00 502E to

0x00 5049

0x00 5050

0x00 5051

0x00 5052

0x00 5053

0x00 5054

Block

Table 8. General hardware register map

Register label Register name

Flash

FLASH_CR1

FLASH_CR2

FLASH _PUKR

FLASH _DUKR

FLASH _IAPSR

Reserved area (44 byte)

Flash control register 1

Flash control register 2

Flash program memory unprotection key register

Flash data EEPROM unprotection key register

Flash in-application programming status register

Reset status

0x00

34/123

DS7204 Rev 11

STM8L151x2, STM8L151x3 Memory and register map

Table 8. General hardware register map (continued)

Block Register label Register name Reset status

0x00 5079

0x00 507A

0x00 507B

0x00 507C

0x00 507D to

0x00 507E

0x00 507F

0x00 5080

0x00 5081

Address

0x00 5055 to

0x00 506F

0x00 5070

0x00 5071

0x00 5072 to

0x00 5074

0x00 5075

0x00 5076

0x00 5077

0x00 5078

0x00 5082

0x00 5083

DMA1

DMA1_GCSR

DMA1_GIR1

Reserved area (27 byte)

DMA1 global configuration & status register

DMA1 global interrupt register 1

Reserved area (3 byte)

DMA1_C0CR

DMA1_C0SPR

DMA1_C0NDTR

DMA1_C0PARH

DMA1_C0PARL

DMA1_C0M0ARH

DMA1_C0M0ARL

DMA1 channel 0 configuration register

DMA1 channel 0 status & priority register

DMA1 number of data to transfer register

(channel 0)

DMA1 peripheral address high register

(channel 0)

DMA1 peripheral address low register

(channel 0)

Reserved area (1 byte)

DMA1 memory 0 address high register

(channel 0)

DMA1 memory 0 address low register

(channel 0)

Reserved area (2 byte)

DMA1_C1CR

DMA1_C1SPR

DMA1_C1NDTR

DMA1_C1PARH

DMA1_C1PARL

DMA1 channel 1 configuration register

DMA1 channel 1 status & priority register

DMA1 number of data to transfer register

(channel 1)

DMA1 peripheral address high register

(channel 1)

DMA1 peripheral address low register

(channel 1)

0xFC

0x00

0x52

0x00

0x52

0x00

DS7204 Rev 11

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0x00 5096

0x00 5097

0x00 5098

0x00 5099

0x00 509A

0x00 509B to

0x00 509C

0x00 508D

0x00 508E

0x00 508F

0x00 5090

0x00 5091

0x00 5092

0x00 5093

0x00 5094

0x00 5095

Address

0x00 5084

0x00 5085

0x00 5086

0x00 5087

0x00 5088

0x00 5089

0x00 508A

0x00 508B

0x00 508C

Memory and register map STM8L151x2, STM8L151x3

Table 8. General hardware register map (continued)

Block Register label Register name

DMA1_C1M0ARH

DMA1_C1M0ARL

Reserved area (1 byte)

DMA1 memory 0 address high register

(channel 1)

DMA1 memory 0 address low register

(channel 1)

DMA1

DMA1_C2CR

DMA1_C2SPR

DMA1_C2NDTR

DMA1_C2PARH

DMA1_C2PARL

DMA1_C2M0ARH

DMA1_C2M0ARL

DMA1_C3CR

DMA1_C3SPR

DMA1_C3NDTR

DMA1_C3PARH_

C3M1ARH

DMA1_C3PARL_

C3M1ARL

DMA_C3M0EAR

DMA1_C3M0ARH

DMA1_C3M0ARL

Reserved area (2 byte)

DMA1 channel 2 configuration register

DMA1 channel 2 status & priority register

DMA1 number of data to transfer register

(channel 2)

DMA1 peripheral address high register

(channel 2)

DMA1 peripheral address low register

(channel 2)

Reserved area (1 byte)

DMA1 memory 0 address high register

(channel 2)

DMA1 memory 0 address low register

(channel 2)

Reserved area (2 byte)

DMA1 channel 3 configuration register

DMA1 channel 3 status & priority register

DMA1 number of data to transfer register

(channel 3)

DMA1 peripheral address high register

(channel 3)

DMA1 peripheral address low register

(channel 3)

DMA channel 3 memory 0 extended address register

DMA1 memory 0 address high register

(channel 3)

DMA1 memory 0 address low register

(channel 3)

Reset status

0x00

0x52

0x00

0x40

0x00

Reserved area (3 byte)

36/123

DS7204 Rev 11

STM8L151x2, STM8L151x3

Address

0x00 509D

0x00 509E

0x00 509F

0x00 50A0

0x00 50A1

0x00 50A2

0x00 50A3

0x00 50A4

0x00 50A5

0x00 50A6

0x00 50A7

0x00 50A8

0x00 50A9

0x00 50AA

0x00 50AB

0x00 50A9 to

0x00 50AF

0x00 50B0

0x00 50B1

0x00 50B2

0x00 50B3

0x00 50B4 to

0x00 50BF

Memory and register map

Table 8. General hardware register map (continued)

Block Register label Register name

SYSCFG_RMPCR3 Remapping register 3

SYSCFG SYSCFG_RMPCR1

ITC - EXTI

SYSCFG_RMPCR2

EXTI_CR1

EXTI_CR2

EXTI_CR3

EXTI_SR1

EXTI_SR2

EXTI_CONF1

WFE_CR1

WFE_CR2

WFE

ITC - EXTI

WFE_CR3

WFE_CR4

EXTI_CR4

EXTI_CONF2

Remapping register 1

Remapping register 2

External interrupt control register 1

External interrupt control register 2

External interrupt control register 3

External interrupt status register 1

External interrupt status register 2

External interrupt port select register 1

WFE control register 1

WFE control register 2

WFE control register 3

WFE control register 4

External interrupt control register 4

External interrupt port select register 2

Reset status

0x00

0x0C

0x2C

(1)

0x00

RST

PWR

RST_CR

RST_SR

PWR_CSR1

PWR_CSR2

Reserved area (7 byte)

Reset control register

Reset status register

Power control and status register 1

Power control and status register 2

0x00

0x01

0x00

Reserved area (12 byte)

DS7204 Rev 11

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Address

0x00 50C0

0x00 50C1

0x00 50C2

0x00 50C3

0x00 50C4

0x00 50C5

0x00 50C6

0x00 50C7

0x00 50C8

0x00 50C9

0x00 50CA

0x00 50CB

0x00 50CC

0x00 50CD

0x00 50CE

0x00 50CF

0x00 50D0

0x00 50D1 to

0x00 50D2

0x00 50D3

0x00 50D4

0x00 50D5 to

00 50DF

0x00 50E0

0x00 50E1

0x00 50E2

0x00 50E3 to

0x00 50EF

0x00 50F0

0x00 50F1

0x00 50F2

0x00 50F3

0x00 50F4 to

0x00 513F

Memory and register map STM8L151x2, STM8L151x3

Table 8. General hardware register map (continued)

Block

CLK

Register label Register name Reset status

CLK_CKDIVR

CLK_CRTCR

CLK_ICKCR

CLK_PCKENR1

CLK_PCKENR2

CLK_CCOR

CLK_ECKCR

CLK clock master divider register

CLK clock RTC register

CLK internal clock control register

CLK peripheral clock gating register 1

CLK peripheral clock gating register 2

CLK configurable clock control register

CLK external clock control register

0x03

0x00

0x11

0x00

CLK_SCSR

CLK_SWR

CLK_SWCR

CLK_CSSR

CLK_CBEEPR

CLK system clock status register

CLK system clock switch register

CLK clock switch control register

CLK clock security system register

CLK clock BEEP register

0x01

0xX0

0x00

CLK_HSICALR CLK HSI calibration register

CLK_HSITRIMR CLK HSI clock calibration trimming register

CLK_HSIUNLCKR CLK HSI unlock register

CLK_REGCSR

CLK_PCKENR3

0xXX

0x00

CLK main regulator control status register 0bxx11 100X

CLK peripheral clock gating register 3 0x00

WWDG

IWDG

BEEP

WWDG_CR

WWDG_WR

IWDG_KR

IWDG_PR

IWDG_RLR

BEEP_CSR1

BEEP_CSR2

Reserved area (2 byte)

WWDG control register

WWDR window register

Reserved area (11 byte)

IWDG key register

IWDG prescaler register

IWDG reload register

Reserved area (13 byte)

BEEP control/status register 1

Reserved area (2 byte)

BEEP control/status register 2

Reserved area (76 byte)

0x7F

0x01

0x00

0xFF

0x00

0x1F

38/123

DS7204 Rev 11

Address

0x00 5155

0x00 5156

0x00 5157

0x00 5158

0x00 5159

0x00 5158

0x00 5159

0x00 515A

0x00 515B

0x00 515C

0x00 515D

0x00 515E

0x00 515F

0x00 5140

0x00 5141

0x00 5142

0x00 5143

0x00 5144

0x00 5145

0x00 5146

0x00 5147

0x00 5148

0x00 5149

0x00 514A

0x00 514B

0x00 514C

0x00 514D

0x00 514E

0x00 514F

0x00 5150

0x00 5151

0x00 5152

0x00 5153

0x00 5154

STM8L151x2, STM8L151x3 Memory and register map

Table 8. General hardware register map (continued)

Block Register label Register name

RTC_TR1

RTC_TR2

RTC_TR3

RTC_DR1

RTC_DR2

RTC_DR3

RTC_CR1

RTC_CR2

RTC_CR3

RTC_ISR1

RTC_ISR2

RTC time register 1

RTC time register 2

RTC time register 3

Reserved area (1 byte)

RTC date register 1

RTC date register 2

RTC date register 3

Reserved area (1 byte)

RTC control register 1

RTC control register 2

RTC control register 3

Reserved area (1 byte)

RTC initialization and status register 1

RTC initialization and Status register 2

RTC

RTC_SPRERH

RTC_SPRERL

RTC_APRER

RTC_WUTRH

RTC_WUTRL

RTC_SSRL

RTC_SSRH

RTC_WPR

RTC_SSRH

RTC_WPR

RTC_SHIFTRH

RTC_SHIFTRL

RTC_ALRMAR1

RTC_ALRMAR2

RTC_ALRMAR3

RTC_ALRMAR4

Reserved area (2 byte)

RTC synchronous prescaler register high

RTC synchronous prescaler register low

RTC asynchronous prescaler register

Reserved area (1 byte)

RTC wakeup timer register high

RTC wakeup timer register low

Reserved area (1 byte)

RTC subsecond register low

RTC subsecond register high

RTC write protection register

RTC subsecond register high

RTC write protection register

RTC shift register high

RTC shift register low

RTC alarm A register 1

RTC alarm A register 2

RTC alarm A register 3

RTC alarm A register 4

Reset status

0x00

0x01

0x21

0x00

0x00

0x00

Table 31: LSE oscillator characteristics on page 74

0x01

0x00

(2)

0x00

0x00

0x00

0x00

DS7204 Rev 11

Memory and register map STM8L151x2, STM8L151x3

Table 8. General hardware register map (continued)

Block Register label Register name Reset status Address

0x00 5160 to

0x00 5163

0x00 5164

0x00 5165

0x00 5166

0x00 5167 to

0x00 5169

0x00 516A

0x00 516B

0x00 516C to

0x00 518F

0x00 5190

0x00 5191 to

0x00 51FF

0x00 5200

0x00 5201

0x00 5202

0x00 5203

0x00 5204

0x00 5205

0x00 5206

0x00 5207

0x00 5208 to

0x00 520F

RTC

SPI1

RTC_ALRMASSRH

RTC_ALRMASSRL

RTC_ALRMASSMS

Reserved area (4 byte)

RTC alarm A subsecond register high

RTC alarm A subsecond register low

RTC alarm A masking register

RTC_CALRH

RTC_CALRL

CSSLSE_CSR

Reserved area (3 byte)

RTC calibration register high

RTC calibration register low

Reserved area (36 byte)

RTC CSS on LSE control and status register

SPI1_CR1

SPI1_CR2

SPI1_ICR

SPI1_SR

SPI1_DR

SPI1_CRCPR

SPI1_RXCRCR

SPI1_TXCRCR

Reserved area (111 byte)

SPI1 control register 1

SPI1 control register 2

SPI1 interrupt control register

SPI1 status register

SPI1 data register

SPI1 CRC polynomial register

SPI1 Rx CRC register

SPI1 Tx CRC register

Reserved area (8 byte)

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x02

0x00

0x07

0x00

40/123

DS7204 Rev 11

Address

0x00 5210

0x00 5211

0x00 5212

0x00 5213

0x00 5214

0x00 5215

0x00 5216

0x00 5217

0x00 5218

0x00 5219

0x00 521A

0x00 521B

0x00 521C

0x00 521D

0x00 521E

0x00 521F to

0x00 522F

0x00 5230

0x00 5231

0x00 5232

0x00 5233

0x00 5234

0x00 5235

0x00 5236

0x00 5237

0x00 5238

0x00 5239

0x00 523A

0x00 523B to

0x00 524F

STM8L151x2, STM8L151x3 Memory and register map

Table 8. General hardware register map (continued)

Block Register label Register name

I2C1

I2C1_CR1

I2C1_CR2

I2C1_FREQR

I2C1_OARL

I2C1_OARH

I2C1_OAR2

I2C1_DR

I2C1_SR1

I2C1_SR2

I2C1_SR3

I2C1_ITR

I2C1_CCRL

I2C1_CCRH

I2C1_TRISER

I2C1_PECR

I2C1 control register 1

I2C1 control register 2

I2C1 frequency register

I2C1 own address register low

I2C1 own address register high

I2C1 own address register for dual mode

I2C1 data register

I2C1 status register 1

I2C1 status register 2

I2C1 status register 3

I2C1 interrupt control register

I2C1 clock control register low

I2C1 clock control register high

I2C1 TRISE register

I2C1 packet error checking register

Reset status

0x00

0x0X

0x00

0x02

0x00

Reserved area (17 byte)

USART1

USART1_SR

USART1_DR

USART1_BRR1

USART1_BRR2

USART1_CR1

USART1_CR2

USART1_CR3

USART1_CR4

USART1_CR5

USART1_GTR

USART1_PSCR

USART1 status register

USART1 data register

USART1 baud rate register 1

USART1 baud rate register 2

USART1 control register 1

USART1 control register 2

USART1 control register 3

USART1 control register 4

USART1 control register 5

USART1 guard time register

USART1 prescaler register

Reserved area (21 byte)

0xC0

0xXX

0x00

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Address

0x00 525F

0x00 5260

0x00 5261

0x00 5262

0x00 5263

0x00 5264

0x00 5265

0x00 5266

0x00 5267 to

0x00 527F

0x00 5250

0x00 5251

0x00 5252

0x00 5253

0x00 5254

0x00 5255

0x00 5256

0x00 5257

0x00 5258

0x00 5259

0x00 525A

0x00 525B

0x00 525C

0x00 525D

0x00 525E

Memory and register map STM8L151x2, STM8L151x3

Table 8. General hardware register map (continued)

Block Register label Register name

TIM2

TIM2_CR1

TIM2_CR2

TIM2_SMCR

TIM2_ETR

TIM2_DER

TIM2_IER

TIM2_SR1

TIM2_SR2

TIM2_EGR

TIM2_CCMR1

TIM2_CCMR2

TIM2_CCER1

TIM2_CNTRH

TIM2_CNTRL

TIM2_PSCR

TIM2_ARRH

TIM2_ARRL

TIM2_CCR1H

TIM2_CCR1L

TIM2_CCR2H

TIM2_CCR2L

TIM2_BKR

TIM2_OISR

TIM2 control register 1

TIM2 control register 2

TIM2 Slave mode control register

TIM2 external trigger register

TIM2 DMA1 request enable register

TIM2 interrupt enable register

TIM2 status register 1

TIM2 status register 2

TIM2 event generation register

TIM2 capture/compare mode register 1

TIM2 capture/compare mode register 2

TIM2 capture/compare enable register 1

TIM2 counter high

TIM2 counter low

TIM2 prescaler register

TIM2 auto-reload register high

TIM2 auto-reload register low

TIM2 capture/compare register 1 high

TIM2 capture/compare register 1 low

TIM2 capture/compare register 2 high

TIM2 capture/compare register 2 low

TIM2 break register

TIM2 output idle state register

Reset status

0x00

0xFF

0x00

Reserved area (25 byte)

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DS7204 Rev 11

Address

0x00 528F

0x00 5290

0x00 5291

0x00 5292

0x00 5293

0x00 5294

0x00 5295

0x00 5296

0x00 5297 to

0x00 52DF

0x00 5280

0x00 5281

0x00 5282

0x00 5283

0x00 5284

0x00 5285

0x00 5286

0x00 5287

0x00 5288

0x00 5289

0x00 528A

0x00 528B

0x00 528C

0x00 528D

0x00 528E

STM8L151x2, STM8L151x3 Memory and register map

Table 8. General hardware register map (continued)

Block Register label Register name

TIM3

TIM3_CR1

TIM3_CR2

TIM3_SMCR

TIM3_ETR

TIM3_DER

TIM3_IER

TIM3_SR1

TIM3_SR2

TIM3_EGR

TIM3_CCMR1

TIM3_CCMR2

TIM3_CCER1

TIM3_CNTRH

TIM3_CNTRL

TIM3_PSCR

TIM3_ARRH

TIM3_ARRL

TIM3_CCR1H

TIM3_CCR1L

TIM3_CCR2H

TIM3_CCR2L

TIM3_BKR

TIM3_OISR

TIM3 control register 1

TIM3 control register 2

TIM3 Slave mode control register

TIM3 external trigger register

TIM3 DMA1 request enable register

TIM3 interrupt enable register

TIM3 status register 1

TIM3 status register 2

TIM3 event generation register

TIM3 Capture/Compare mode register 1

TIM3 Capture/Compare mode register 2

TIM3 Capture/Compare enable register 1

TIM3 counter high

TIM3 counter low

TIM3 prescaler register

TIM3 Auto-reload register high

TIM3 Auto-reload register low

TIM3 Capture/Compare register 1 high

TIM3 Capture/Compare register 1 low

TIM3 Capture/Compare register 2 high

TIM3 Capture/Compare register 2 low

TIM3 break register

TIM3 output idle state register

Reset status

0x00

0xFF

0x00

Reserved area (72 byte)

DS7204 Rev 11

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Address

0x00 52E0

0x00 52E1

0x00 52E2

0x00 52E3

0x00 52E4

0x00 52E5

0x00 52E6

0x00 52E7

0x00 52E8

0x00 52E9

0x00 52EA to

0x00 52FE

0x00 52FF

0x00 5317 to

0x00 533F

0x00 5340

0x00 5341

0x00 5342

0x00 5343

0x00 5344

0x00 5345

0x00 5346

0x00 5347

0x00 5348

0x00 5349

0x00 534A

0x00 534B

0x00 534C

0x00 534D

0x00 534E

0x00 534F

0x00 5350

0x00 5351

Memory and register map STM8L151x2, STM8L151x3

Table 8. General hardware register map (continued)

Block Register label Register name

TIM4

TIM4_CR1

TIM4_CR2

TIM4_SMCR

TIM4_DER

TIM4_IER

TIM4_SR1

TIM4_EGR

TIM4_CNTR

TIM4_PSCR

TIM4_ARR

TIM4 control register 1

TIM4 control register 2

TIM4 Slave mode control register

TIM4 DMA1 request enable register

TIM4 Interrupt enable register

TIM4 status register 1

TIM4 Event generation register

TIM4 counter

TIM4 prescaler register

TIM4 Auto-reload register

IRTIM

ADC1

IR_CR

Reserved area (21 byte)

Infrared control register

ADC1_CR1

ADC1_CR2

ADC1_CR3

ADC1_SR

ADC1_DRH

ADC1_DRL

ADC1_HTRH

ADC1_HTRL

ADC1_LTRH

ADC1_LTRL

ADC1_SQR1

ADC1_SQR2

ADC1_SQR3

ADC1_SQR4

ADC1_TRIGR1

ADC1_TRIGR2

ADC1_TRIGR3

ADC1_TRIGR4

Reserved area (41 byte)

ADC1 configuration register 1

ADC1 configuration register 2

ADC1 configuration register 3

ADC1 status register

ADC1 data register high

ADC1 data register low

ADC1 high threshold register high

ADC1 high threshold register low

ADC1 low threshold register high

ADC1 low threshold register low

ADC1 channel sequence 1 register

ADC1 channel sequence 2 register

ADC1 channel sequence 3 register

ADC1 channel sequence 4 register

ADC1 trigger disable 1

ADC1 trigger disable 2

ADC1 trigger disable 3

ADC1 trigger disable 4

0x00

0x1F

0x00

0x0F

0xFF

0x00

Reset status

0x00

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Memory and register map

Address

Table 8. General hardware register map (continued)

Block Register label Register name

0x00 53C8 to

0x00 542F

0x00 5430

0x00 5431

0x00 5432

0x00 5433

0x00 5434

0x00 5435

0x00 5436

0x00 5437

0x00 5438

0x00 5439

0x00 543A

0x00 543B

Reserved area (104 byte)

RI_ICR1

RI_ICR2

RI_IOIR1

RI_IOIR2

RI_IOIR3

RI_IOCMR1

RI_IOCMR2

RI_IOCMR3

RI_IOSR1

RI_IOSR2

RI_IOSR3

Reserved area (1 byte)

RI timer input capture routing register 1

RI timer input capture routing register 2

RI I/O input register 1

RI I/O input register 2

RI I/O input register 3

RI I/O control mode register 1

RI I/O control mode register 2

RI I/O control mode register 3

RI I/O switch register 1

RI I/O switch register 2

RI I/O switch register 3

0x00 543C

0x00 543D

0x00 543E

0x00 543F

0x00 5440

0x00 5441

0x00 5442

0x00 5443

RI_IOGCR

RI_ASCR1

RI_ASCR2

RI_RCR

COMP_CSR1

COMP_CSR2

RI I/O group control register

RI analog switch register 1

RI analog switch register 2

RI resistor control register

Comparator control and status register 1

Comparator control and status register 2

COMP1/

COMP2

COMP_CSR3

COMP_CSR4

COMP_CSR5

Comparator control and status register 3

Comparator control and status register 4

Comparator control and status register 5 0x00 5444

0x00 5445 to

0x00 544F

0x00 5450

0x00 5451

0x00 5452

RI_CR

RI_MASKR1

RI_MASKR2

Reserved area (11 byte)

RI I/O control register

RI I/O mask register 1

RI I/O mask register 2

0x00 5453

0x00 5454

0x00 5455

0x00 5456

0x00 5457

RI_MASKR3

RI_MASKR4

RI_IOIR4

RI_IOCMR4

RI_IOSR4

RI I/O mask register 3

RI I/O mask register 4

RI I/O input register 4

RI I/O control mode register 4

RI I/O switch register 4

For device in 20-pin packages

These registers are not impacted by a system reset. They are reset at power-on.

Reset status

0x00

0xXX

0x00

0xFF

0x00

0xXX

0x00

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Memory and register map STM8L151x2, STM8L151x3

Address

Table 9. CPU/SWIM/debug module/interrupt controller registers

Block Register Label Register Name

0x00 7F60

0x00 7F70

0x00 7F71

0x00 7F72

0x00 7F73

0x00 7F74

0x00 7F75

0x00 7F76

0x00 7F77

0x00 7F78 to

0x00 7F79

0x00 7F80

0x00 7F81 to

0x00 7F8F

0x00 7F00

0x00 7F01

0x00 7F02

0x00 7F03

0x00 7F04

0x00 7F05

0x00 7F06

0x00 7F07

0x00 7F08

0x00 7F09

0x00 7F0A

0x00 7F0B to

0x00 7F5F

CPU

(1)

CPU

ITC-SPR

SWIM

CFG_GCR

ITC_SPR1

ITC_SPR2

ITC_SPR3

ITC_SPR4

ITC_SPR5

ITC_SPR6

ITC_SPR7

ITC_SPR8

PCE

PCH

PCL

SPH

SPL

CCR

SWIM_CSR

Accumulator

Program counter extended

Program counter high

Program counter low

X index register high

X index register low

Y index register high

Y index register low

Stack pointer high

Stack pointer low

Condition code register

Reserved area (85 byte)

Global configuration register

Interrupt Software priority register 1

Interrupt Software priority register 2

Interrupt Software priority register 3

Interrupt Software priority register 4

Interrupt Software priority register 5

Interrupt Software priority register 6

Interrupt Software priority register 7

Interrupt Software priority register 8

Reserved area (2 byte)

SWIM control status register

Reserved area (15 byte)

0x00

0xFF

Reset

Status

0x00

0x03

0xFF

0x28

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Memory and register map

Address

Table 9. CPU/SWIM/debug module/interrupt controller registers (continued)

Block Register Label Register Name

0x00 7F90

0x00 7F91

0x00 7F92

0x00 7F93

0x00 7F94

0x00 7F95

0x00 7F96

0x00 7F97

0x00 7F98

0x00 7F99

0x00 7F9A

0x00 7F9B to

0x00 7F9F

Accessible by debug module only

DM_BK1RE

DM_BK1RH

DM_BK1RL

DM_BK2RE

DM_BK2RH

DM_BK2RL

DM_CR1

DM_CR2

DM_CSR1

DM_CSR2

DM_ENFCTR

DM breakpoint 1 register extended byte

DM breakpoint 1 register high byte

DM breakpoint 1 register low byte

DM breakpoint 2 register extended byte

DM breakpoint 2 register high byte

DM breakpoint 2 register low byte

DM Debug module control register 1

DM Debug module control register 2

DM Debug module control/status register 1

DM Debug module control/status register 2

DM enable function register

Reserved area (5 byte)

Reset

Status

0xFF

0x00

0x10

0x00

0xFF

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Interrupt vector mapping

6 Interrupt vector mapping

STM8L151x2, STM8L151x3

IRQ

No.

Source block

Description

Table 10. Interrupt mapping

Wakeup from Halt mode

Wakeup from

Active-halt mode

Wakeup from Wait

(WFI mode)

Wakeup from Wait

(WFE mode)

(1)

RESET Reset

TRAP

TLI

(2)

Software interrupt

FLASH

External top level interrupt

FLASH end of programing/ write attempted to protected page interrupt

DMA1 0/1

DMA1 channels 0/1 half transaction/transaction complete interrupt

DMA1 2/3

RTC

EXTIE/

PVD

EXTIB

DMA1 channels 2/3 half transaction/transaction complete interrupt

RTC alarm A/ wakeup/tamper 1/ tamper 2/tamper 3

External interrupt port E

PVD interrupt

External interrupt port B

EXTID

EXTI0

EXTI1

EXTI2

EXTI3

EXTI4

EXTI5

EXTI6

EXTI7

External interrupt port D

External interrupt 0

External interrupt 1

External interrupt 2

External interrupt 3

External interrupt 4

External interrupt 5

External interrupt 6

External interrupt 7

Yes

Reserved

CLK

CLK system clock switch/

CSS interrupt -

Yes

Vector address

0x00 8000

0x00 8004

0x00 8008

0x00 800C

0x00 8010

0x00 8014

0x00 8018

0x00 801C

0x00 8020

0x00 8024

0x00 8028

0x00 802C

0x00 8030

0x00 8034

0x00 8038

0x00 803C

0x00 8040

0x00 8044

0x00 8048

0x00 804C

COMP1/

COMP2/

ADC1

COMP1 interrupt

COMP2 interrupt

ACD1 end of conversion/ analog watchdog/ overrun interrupt

Yes Yes Yes Yes 0x00 8050

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Interrupt vector mapping

IRQ

No.

Source block

Table 10. Interrupt mapping (continued)

Description

Wakeup from Halt mode

Wakeup from

Active-halt mode

Wakeup from Wait

(WFI mode)

Wakeup from Wait

(WFE mode)

(1)

Vector address

TIM2

TIM3

TIM2 update/overflow/ trigger/break interrupt

TIM2 capture/ compare interrupt

TIM3 update/overflow/ trigger/break interrupt

TIM3 capture/ compare interrupt

RI trigger interrupt

Yes

0x00 8054

0x00 8058

0x00 805C

0x00 8060

RI -

Reserved

Yes 0x00 8064

0x00 8068

TIM4

SPI1

USART1

TIM4 update/overflow/ trigger interrupt

SPI1 TX buffer empty/

RX buffer not empty/ error/wakeup interrupt

USART1 transmit data register empty/ transmission complete interrupt

USART1 received data ready/overrun error/ idle line detected/parity error/global error interrupt

C1 interrupt

(3)

Yes

0x00 806C

0x00 8070

0x00 8074

0x00 8078

29 I

C1 Yes Yes Yes Yes 0x00 807C

The Low power wait mode is entered when executing a WFE instruction in Low power run mode. In WFE mode, the interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode.

When the interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.

The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts.

The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.

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Option bytes STM8L151x2, STM8L151x3

Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated memory block.

All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM

address. See Table 11

for details on option byte addresses.

The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for the ROP and UBC values which can only be taken into account when they are modified in

ICP mode (with the SWIM).

Refer to the STM8L15x Flash programming manual (PM0054) and STM8 SWIM and Debug

Manual (UM0470) for information on SWIM programming procedures.

Addr.

Option name

Option byte

No.

Table 11. Option byte addresses

Option bits

7 6 5 4 3

0x00 4800

Read-out protection

(ROP)

0x00 4802

UBC (User

Boot code size)

0x00 4807

0x00 4808

Independent watchdog option

0x00 4809

Number of stabilization clock cycles for

HSE and LSE oscillators

OPT0

OPT1

OPT3

[3:0]

OPT4

0x00 480A

Brownout reset

(BOR)

0x00 480B

0x00 480C

Bootloader option bytes

(OPTBL)

OPT5

[3:0]

OPTBL

[15:0]

Reserved

ROP[7:0]

UBC[7:0]

WWDG

_HALT

WWDG

_HW

IWDG

_HALT

IWDG

_HW

LSECNT[1:0]

BOR_TH

OPTBL[15:0]

1 0

HSECNT[1:0]

BOR_

Factory default setting

0xAA

0x00

0x01

0x00

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Option bytes

Table 12. Option byte description

Option byte

No.

Option description

OPT0

OPT1

ROP[7:0] Memory readout protection (ROP)

0xAA: Disable readout protection (write access via SWIM protocol)

Refer to Readout protection section in the STM8L15x and STM8L16x reference manual (RM0031).

UBC[7:0] Size of the user boot code area

0x00: UBC is not protected.

0x01: Page 0 is write protected.

0x02: Page 0 and 1 reserved for the UBC and write protected. It covers only the interrupt vectors.

0x03: Page 0 to 2 reserved for UBC and write protected.

0x7F to 0xFF - All 128 pages reserved for UBC and write protected.

The protection of the memory area not protected by the UBC is enabled through the MASS keys.

Refer to User boot code section in the STM8L15x and STM8L16x reference manual (RM0031).

OPT2 Reserved

IWDG_HW: Independent watchdog

0: Independent watchdog activated by software

1: Independent watchdog activated by hardware

OPT3

IWDG_HALT: Independent window watchdog off on Halt/Active-halt

0: Independent watchdog continues running in Halt/Active-halt mode

1: Independent watchdog stopped in Halt/Active-halt mode

WWDG_HW: Window watchdog

0: Window watchdog activated by software

1: Window watchdog activated by hardware

OPT4

WWDG_HALT: Window window watchdog reset on Halt/Active-halt

0: Window watchdog stopped in Halt mode

1: Window watchdog generates a reset when MCU enters Halt mode

HSECNT : Number of HSE oscillator stabilization clock cycles

0x00 - 1 clock cycle

0x01 - 16 clock cycles

0x10 - 512 clock cycles

0x11 - 4096 clock cycles

LSECNT : Number of LSE oscillator stabilization clock cycles

0x00 - 1 clock cycle

0x01 - 16 clock cycles

0x10 - 512 clock cycles

0x11 - 4096 clock cycles

Refer to

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Option bytes STM8L151x2, STM8L151x3

Table 12. Option byte description (continued)

Option byte

No.

Option description

OPT5

OPTBL

BOR_ON :

0: Brownout reset off

1: Brownout reset on

BOR_TH[3:1]

: Brownout reset thresholds. Refer to Table 22

for details on the thresholds according to the value of BOR_TH bits.

OPTBL[15:0] :

This option is checked by the boot ROM code after reset. Depending on content of addresses 00 480B, 00 480C and 0x8000 (reset vector) the

CPU jumps to the bootloader or to the reset vector.

Refer to the UM0560 bootloader user manual for more details.

52/123

DS7204 Rev 11

STM8L151x2, STM8L151x3 Unique ID

STM8 devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user.

The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.

The unique device identifier is ideally suited:

• For use as serial numbers

• For use as security keys to increase the code security in the program memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal memory.

• To activate secure boot processes

0x4926

0x4927

0x4928

0x4929

0x492A

0x492B

0x492C

0x492D

0x492E

0x492F

0x4930

0x4931

Address

Content description

Table 13. Unique ID registers (96 bits)

Unique ID bits

7 6 5 4 3

X co-ordinate on the wafer

Y co-ordinate on the wafer

Wafer number

Lot number

U_ID[7:0]

U_ID[15:8]

U_ID[23:16]

U_ID[31:24]

U_ID[39:32]

U_ID[47:40]

U_ID[55:48]

U_ID[63:56]

U_ID[71:64]

U_ID[79:72]

U_ID[87:80]

U_ID[95:88]

2 1 0

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Electrical parameters STM8L151x2, STM8L151x3

9.1.1

Unless otherwise specified, all voltages are referred to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

= 25 °C and T

= T

A max (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics is indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3

Unless otherwise specified, typical data is based on T

= 25 °C, V design guidelines and is not tested.

= 3 V. It is given only as

Typical ADC1 accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 Σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 9

Figure 9. Pin loading conditions

STM8AL PIN

50 pF

MSv37774V1

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DS7204 Rev 11

STM8L151x2, STM8L151x3

9.1.5

Electrical parameters

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 10 .

Figure 10. Pin input voltage

STM8S PIN

MSv37775V1

9.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 14: Voltage characteristics

Table 15: Current characteristics

, and

Table 16: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Device mission profile (application conditions) is compliant with JEDEC JESD47

Qualification Standard, extended mission profiles are available on demand.

Symbol

Table 14. Voltage characteristics

Ratings Min Max Unit

- V

(2)

ESD

External supply voltage (including V

DDA

, and V

DDIO

)

(1)

Input voltage on true open-drain pins

(PC0 and PC1)

Input voltage on any other pin

Electrostatic discharge voltage

- 0.3

4.0

+ 4.0

- 0.3

4.0

see Absolute maximum ratings (electrical sensitivity) on page 102

All power (V

, V

DDA

, V external power supply.

DDIO

) and ground (V

, V

SSA

, V

SSIO

) pins must always be connected to the

maximum must always be respected. Refer to

Table 15.

for maximum allowed injected current values.

DS7204 Rev 11

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102

Electrical parameters STM8L151x2, STM8L151x3

Symbol

Table 15. Current characteristics

Ratings Max.

Unit

VDD

VSS

Total current into V

DD power line (source)

Total current out of V

SS ground line (sink)

Output current sunk by IR_TIM pin (with high sink LED driver capability)

Output current sunk by any other I/O and control pin

80 mA

Output current sourced by any I/Os and control pin

Injected current on true open-drain pins (PC0 and PC1)

Injected current on 3.6 V tolerant pins

for maximum allowed input voltage values.

- 25

- 5 / +0

INJ(PIN)

- 5 / +0 mA

Σ I

INJ(PIN)

Injected current on any other pin

(1)

Total injected current (sum of all I/O and control pins)

(2)

- 5 / +5

± 25 mA

A positive injection is induced by V

while a negative injection is induced by V

IN never be exceeded. Refer to

Table 14.

. I

INJ(PIN)

must

When several inputs are submitted to a current injection, the maximum Σ I positive and negative injected currents (instantaneous values).

INJ(PIN)

is the absolute sum of the

Symbol

STG

Table 16. Thermal characteristics

Ratings Value

Storage temperature range

Maximum junction temperature

-65 to +150

150

Unit

° C

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

Subject to general operating conditions for V

and T

9.3.1 General operating conditions

Symbol Parameter

Table 17. General operating conditions

Conditions Min.

Max.

Unit f

SYSCLK

(1)

DDA

(3)

System clock frequency

Standard operating voltage

1.65 V ≤ V

< 3.6 V 0

1.65

(2)

Analog operating voltage

Power dissipation at

= 85 °C for suffix 3 and suffix 6 devices

Power dissipation at

= 125 °C for suffix 3 devices

Temperature range

Junction temperature range

ADC1 not used

ADC1 used

Must be at the same potential as V

1.65

LQFP48

UFQFPN32

UFQFPN28 -

UFQFPN20 -

TSSOP20 -

1.8

LQFP48

UFQFPN32

UFQFPN28 -

UFQFPN20

TSSOP20

1.65 V ≤ V

< 3.6 V (6 suffix version)

1.65 V ≤ V

< 3.6 V (3 suffix version)

-40 °C ≤ T

< 85 °C

(6 suffix version)

-40 °C

≤

125 °C

(3 suffix version)

-40

3.6

105

(4)

130

MHz

V mW

°C

SYSCLK

= f

CPU

1.8 V at power-up, 1.65 V at power-down if BOR is disabled

To calculate P

Dmax table.

), use the formula P

Dmax

=(T

Jmax

-T

with T

Jmax

in this table and

JA in “Thermal characteristics”

max is given by the test limit. Above this value, the product behavior is not guaranteed.

185

125

3.6

288

250

196

181

DS7204 Rev 11

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102

Electrical parameters STM8L151x2, STM8L151x3

9.3.2 Embedded reset and power control block characteristics

Table 18. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max t

V t

VDD

TEMP

PDR

BOR0

BOR1

BOR2

BOR3

BOR4

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6

rise time rate

fall time rate

BOR detector enabled

Reset release delay V

rising

Power-down reset threshold Falling edge

Brown-out reset threshold 0

(BOR_TH[2:0]=000)

Brown-out reset threshold 1

(BOR_TH[2:0]=001)

Falling edge

Rising edge

Falling edge

Rising edge

Brown-out reset threshold 2

(BOR_TH[2:0]=010)

Brown-out reset threshold 3

(BOR_TH[2:0]=011)

Brown-out reset threshold 4

(BOR_TH[2:0]=100)

PVD threshold 0

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Guaranteed by design.

Guaranteed by characterization results.

(1)

1.82

1.89

2.04

2.12

2.50

2.59

2.74

2.83

1.30

(2)

1.66

1.69

1.89

1.98

2.25

2.35

2.61

2.71

2.79

2.90

2.21

2.31

2.41

2.51

3.01

3.12

∞

∞

1.85

1.94

2.05

2.14

2.55

2.65

2.79

2.89

1.50

1.70

1.75

1.93

2.03

2.30

2.40

2.64

2.74

2.83

2.94

2.24

2.33

2.44

2.53

3.04

3.15

Unit

µs/V

2.69

2.79

2.88

2.99

2.28

2.37

2.48

2.57

3.09

3.20

1.88

1.97

2.08

2.17

2.60

2.70

2.85

2.95

1.65 V

1.74

1.81

1.97

2.07

2.35

2.44

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DS7204 Rev 11

STM8L151x2, STM8L151x3

3.6 V

1.8 V

BOR threshold

Electrical parameters

Figure 11. POR/BOR thresholds

DD without BOR = battery life extension

Operatin g power supply

BOR threshold_0

PDR threshold

VBOR0

VPDR

9.3.3

Internal NRST

BOR always active at power up with

BOR with

BOR without

BOR

BOR activated by user for power-down detection

Time ai17033b

Supply current characteristics

Total current consumption

The MCU is placed under the following conditions: l All I/O pins in input mode with a static value at V

or V

(no load) l All peripherals are disabled except if explicitly mentioned.

In the following table, data is based on characterization results, unless otherwise specified.

Subject to general operating conditions for V

and T

DS7204 Rev 11

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102

Electrical parameters STM8L151x2, STM8L151x3

Symbol

Para meter

Table 19. Total current consumption in Run mode

Conditions

(1) Typ

Max

55 °C 85 °C 105°C

(2)

125 °C

(2)

Unit f

CPU

= 125 kHz 0.39

0.47

0.49

LSE external clock

(32.768 kHz) f

CPU

= f

LSE

0.035 0.040 0.048

0.52

CPU

= 1 MHz 0.48

0.56

0.58

HSI RC osc.

(16 MHz)

(4) f

CPU

= 4 MHz 0.75

0.84

0.86

CPU

= 8 MHz 1.10

1.20

1.25

DD(RUN)

Supply current in run mode

(3)

All peripherals

OFF, code executed from RAM,

from

1.65 V to

3.6 V

HSE external clock

CPU

HSE

)

(5) f

CPU

= 1 MHz f

CPU

= 4 MHz f

CPU

= 8 MHz f f f

CPU

= 16 MHz 1.85

1.93

2.12

= 125 kHz 0.05

0.18

0.55

0.99

0.06

0.19

0.62

1.20

0.09

0.20

0.64

1.21

= 16 MHz 1.90

2.22

2.23

LSI RC osc.

(typ. 38 kHz) f

CPU

= f

LSI

0.040 0.045

0.046

0.61

0.91

1.31

2.29

0.11

0.22

0.71

1.22

2.24

0.048

0.050

HSI RC osc.

(7) f

CPU

= 125 kHz 0.43

0.55

0.56

CPU

= 1 MHz 0.60

0.77

0.80

CPU

= 4 MHz f

CPU

= 8 MHz

1.11

1.90

1.34

2.20

1.37

2.23

DD(RUN)

Supply current in Run mode

All peripherals

OFF, code executed from Flash,

from

1.65 V to

3.6 V f f

CPU

= 16 MHz

= 125 kHz

HSE external clock

CPU

HSE

)

CPU

= 1 MHz f

CPU

= 4 MHz f

CPU

= 8 MHz

3.8

0.30

0.40

1.15

2.17

4.60

0.36

0.50

1.31

2.33

4.75

0.39

0.52

1.40

2.44

CPU

= 16 MHz 4.0

4.46

4.52

LSI RC osc.

CPU

= f

LSI

LSE ext. clock

(32.768 kHz)

(8) f

CPU

= f

LSE

0.110 0.123

0.100 0.101

0.130

0.104

0.58

0.82

1.39

2.31

4.87

0.44

0.55

1.45

2.56

4.59

0.140

0.119

All peripherals OFF, V

from 1.65 V to 3.6 V, HSI internal RC osc., f

CPU

SYSCLK

For devices with suffix 3

CPU executing typical data processing

0.55

0.65

0.99

1.40

2.36

0.12

0.23

0.77

1.24

2.28

) must be added. Refer to Table 30 .

0.050

0.062

0.122

mA mA

4.88

0.47

0.56

1.48

0.62

0.87

1.43

2.40

2.77

4.77

0.150

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

The run from RAM consumption can be approximated with the linear formula:

(run_from_RAM) = Freq * 90 µA/MHz + 380 µA

Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption

DD HSE

Tested in production.

The run from Flash consumption can be approximated with the linear formula:

(run_from_Flash) = Freq * 195 µA/MHz + 440 µA

Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption

DD LSE

3.00

Figure 12. Typ. I

DD(RUN)

vs. V

, f

CPU

= 16 MHz

2.75

-40°C

25°C

85°C

2.50

2.25

2.00

1.75

1.50

1.8

2.1

2.6

[V]

3.1

3.6

ai18213b

Typical current consumption measured with code executed from RAM

DS7204 Rev 11

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102

Electrical parameters STM8L151x2, STM8L151x3

In the following table, data is based on characterization results, unless otherwise specified.

Symbol Parameter

Table 20. Total current consumption in Wait mode

Conditions

(1) Typ

Max

55°C 85 °C

105 °C

(2)

125 °C

(2)

Unit f

CPU

= 125 kHz 0.33

0.39

0.41

0.43

0.45

CPU

= 1 MHz 0.35

0.41

0.44

0.45

0.48

CPU

= 4 MHz 0.42

0.51

0.52

0.54

0.58

HSI f

CPU

= 8 MHz 0.52

0.57

0.58

0.59

0.62

DD(Wait)

Supply current in

Wait mode

CPU not clocked, all peripherals

OFF, code executed from RAM with Flash in

DDQ

mode

(3)

from

1.65 V to 3.6 V

HSE external clock

CPU

HSE

)

(4) f

CPU

= 1 MHz 0.078 0.121 0.144

0.163

0.197

CPU

= 4 MHz 0.218

0.26

0.30

0.36

0.40

CPU

= 8 MHz 0.40

0.52

0.57

0.62

0.66

f f f

CPU

= 16 MHz 0.68

0.76

0.79

0.82

= 125 kHz 0.032 0.056 0.068 0.072

= 16 MHz 0.760 1.01

1.05

1.09

(5)

0.85

0.093

1.16

LSI f

CPU

= f

LSI

0.035 0.044 0.046

0.049

0.054

LSE

external clock

(32.768 kHz) f

CPU

= f

LSE

0.032 0.036 0.038

0.044

0.051

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

Symbol Parameter

Table 20. Total current consumption in Wait mode (continued)

Conditions

(1) Typ

Max

55°C 85 °C

105 °C

(2)

125 °C

(2)

Unit f

CPU

= 125 kHz 0.38

0.48

0.49

0.50

0.56

DD(Wait)

Supply current in

Wait mode

CPU not clocked, all peripherals

OFF, code executed from Flash,

from

1.65 V to 3.6 V

HSI

HSE

LSI

) must be added. Refer to Table 30 .

external clock

CPU

=HSE) f

CPU

= 1 MHz 0.41

0.49

0.51

0.53

0.59

CPU

= 4 MHz 0.50

0.57

0.58

0.62

0.66

CPU

= 8 MHz 0.60

0.66

0.68

0.72

0.74

CPU

= 16 MHz 0.79

0.84

0.86

0.87

0.90

CPU

= 125 kHz 0.06

0.08

0.09

0.10

0.12

CPU

= 1 MHz 0.10

0.17

0.18

0.19

0.22

CPU

= 4 MHz 0.24

0.36

0.39

0.41

0.44

CPU

= 8 MHz 0.50

0.58

0.61

0.62

0.64

CPU

= 16 MHz 1.00

1.08

1.14

1.16

1.18

CPU

= f

LSI

0.055 0.058 0.065

0.073

0.080

LSE

(6) external clock

(32.768 kHz) f

CPU

= f

LSE

0.051 0.056 0.060

0.065

0.073

All peripherals OFF, V

from 1.65 V to 3.6 V, HSI internal RC osc., f

CPU

= f

SYSCLK

For temperature range 3.

Flash is configured in I

DDQ

mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register.

Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption

DD HSE

Tested in production.

Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption

DD HSE

) must be added. Refer to Table 31 .

DS7204 Rev 11

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102

Electrical parameters STM8L151x2, STM8L151x3

Figure 13. Typ. I

DD(Wait) vs. V

, f

CPU

= 16 MHz 1)

750

700

650

600

550

500

1000

950

900

850

800

1.8

2.1

2.6

[V]

3.1

Typical current consumption measured with code executed from Flash memory.

-40°C

25°C

85°C

3.6

ai18214b

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

In the following table, data is based on characterization results, unless otherwise specified.

Symbol

Table 21. Total current consumption and timing in Low power run mode

at V

= 1.65 V to 3.6 V

Parameter Conditions

(1)(2) Typ Max Unit

LSI RC osc.

(at 38 kHz) all peripherals OFF

= -40 °C to 25 °C

5.1

= 55 °C 5.7

= 85 °C 6.8

= 105 °C 9.2

= 125 °C 13.4

= -40 °C to 25 °C

5.4

5.7

DD(LPR)

Supply current in Low power run mode

LSE

(4) clock

external

(32.768 kHz) with TIM2 active

(3) all peripherals OFF

= 55 °C

= 85 °C

6.0

7.2

= 105 °C 9.4

= 125 °C 13.8

= -40 °C to 25 °C

5.25

= 55 °C 5.67

= 85 °C 5.85

= 105 °C 7.11

= 125 °C 9.84

= -40 °C to 25 °C

5.59

6.3

7.8

10.7

5.6

6.1

6.3

7.6

6 with TIM2 active

= 55 °C

= 85 °C

6.10

6.30

= 105 °C 7.55

= 125 °C 10.1

6.4

8.4

No floating I/Os

> 85 °C is valid only for devices with suffix 3 temperature range.

Timer 2 clock enabled and counter running

Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption

DD LSE

7.5

10.4

16.6

μ A

DS7204 Rev 11

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102

Electrical parameters STM8L151x2, STM8L151x3

Figure 14. Typ. I

DD(LPR) vs. V

(LSI clock source)

-40° C

25° C

85° C

1.8

2.1

2.6

[V]

3.1

3.6

ai18216b

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

In the following table, data is based on characterization results, unless otherwise specified.

Symbol

Table 22. Total current consumption in Low power wait mode at V

= 1.65 V to 3.6 V

Parameter Conditions

(1)(2) Typ Max Unit

DD(LPW)

Supply current in

Low power wait mode

LSI RC osc.

(at 38 kHz)

LSE external clock

(4)

(32.768 kHz) all peripherals OFF with TIM2 active with TIM2 active

(3) all peripherals OFF

= -40 °C to 25 °C 3 3.3

= 55 °C

= 85 °C

= 105 °C

3.3

4.4

6.7

3.6

= 125 °C 11 14

= -40 °C to 25 °C 3.4

3.7

= 55 °C

= 85 °C

= 105 °C

3.7

4.8

5.4

8.3

= 125 °C 11.3 14.5

= -40 °C to 25 °C 2.35

2.7

= 55 °C

= 85 °C

= 105 °C

2.42 2.82

3.10 3.71

4.36

5.7

= 125 °C 7.20

= -40 °C to 25 °C 2.46 2.75

= 55 °C

= 85 °C

= 105 °C

= 125 °C

2.50 2.81

3.16 3.82

4.51

7.28

5.9

No floating I/Os.

> 85 °C is valid only for devices with suffix 3 temperature range.

Timer 2 clock enabled and counter is running.

Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption

DD LSE

μ A

DS7204 Rev 11

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102

Electrical parameters STM8L151x2, STM8L151x3

16.00

14.00

12.00

10.00

8.00

6.00

4.00

2.00

0.00

1.8

Figure 15. Typ. I

DD(LPW) vs. V

(LSI clock source)

2.1

2.6

[V]

3.1

-40°C

25°C

85°C

3.6

ai18217b

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

In the following table, data is based on characterization results, unless otherwise specified.

Table 23. Total current consumption and timing in Active-halt mode at V

= 1.65 V to 3.6 V

Symbol Parameter Conditions

(1)(2) Typ Max Unit

DD(AH)

Supply current in

Active-halt mode

LSI RC (at 38 kHz)

LSE external clock (32.768 kHz)

(3)

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

= 125 °C

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

= 125 °C

DD(WUFAH) t

WU_HSI(AH)

(4)(5)

Supply current during wakeup time from

Active-halt mode

(using HSI)

Wakeup time from

Active-halt mode to

Run mode (using HSI) t

WU_LSI(AH)

Wakeup time from

Active-halt mode to

Run mode (using LSI)

2.4

4.7

150

No floating I/O, unless otherwise specified.

> 85 °C is valid only for devices with suffix 3 temperature range.

Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption

DD LSE

Wakeup time until start of interrupt vector fetch.

The first word of interrupt routine is fetched 4 CPU cycles after t

ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.

0.9

2.1

1.2

1.5

3.4

2.6

6.6

5.1

0.5

1.2

0.62

1.4

0.88

2.1

4.85

4.8

μ A mA

μ s

Table 24. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal

Symbol Parameter Condition

(1)

Typ Unit

DD(AH)

(2)

Supply current in Active-halt mode

= 1.8 V

= 3 V

= 3.6 V

LSE

LSE/32

(3)

LSE

LSE/32

LSE

LSE/32

1.15

1.05

1.30

1.20

1.45

1.35

µA

No floating I/O, unless otherwise specified.

Based on measurements on bench with 32.768 kHz external crystal oscillator.

RTC clock is LSE divided by 32.

DS7204 Rev 11

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102

Electrical parameters STM8L151x2, STM8L151x3

In the following table, data is based on characterization results, unless otherwise specified.

Table 25. Total current consumption and timing in Halt mode at V

= 1.65 to 3.6 V

Symbol Parameter Condition

(1)(2)

Typ Max Unit t t

DD(Halt)

DD(WUHalt)

WU_HSI(Halt)

(4)(5)

WU_LSI(Halt)

(4)(5)

= -40 °C to 25 °C

Supply current in Halt mode

(Ultra-low-power ULP bit =1 in the PWR_CSR2 register )

= 55 °C

= 85 °C

= 105 °C

= 125 °C

Supply current during wakeup time from Halt mode (using

HSI)

Wakeup time from Halt to Run mode (using HSI)

Wakeup time from Halt mode to Run mode (using LSI)

= -40 to 125 °C, no floating I/O, unless otherwise specified.

> 85 °C is valid only for devices with suffix 3 temperature range.

Tested in production.

ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.

Wakeup time until start of interrupt vector fetch.

The first word of interrupt routine is fetched 4 CPU cycles after t

350

580

1160

2560

4.4

2.4

4.7

150

1400

(3)

2000

2800

6700

µA mA

µs

70/123

DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

Current consumption of on-chip peripherals

Table 26. Peripheral current consumption

Symbol Parameter

Typ.

= 3.0 V

Unit

DD(TIM2)

DD(TIM3)

DD(TIM4)

DD(USART1)

DD(SPI1)

TIM2 supply current

(1)

TIM3 supply current

TIM4 timer supply current

USART1 supply current

SPI1 supply current

µA/MHz

DD(I2C1)

DD(DMA1)

DD(WWDG)

DD(ALL)

DMA1 supply current

Peripherals ON

(3)

ADC1 supply current

(4)

Comparator 1 supply current

(5)

38 µA/MHz

DD(ADC1)

DD(COMP1)

1500

0.160

µA

DD(COMP2)

DD(PVD/BOR)

DD(BOR)

DD(IDWDG)

Comparator 2 supply current

Brownout Reset unit supply current

Slow mode

Fast mode

Power voltage detector and brownout Reset unit supply current

(6)

Independent watchdog supply current including LSI supply current excluding LSI supply current

2.6

2.4

0.45

0.05

µA

Data based on a differential I

measurement between all peripherals OFF and a timer counter running at 16 MHz. The

CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.

Data based on a differential I

measurement between the on-chip peripheral in reset configuration and not clocked and the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling.

Not tested in production.

Peripherals listed above the I

DD(ALL)

parameter ON: TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.

Data based on a differential I

measurement between ADC1 in reset configuration and continuous ADC1 conversion.

Data based on a differential I

measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2 enabled with static inputs. Supply current of internal reference voltage excluded.

Including supply current of internal reference voltage.

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102

Electrical parameters STM8L151x2, STM8L151x3

Symbol

Table 27. Current consumption under external reset

Parameter Conditions Typ Unit

DD(RST)

Supply current under external reset

(1)

All pins are externally tied to V

= 1.8 V

= 3 V

= 3.6 V

All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.

µA

9.3.4 Clock and timing characteristics

HSE external clock (HSEBYP = 1 in CLK_ECKCR)

Subject to general operating conditions for V

and T

Symbol

Table 28. HSE external clock characteristics

Parameter Conditions Min f

HSE_ext

HSEH

HSEL in(HSE)

External clock source frequency

(1)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN input

capacitance

LEAK_HSE

OSC_IN input leakage current

< V

0.7 x V

Guaranteed by design.

Typ

2.6

Max

0.3 x V

±1

Unit

MHz

V pF

µA

LSE external clock (LSEBYP=1 in CLK_ECKCR)

Subject to general operating conditions for V

and T

Symbol

Table 29. LSE external clock characteristics

Parameter f

LSE_ext

LSEH

(2)

LSEL

C in(LSE)

External clock source frequency

(1)

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

OSC32_IN input capacitance

LEAK_LSE

OSC32_IN input leakage current

Guaranteed by design.

Guaranteed by characterization results.

Min

0.7 x V

Typ

32.768

0.6

Max

0.3 x V

±1

Unit kHz

V pF

µA

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DS7204 Rev 11

STM8L151x2, STM8L151x3

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

Symbol

Table 30. HSE oscillator characteristics

Parameter Conditions Min Typ Max Unit f

HSE

High speed external oscillator frequency

Feedback resistor

1 16 MHz

(1)

Recommended load capacitance

(2)

200

k Ω pF

DD(HSE)

HSE oscillator power consumption

C = 20 pF, f

OSC

= 16 MHz

C = 10 pF, f

OSC

=16 MHz

2.5 (startup)

0.7 (stabilized)

2.5 (startup)

0.46 (stabilized)

(3)

mA g m t

SU(HSE)

(4)

Oscillator transconductance

Startup time V

is stabilized

3.5

mA/V

C= C

= C

is approximately equivalent to 2 x crystal C

LOAD

The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R m

Refer to crystal manufacturer for more details

value.

Guaranteed by design.

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Figure 16. HSE oscillator circuit diagram

Resonator

OSCIN

F gm

Electrical parameters f

HSE

to core

Consumption control

Resonator

OSCOUT

STM8

MS36490V3

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102

Electrical parameters STM8L151x2, STM8L151x3

HSE oscillator critical g m

formula g mcrit

= ( 2 × Π × f

HSE

) 2 × R m

( 2Co + C )

R m

C m

: Motional resistance (see crystal specification), L

L2 g m

>> g mcrit m

: Motional inductance (see crystal specification),

: Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),

=C: Grounded external capacitance

LSE crystal/ceramic resonator oscillator

The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

Symbol

Table 31. LSE oscillator characteristics

Parameter Conditions Min Typ Max Unit f

LSE

Low speed external oscillator frequency

Feedback resistor

32.768

kHz

(1)

Recommended load capacitance

(2)

Δ V = 200 mV

1.2

1.4

(3)

M Ω pF

µA

DD(LSE)

LSE oscillator power consumption

= 1.8 V

= 3 V -

450

600 -

nA g m t

SU(LSE)

(4)

Oscillator transconductance

Startup time

= 3.6 V

is stabilized

750

µA/V

C= C

= C

is approximately equivalent to 2 x crystal C

LOAD

The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small R m

value. Refer to crystal manufacturer for more details.

Guaranteed by design.

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

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DS7204 Rev 11

STM8L151x2, STM8L151x3

Resonator

Figure 17. LSE oscillator circuit diagram

Electrical parameters f

LSE

OSCIN

F gm

Consumption control

Resonator

OSCOUT

STM8

MSv37776V1

Internal clock sources

Subject to general operating conditions for V

, and T

High speed internal RC oscillator (HSI)

In the following table, data is based on characterization results, not tested in production, unless otherwise specified.

Symbol Parameter

Table 32. HSI oscillator characteristics

Conditions

(1)(2) Min Typ Max Unit f

HSI

ACC

I t

HSI

TRIM su(HSI)

DD(HSI)

Frequency V

= 3.0 V

Accuracy of HSI oscillator (factory calibrated)

HSI user trimming step

(4)

= 3.0 V, T

= 25 °C

= 3.0 V, 0 °C ≤ T

55 °C

= 3.0 V, -10 °C ≤ T

70 °C

= 3.0 V, -10 °C ≤ T

85 °C

= 3.0 V, -10 °C ≤ T

125 °C

1.65 V ≤ V

≤ 3.6 V,

-40 °C ≤ T

Trimming code ≠ multiple of 16

Trimming code = multiple of 16

HSI oscillator setup time (wakeup time)

HSI oscillator power consumption

-1

-1.5

-2

-2.5

-4.5

-4.5 -

(3)

0.4

3.7

100

1.5

3 %

0.7

± 1.5

(5)

140

= 3.0 V, T

= -40 to 125 °C unless otherwise specified.

> 85 °C is valid only for devices with suffix 3 temperature range.

Tested in production.

The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16

(0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for more details.

Guaranteed by design.

µs

µA

MHz

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Electrical parameters STM8L151x2, STM8L151x3

Figure 18. Typical HSI frequency vs V

18.0

17.5

17.0

16.5

16.0

15.5

15.0

14.5

-40°C

25°C

85°C 14.0

13.5

13.0

1.8 1.95

2.1

2.25

2.4

2.55

2.7

2.85

3 3.15

3.3 3.45

3.6

[V] ai18218c

Low speed internal RC oscillator (LSI)

In the following table, data is based on characterization results, not tested in production.

Symbol Parameter

(1)

Table 33. LSI oscillator characteristics

Conditions

(1)

Min Typ Max Unit

200

(2) kHz

µs t f

LSI su(LSI)

DD(LSI)

Frequency -

LSI oscillator wakeup time -

LSI oscillator frequency drift

(3)

0 °C ≤ T

≤

-12

= 1.65 V to 3.6 V, T

= -40 to 125 °C unless otherwise specified.

Guaranteed by design.

This is a deviation for an individual part, once the initial frequency has been measured.

11 %

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STM8L151x2, STM8L151x3

1.8

2.1

Electrical parameters

Figure 19. Typical LSI frequency vs. V

2.6

[V]

3.1

-40°C

25°C

85°C

3.6

ai18219b

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Electrical parameters STM8L151x2, STM8L151x3

= -40 to 125 °C unless otherwise specified.

Table 34. RAM and hardware registers

Symbol Parameter Conditions Min Typ Max Unit

Data retention mode

(1)

Halt mode (or Reset) 1.65

Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization results.

Flash memory

Symbol

Table 35. Flash program and data EEPROM memory

Parameter Conditions Min Typ

Max

(1)

Unit

Operating voltage

(all modes, read/write/erase)

Programming time for 1 or 64 bytes (block) erase/write cycles (on programmed byte) f

SYSCLK

= 16 MHz

1.65

3.6

V ms t prog

Programming time for 1 to 64 bytes (block) write cycles (on erased byte)

3 ms

I prog

Programming/ erasing consumption

= +25 °C, V

= 3.0 V

+25 °C, V

= 1.8 V

0.7

mA t

RET

(2)

Data retention (program memory) after 10000 erase/write cycles at T

= –40 to +85 °C

(3 and 6 suffix)

Data retention (program memory) after 10000 erase/write cycles at T

= –40 to +125 °C

(3 suffix)

Data retention (data memory) after 300000 erase/write cycles at T

= –40 to +85 °C

(3 and 6 suffix)

Data retention (data memory) after 300000 erase/write cycles at T

= –40 to +125 °C

(3 suffix)

Erase/write cycles (program memory)

RET

+85 °C

+125 °C

+85 °C

+125 °C

years

(3)

Erase/write cycles (data memory)

= –40 to +85 °C

(3 and 6 suffix),

= –40 to +105 °C

(3 suffix) or

= –40 to +125 °C

(3 suffix)

300

(4)

kcycles

Guaranteed by characterization results.

Conforming to JEDEC JESD22a117

The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.

Data based on characterization performed on the whole data memory.

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

As a general rule, current injection to the I/O pins, due to external voltage below V

or above V

(for standard pins) should be avoided during normal product operation.

However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC1 error, out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation, etc.).

The test results are given in the following table.

Symbol

INJ

Table 36. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

Injected current on true open-drain pins (PC0 and

PC1)

Injected current on all five-volt tolerant pins

Injected current on all 3.6 V tolerant pins

Injected current on any other pin

-5

Unit mA

9.3.7 I/O port pin characteristics

General characteristics

Subject to general operating conditions for V

and T

unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.

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Electrical parameters STM8L151x2, STM8L151x3

Symbol Parameter

Table 37. I/O static characteristics

Conditions

(1) Min Typ Max

IH hys lkg

Input low level voltage hysteresis

(3)

Input leakage current

(2)

Input high level voltage

Schmitt trigger voltage

(4)

current sourced must always respect the absolute maximum rating specified in Table 15 and the

Input voltage on true open-drain pins (PC0 and PC1)

-0.3

Input voltage on any other pin V

-0.3

Input voltage on true open-drain pins (PC0 and PC1) with V

< 2 V

Input voltage on true open-drain pins (PC0 and PC1) with V

≥

2 V

0.70 x V

Input voltage on any other pin 0.70 x V

I/Os

True open drain I/Os

≤ V

High sink I/Os

≤ V

True open drain I/Os

≤ V

PA0 with high sink LED driver capability

200

0.3 x V

5.2

5.5

+0.3

200

(5)

Weak pull-up equivalent

resistor

(2)(6)

= V

30 45 60

I/O pin capacitance 5 -

= 3.0 V, T

= -40 to 125 °C unless otherwise specified.

Guaranteed by characterization results.

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

The max. value may be exceeded if negative current is injected on adjacent pins.

Not tested in production.

pull-up equivalent resistor based on a resistive transistor (corresponding I

PU current characteristics described in

Figure 23 ).

Unit

V mV nA k Ω pF

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

Figure 20. Typical V

and V

IH vs V

(high sink I/Os)

2.5

-40°C

25°C

85°C

1.5

0.5

1.8

2.1

2.6

[V]

3.1

3.6

ai18220c

2.5

1.5

0.5

1.8

Figure 21. Typical V

and V

IH vs V

(true open drain I/Os)

-40°C

25°C

85°C

2.1

2.6

[V]

3.1

3.6

ai18221b

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Electrical parameters STM8L151x2, STM8L151x3

Figure 22. Typical pull-up resistance R

vs V

with V

-40°C

25°C

85°C

1.8

2 2.2

2.4

2.6

[V]

2.8

3 3.2

3.4

3.6

ai18222b

Figure 23. Typical pull-up current I pu

vs V

with V

120

100

-40°C

25°C

85°C

1.8

1.95

2.1

2.25

2.4

2.55

2.7

2.85

3 3.15

3.3

3.45

3.6

[V] ai18223b

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

Output driving current

Subject to general operating conditions for V

DD and T

unless otherwise specified.

Table 38. Output driving current (high sink ports)

I/O

Type

Symbol Parameter Conditions Min Max Unit

(1)

(2)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

= +2 mA,

= 3.0 V

= +2 mA,

= 1.8 V

= +10 mA,

= 3.0 V

= -2 mA,

= 3.0 V

-0.45

= -1 mA,

= 1.8 V

= -10 mA,

= 3.0 V

-0.45

-0.7

0.45

0.7

The I

current sunk must always respect the absolute maximum rating specified in

Table 15 and the sum

of I

(I/O ports and control pins) must not exceed I

VSS

The I

sum of I

(I/O ports and control pins) must not exceed I

VDD

Table 39. Output driving current (true open drain ports)

I/O

Type

Symbol Parameter Conditions Min Max Unit

(1) Output low level voltage for an I/O pin

= +3 mA,

= 3.0 V

= +1 mA,

= 1.8 V

0.45

The I

current sunk must always respect the absolute maximum rating specified in

Table 15 and the sum

of I

(I/O ports and control pins) must not exceed I

VSS

I/O

Type

Table 40. Output driving current (PA0 with high sink LED driver capability)

Symbol Parameter Conditions Min Max Unit

(1)

Output low level voltage for an I/O pin

= +20 mA,

= 2.0 V

0.45

The I

current sunk must always respect the absolute maximum rating specified in

Table 15 and the sum

of I

(I/O ports and control pins) must not exceed I

VSS

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Electrical parameters STM8L151x2, STM8L151x3

Figure 24. Typ. V

@ V

= 3.0 V (high sink ports)

0.75

0.5

0.25

-40°C

25°C

90°C

130°C

0 2 4 6 8 10

[mA]

12 14 16 18 20 ai18226

Figure 26. Typ. V

@ V

= 3.0 V (true open drain ports)

Figure 25. Typ. V

@ V

DD ports)

= 1.8 V (high sink

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0 1 2

-40°C

25°C

90°C

130°C

3 4

[mA]

5 6 7 8 ai18227

Figure 27. Typ. V

@ V

= 1.8 V (true open drain ports)

0.3

0.2

0.1

0.5

0.4

-40°C

25°C

90°C

130°C

0 1 2 3

[mA]

4 5 6 ai18228

Figure 28. Typ. V

DD -

@ V

= 3.0 V (high sink ports)

1.75

1.5

1.25

0.75

0.5

0.25

0 2

-40°C

25°C

90°C

130°C

4 6 8 10

[mA]

12 14 16 18 20 ai12830

0.5

0.4

0.3

0.2

0.1

-40°C

25°C

90°C

130°C

1 2 3

[mA]

4 5 6 7 ai18229

Figure 29. Typ. V

DD -

@ V

= 1.8 V (high sink ports)

0.5

0.4

0.3

0.2

0.1

0 1

-40°C

25°C

90°C

130°C

2 3

[mA]

4 5 6 7 ai18231

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

Symbol

NRST pin

Subject to general operating conditions for V

and T

unless otherwise specified.

Parameter

Table 41. NRST pin characteristics

Conditions Min Typ Max

IL(NRST)

IH(NRST)

OL(NRST)

NRST input low level voltage

(1)

NRST input high level voltage

NRST output low level voltage

= 2 mA for 2.7 V ≤

3.6 V

= 1.5 mA for V

< 2.7 V

1.4

0.8

0.4

HYST NRST input hysteresis

10%V

(2)

PU(NRST)

NRST pull-up equivalent resistor

F(NRST)

NF(NRST)

NRST input filtered pulse

Guaranteed by characterization results.

200 mV min.

Guaranteed by design.

(3)

NRST input not filtered pulse

The reset network shown in Figure 32

300

Unit

V mV k

Ω ns

Figure 30. Typical NRST pull-up resistance R

vs V

-40°C

25°C

85°C

1.8

2 2.2

2.4

2.6

2.8

[V]

3 3.2

3.4

3.6

ai18224b

DS7204 Rev 11

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102

Electrical parameters STM8L151x2, STM8L151x3

120

Figure 31. Typical NRST pull-up current I pu

vs V

100

-40°C

25°C

85°C

1.8

1.95 2.1

2.25 2.4

2.55 2.7

2.85

3 3.15 3.3

3.45 3.6

[V] ai18225b

protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max. level specified in

Table 41 . Otherwise the reset is not taken into account internally.

For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, attention must be paid to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. The minimum recommended capacity is 10 nF.

Figure 32. Recommended NRST pin configuration

External reset circuit

(Optional)

0.1 uF

N RST

Filter

Internal reset

STM8

MS34928V1

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

SPI1 - Serial peripheral interface

Unless otherwise specified, the parameters given in

Table 42 are derived from tests

performed under ambient temperature, f

SYSCLK

frequency and V

supply voltage conditions summarized in

Section 9.3.1

. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol Parameter

Table 42. SPI1 characteristics

Conditions

(1)

Min Max Unit

1/t t su(NSS)

(2) t

t t

t t t su(MI)

t h(MI)

h(SI) t a(SO)

t dis(SO)

t t t f

SCK c(SCK) t r(SCK) t f(SCK) v(MO)

(2) h(SO)

(2) h(MO)

SPI1 clock frequency

Master mode

Slave mode

SPI1 clock rise and fall time

NSS setup time

Capacitive load: C = 30 pF

Slave mode

NSS hold time

SCK high and low time

Slave mode

Master mode, f

MASTER

= 8 MHz, f

SCK

= 4 MHz

Master mode

Data input setup time

Slave mode

Master mode

Data input hold time

Slave mode

Data output access time Slave mode

Data output disable time Slave mode

Data output valid time

Slave mode (after enable edge)

Master mode (after enable edge)

Data output hold time

Slave mode (after enable edge)

Master mode (after enable edge)

4 x 1/f

SYSCLK

105

145

3x 1/f

SYSCLK

Parameters are given by selecting 10 MHz I/O output frequency.

Values based on design simulation and/or characterization results.

Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.

Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.

MHz ns

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102

Electrical parameters STM8L151x2, STM8L151x3

Figure 33. SPI1 timing diagram - slave mode and CPHA=0

Figure 34. SPI1 timing diagram - slave mode and CPHA=1

(1)

Measurement points are done at CMOS levels: 0.3V

and 0.7V

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DS7204 Rev 11

STM8L151x2, STM8L151x3

Figure 35. SPI1 timing diagram - master mode

(1)

NSS input

High tc(SCK)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1

Electrical parameters

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MS BIN th(MI)

M SB OUT tv(MO)

BI T6 IN

B I T1 OUT th(MO)

Measurement points are done at CMOS levels: 0.3V

and 0.7V

tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136V2

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102

Electrical parameters

Note:

STM8L151x2, STM8L151x3

I

C - Inter IC control interface

Subject to general operating conditions for V

, f

SYSCLK

, and T

unless otherwise specified.

The STM8L I

C interface (I2C1) meets the requirements of the Standard I

C communication protocol described in the following table with the restriction mentioned below:

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL).

Symbol

Table 43. I2C characteristics

Standard mode

Parameter

Min

(2)

Max

Fast mode I

(1)

Min

Max

t w(SCLL) t w(SCLH) t su(SDA) t h(SDA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

4.7

4.0

250

0 -

1.3

0.6

100

900 t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SDA and SCL rise time

SDA and SCL fall time

START condition hold time

4.0

1000

300

0.6

300

t su(STA)

Repeated START condition setup time t su(STO)

STOP condition setup time t w(STO:STA)

STOP to START condition time (bus free)

4.7

4.0

4.7

0.6 -

0.6

1.3

C b

Capacitive load for each bus line 400

SYSCLK

must be at least equal to 8 MHz to achieve max fast I

C speed (400 kHz).

Data based on standard I

C protocol requirement, not tested in production.

400

Unit

μ s ns

μ s

μ s pF

For speeds around 200 kHz, the achieved speed can have a

5% tolerance

For other speed ranges, the achieved speed can have a

2% tolerance

The above variations depend on the accuracy of the external components used.

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

Figure 36. Typical application with I

C bus and timing diagram 1)

I2C BUS

4.7kΩ

100Ω

SDA

SCL

STM8L

Start

SDA t f(SDA)

SCL t r(SDA) t su(SDA) t h(SDA) t h(STA) t w(SCLH) t w(SCLL) t r(SCL) t f(SCL)

Repeated start t su(STA) t w(STO:STA)

Start

Stop t su(STO)

MS32620V2

1. Measurement points are done at CMOS levels: 0.3 x V

and 0.7 x V

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102

Electrical parameters STM8L151x2, STM8L151x3

In the following table, data is based on characterization results, not tested in production, unless otherwise specified.

Symbol

Table 44. Reference voltage characteristics

Parameter Conditions Min Typ Max.

REFINT

Internal reference voltage consumption

S_VREFINT

(1)(2)

ADC1 sampling time when reading the internal reference voltage

BUF

REFINT out

Internal reference voltage buffer consumption (used for ADC1)

Reference voltage output

REFOUT

Internal reference voltage low power buffer consumption (used for comparators or output)

Buffer output current

(4) t

VREFINT

Reference voltage output load

Internal reference voltage startup time t

BUFEN

startup time once enabled

ACC

STAB

VREFINT

Internal reference voltage buffer

Accuracy of V

REFINT

stored in the

VREFINT_Factory_CONV byte

(5)

Stability of V

REFINT

over temperature

-40 °C ≤ T

≤ 125 °C

Stability of V

REFINT

over temperature

Stability of V

REFINT after 1000 hours

0 °C ≤ T

≤ 50 °C

1.202

(3)

1.4

13.5

1.224

730

1.242

1200

± 5

TBD

Defined when ADC1 output reaches its final value ±1/2LSB

Guaranteed by design.

Tested in production at V

= 3 V ±10 mV.

To guaranty less than 1% V

REFOUT deviation.

Measured at V

= 3 V ±10 mV. This value takes into account V

accuracy and ADC1 conversion accuracy.

Unit

µA

µs

µA

V nA

µA pF ms

µs mV ppm/°C ppm/°C ppm

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

In the following table, data is based on characterization results, not tested in production, unless otherwise specified.

Table 45. TS characteristics

Symbol Parameter Min

(1)

START

(2)(3)

Sensor reference voltage at 90°C ±5 °C, 0.580

SENSOR linearity with temperature

Average slope

1.59

Consumption -

Temperature sensor startup time

S_TEMP

Propagation delay in fast mode

ADC1 sampling time when reading the temperature sensor

Typ

0.597

±1

1.62

3.4

Max.

0.614

±2

1.65

Unit

µs

Tested in production at V

= 3 V ±10 mV. The 8 LSB of the V

ADC1 conversion result are stored in the

TS_Factory_CONV_V90 byte.

Guaranteed by design.

Defined for ADC1 output reaching its final value ±1/2LSB.

°C mV/°C

µA

µs

In the following table, data is guaranteed by design, not tested in production, unless otherwise specified.

Symbol

Table 46. Comparator 1 characteristics

Parameter Min Typ Max

(1) Unit

DDA

400K

10K

Analog supply voltage

Temperature range

400K

value

10K

value

Comparator 1 input voltage range

1.65

-40

300

7.5

0.6

400

3.6

125

500

12.5

DDA

°C k

1.202

1.224

1.242

REFINT Internal reference voltage

(2) t

START t d

V offset

COMP1

Comparator startup time

Propagation delay

(3)

Comparator offset error

Current consumption

(4)

±3

160

±10

µs mV

260 nA

Guaranteed by characterization results.

Tested in production at V

= 3 V ±10 mV.

The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.

Comparator consumption only. Internal reference voltage not included.

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102

Electrical parameters STM8L151x2, STM8L151x3

In the following table, data is guaranteed by design, not tested in production.

Symbol Parameter

Table 47. Comparator 2 characteristics

Conditions Min Typ Max

(1) Unit t t

DDA

IN t

START

V d slow d fast offset

COMP2

Analog supply voltage

Temperature range

Comparator 2 input voltage range

Fast mode

Comparator startup time

Propagation delay in slow mode

(2)

Comparator offset error

Slow mode

1.65 V

≤

DDA

≤

2.7 V

2.7 V ≤ V

DDA

≤

1.65 V

≤

DDA

≤

2.7 V

2.7 V ≤ V

DDA

≤

Fast mode

Current consumption

(3)

Slow mode

1.65

-40

1.8

2.5

0.8

1.2

±4

3.5

3.6

125

DDA

3.5

±20

0.5

Guaranteed by characterization results.

The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.

Comparator consumption only. Internal reference voltage not included.

°C

µs mV

µA

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DS7204 Rev 11

STM8L151x2, STM8L151x3 Electrical parameters

REF-

VDDA

In the following table, data is guaranteed by design, not tested in production.

Symbol

DDA

Analog supply voltage

REF+

Reference supply voltage

Lower reference voltage

Current on the V DDA input pin

Table 48. ADC1 characteristics

Min Typ

2.4 V ≤ V

DDA

≤ 3.6 V

1.8 V ≤ V

DDA

≤ 2.4 V

1.8

2.4

DDA

SSA

1000

Max

3.6

DDA

1450

VREF+

Current on the V REF+ input pin

400

700

(peak)

(1)

450

(average)

AIN

ADC1 f

CONV f

TRIG t

LAT

Conversion voltage range

Temperature range

External resistance on

AIN

Internal sample and hold capacitor

ADC1 sampling clock frequency

12-bit conversion rate

on PF0 fast channel on all other channels on PF0 fast channel on all other channels

2.4 V ≤ V

DDA

≤ 3.6 V without zooming

1.8 V

≤

DDA

≤

2.4 V with zooming

AIN

on PF0 fast channel

AIN

on all other channels

External trigger frequency

External trigger latency -

(2)

-40

0.320

REF+

125

(3)

(4)(5)

760

(4)(5)

t conv

3.5

Unit

µA

°C k Ω pF

MHz

MHz kHz

1/f

ADC1

1/f

SYSCLK

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102

Electrical parameters STM8L151x2, STM8L151x3

Symbol

Table 48. ADC1 characteristics (continued)

Min Typ Max Unit t

Sampling time

AIN

on PF0 fast channel

DDA

< 2.4 V

AIN

on PF0 fast channel

2.4 V ≤ V

DDA

≤ 3.6 V

AIN

on slow channels

DDA

< 2.4 V

AIN

on slow channels

2.4 V ≤ V

DDA

≤ 3.6 V

µs

µs t conv

12-bit conversion time

16 MHz

12 + t