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STM8L051F3
8-bit ultra-low-power MCU, 8-Kbyte Flash memory,
256-byte data EEPROM, RTC, timers, USART, I2C, SPI, ADC
Datasheet
-
production data
Features
• Operating conditions
– Operating power supply: 1.8 V to 3.6 V
Temperature range: − 40 °C to 85 °C
• Low-power features
– 5 low-power modes: Wait, Low-power run
(5.1 µA), Low-power wait (3 µA), Activehalt with RTC (1.3 µA), Halt (350 nA)
– Ultra-low leakage per I/O: 50 nA
– Fast wakeup from Halt: 5 µs
• Advanced STM8 core
– Harvard architecture and 3-stage pipeline
– Max freq: 16 MHz, 16 CISC MIPS peak
– Up to 40 external interrupt sources
• Reset and supply management
– Low power, ultra-safe BOR reset with 5 selectable thresholds
– Ultra-low power POR/PDR
– Programmable voltage detector (PVD)
• Clock management
– 32 kHz and 1 to 16 MHz crystal oscillators
– Internal 16 MHz factory-trimmed RC
– Internal 38 kHz low consumption RC
– Clock security system
• Low-power RTC
– BCD calendar with alarm interrupt
– Digital calibration with +/- 0.5 ppm accuracy
– LSE security system
– Auto-wakeup from Halt w/ periodic interrupt
• Memories
– 8 Kbytes of Flash program memory and
256 bytes of data EEPROM with ECC
– Flexible write and read protection modes
– 1 Kbyte of RAM
TSSOP20 (6.4x4.4 mm or 169 mils width)
• DMA
– 4 channels supporting ADC, SPI, I2C,
USART, timers
– 1 channel for memory-to-memory
• 12-bit ADC up to 1 Msps/10 channels
– Internal reference voltage
• Timers
– Two 16-bit timers with 2 channels (used as
IC, OC, PWM), quadrature encoder
– One 8-bit timer with 7-bit prescaler
– 2 watchdogs: 1 Window, 1 Independent
– Beeper timer with 1, 2 or 4 kHz frequencies
• Communication interfaces
– Synchronous serial interface (SPI)
– Fast I2C 400 kHz SMBus and PMBus
– USART
• Up to 18 I/Os, all mappable on interrupt vectors
• Development support
– Fast on-chip programming and nonintrusive debugging with SWIM
– Bootloader using USART
September 2018
This is information on a product in full production.
DS9178 Rev 4 1/96 www.st.com
Contents
Contents
2/96
STM8L051F3
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
System configuration controller and routing interface . . . . . . . . . . . . . . . 19
16-bit general purpose timers (TIM2, TIM3) . . . . . . . . . . . . . . . . . . . . . 19
Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DS9178 Rev 4
STM8L051F3
Contents
System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Embedded reset and power control block characteristics . . . . . . . . . . . 49
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
DS9178 Rev 4 3/96
4
Contents STM8L051F3
TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4/96 DS9178 Rev 4
STM8L051F3
List of tables
List of tables
Legend/abbreviation for Table 4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Total current consumption and timing in Low power run mode
Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . 56
Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V. . . . . . 57
Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 57
Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V . . . . . . . . . . . . 58
ADC1 accuracy with VDDA = VREF
max for f
ADC
= 1.8 V to 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
DS9178 Rev 4 5/96
6
List of tables STM8L051F3
6/96 DS9178 Rev 4
STM8L051F3
List of figures
List of figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PU
vs V
vs V
DD
DD
with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Typical NRST pull-up resistance R
PU
Typical NRST pull-up current I pu
vs V
vs V
DD
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SPI1 timing diagram - slave mode and CPHA=1
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SPI1 timing diagram - master mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Maximum dynamic current consumption on V
supply pin during ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Power supply and reference decoupling (V
REF+ not connected to V
DDA
). . . . . . . . . . . . . . 84
Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 85
Device marking for TSSOP20 – 20-lead thin shrink small outline,
Low density value line STM8L051F3 ordering information scheme . . . . . . . . . . . . . . . . . . 93
DS9178 Rev 4 7/96
7
Introduction
1 Introduction
STM8L051F3
This document describes the features, pinout, mechanical data and ordering information for the low density STM8L051F3 microcontroller with 8-Kbyte Flash memory density.
For further details on the whole STMicroelectronics low density family please refer to
Section 2.2: Ultra-low-power continuum .
For detailed information on device operation and registers, refer to the STM8L050J3,
STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162,
STM8AL31, STM8AL3L lines reference manual (RM0031).
For information on to the Flash program memory and data EEPROM, refer to the How to program STM8L and STM8AL Flash program memory and data EEPROM programming manual (PM0054).
For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).
The low density value line devices, including STM8L051F3, provide the following benefits:
• Integrated system
– 8 Kbytes of low-density embedded Flash program memory
– 256 bytes of data EEPROM
– 1 Kbyte of RAM
– Internal high-speed and low-power low speed RC
– Embedded reset
• Ultra-low-power consumption
– 1 µA in Active-halt mode
– Clock gated system and optimized power management
– Capability to execute from RAM for Low-power wait mode and Low-power run mode
• Advanced features
– Up to 16 MIPS at 16 MHz CPU clock frequency
– Direct memory access (DMA) for memory-to-memory or peripheral-to-memory access
• Short development cycles
– Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals
– Wide choice of development tools
These features make STM8L051F3 suitable for a wide range of consumer and mass market applications.
Refer to Table 1: STM8L051F3 features and peripheral counts
and Section 3: Functional overview
for an overview of the complete range of peripherals proposed in this family.
Figure 1 shows the block diagram of the low density STM8L051F3 device.
8/96 DS9178 Rev 4
STM8L051F3
2 Description
Description
STM8L051F3 is member of the STM8L ultra-low-power 8-bit family.
STM8L051F3 features an enhanced STM8 CPU core providing increased processing power
(up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low-power operations.
The STM8L051F3 MCU includes an integrated debug module with a hardware interface
(SWIM) which allows non-intrusive In-Application debugging and ultra-fast Flash programming. It features an embedded data EEPROM and low-power, low-voltage, singlesupply program Flash memory.
The device incorporates an extensive range of enhanced I/Os and peripherals, a 12-bit
ADC, a real-time clock, two 16-bit timers, one 8-bit timer, as well as standard communication interfaces such as an SPI, an I2C interface, and one USART.
The modular design of the peripheral set allows this device to have the same peripherals that can be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, supported also by the use of a common set of development tools.
STM8L051F3 as all the value line STM8L ultra-low-power products are based on the same architecture with the same memory mapping and a coherent pinout.
DS9178 Rev 4 9/96
41
Description STM8L051F3
Features
Table 1. STM8L051F3 features and peripheral counts
STM8L051F3
Flash (Kbytes)
Data EEPROM (Bytes)
RAM (Kbytes)
Basic
Timers
General purpose
SPI
Communicati on interfaces
I2C
USART
GPIOs
12-bit synchronized ADC
(number of channels)
Others
8
256
1
1
(8-bit)
2
(16-bit)
1
1
1
18
(1)
1
(10)
RTC, window watchdog, independent watchdog,
16-MHz and 32-kHz internal RC,
1- to 16-MHz and 32-kHz external oscillator
CPU frequency
Operating voltage
Operating temperature
Package
16 MHz
1.8 to 3.6 V
− 40 to +85 °C
TSSOP20
1. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the
NRST/PA1 pin as general purpose output only (PA1).
10/96 DS9178 Rev 4
STM8L051F3 Description
STM8L051F3 is part of STM8’s ultra-low-power value line on which all the devices are pinto-pin, software and feature compatible. Besides the full compatibility within the STM8L family, the devices are part of STMicroelectronics microcontrollers ultra-low-power strategy which also includes the STM8L001xx, STM8L101xx and STM32L15xxx devices. The
STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features.
They are all based on STMicroelectronics 0.13 µm ultra-low leakage process.
Note: 1 STM8L051F3 is pin-to-pin compatible with STM8L101xx devices.
2 The STM32L family is pin-to-pin compatible with the general purpose STM32F family.
Please refer to STM32L15x documentation for more information on these devices.
Performance
All the STMicroelectronics ultra-low-power families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM
®
32-bit Cortex
®
-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
Shared peripherals
The STM8L05xxx, STM8L15xxx and STM32L15xxx devices share identical peripherals which ensure a very easy migration from one family to another:
• Analog peripheral: ADC1
• Digital peripherals: RTC and some communication interfaces
Common system strategy
To offer flexibility and optimize performance, the STM8L and STM32L devices use a common architecture:
• Same power supply range from 1.8 to 3.6 V
• Architecture optimized to reach ultra-low consumption both in low-power modes and
Run mode
• Fast startup strategy from low-power modes
• Flexible system clock
• Ultra-safe reset: same reset strategy for both STM8L and STM32L including power-on reset, power-down reset, brownout reset and programmable voltage detector.
Features
ST ultra-low-power continuum also lies in feature compatibility:
• More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm
• Memory density ranging from 4 to 128 Kbytes
DS9178 Rev 4 11/96
41
Functional overview STM8L051F3
12/96
OSC_IN,
OSC_OUT
OSC32_IN,
OSC32_OUT
SWIM
2 channels
2 channels
IR_TIM
SCL, SDA,
SMB
SPI1_MOSI, SPI1_MISO,
SPI1_SCK, SPI1_NSS
USART1_RX, USART1_TX,
USART1_CK
V
DDA,
V
SSA
ADC1_INx
V
DDREF
V
SSREF
VREFINT out
1-16 MHz oscillator
16 MHz internal RC
32 kHz oscillator
38 kHz internal RC
Interrupt controller
STM8 Core
Debug module
(SWIM)
16-bit Timer 2
(2)
16-bit Timer 3
(2)
8-bit Timer 4
(2)
Infrared interface
DMA1 (4 channels)
I²C1
SPI1
USART1
@V
DDA
/V
SSA
12-bit ADC1
Figure 1. STM8L051F3 block diagram
Clock controller and CSS
VDD18
@V DD
Power
VOLT. REG.
Clocks to core and peripherals
RESET
POR/PDR
BOR
PVD
8-Kbyte
Program memory
256-byte
Data EEPROM
1-Kbyte RAM
Port A
Port B
Port C
Port D
Internal reference voltage
Beeper
RTC
IWDG
(38 kHz clock)
WWDG
V DD =1.8 V
3.6 V
V SS to
NRST
PVD_IN
PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
BEEP
ALARM,
TAMP1/2/3
MS30321V2
1.
Legend :
ADC: Analog-to-digital converter
BOR: Brownout reset
DMA: Direct memory access
I²C: Inter-integrated circuit multimaster interface
IWDG: Independent watchdog
POR/PDR: Power-on reset / power-down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
DS9178 Rev 4
STM8L051F3 Functional overview
STM8L051F3 as well as all the low density value line STM8L05xxx devices support five lowpower modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
• Wait mode : The CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt or a Reset can be used to exit the microcontroller from
Wait mode (WFE or WFI mode).
• Low-power run mode : The CPU and the selected peripherals are running. Execution is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data
EEPROM are stopped and the voltage regulator is configured in ultra-low-power mode.
The microcontroller enters Low-power run mode by software and can exit from this mode by software or by a reset.
All interrupts must be masked. They cannot be used to exit the microcontroller from this mode.
• Low-power wait mode: This mode is entered when executing a Wait for event in Lowpower run mode. It is similar to Low-power run mode except that the CPU clock is stopped. The wakeup from this mode is triggered by a Reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, DMA controller (DMA1) and I/O ports). When the wakeup is triggered by an event, the system goes back to Low-power run mode.
All interrupts must be masked. They cannot be used to exit the microcontroller from this mode.
• Active-halt mode : CPU and peripheral clocks are stopped, except RTC. The wakeup can be triggered by RTC interrupts, external interrupts or reset.
• Halt mode : CPU and peripheral clocks are stopped, the device remains powered on.
The RAM content is preserved. The wakeup is triggered by an external interrupt or reset. A few peripherals have also a wakeup from Halt capability. Switching off the internal reference voltage reduces power consumption. Through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 µs.
DS9178 Rev 4 13/96
41
Functional overview STM8L051F3
The central processing unit represents the core of the microcontroller; it executes code and controls the peripherals.
The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline.
It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions.
Architecture and registers
• Harvard architecture
• 3-stage pipeline
• 32-bit wide program memory bus - single cycle fetching most instructions
• X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations
• 8-bit accumulator
• 24-bit program counter - 16-Mbyte linear memory space
• 16-bit stack pointer - access to a 64-Kbyte level stack
• 8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
• 20 addressing modes
• Indexed indirect addressing mode for lookup tables located anywhere in the address space
• Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
• 80 instructions with 2-byte average instruction size
• Standard data movement and logic/arithmetic functions
• 8-bit by 8-bit multiplication
• 16-bit by 8-bit and 16-bit by 16-bit division
• Bit manipulation
• Data transfer between stack and accumulator (push/pop) with direct stack access
• Data transfer using the X and Y registers or direct memory-to-memory transfers
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STM8L051F3 and all the low density value line STM8L05xxx feature a nested vectored interrupt controller:
• Nested interrupts with 3 software priority levels
• 32 interrupt vectors with hardware priority
• Up to 17 external interrupt sources on 11 vectors
• Trap and reset interrupts
DS9178 Rev 4
STM8L051F3
3.3
3.3.1
3.3.2
Functional overview
Reset and supply management
The power supplies requirements must be defined in order to have a correct microcontroller operation. The reset and supply management controls the microcontroller operation under defined conditions.
Power supply scheme
The device requires a 1.8 V to 3.6 V operating supply voltage (V
DD supply pins must be connected as follows:
). The external power
• V
SS1
; V
DD1
= 1.8 to 3.6 V: external power supply for I/Os and for the internal regulator.
Provided externally through V
DD1
pins, the corresponding ground pin is V
SS1
.
• V
SSA
; V
DDA
= 1.8 to 3.6 V: external power supplies for analog peripherals. V
V
SSA
must be connected to V
DD1
and V
SS1
, respectively.
DDA
and
• V
SS2
; V
DD2
= 1.8 to 3.6 V: external power supplies for I/Os. V
DD2 connected to V
DD1
and V
SS1
, respectively.
and V
SS2
must be
• V
REF+
, V
REF-
(for ADC1): external reference voltage for ADC1. Must be providedexternally through V
REF+
and V
REF-
pin.
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR), coupled with a brownout reset (BOR) circuitry. When the microcontroller operates between 1.8 and 3.6 V, BOR is always active and ensures proper operation starting from
1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the BOR) in Halt mode. The device remains in reset state when V
DD is below a specified threshold, V
POR/PDR or V
BOR
, without the need for any external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
DD
/V
DDA
power supply and compares it to the V
PVD
threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when V
V
DD
/V
DDA
is higher than the V
PVD
DD
/V
DDA
drops below the V
PVD
threshold and/or when
threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
STM8L051F3 as all the low density value line STM8L05xxx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals.
This regulator has two different modes:
• Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes.
• Low-power voltage regulator mode (LPVR) for Halt, Active-halt, Low-power run and
Low-power wait modes.
When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption.
DS9178 Rev 4 15/96
41
Functional overview STM8L051F3
The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness.
Features
• Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
• Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register.
• Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.
• System clock sources: four different clock sources can be used to drive the system clock:
– 1-16 MHz High speed external crystal (HSE)
– 16 MHz High speed internal RC oscillator (HSI)
– 32.768 Low speed external crystal (LSE)
– 38 kHz Low speed internal RC (LSI)
• RTC clock sources: the above four sources can be chosen to clock the RTC whatever the system clock.
• Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.
• Clock security system (CSS): This feature can be enabled by software. If a HSE clock failure occurs, it is automatically switched to HSI.
• Configurable main clock output (CCO): This outputs an external clock for use by the application.
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STM8L051F3
OSC_OUT
OSC_IN
Functional overview
HSE OSC
1-16 MHz
HSI RC
1-16 MHz
Figure 2. STM8L051F3 clock tree diagram
HSE
HSI
LSI
LSE
SWIM[3:0]
SYSCLK to core and memory
SYSCLK prescaler
/1;2;4;8;16;32;64
Peripheral
Clock enable (13 bits)
PCLK to peripherals
LSE
BEEPCLK
BEEP to
CLKBEEPSEL[1:0]
LSI
LSI RC
38 kHz IWDGCLK to
IWDG
LSE OSC
32.768 kHz
RTCSEL[3:0]
RTC prescaler
/1;2;4;8;16;32;64 RTCCLK
RTC to
OSC32_OUT
OSC32_IN
CCO
Configurable clock output
CCO prescaler
/1;2;4;8;16;32;64
CCOSEL[3:0]
HSI
LSI
HSE
LSE
MS18281V2
1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE bypass). Refer to Section HSE clock in the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8
MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031).
2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE bypass). Refer to Section LSE clock in the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8
MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031).
DS9178 Rev 4 17/96
41
Functional overview
3.5 Low power real-time clock
STM8L051F3
The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.
Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically.
It provides a programmable alarm and programmable periodic interrupts with wakeup from
Halt capability.
• Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach
36 hours
• Periodic alarms based on the calendar can also be generated from every second to every year
3.6 Memories
STM8L051F3 as all the low density value line STM8L05xxx devices have the following main features:
• Up to 1 Kbyte of RAM
• The non-volatile memory is divided into three arrays:
– 8 Kbytes of low-density embedded Flash program memory
– 256 bytes of Data EEPROM
– Option bytes
The EEPROM embeds the error correction code (ECC) feature.
The option byte protects part of the Flash program memory from write and readout piracy.
3.7 DMA
A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and peripherals-from/to-memory transfer capability. The 4 channels are shared between the following IPs with DMA capability: ADC1, I2C1, SPI1, USART1, and the three timers.
Note:
18/96
• 12-bit analog-to-digital converter (ADC1) with 10 channels (no fast channel) and internal reference voltage
• Conversion time down to 1 µs with f
SYSCLK
= 16 MHz
• Programmable resolution
• Programmable sampling time
• Single and continuous mode of conversion
• Scan capability: automatic conversion performed on a selected group of analog inputs
• Analog watchdog
• Triggered by timer
ADC1 can be served by DMA1.
DS9178 Rev 4
STM8L051F3
3.9
Functional overview
System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.
The highly flexible routing interface controls the routing of internal analog signals to ADC1 and the internal reference voltage V
REFINT
.
3.10 Timers
STM8L051F3 contains two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4).
All the timers can be served by DMA1.
Table 2 compares the features of the advanced control, general-purpose and basic timers.
Timer
Counter resolution
Counter type
TIM2
TIM3
TIM4
16-bit
8-bit up/down up
Table 2. Timer feature comparison
Prescaler factor
DMA1 request generation
Capture/compare channels
Any power of 2 from 1 to 128
Yes
2
2
Any power of 2 from 1 to 32768
0
Complementary outputs
None
3.10.1 16-bit general purpose timers (TIM2, TIM3)
• 16-bit autoreload (AR) up/down-counter
• 7-bit prescaler adjustable to fixed power of 2 ratios (1…128)
• 2 individually configurable capture/compare channels
• PWM mode
• Interrupt capability on various events (capture, compare, overflow, break, trigger)
• Synchronization with other timers or external signals (external clock, reset, trigger and enable)
3.10.2 8-bit basic timer (TIM4)
The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow.
The watchdog system is based on two independent timers providing maximum security to the applications.
DS9178 Rev 4 19/96
41
Functional overview STM8L051F3
The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.
The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures.
It is clocked by the internal LSI RC clock source, and thus stays active even in case of a
CPU clock failure.
3.12 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.
This section describes the three communication interfaces of STM8L050J3: SPI, I2C and
USART.
3.13.1 SPI
Note:
The serial peripheral interfaces (SPI1) provide half/ full duplex synchronous serial communication with external devices.
• Maximum speed: 8 Mbit/s (f
SYSCLK
/2) both for master and slave
• Full duplex synchronous transfers
• Simplex synchronous transfers on 2 lines with a possible bidirectional data line
• Master or slave operation - selectable by hardware or software
• Hardware CRC calculation
• Slave/master selection input pin
SPI1 can be served by the DMA1 Controller.
3.13.2 I2C
Note:
The I2C bus interface (I2C1) provides multi-master capability, and controls all I2C busspecific sequencing, protocol, arbitration and timing.
• Master, slave and multi-master capability
• Standard mode up to 100 kHz and fast speed modes up to 400 kHz
• 7-bit and 10-bit addressing modes
• SMBus 2.0 and PMBus support
• Hardware CRC calculation
I2C1 can be served by the DMA1 Controller.
20/96 DS9178 Rev 4
STM8L051F3 Functional overview
3.13.3 USART
Note:
The USART interface (USART1) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates.
• 1 Mbit/s full duplex SCI
• SPI1 emulation
• High precision baud rate generator
• Smartcard emulation
• IrDA SIR encoder decoder
• Single wire half duplex mode
USART1 can be served by the DMA1 Controller.
The low density STM8L05xxx devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals.
Development tools
Development tools for the STM8 microcontrollers include:
• The STice emulation system offering tracing and code profiling
• The STVD high-level language debugger including C compiler, assembler and integrated development environment
• The STVP Flash programming software
The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.
Single wire data interface (SWIM) and debug module
The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming.
The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes.
The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, CPU operation can also be monitored in realtime by means of shadow registers.
If the initial delay is not acceptable for the application there is the option that the firmware reenables the SWIM pin functionality under specific conditions such as during firmware startup or during application run. Once that this procedure is done, the SWIM interface can be used for device debug/programming.
DS9178 Rev 4 21/96
41
Functional overview STM8L051F3
Bootloader
STM8L051F3 features a built-in bootloader. See STM8 bootloader user manual (UM0560).
The bootloader is used to download application software into the device memories, including RAM, program and data memory, using standard serial interfaces. It is a complementary solution to programming via the SWIM debugging interface.
22/96 DS9178 Rev 4
STM8L051F3 Pin description
Figure 3. STM8L051F3 20-pin TSSOP20 package pinout
PC5
PC6
PA0
NRST / PA1
PA2
PA3
VSS/VSSA/VREF-
VDD/VDDA/VREF+
PD0
PB0
1
2
7
8
9
10
3
4
5
6
14
13
12
11
20
19
18
17
16
15
PC4
PC1
PC0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
MS18280V1
Type
Level
Port and control configuration
Reset state
Table 3. Legend/abbreviation for Table 4
I= input, O = output, S = power supply
Output
Input
HS = high sink/source (20 mA)
FT - five volt tolerant
Input
Output float = floating, wpu = weak pull-up
T = true open drain, OD = open drain, PP = push pull
Bold X (pin state after reset release).
Unless otherwise specified, the pin state is the same during the reset phase
(i.e. “under reset”) and after internal reset release (i.e. at reset state).
DS9178 Rev 4 23/96
41
Pin description pin n°
Pin name
Table 4. STM8L051F3 pin description
Input Output
STM8L051F3
Default alternate function
4 NRST/PA1
(1)
5
PA2/OSC_IN/ [USART_TX]
(2)
/
6
PA3/OSC_OUT/ [USART_RX]
I/O X - HS X Reset PA1
I/O X X X HS X X
I/O X X X HS X X
Port
A2
Port
A3
HSE oscillator input / [USART transmit] / [SPI master in- slave out]
HSE oscillator output / [USART receive]/ [SPI master out/slave in]
10 PB0
(3)
/TIM2_CH1/ADC1_IN18 I/O X X X HS X X
Port
B0
11 PB1/TIM3_CH1/ADC1_IN17 I/O X X X HS X X
Port
B1
12 PB2/ TIM2_CH2/ ADC1_IN16 I/O X X X HS X X
Port
B2
13
PB3/TIM2_ETR/
ADC1_IN15/RTC_ALARM
I/O X X X HS X X
Port
B3
14 PB4
/SPI1_NSS/ADC1_IN14 I/O X X X HS X X
Port
B4
15
PB5/SPI_SCK/
/ADC1_IN13
16
PB6/SPI1_MOSI/
ADC1_IN12
I/O X X X HS X X
Port
B5
I/O X X X HS X X
Port
B6
17 PB7/SPI1_MISO/ADC1_IN11 I/O X X X HS X X
Port
B7
18 PC0/I2C_SDA I/O FT X X - T
(4)
Port
C0
19 PC1/I2C_SCL I/O FT X X
Port
C1
Timer 2 - channel 1 / ADC1_IN18
Timer 3 - channel 1 / ADC1_IN17
Timer 2 - channel 2 ADC1_IN16
Timer 2 - external trigger /
ADC1_IN15 / RTC_ALARM
SPI master/slave select /
ADC1_IN14
[SPI clock] / ADC1_IN13
SPI master out/ slave in / ADC1_IN12
SPI1 master in- slave out/
ADC1_IN11
I2C data
I2C clock
20
PC4/USART_CK/
I2C_SMB/CCO/ADC1_IN4
1
PC5/OSC32_IN /
/
[USART_TX] / [TIM2_CH1]
I/O X X X HS X X
Port
C4
I/O X X X HS X X
Port
C5
USART synchronous clock /
I2C1_SMB / Configurable clock output / ADC1_IN4
LSE oscillator input / [SPI master/slave select] / [USART transmit]/Timer 2 -channel 1
24/96 DS9178 Rev 4
STM8L051F3 pin n°
Table 4. STM8L051F3 pin description (continued)
Input Output
Pin description
Pin name Default alternate function
2
PC6/OSC32_OUT/ [SPI_SCK]
/[USART_RX] / [TIM2_CH2]
I/O X X X HS X X
Port
C6
LSE oscillator output / [SPI clock] /
[USART receive]/
Timer 2 -channel 2
9
PD0/TIM3_CH2/
I/O X X X HS X X
8 V
DD
/ V
DDA
/ V
REF+
S -
Port
D0
Timer 3 - channel 2 /
[ADC1_Trigger] / ADC1_IN22
Digital supply voltage /
ADC1 positive voltage reference
7 V
SS
/ V
REF-
/ V
SSA
3
PA0
(5)
/ [USART_CK]
SWIM/BEEP/IR_TIM
/
(6)
-
I/O X X X
HS
X X
Ground voltage / ADC1 negative voltage reference / Analog ground voltage
Port
A0
[USART1 synchronous clock]
/
SWIM input and output /
Beep output / Infrared timer output
1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L051/L052 Value Line, STM8L151/L152, STM8L162, STM8AL31, STM8AL3L
MCU lines reference manual (RM0031).
2. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function).
3. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.
4. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to V implemented).
DD
are not
5. The PA0 pin is in input pull-up during the reset phase and after reset release.
6. High Sink LED driver capability available on PA0.
Note: 1 The slope control of all GPIO pins, except true open drain pins, can be programmed. By default, the slope control is limited to 2 MHz.
As shown in
Table 4: STM8L051F3 pin description , some alternate functions can be
remapped on different I/O ports by programming one of the two remapping registers described in the “Routing interface (RI) and system configuration controller” section in the
STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152,
STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031).
DS9178 Rev 4 25/96
41
Memory and register map
5 Memory and register map
STM8L051F3
The following sections describe the mapping of the device’s memory and peripherals.
26/96
The memory map is shown in
Figure 4. Memory map
0x00 0000
RAM including
Stack (512 bytes)
0x00 03FF
0x00 0400
0x00 1FFF
0x00 1000
Reserved
Data EEPRO M
(256 Bytes)
0x00 10FF
0x00 1100
Reserved
0x00 47FF
0x00 4800
0x00 487F
0x00 4880
0x00 4FFF
0x00 5000
0x00 5457
0x00 5458
0x00 5FFF
0x00 6000
Option bytes
Reserved
G PIO and peripheral registers
Reserved
Boot ROM
(2 Kbyt es)
0x00 67FF
0x00 6800
Reserved
0x00 7EFF
0x00 7F00
CPU/ SWIM/ Debug/I TC
Registers
0x00 7FFF
0x00 8000
0x00 80FF
0x00 8100
Reset and int errupt vectors
Low densit y
Flash program memory
(8 Kbyt es)
0x00 9FFF
GPIO ports
Reserved
Flash
Reserved
DMA1
SYSCFG
ITC-EXT1
WFE
ITC-EXT1
Reserved
RST
PWR
Reserved
CLK
Reserved
WWDG
Reserved
IWDG
Reserved
BEEP
Reserved
RTC
Reserved
SPI1
Reserved
I2C1
Reserved
USART1
Reserved
TIM2
Reserved
TIM3
Reserved
TIM4
Reserved
IRTIM
Reserved
ADC1
Reserved
RI
Reserved
RI
0x00 5000
0x00 501E
0x00 5050
0x00 5055
0x00 5070
0x00 509D
0x00 50A0
0x00 50A6
0x00 50AA
0x00 52E0
0x00 52EA
0x00 52FF
0x00 5317
0x00 5340
0x00 53C8
0x00 5430
0x00 5440
0x00 5450
0x00 5457
0x00 50A9
0x00 50B0
0x00 50B2
0x00 50B4
0x00 50C0
0x00 50D1
0x00 50D3
0x00 50D5
0x00 50E0
0x00 50E3
0x00 50F0
0x00 50F4
0x00 5040
0x00 5191
0x00 5200
0x00 5208
0x00 5210
0x00 521F
0x00 5230
0x00 523B
0x00 5250
0x00 5267
0x00 5280
0x00 5297
1.
lists the boundary addresses for each memory size. The top of the stack is at the RAM end
MS18274V3
DS9178 Rev 4
STM8L051F3 Memory and register map address.
for an overview of hardware register mapping, to Table 6
for details on I/O port hardware registers, and to
Table 8 for information on CPU/SWIM/debug module controller registers.
Memory area
Table 5. Flash and RAM boundary addresses
Size Start address End address
RAM
Flash program memory
1 Kbyte
8 Kbytes
0x00 0000
0x00 8000
0x00 03FF
0x00 9FFF
Address
0x00 500C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
0x00 5014 to
0x00 501D
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
Block
Port A
Port B
Port C
Port D
Table 6. I/O port hardware register map
Register label Register name
PA_ODR
PA_IDR
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PB_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
Port A control register 2
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
Port B control register 2
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
Port C control register 2
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
Port D control register 2
Reserved area (0 bytes)
Reset status
0xXX
0x00
0x00
0x00
0x00
0xXX
0x00
0xXX
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0xXX
0x00
0x00
0x00
DS9178 Rev 4 27/96
41
Address
0x00 502E to
0x00 5049
0x00 5050
0x00 5051
0x00 5052
0x00 5053
0x00 5054
0x00 5055 to
0x00 506F
0x00 5070
0x00 5071
0x00 5072 to
0x00 5074
0x00 5075
0x00 5076
0x00 5077
0x00 5078
0x00 5079
0x00 507A
0x00 507B
0x00 507C
Block
Flash
DMA1
Memory and register map STM8L051F3
Table 7. General hardware register map
Register label Register name
Reset status
FLASH_CR1
FLASH_CR2
FLASH _PUKR
FLASH _DUKR
FLASH _IAPSR
Reserved area (44 bytes)
Flash control register 1
Flash control register 2
Flash program memory unprotection key register
Data EEPROM unprotection key register
Flash in-application programming status register
0x00
0x00
0x00
0x00
0x00
DMA1_GCSR
DMA1_GIR1
Reserved area (3 bytes)
DMA1_C0CR
DMA1_C0SPR
DMA1_C0NDTR
DMA1_C0PARH
DMA1_C0PARL
DMA1_C0M0ARH
DMA1_C0M0ARL
Reserved area (27 bytes)
DMA1 global configuration & status register
DMA1 global interrupt register 1
DMA1 channel 0 configuration register
DMA1 channel 0 status & priority register
DMA1 number of data to transfer register
(channel 0)
DMA1 peripheral address high register
(channel 0)
DMA1 peripheral address low register
(channel 0)
Reserved area (1 byte)
DMA1 memory 0 address high register
(channel 0)
DMA1 memory 0 address low register
(channel 0)
0xFC
0x00
0x00
0x00
0x00
0x00
0x00
0x52
0x00
28/96 DS9178 Rev 4
STM8L051F3 Memory and register map
Block
Table 7. General hardware register map (continued)
Register label Register name
0x00 508D
0x00 508E
0x00 508F
0x00 5090
0x00 5091
0x00 5092
0x00 5093
0x00 5094
0x00 5095
0x00 5096
0x00 5097
Address
0x00 507D to
0x00 507E
0x00 507F
0x00 5080
0x00 5081
0x00 5082
0x00 5083
0x00 5084
0x00 5085
0x00 5086
0x00 5087
0x00 5088
0x00 5089
0x00 508A
0x00 508B
0x00 508C
DMA1
DMA1_C1CR
DMA1_C1SPR
DMA1_C1NDTR
DMA1_C1PARH
DMA1_C1PARL
DMA1_C1M0ARH
DMA1_C1M0ARL
DMA1_C2CR
DMA1_C2SPR
DMA1_C2NDTR
DMA1_C2PARH
DMA1_C2PARL
DMA1_C2M0ARH
DMA1_C2M0ARL
DMA1_C3CR
DMA1_C3SPR
DMA1_C3NDTR
DMA1_C3PARH_
C3M1ARH
DMA1_C3PARL_
C3M1ARL
Reserved area (2 bytes)
DMA1 channel 1 configuration register
DMA1 channel 1 status & priority register
DMA1 number of data to transfer register
(channel 1)
DMA1 peripheral address high register
(channel 1)
DMA1 peripheral address low register
(channel 1)
Reserved area (1 byte)
DMA1 memory 0 address high register
(channel 1)
DMA1 memory 0 address low register
(channel 1)
Reserved area (2 bytes)
DMA1 channel 2 configuration register
DMA1 channel 2 status & priority register
DMA1 number of data to transfer register
(channel 2)
DMA1 peripheral address high register
(channel 2)
DMA1 peripheral address low register
(channel 2)
Reserved area (1 byte)
DMA1 memory 0 address high register
(channel 2)
DMA1 memory 0 address low register
(channel 2)
Reserved area (2 bytes)
DMA1 channel 3 configuration register
DMA1 channel 3 status & priority register
DMA1 number of data to transfer register
(channel 3)
DMA1 peripheral address high register
(channel 3)
DMA1 peripheral address low register
(channel 3)
Reset status
0x00
0x00
0x00
0x40
0x00
0x00
0x00
0x00
0x52
0x00
0x00
0x00
0x00
0x52
0x00
0x00
0x00
0x00
0x00
DS9178 Rev 4 29/96
41
Memory and register map STM8L051F3
Address
0x00 5098
0x00 5099
DMA1
0x00 509A
0x00 50A6
0x00 50A7
0x00 50A8
0x00 50A9
0x00 50AA
0x00 50AB
0x00 50A9 to
0x00 50AF
0x00 50B0
0x00 50B1
0x00 50B2
0x00 50B3
0x00 50B4 to
0x00 50BF
0x00 50C0
0x00 50C1
0x00 50C2
0x00 50C3
0x00 509B to
0x00 509C
0x00 509D
0x00 509E
0x00 509F
0x00 50A0
0x00 50A1
0x00 50A2
0x00 50A3
0x00 50A4
0x00 50A5
SYSCFG
ITC - EXTI
WFE
ITC - EXTI
RST
PWR
CLK
Block
Table 7. General hardware register map (continued)
Register label Register name
DMA_C3M0EAR
DMA1_C3M0ARH
DMA1_C3M0ARL
SYSCFG_RMPCR3
SYSCFG_RMPCR1
SYSCFG_RMPCR2
EXTI_CR1
EXTI_CR2
EXTI_CR3
EXTI_SR1
EXTI_SR2
EXTI_CONF1
WFE_CR1
WFE_CR2
WFE_CR3
WFE_CR4
EXTI_CR4
EXTI_CONF2
DMA channel 3 memory 0 extended address register
DMA1 memory 0 address high register
(channel 3)
DMA1 memory 0 address low register
(channel 3)
Reserved area (3 bytes)
Remapping register 3
Remapping register 1
Remapping register 2
External interrupt control register 1
External interrupt control register 2
External interrupt control register 3
External interrupt status register 1
External interrupt status register 2
External interrupt port select register 1
WFE control register 1
WFE control register 2
WFE control register 3
WFE control register 4
External interrupt control register 4
External interrupt port select register 2
RST_CR
RST_SR
PWR_CSR1
PWR_CSR2
CLK_CKDIVR
CLK_CRTCR
CLK_ICKCR
CLK_PCKENR1
Reserved area (7 bytes)
Reset control register
Reset status register
Power control and status register 1
Power control and status register 2
Reserved area (12 bytes)
CLK Clock master divider register
CLK Clock RTC register
CLK Internal clock control register
CLK Peripheral clock gating register 1
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x03
0x11
0x00
30/96 DS9178 Rev 4
STM8L051F3 Memory and register map
Address
0x00 50C4
0x00 50C5
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
0x00 50CA
0x00 50CB
0x00 50CC
0x00 50CD
0x00 50CE
0x00 50CF
0x00 50E3 to
0x00 50EF
0x00 50F0
0x00 50F1
0x00 50F2
0x00 50F3
0x00 50F4 to0x00 513F
0x00 5140
0x00 5141
0x00 5142
0x00 50D0
0x00 50D1 to
0x00 50D2
0x00 50D3
0x00 50D4
0x00 50D5 to
00 50DF
0x00 50E0
0x00 50E1
0x00 50E2
Block
Table 7. General hardware register map (continued)
Register label Register name
CLK
CLK_PCKENR2
CLK_CCOR
CLK_ECKCR
CLK_SCSR
CLK_SWR
CLK_SWCR
CLK_CSSR
CLK_CBEEPR
CLK_HSICALR
CLK_HSITRIMR
CLK_HSIUNLCKR
CLK_REGCSR
CLK_PCKENR3
CLK Peripheral clock gating register 2
CLK Configurable clock control register
CLK External clock control register
CLK System clock status register
CLK System clock switch register
CLK Clock switch control register
CLK Clock security system register
CLK Clock BEEP register
CLK HSI calibration register
CLK HSI clock calibration trimming register
CLK HSI unlock register
CLK Main regulator control status register
CLK Peripheral clock gating register 3
Reset status
0x00
0xXX
0x00
0x00
0bxx11 1
00X
0x00
0x00
0x00
0x00
0x01
0x01
0xX0
0x00
WWDG
WWDG_CR
WWDG_WR
Reserved area (2 bytes)
WWDG control register
WWDR window register
0x7F
0x7F
IWDG
BEEP
RTC
IWDG_KR
IWDG_PR
IWDG_RLR
Reserved area (11 bytes)
IWDG key register
IWDG prescaler register
IWDG reload register
Reserved area (13 bytes)
BEEP_CSR1
BEEP_CSR2
RTC_TR1
RTC_TR2
RTC_TR3
BEEP control/status register 1
Reserved area (2 bytes)
BEEP control/status register 2
Reserved area (76 bytes)
RTC Time register 1
RTC Time register 2
RTC Time register 3
0x01
0x00
0xFF
0x00
0x1F
0x00
0x00
0x00
DS9178 Rev 4 31/96
41
Address
0x00 5143
0x00 5144
0x00 5145
0x00 5146
0x00 5147
0x00 5148
0x00 5149
0x00 514A
0x00 514B
0x00 514C
0x00 514D
0x00 514E
0x00 514F
0x00 5150
0x00 5151
0x00 5152
0x00 5153
0x00 5154
0x00 5155
0x00 5156
0x00 5157
0x00 5158
0x00 5159
0x00 5158
0x00 5159
0x00 515A
0x00 515B
0x00 515C
0x00 515D
0x00 515E
0x00 515F
0x00 5160 to
0x00 5163
0x00 5164
0x00 5165
Memory and register map
Block
Table 7. General hardware register map (continued)
Register label Register name
RTC
RTC_DR1
RTC_DR2
RTC_DR3
RTC_CR1
RTC_CR2
RTC_CR3
RTC_ISR1
RTC_ISR2
RTC_SPRERH
RTC_SPRERL
RTC_APRER
RTC_WUTRH
RTC_WUTRL
RTC_SSRL
RTC_SSRH
RTC_WPR
RTC_SSRH
RTC_WPR
RTC_SHIFTRH
RTC_SHIFTRL
RTC_ALRMAR1
RTC_ALRMAR2
RTC_ALRMAR3
RTC_ALRMAR4
RTC_ALRMASSRH
RTC_ALRMASSRL
Reserved area (1 byte)
RTC Date register 1
RTC Date register 2
RTC Date register 3
Reserved area (1 byte)
RTC Control register 1
RTC Control register 2
RTC Control register 3
Reserved area (1 byte)
RTC Initialization and status register 1
RTC Initialization and Status register 2
Reserved area (2 bytes)
RTC Synchronous prescaler register high
RTC Synchronous prescaler register low
RTC Asynchronous prescaler register
Reserved area (1 byte)
RTC Wakeup timer register high
RTC Wakeup timer register low
Reserved area (1 byte)
RTC Subsecond register low
RTC Subsecond register high
RTC Write protection register
RTC Subsecond register high
RTC Write protection register
RTC Shift register high
RTC Shift register low
RTC Alarm A register 1
RTC Alarm A register 2
RTC Alarm A register 3
RTC Alarm A register 4
Reserved area (4 bytes)
RTC Alarm A subsecond register high
RTC Alarm A subsecond register low
STM8L051F3
Reset status
0x01
0x21
0x00
0x01
0x00
0x00
(1)
0x7F
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
32/96 DS9178 Rev 4
STM8L051F3 Memory and register map
Address
0x00 5166
0x00 5167 to
0x00 5169
0x00 516A
0x00 516B
0x00 516C
0x00 516D
0x00 516E to
0x00 518A
0x00 5190
0x00 519A to
0x00 51FF
0x00 5200
0x00 5201
0x00 5202
0x00 5203
0x00 5204
0x00 5205
0x00 5206
0x00 5207
0x00 5208 to
0x00 520F
0x00 5210
0x00 5211
0x00 5212
0x00 5213
0x00 5214
0x00 5215
0x00 5216
0x00 5217
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
Block
Table 7. General hardware register map (continued)
Register label Register name
RTC
SPI1
RTC_ALRMASSMSKR
RTC_CALRH
RTC_CALRL
RTC_TCR1
RTC_TCR2
RTC Alarm A masking register
Reserved area (3 bytes)
RTC Calibration register high
RTC Calibration register low
RTC Tamper control register 1
RTC Tamper control register 2
CSSLSE_CSR
Reserved area (36 bytes)
CSS on LSE control and status register
SPI1_CR1
SPI1_CR2
SPI1_ICR
SPI1_SR
SPI1_DR
SPI1_CRCPR
SPI1_RXCRCR
SPI1_TXCRCR
Reserved area (111 bytes)
SPI1 control register 1
SPI1 control register 2
SPI1 interrupt control register
SPI1 status register
SPI1 data register
SPI1 CRC polynomial register
SPI1 Rx CRC register
SPI1 Tx CRC register
I2C1
I2C1_CR1
I2C1_CR2
I2C1_FREQR
I2C1_OARL
I2C1_OARH
I2C1_OAR2
I2C1_DR
I2C1_SR1
I2C1_SR2
I2C1_SR3
I2C1_ITR
I2C1_CCRL
I2C1_CCRH
Reserved area (8 bytes)
I2C1 control register 1
I2C1 control register 2
I2C1 frequency register
I2C1 own address register low
I2C1 own address register high
I2C1 own address register for dual mode
I2C1 data register
I2C1 status register 1
I2C1 status register 2
I2C1 status register 3
I2C1 interrupt control register
I2C1 clock control register low
I2C1 clock control register high
Reset status
0x00
0x00
0x00
0x02
0x00
0x07
0x00
0x00
0x00
0x00
0x00
0x0X
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DS9178 Rev 4 33/96
41
Memory and register map
Address
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
0x00 525C
0x00 525D
0x00 525E
0x00 525F
0x00 521D
0x00 521E
0x00 521F to
0x00 522F
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5237
0x00 5238
0x00 5239
0x00 523A
0x00 523B to
0x00 524F
0x00 5250
Block
Table 7. General hardware register map (continued)
Register label Register name
I2C1
I2C1_TRISER
I2C1_PECR
I2C1 TRISE register
I2C1 packet error checking register
USART1
TIM2
TIM2_CR1
TIM2_CR2
TIM2_SMCR
TIM2_ETR
TIM2_DER
TIM2_IER
TIM2_SR1
TIM2_SR2
TIM2_EGR
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCER1
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
USART1_SR
USART1_DR
USART1_BRR1
USART1_BRR2
USART1_CR1
USART1_CR2
USART1_CR3
USART1_CR4
USART1_CR5
USART1_GTR
USART1_PSCR
Reserved area (17 bytes)
USART1 status register
USART1 data register
USART1 baud rate register 1
USART1 baud rate register 2
USART1 control register 1
USART1 control register 2
USART1 control register 3
USART1 control register 4
USART1 control register 5
USART1 guard time register
USART1 prescaler register
Reserved area (21 bytes)
TIM2 control register 1
TIM2 control register 2
TIM2 Slave mode control register
TIM2 external trigger register
TIM2 DMA1 request enable register
TIM2 interrupt enable register
TIM2 status register 1
TIM2 status register 2
TIM2 event generation register
TIM2 capture/compare mode register 1
TIM2 capture/compare mode register 2
TIM2 capture/compare enable register 1
TIM2 counter high
TIM2 counter low
TIM2 prescaler register
TIM2 auto-reload register high
STM8L051F3
Reset status
0x02
0x00
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
34/96 DS9178 Rev 4
Address
0x00 5288
0x00 5289
0x00 528A
0x00 528B
0x00 528C
0x00 528D
0x00 528E
0x00 528F
0x00 5290
0x00 5291
0x00 5292
0x00 5293
0x00 5294
0x00 5295
0x00 5296
0x00 5297 to
0x00 52DF
0x00 5260
0x00 5261
0x00 5262
0x00 5263
0x00 5264
0x00 5265
0x00 5266
0x00 5267 to
0x00 527F
0x00 5280
0x00 5281
0x00 5282
0x00 5283
0x00 5284
0x00 5285
0x00 5286
0x00 5287
STM8L051F3 Memory and register map
Block
Table 7. General hardware register map (continued)
Register label Register name
TIM2
TIM3
TIM2_ARRL
TIM2_CCR1H
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2_BKR
TIM2_OISR
TIM3_CR1
TIM3_CR2
TIM3_SMCR
TIM3_ETR
TIM3_DER
TIM3_IER
TIM3_SR1
TIM3_SR2
TIM3_EGR
TIM3_CCMR1
TIM3_CCMR2
TIM3_CCER1
TIM3_CNTRH
TIM3_CNTRL
TIM3_PSCR
TIM3_ARRH
TIM3_ARRL
TIM3_CCR1H
TIM3_CCR1L
TIM3_CCR2H
TIM3_CCR2L
TIM3_BKR
TIM3_OISR
TIM2 auto-reload register low
TIM2 capture/compare register 1 high
TIM2 capture/compare register 1 low
TIM2 capture/compare register 2 high
TIM2 capture/compare register 2 low
TIM2 break register
TIM2 output idle state register
Reserved area (25 bytes)
TIM3 control register 1
TIM3 control register 2
TIM3 Slave mode control register
TIM3 external trigger register
TIM3 DMA1 request enable register
TIM3 interrupt enable register
TIM3 status register 1
TIM3 status register 2
TIM3 event generation register
TIM3 Capture/Compare mode register 1
TIM3 Capture/Compare mode register 2
TIM3 Capture/Compare enable register 1
TIM3 counter high
TIM3 counter low
TIM3 prescaler register
TIM3 Auto-reload register high
TIM3 Auto-reload register low
TIM3 Capture/Compare register 1 high
TIM3 Capture/Compare register 1 low
TIM3 Capture/Compare register 2 high
TIM3 Capture/Compare register 2 low
TIM3 break register
TIM3 output idle state register
Reserved area (72 bytes)
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Reset status
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
DS9178 Rev 4 35/96
41
Address
0x00 52FF
0x00 5317 to
0x00 533F
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
0x00 5347
0x00 5348
0x00 5349
0x00 534A
0x00 534B
0x00 52E0
0x00 52E1
0x00 52E2
0x00 52E3
0x00 52E4
0x00 52E5
0x00 52E6
0x00 52E7
0x00 52E8
0x00 52E9
0x00 52EA to
0x00 52FE
0x00 534C
0x00 534D
0x00 534E
0x00 534F
0x00 5350
0x00 5351
Memory and register map
Block
Table 7. General hardware register map (continued)
Register label Register name
TIM4
TIM4_CR1
TIM4_CR2
TIM4_SMCR
TIM4_DER
TIM4_IER
TIM4_SR1
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 control register 1
TIM4 control register 2
TIM4 Slave mode control register
TIM4 DMA1 request enable register
TIM4 Interrupt enable register
TIM4 status register 1
TIM4 Event generation register
TIM4 counter
TIM4 prescaler register
TIM4 Auto-reload register
IRTIM
ADC1
IR_CR
Reserved area (21 bytes)
Infrared control register
ADC1_CR1
ADC1_CR2
ADC1_CR3
ADC1_SR
ADC1_DRH
ADC1_DRL
ADC1_HTRH
ADC1_HTRL
ADC1_LTRH
ADC1_LTRL
ADC1_SQR1
ADC1_SQR2
ADC1_SQR3
ADC1_SQR4
ADC1_TRIGR1
ADC1_TRIGR2
ADC1_TRIGR3
ADC1_TRIGR4
Reserved area (41 bytes)
ADC1 configuration register 1
ADC1 configuration register 2
ADC1 configuration register 3
ADC1 status register
ADC1 data register high
ADC1 data register low
ADC1 high threshold register high
ADC1 high threshold register low
ADC1 low threshold register high
ADC1 low threshold register low
ADC1 channel sequence 1 register
ADC1 channel sequence 2 register
ADC1 channel sequence 3 register
ADC1 channel sequence 4 register
ADC1 trigger disable 1
ADC1 trigger disable 2
ADC1 trigger disable 3
ADC1 trigger disable 4
STM8L051F3
0x00
0x0F
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x1F
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
36/96 DS9178 Rev 4
STM8L051F3 Memory and register map
Block
Table 7. General hardware register map (continued)
Register label Register name Address
0x00 53C8 to
0x00 542F
0x00 5430
0x00 5433
0x00 5434
0x00 5435
0x00 5436
0x00 5437
0x00 5438
0x00 5439
0x00 543A
0x00 543B
0x00 543C
0x00 543D
0x00 543E
0x00 543F
0x00 5440 to
0x00 544F
0x00 5450
0x00 5451
0x00 5452
0x00 5453
0x00 5454
0x00 5455
RI
RI
RI_IOIR1
RI_IOIR2
RI_IOIR3
RI_IOCMR1
RI_IOCMR2
RI_IOCMR3
RI_IOSR1
RI_IOSR2
RI_IOSR3
RI_IOGCR
RI_ASCR1
RI_ASCR2
RI_RCR
RI_CR
RI_MASKR1
RI_MASKR2
RI_MASKR3
RI_MASKR4
RI_IOIR4
Reserved area(104 bytes)
Reserved area (1 byte)
RI I/O input register 1
RI I/O input register 2
RI I/O input register 3
RI I/O control mode register 1
RI I/O control mode register 2
RI I/O control mode register 3
RI I/O switch register 1
RI I/O switch register 2
RI I/O switch register 3
RI I/O group control register
Analog switch register 1
RI Analog switch register 2
RI Resistor control register
Reserved area (16 bytes)
RI I/O control register
RI I/O mask register 1
RI I/O mask register 2
RI I/O mask register 3
RI I/O mask register 4
RI I/O input register 4
0x00 5456
0x00 5457
RI_IOCMR4
RI_IOSR4
RI I/O control mode register 4
RI I/O switch register 4
1. These registers are not impacted by a system reset. They are reset at power-on.
Reset status
0x00
0x00
0x00
0x00
0x00
0xXX
0x00
0x00
0x00
0x00
0x00
0xFF
0x00
0x00
0x00
0x00
0xXX
0xXX
0xXX
0x00
0x00
0x00
DS9178 Rev 4 37/96
41
Memory and register map
Address
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
0x00 7F0B to
0x00 7F5F
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76
0x00 7F77
0x00 7F78 to
0x00 7F79
0x00 7F80
0x00 7F81 to
0x00 7F8F
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
Table 8. CPU/SWIM/debug module/interrupt controller registers
Block Register label Register name
CPU
(1)
CPU
ITC-SPR
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
A
PCE
PCH
PCL
XH
XL
YH
YL
SPH
SPL
CCR
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
Stack pointer low
Condition code register
Reserved area (85 bytes)
Global configuration register
Interrupt Software priority register 1
Interrupt Software priority register 2
Interrupt Software priority register 3
Interrupt Software priority register 4
Interrupt Software priority register 5
Interrupt Software priority register 6
Interrupt Software priority register 7
Interrupt Software priority register 8
SWIM
DM
SWIM_CSR
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
Reserved area (2 bytes)
SWIM control status register
Reserved area (15 bytes)
DM breakpoint 1 register extended byte
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
DM breakpoint 2 register extended byte
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
DM Debug module control register 1
STM8L051F3
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0xFF
0x28
38/96 DS9178 Rev 4
STM8L051F3 Memory and register map
Address
Table 8. CPU/SWIM/debug module/interrupt controller registers (continued)
Block Register label Register name
0x00 7F97
0x00 7F98
0x00 7F99
0x00 7F9A
0x00 7F9B to
0x00 7F9F
DM
1. Accessible by debug module only
DM_CR2
DM_CSR1
DM_CSR2
DM_ENFCTR
DM Debug module control register 2
DM Debug module control/status register 1
DM Debug module control/status register 2
DM enable function register
Reserved area (5 bytes)
Reset status
0x00
0x10
0x00
0xFF
DS9178 Rev 4 39/96
41
Interrupt vector mapping
6 Interrupt vector mapping
STM8L051F3
The interrupt vector mapping is described in
.
12
13
14
15
16
5
6
7
8
9
10
11
IRQ
No.
0
1
2
3
4
17
18
I
Source block
Description
Table 9. Interrupt mapping
Wakeup from Halt mode
Wakeup from
Active-halt mode
Wakeup from Wait
(WFI mode)
PVD
EXTIB
EXTID
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
EXTI5
EXTI6
EXTI7
RESET Reset
TRAP
TLI (2)
Software interrupt
External Top level Interrupt
FLASH
DMA1 0/1
DMA1 2/3
RTC
FLASH end of programing/ write attempted to protected page interrupt
DMA1 channels 0/1 half transaction/transaction complete interrupt
DMA1 channels 2/3 half transaction/transaction complete interrupt
RTC alarm A/wakeup/ tamper 1/tamper 2/tamper 3
PVD interrupt
External interrupt port B
External interrupt port D
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
External interrupt 7
Yes
-
-
-
-
-
Yes
Yes
Yes
Yes
Yes
Reserved
Yes
Yes
Yes
Yes
Yes
Yes
Yes
CLK
ADC1
CLK system clock switch/CSS interrupt
ACD1 end of conversion/ analog watchdog/ overrun interrupt
-
Yes
Yes
-
-
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Wakeup from Wait
(WFE mode)
(1)
Yes
-
-
Vector address
0x00 8000
0x00 8004
0x00 8008
Yes
Yes
Yes
Yes
Yes
Yes
0x00 800C
0x00 8010
0x00 8014
0x00 8018
0x00 804C
0x00 8050
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
0x00 8034
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
40/96 DS9178 Rev 4
STM8L051F3 Interrupt vector mapping
IRQ
No.
Source block
Table 9. Interrupt mapping (continued)
Description
Wakeup from Halt mode
Wakeup from
Active-halt mode
Wakeup from Wait
(WFI mode)
Wakeup from Wait
(WFE mode)
(1)
Vector address
19
20
21
22
TIM2
TIM2
TIM3
TIM3
TIM2 update
/overflow/trigger/break interrupt
TIM2 Capture/Compare interrupt
TIM3 Update
/Overflow/Trigger/Break interrupt
TIM3 Capture/Compare interrupt
RI trigger interrupt
-
-
-
-
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0x00 8054
0x00 8058
0x00 805C
0x00 8060
23
24
RI -
Reserved
Yes 0x00 8064
0x00 8068
25
26
27
28
TIM4
SPI1
USART 1
USART 1
TIM4 update/overflow/ trigger interrupt
SPI1 TX buffer empty/
RX buffer not empty/ error/wakeup interrupt
USART1 transmit data register empty/ transmission complete interrupt
USART1 received data ready/overrun error/ idle line detected/parity error/global error interrupt
I2C1 interrupt
(3)
-
Yes
-
-
-
Yes
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0x00 806C
0x00 8070
0x00 8074
0x00 8078
29 I2C1 Yes Yes Yes Yes 0x00 807C
1. The Low-power wait mode is entered when executing a WFE instruction in Low-power run mode. In WFE mode, the interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode.
When the interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.
2. The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts.
3. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.
DS9178 Rev 4 41/96
41
Option bytes STM8L051F3
Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated memory block.
All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM
for details on option byte addresses.
The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for the ROP and UBCvalues which can only be taken into account when they are modified in
ICP mode (with the SWIM).
Refer to the How to program STM8L and STM8AL Flash program memory and data
EEPROM programming manual (PM0054) and the STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures.
Addr.
Option name
Option byte
No.
Table 10. Option byte addresses
Option bits
7 6 5 4 3
0x00 4800
0x00 4802
Read-out protection
(ROP)
UBC (User
Boot code size)
0x00 4807
0x00 4808
0x00 4809
0x00 480A
0x00 480B
0x00 480C
OPT0
OPT1
Independent watchdog option
Number of stabilization clock cycles for
HSE and LSE oscillators
Brownout reset
(BOR)
Bootloader option bytes
(OPTBL)
OPT3
[3:0]
OPT4
OPT5
[3:0]
OPTBL
[15:0]
Reserved
Reserved
Reserved
Reserved
ROP[7:0]
UBC[7:0]
WWDG
_HALT
WWDG
_HW
IWDG
_HALT
LSECNT[1:0]
BOR_TH
OPTBL[15:0]
2 1 0
IWDG
_HW
HSECNT[1:0]
BOR_
ON
Factory default setting
0xAA
0x00
0x00
0x00
0x00
0x00
0x00
0x00
42/96 DS9178 Rev 4
STM8L051F3 Option bytes
Table 11. Option byte description
Option byte
No.
Option description
OPT0
ROP[7:0] Memory readout protection (ROP)
0xAA: Disable readout protection (write access via SWIM protocol)
Refer to the “Readout protection” section in the STM8L050J3, STM8L051F3, STM8L052C6,
STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031).
OPT1
UBC[7:0] Size of the user boot code area
0x00: UBC is not protected.
0x01: Page 0 is write protected.
0x02: Page 0 and 1 reserved for the UBC and write protected. It covers only the interrupt vectors.
0x03: Page 0 to 2 reserved for UBC and write protected.
0x7F to 0xFF - All 128 pages reserved for UBC and write protected.
The protection of the memory area not protected by the UBC is enabled through the MASS keys.
Refer to the “User boot code” section in the STM8L050J3, STM8L051F3, STM8L052C6,
STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031).
OPT2 Reserved
IWDG_HW: Independent watchdog
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
IWDG_HALT: Independent window watchdog off on Halt/Active-halt
0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode
OPT3
WWDG_HW: Window watchdog
0: Window watchdog activated by software
1: Window watchdog activated by hardware
WWDG_HALT: Window window watchdog reset on Halt/Active-halt
0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode
OPT4
HSECNT : Number of HSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
LSECNT : Number of LSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
Refer to
Table 29: LSE oscillator characteristics on page 62
.
DS9178 Rev 4 43/96
44
Option bytes STM8L051F3
Table 11. Option byte description (continued)
Option byte
No.
Option description
OPT5
OPTBL
BOR_ON :
0: Brownout reset off
1: Brownout reset on
BOR_TH[3:1] : Brownout reset thresholds. Refer to for details on the thresholds according to the value of BOR_TH bits.
OPTBL[15:0] :
This option is checked by the boot ROM code after reset. Depending on content of addresses 00 480B, 00 480C and 0x8000 (reset vector) the
CPU jumps to the bootloader or to the reset vector.
Refer to the UM0560 STM8 bootloader user manual for more details.
44/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
This section describes the quantification of the given device’s parameters.
8.1.1
Unless otherwise specified, all voltages are referred to V
SS
.
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
A the selected temperature range).
= 25 °C and T
A
= T
A max (given by
Data based on characterization results, design simulation and/or technology characteristics is indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 Σ ).
Unless otherwise specified, typical data is based on T
A design guidelines and is not tested.
= 25 °C, V
DD
= 3 V. It is given only as
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 Σ )
.
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
The loading conditions used for pin parameter measurement are shown in
.
Figure 5. Pin loading conditions
STM8 PIN
50 pF
MSv37774V1
DS9178 Rev 4 45/96
87
Electrical parameters
8.1.5 Pin input voltage
STM8L051F3
The input voltage measurement on a pin of the device is described in
Figure 6. Pin input voltage
STM8 PIN
V
IN
MSv37775V1
8.2
46/96
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in
Table 12: Voltage characteristics
,
Table 13: Current characteristics
, and
Table 14: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device's reliability.
The device's mission profile (application conditions) is compliant with the JEDEC JESD47
Qualification Standard, extended mission profiles are available on demand.
Symbol
Table 12. Voltage characteristics
Ratings Min Max Unit
V
DD
V
V
- V
IN
(2)
ESD
SS
External supply voltage (including V
DDA and V
DD2
)
(1)
Input voltage on true open-drain pins
(PC0 and PC1)
Input voltage on five-volt tolerant (FT) pins (PA7 and PE0)
Input voltage on 3.6 V tolerant (TT) pins
Input voltage on any other pin
Electrostatic discharge voltage
V
V
- 0.3
SS
SS
- 0.3
- 0.3
V
V
DD
4.0
DD
+ 4.0
+ 4.0
V
SS
- 0.3
4.0
V
SS
- 0.3
4.0
see Absolute maximum ratings (electrical sensitivity) on page 86
V
V
1. All power (V , V external power supply.
, V
DDA
) and ground (V
SS1
, V
SS2
, V
SSA
) pins must always be connected to the
2. V
IN
maximum must always be respected. Refer to
Table 13: Current characteristics for maximum allowed
injected current values.
Symbol
I
VDD
I
VSS
Table 13. Current characteristics
Ratings
Total current into V
DD power line (source)
Total current out of V
SS ground line (sink)
Max.
80
80
Unit mA
DS9178 Rev 4
STM8L051F3 Electrical parameters
Symbol
Table 13. Current characteristics (continued)
Ratings Max.
Unit
I
IO
Output current sunk by IR_TIM pin (with high sink LED driver capability)
Output current sunk by any other I/O and control pin
Output current sourced by any I/Os and control pin
80
25
- 25
I
INJ(PIN)
Injected current on true open-drain pins (PC0 and PC1)
(1)
Injected current on five-volt tolerant (FT) pins (PA7 and PE0)
Injected current on 3.6 V tolerant (TT) pins
Injected current on any other pin
(2)
Total injected current (sum of all I/O and control pins)
(3)
- 5 / +0
- 5 / +0
- 5 / +0
- 5 / +5
Σ I
INJ(PIN)
± 25
1. Positive injection is not possible on these I/Os. A negative injection is induced by V
IN
<V
SS
. I
INJ(PIN)
must never be exceeded. Refer to
Table 13: Current characteristics
for maximum allowed input voltage values.
2. A positive injection is induced by V
IN
>V
DD
while a negative injection is induced by V
IN
<V
SS
. I
INJ(PIN)
must never be exceeded. Refer to
Table 13: Current characteristics
for maximum allowed input voltage values.
3. When several inputs are submitted to a current injection, the maximum Σ I positive and negative injected currents (instantaneous values).
INJ(PIN)
is the absolute sum of the
Symbol
T
STG
T
J
Table 14. Thermal characteristics
Ratings Value
Storage temperature range
Maximum junction temperature
-65 to +150
150
Unit
° C
DS9178 Rev 4 47/96
87
Electrical parameters STM8L051F3
8.3.1
Subject to general operating conditions for V
DD
and T
A
.
General operating conditions
The operating conditions define the conditions under which the device operates correctly according to its specification (see
Symbol Parameter
Table 15. General operating conditions
Conditions Min.
Max.
Unit f
SYSCLK
(1)
V
DD
V
DDA
P
D
(2)
T
A
T
J
System clock frequency
Standard operating voltage
Analog operating voltage
Power dissipation at
T
A
= 85 °C
Temperature range
Junction temperature range
1.8 V ≤ V
DD
< 3.6 V
-
Must be at the same potential as V
DD
TSSOP20
1.8 V ≤ V
DD
< 3.6 V
-40 °C ≤ T
A
< 85 °C
0
1.8
1.8
-
-40
-40
16
3.6
3.6
181
85
105
(3)
MHz
V
V mW
°C
°C
1. f
SYSCLK
= f
CPU
2. To calculate P table.
Dmax
(T
A
), use the formula P
Dmax
=(T
Jmax
-T
A
)/ Θ
JA
with T
Jmax
in this table and Θ
JA in “Thermal characteristics”
3. T
Jmax
is given by the test limit. Above this value, the product behavior is not guaranteed.
48/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
8.3.2 Embedded reset and power control block characteristics
The reset and power block parameters are described in Table 16
and are derived from tests performed under the ambient temperature conditions summarized in
Table 15: General operating conditions
.
Table 16. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max t
V
V
V
V
V
V
V
V
V
V
V
V t
VDD
TEMP
V
PDR
BOR0
BOR1
BOR2
BOR3
BOR4
PVD0
PVD1
PVD2
PVD3
PVD4
PVD5
PVD6
V
V
DD
DD
rise time rate
fall time rate
BOR detector enabled
BOR detector enabled
Reset release delay V
DD
rising
Power-down reset threshold Falling edge
Brown-out reset threshold 0
(BOR_TH[2:0]=000)
Brown-out reset threshold 1
(BOR_TH[2:0]=001)
Falling edge
Rising edge
Falling edge
Rising edge
Brown-out reset threshold 2
(BOR_TH[2:0]=010)
Brown-out reset threshold 3
(BOR_TH[2:0]=011)
Brown-out reset threshold 4
(BOR_TH[2:0]=100)
PVD threshold 0
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
PVD threshold 5
PVD threshold 6
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
1. Guaranteed by design.
2. Guaranteed by characterization results.
0
(1)
1.80
1.88
1.98
2.08
2.45
2.54
2.68
2.78
-
1.30
(2)
1.67
1.69
1.87
1.96
2.22
2.31
2.57
2.68
2.77
2.87
2.2
2.28
2.39
2.47
2.97
3.08
-
∞
∞
3
1.84
1.94
2.04
2.14
2.55
2.66
2.80
2.90
1.50
1.70
1.75
1.93
2.04
2.3
2.41
2.64
2.74
2.83
2.94
2.24
2.34
2.44
2.54
3.05
3.15
Unit
µs/V
ms
2.69
2.79
2.88
2.99
2.28
2.38
2.48
2.58
3.09
3.20
1.88
1.99
2.09
2.18
2.60
2.7
2.85
2.95
1.65 V
1.74
1.80
1.97
2.07
2.35
2.44
V
V
DS9178 Rev 4 49/96
87
Electrical parameters
V
DD
3.6 V
1.8 V
BOR threshold
STM8L051F3
Figure 7. POR/BOR thresholds
V
DD
V
DD without BOR = battery life extension
Operatin g power supply
BOR threshold_0
PDR threshold
VBOR0
VPDR
Internal NRST
BOR always active at power up with
BOR with
BOR without
BOR
BOR activated by user for power-down detection
Time ai17033b
8.3.3 Supply current characteristics
Total current consumption
The MCU is placed under the following conditions:
• All I/O pins in input mode with a static value at V
DD
or V
SS
(no load)
• All peripherals are disabled except if explicitly mentioned.
In the following table, data is based on characterization results, unless otherwise specified.
Subject to general operating conditions for V
DD
and T
A
.
50/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
Table 17. Total current consumption in Run mode
Symbol
Para meter
Conditions
(1) Typ
Max
55 °C 85 °C
HSI RC osc.
(16 MHz)
(3) f
CPU
= 125 kHz f
CPU
= 1 MHz f
CPU
= 4 MHz f
CPU
= 8 MHz
I
DD(RUN)
Supply current in run mode
(2)
All peripherals
OFF, code executed from RAM,
V
DD
from
1.8 V to 3.6 V
HSE external clock
(f
CPU
=f
HSE
)
(4) f
CPU
= 16 MHz f
CPU
= 125 kHz f
CPU
= 1 MHz f
CPU
= 4 MHz f
CPU
= 8 MHz f
CPU
= 16 MHz
LSI RC osc.
(typ. 38 kHz)
LSE external clock
(32.768 kHz) f f
CPU
CPU
= f
= f
LSI
LSE f
CPU
= 125 kHz f
CPU
= 1 MHz
HSI RC osc.
(6) f
CPU
= 4 MHz f
CPU
= 8 MHz
I
DD(RUN)
Supply current in Run mode
All peripherals
OFF, code executed from Flash,
V
DD
from
1.8 V to 3.6 V
HSE external clock
(f
CPU
=f
HSE
f
CPU
= 16 MHz f
CPU
= 125 kHz f
CPU
= 1 MHz f
CPU
= 4 MHz f
CPU
= 8 MHz f
CPU
= 16 MHz
LSI RC osc.
f
CPU
= f
LSI
LSE ext. clock
(32.768 kHz)
(7) f
CPU
= f
LSE
0.39
0.48
0.75
1.10
0.05
0.18
0.55
0.99
0.040 0.045
1. All peripherals OFF, V
DD
from 1.8 V to 3.6 V, HSI internal RC osc. , f
CPU
=f
SYSCLK
2. CPU executing typical data processing
3. The run from RAM consumption can be approximated with the linear formula:
I
DD
(run_from_RAM) = Freq * 90 µA/MHz + 380 µA
0.47
0.56
0.84
1.20
0.49
0.58
0.86
1.25
1.85
1.93
2.12
0.06
0.19
0.62
1.20
0.09
0.20
0.64
1.21
1.90
2.22
2.23
(5)
0.046
0.035 0.040 0.048
0.43
0.60
1.11
1.90
3.8
0.30
0.40
1.15
2.17
4.0
0.55
0.77
1.34
2.20
4.60
0.36
0.50
1.31
2.33
4.46
0.110 0.123
0.100 0.101
0.56
0.80
1.37
2.23
4.75
0.39
0.52
1.40
2.44
4.52
0.130
0.104
Unit mA mA
DS9178 Rev 4 51/96
87
Electrical parameters STM8L051F3
4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption
(I
DD HSE
) must be added. Refer to Table 28 .
5. Tested in production.
6. The run from Flash consumption can be approximated with the linear formula:
I
DD
(run_from_Flash) = Freq * 195 µA/MHz + 440 µA
7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption
(I
DD LSE
) must be added. Refer to
.
Figure 8. Typ. I
DD(RUN)
vs. V
DD
, f
CPU
= 16 MHz
3.00
2.75
-40°C
25°C
85°C
2.50
2.25
2.00
1.75
1.50
1.8
2.1
2.6
V
DD
[V]
3.1
3.6
ai18213b
1. Typical current consumption measured with code executed from RAM
52/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
In the following table, data is based on characterization results, unless otherwise specified.
Table 18. Total current consumption in Wait mode
Symbol Parameter Conditions
(1) Typ
Max
55°C 85°C
Unit
I
I
DD(Wait)
DD(Wait)
Supply current in
Wait mode
Supply current in
Wait mode
CPU not clocked, all peripherals
OFF, code executed from RAM with Flash in
I
DDQ
V
DD
mode
from
(2)
,
1.8 V to 3.6 V
CPU not clocked, all peripherals
OFF, code executed from Flash,
V
DD
from
1.8 V to 3.6 V
HSI f
CPU
= 125 kHz 0.33
0.39
0.41
f
CPU
= 1 MHz 0.35
0.41
0.44
f
CPU
= 4 MHz f
CPU
= 8 MHz
0.42
0.52
0.51
0.57
0.52
0.58
HSE external clock
(f
CPU
=f
HSE
)
(3) f
CPU
= 16 MHz 0.68
0.76
0.79
f
CPU
= 125 kHz 0.032 0.056 0.068
f
CPU
= 1 MHz 0.078 0.121 0.144
f
CPU
= 4 MHz 0.218 0.26
0.30
f
CPU
= 8 MHz 0.40
0.52
0.57
f
CPU
= 16 MHz 0.760 1.01
1.05
LSI f
CPU
= f
LSI
external clock
(32.768 kHz) f
CPU
= f
LSE
0.035 0.044 0.046
0.032 0.036 0.038
HSI f
CPU
= 125 kHz 0.38
0.48
0.49
f
CPU
= 1 MHz 0.41
0.49
0.51
f
CPU
= 4 MHz f
CPU
= 8 MHz
0.50
0.60
0.57
0.66
0.58
0.68
f
CPU
= 16 MHz 0.79
0.84
0.86
f
CPU
= 125 kHz 0.06
0.08
0.09
external clock
(f
CPU
=HSE) f
CPU
= 1 MHz f
CPU
= 4 MHz f
CPU
= 8 MHz
0.10
0.24
0.50
0.17
0.36
0.58
0.18
0.39
0.61
LSI f
CPU
= 16 MHz 1.00
1.08
1.14
f
CPU
= f
LSI
0.055 0.058 0.065
LSE
(4) external clock
(32.768 kHz) f
CPU
= f
LSE
0.051 0.056 0.060
mA mA
1. All peripherals OFF, V
DD
from 1.8 V to 3.6 V, HSI internal RC osc. , f
CPU
= f
SYSCLK
2. Flash is configured in I
DDQ
mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register.
DD HSE
) must be added. Refer to Table 28 .
DS9178 Rev 4 53/96
87
Electrical parameters STM8L051F3
DD HSE
) must be added. Refer to Table 29 .
Figure 9. Typ. I
DD(Wait) vs. V
DD
, f
CPU
= 16 MHz 1)
1000
950
900
850
800
750
700
650
600
550
500
1.8
2.1
2.6
V
DD
[V]
3.1
-40°C
25°C
85°C
3.6
1. Typical current consumption measured with code executed from Flash memory.
ai18214b
54/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
In the following table, data is based on characterization results, unless otherwise specified.
Symbol
Table 19. Total current consumption and timing in Low power run mode
at V
DD
= 1.8 V to 3.6 V
Parameter Conditions
(1) Typ Max Unit
T
A
= -40 °C to 25 °C 5.1
5.4
LSI RC osc.
(at 38 kHz) all peripherals OFF T
A
= 55 °C
T
A
= 85 °C
5.7
6.8
6
7.5
T
A
= -40 °C to 25 °C 5.4
5.7
I
DD(LPR)
Supply current in
Low power run mode with TIM2 active
(2) T
A
= 55 °C
T
A
= 85 °C
6.0
7.2
6.3
7.8
T
A
= -40 °C to 25 °C 5.25 5.6
LSE
(3)
external clock
(32.768 kHz) all peripherals OFF T
A
= 55 °C
T
A
= 85 °C
5.67 6.1
5.85 6.3
T
A
= -40 °C to 25 °C 5.59
6
T
A
= 55 °C
T
A
= 85 °C
6.10 6.4
6.30
1. No floating I/Os
2. Timer 2 clock enabled and counter running
3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption
(I
DD LSE
) must be added. Refer to Table 29
7
μ A
Figure 10. Typ. I
DD(LPR) vs. V
DD
(LSI clock source)
18
16
14
12
6
4
2
10
8
0
1.8
2.1
2.6
V
DD
[V]
3.1
-40° C
25° C
85° C
3.6
ai18216b
DS9178 Rev 4 55/96
87
Electrical parameters STM8L051F3
In the following table, data is based on characterization results, unless otherwise specified.
Symbol
Table 20. Total current consumption in Low power wait mode at V
DD
= 1.8 V to 3.6 V
Parameter Conditions
(1) Typ Max Unit
LSI RC osc.
(at 38 kHz) all peripherals OFF
T
A
= -40 °C to 25 °C 3 3.3
T
A
= 55 °C 3.3
3.6
T
A
= 85 °C 4.4
5
T
A
= -40 °C to 25 °C 3.4
3.7
I
DD(LPW)
Supply current in
Low power wait mode with TIM2 active
(2)
T
A
= 55 °C
T
A
= 85 °C
3.7
4.8
4
5.4
T
A
= -40 °C to 25 °C 2.35 2.7
LSE external clock
(3)
(32.768 kHz) all peripherals OFF with TIM2 active
T
A
= 55 °C
T
A
= 85 °C
2.42 2.82
3.10 3.71
T
A
= -40 °C to 25 °C 2.46 2.75
T
A
= 55 °C
T
A
= 85 °C
2.50 2.81
3.16 3.82
1. No floating I/Os.
2. Timer 2 clock enabled and counter is running.
3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption
(I
DD LSE
) must be added. Refer to
μ A
Figure 11. Typ. I
DD(LPW) vs. V
DD
(LSI clock source)
16.00
14.00
12.00
10.00
8.00
6.00
4.00
2.00
0.00
1.8
2.1
2.6
V
DD
[V]
3.1
-40°C
25°C
85°C
3.6
ai18217b
56/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
In the following table, data is based on characterization results, unless otherwise specified.
Table 21. Total current consumption and timing in Active-halt mode at V
DD
= 1.8 V to 3.6 V
Symbol Parameter Conditions
(1) Typ Max Unit
I
DD(AH)
Supply current in
Active-halt mode
LSI RC (at 38 kHz)
LSE external clock (32.768 kHz)
(2)
T
A
= -40 °C to 25 °C
T
A
= 55 °C
T
A
= 85 °C
T
A
= -40 °C to 25 °C
T
A
= 55 °C
T
A
= 85 °C
0.9
1.2
1.5
0.5
2.1
3
3.4
1.2
0.62
1.4
0.88
2.1
t
WU_HSI(AH)
(3)(4) t
I
DD(WUFAH)
WU_LSI(AH)
Supply current during wakeup time from
Active-halt mode
(using HSI)
Wakeup time from
Active-halt mode to
Run mode (using HSI)
Wakeup time from
Active-halt mode to
Run mode (using LSI)
-
-
-
-
-
2.4
4.7
150
1. No floating I/O, unless otherwise specified.
2. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption
(I
DD LSE
) must be added. Refer to Table 29
.
3. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after t
WU
.
4. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
-
-
7
μ A mA
μ s
μ s
Symbol
Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal
Parameter Condition (1) Typ Unit
I
DD(AH)
(2)
Supply current in Active-halt mode
V
DD
= 1.8 V
V
DD
= 3 V
V
DD
= 3.6 V
LSE
LSE/32 (3)
LSE
LSE/32
LSE
LSE/32
1.15
1.05
1.30
1.20
1.45
1.35
µA
1. No floating I/O, unless otherwise specified.
2. Based on measurements on bench with 32.768 kHz external crystal oscillator.
3. RTC clock is LSE divided by 32.
DS9178 Rev 4 57/96
87
Electrical parameters STM8L051F3
In the following table, data is based on characterization results, unless otherwise specified.
Table 23. Total current consumption and timing in Halt mode at V
DD
= 1.8 to 3.6 V
Symbol Parameter Condition (1) Typ Max Unit t t
I
I
DD(Halt)
DD(WUHalt)
WU_HSI(Halt)
WU_LSI(Halt)
Supply current in Halt mode
(Ultra-low-power ULP bit =1 in the PWR_CSR2 register )
T
T
A
A
= -40 °C to 25 °C
= 55 °C
T
A
= 85 °C
Supply current during wakeup time from Halt mode (using
HSI)
-
Wakeup time from Halt to Run mode (using HSI)
Wakeup time from Halt mode to Run mode (using LSI)
-
-
1. T
A
= -40 to 85 °C, no floating I/O, unless otherwise specified.
2. Tested in production.
3. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
4. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after t
WU
.
350
580
1160
2.4
4.7
150
1400
(2)
2000
2800
7
-
nA mA
µs
µs
58/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
Current consumption of on-chip peripherals
Table 24. Peripheral current consumption
Symbol Parameter
Typ.
V
DD
= 3.0 V
Unit
I
I
DD(TIM2)
I
DD(TIM3)
I
DD(TIM4)
I
DD(USART1)
I
DD(SPI1)
I
DD(I2C1)
I
DD(DMA1)
I
DD(WWDG)
I
DD(ALL)
I
DD(ADC1)
I
DD(COMP1)
I
I
DD(COMP2)
DD(PVD/BOR)
I
DD(BOR)
DD(IDWDG)
TIM2 supply current
(1)
TIM3 supply current
TIM4 timer supply current
USART1 supply current
(2)
I2C1 supply current
DMA1 supply current
Peripherals ON
(3)
ADC1 supply current
(4)
Comparator 1 supply current
(5)
Comparator 2 supply current
Slow mode
Fast mode
Power voltage detector and brownout Reset unit supply current
(6)
Brownout Reset unit supply current
Independent watchdog supply current including LSI supply current excluding LSI supply current
8
8
3
6
3
5
3
2
44
1500
0.160
2
5
2.6
2.4
0.45
0.05
µA/MHz
µA/MHz
µA
1. Data based on a differential I
DD
measurement between all peripherals OFF and a timer counter running at 16 MHz. The
CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.
2. Data based on a differential I
Not tested in production.
DD
measurement between the on-chip peripheral in reset configuration and not clocked and the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling.
3. Peripherals listed above the I
DD(ALL)
parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.
4. Data based on a differential I
DD
measurement between ADC in reset configuration and continuous ADC conversion.
5. Data based on a differential IDD measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2 enabled with static inputs. Supply current of internal reference voltage excluded.
6. Including supply current of internal reference voltage.
DS9178 Rev 4 59/96
87
Electrical parameters STM8L051F3
Symbol
Table 25. Current consumption under external reset
Parameter Conditions Typ Unit
I
DD(RST)
Supply current under external reset
(1)
All pins are externally tied to V
DD
V
DD
= 1.8 V
V
DD
= 3 V
V
DD
= 3.6 V
48
76
91
1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.
µA
8.3.4 Clock and timing characteristics
HSE external clock (HSEBYP = 1 in CLK_ECKCR)
Subject to general operating conditions for V
DD
and T
A
.
Symbol
Table 26. HSE external clock characteristics
Parameter Conditions f
HSE_ext
V
V
HSEH
HSEL
External clock source frequency
(1)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
-
-
-
C in(HSE)
I
LEAK_HSE
1. Guaranteed by design.
OSC_IN input leakage current V
SS
-
< V
IN
< V
DD
Min
1
0.7 x V
DD
V
SS
-
-
Typ
-
-
-
2.6
-
Max
16
V
DD
0.3 x V
DD
-
±1
Unit
MHz
V pF
µA
LSE external clock (LSEBYP=1 in CLK_ECKCR)
Subject to general operating conditions for V
DD
and T
A
.
Symbol
Table 27. LSE external clock characteristics
Parameter f
LSE_ext
V
LSEH
(2)
V
C in(LSE)
I
LEAK_LSE
External clock source frequency
OSC32_IN input capacitance
OSC32_IN input leakage current
(1)
OSC32_IN input pin high level voltage
OSC32_IN input pin low level voltage
1. Guaranteed by design.
2. Guaranteed by characterization results.
Min
-
0.7 x V
DD
V
SS
-
-
Typ
32.768
-
-
0.6
-
Max
-
V
DD
0.3 x V
DD
-
±1
Unit kHz
V pF
µA
60/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Symbol
Table 28. HSE oscillator characteristics
Parameter Conditions Min Typ Max Unit f
HSE
R
C
F
(1)
High speed external oscillator frequency
Feedback resistor
Recommended load capacitance
(2) -
-
1
-
-
-
200
20
16
-
-
MHz k Ω pF
I
DD(HSE)
HSE oscillator power consumption
C = 20 pF, f
OSC
= 16 MHz f
C = 10 pF,
OSC
=16 MHz
-
-
-
-
-
2.5 (startup)
0.7 (stabilized)
2.5 (startup)
0.46 (stabilized)
(3)
mA g m t
SU(HSE)
(4)
Oscillator transconductance
Startup time V
DD
is stabilized
3.5
-
-
1
-
mA/V
1. C= C
L1
= C
L2
is approximately equivalent to 2 x crystal C
LOAD
.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R
Refer to crystal manufacturer for more details m
value.
3. Guaranteed by design.
4. t
SU(HSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
ms
Figure 12. HSE oscillator circuit diagram
HSE oscillator critical g m
formula g mcrit
= ( 2 × Π × f
HSE
) 2 × R m
( )
2
R m
C m
: Motional resistance (see crystal specification), L
C
L1
=C
L2 g m
>> g mcrit m
: Motional inductance (see crystal specification),
: Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),
=C: Grounded external capacitance
DS9178 Rev 4 61/96
87
Electrical parameters STM8L051F3
LSE crystal/ceramic resonator oscillator
The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Symbol
Table 29. LSE oscillator characteristics
Parameter Conditions Min Typ Max Unit f
LSE
Low speed external oscillator frequency
32.768
kHz
R
F
C
(1)
Feedback resistor
Recommended load capacitance
(2)
Δ V = 200 mV
-
-
-
-
-
1.2
8
-
-
-
1.4
(3)
M Ω pF
µA
I
DD(LSE) g m t
SU(LSE)
(4)
LSE oscillator power consumption
Oscillator transconductance
Startup time
V
DD
= 1.8 V
V
DD
= 3 V
V
DD
= 3.6 V
-
V
DD
is stabilized
3
-
-
-
-
450
600
750
-
1
-
-
-
-
nA
µA/V
1. C= C
L1
= C
L2
is approximately equivalent to 2 x crystal C
LOAD
.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small R
Refer to crystal manufacturer for more details.
m
value.
3. Guaranteed by design.
4. t
SU(LSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.
This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
s
Figure 13. LSE oscillator circuit diagram
62/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
Internal clock sources
Subject to general operating conditions for V
DD
, and T
A
.
High speed internal RC oscillator (HSI)
In the following table, data is based on characterization results, not tested in production, unless otherwise specified.
Symbol Parameter
Table 30. HSI oscillator characteristics
Conditions
(1) Min Typ Max Unit
I t f
HSI
ACC
HSI
TRIM su(HSI)
DD(HSI)
Frequency V
Accuracy of HSI oscillator (factory calibrated)
HSI user trimming step
(3)
HSI oscillator setup time (wakeup time)
HSI oscillator power consumption
V
DD
DD
= 3.0 V
= 3.0 V, T
A
= 25 °C
1.8 V ≤
DD
≤
-40 °C ≤ T
A
≤
3.6 V,
85 °C
Trimming code ≠ multiple of 16
Trimming code = multiple of 16
-
-
-
-1
(2)
-2.5
-5
-
-
-
-
16
-
-
0.4
-
3.7
100
-
0.7
± 1.5
6
5
(4)
140
1. V
DD
= 3.0 V, T
A
= -40 to 85 °C unless otherwise specified.
2. Tested in production.
3. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16
(0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for more details.
4. Guaranteed by design.
MHz
%
%
%
%
µs
µA
Figure 14. Typical HSI frequency vs V
DD
18.0
17.5
17.0
16.5
16.0
15.5
15.0
14.5
-40°C
25°C
85°C 14.0
13.5
13.0
1.8 1.95
2.1
2.25
2.4
2.55
2.7
2.85
3 3.15
3.3 3.45
3.6
V
DD
[V] ai18218c
DS9178 Rev 4 63/96
87
Electrical parameters STM8L051F3
Low speed internal RC oscillator (LSI)
In the following table, data is based on characterization results, not tested in production.
Symbol Parameter
(1)
Table 31. LSI oscillator characteristics
Conditions
Min Typ Max Unit
I t f
LSI su(LSI)
DD(LSI)
Frequency -
LSI oscillator wakeup time
LSI oscillator frequency drift
(3)
0 °C ≤ T
A
≤
-
26
-
-12
38
-
-
1. V
DD
= 1.8 V to 3.6 V, T
A
= -40 to 85 °C unless otherwise specified.
2. Guaranteed by design.
3. This is a deviation for an individual part, once the initial frequency has been measured.
56
200
(2)
11 kHz
µs
%
Figure 15. Typical LSI frequency vs. V
DD
45
43
41
39
37
35
33
31
29
27
25
1.8
2.1
2.6
V
DD
[V]
3.1
-40°C
25°C
85°C
3.6
ai18219b
64/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
T
A
= -40 to 85 °C unless otherwise specified.
Table 32. RAM and hardware registers
Symbol Parameter Conditions Min Typ Max Unit
V
RM
Data retention mode
(1)
Halt mode (or Reset) 1.8
-
1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization.
V
Flash memory
Symbol
Table 33. Flash program and data EEPROM memory
Parameter Conditions Min Typ
Max
(1)
Unit t
V
DD prog
Operating voltage
(all modes, read/write/erase)
Programming time for 1 or 64 bytes (block) erase/write cycles (on programmed byte)
Programming time for 1 to 64 bytes (block) write cycles (on erased byte) f
SYSCLK
= 16 MHz 1.8
6
3
3.6
V ms ms t
I prog
RET
(2)
N
RW
(3)
Programming/ erasing consumption
Data retention (program memory) after 100 erase/write cycles at T
A
= –40 to +85 °C
Data retention (data memory) after 100000 erase/write cycles at T
A
Erase/write cycles
Erase/write cycles
= –40 to +85 °C
(program memory)
(data memory)
T
A
= +25 °C, V
DD
= 3.0 V
T
A
= +25 °C, V
DD
= 1.8 V
T
T
T
A
RET
RET
=
=
+85 °C
+85 °C
= –40 to +85 °C
30
30
100
100
0.7
mA years cycles kcycles
1. Guaranteed by characterization results.
2. Conforming to JEDEC JESD22a117
3. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.
4. Data based on characterization performed on the whole data memory.
DS9178 Rev 4 65/96
87
Electrical parameters STM8L051F3
As a general rule, current injection to the I/O pins, due to external voltage below V
SS
(for standard pins) should be avoided during normal product operation.
or above V
DD
However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error, out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation, LCD levels, etc.).
The test results are given in the following table.
Symbol
I
INJ
Table 34. I/O current injection susceptibility
Functional susceptibility
Description
Negative injection
Positive injection
Injected current on true open-drain pins (PC0 and
PC1)
Injected current on all five-volt tolerant (FT) pins
Injected current on all 3.6 V tolerant (TT) pins
Injected current on any other pin
-5
-5
-5
-5
+0
+0
+0
+5
Unit mA
8.3.7 I/O port pin characteristics
General characteristics
Subject to general operating conditions for V
DD
and T
A
unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.
66/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
Symbol Parameter
Table 35. I/O static characteristics
Conditions
(1) Min Typ Max
V
V
V
I
IL
IH hys lkg
Input low level voltage
(2)
Input high level voltage
Schmitt trigger voltage hysteresis
(3)
Input leakage current
(4)
Input voltage on true open-drain pins (PC0 and PC1)
Input voltage on five-volt tolerant (FT) pins (PA7 and
PE0)
Input voltage on 3.6 V tolerant
(TT) pins
V
V
V
SS
SS
SS
-0.3
-0.3
-0.3
Input voltage on any other pin V
SS
-0.3
Input voltage on true open-drain pins (PC0 and PC1) with V
DD
< 2 V
Input voltage on true open-drain pins (PC0 and PC1) with V
DD
≥ 2 V
0.70 x V
DD
Input voltage on five-volt tolerant (FT) pins (PA7 and
PE0) with V
DD
< 2 V
Input voltage on five-volt tolerant (FT) pins (PA7 and
PE0) with V
DD
≥ 2 V
Input voltage on 3.6 V tolerant
(TT) pins
0.70 x V
DD
Input voltage on any other pin 0.70 x V
DD
I/Os
True open drain I/Os
V
SS
≤ V
IN
≤ V
DD
High sink I/Os
V
SS
≤ V
IN
≤ V
DD
True open drain I/Os
V
SS
≤ V
IN
≤ V
DD
PA0 with high sink LED driver capability
-
-
-
200
200
-
-
-
0.3 x V
0.3 x V
0.3 x V
0.3 x V
V
5.2
5.5
5.2
5.5
3.6
DD
50
+0.3
200
200
(5)
DD
DD
DD
DD
R
PU
Weak pull-up equivalent
I/O pin capacitance
V
IN
= V
SS
30 45 60
C
IO
5
1. V
DD
= 3.0 V, T
A
= -40 to 85 °C unless otherwise specified.
2. Guaranteed by characterization results.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Not tested in production.
6. R pull-up equivalent resistor based on a resistive transistor (corresponding I
PU current characteristics described in
Unit
V
V mV nA k Ω pF
DS9178 Rev 4 67/96
87
Electrical parameters STM8L051F3
Figure 16. Typical V
IL
and V
IH vs V
DD
(high sink I/Os)
3
2.5
2
1.5
1
0.5
0
1.8
-40°C
25°C
85°C
2.1
2.6
V
DD
[V]
3.1
3.6
ai18220c
3
2.5
2
1.5
1
0.5
0
1.8
Figure 17. Typical V
IL
and V
IH vs V
DD
(true open drain I/Os)
-40°C
25°C
85°C
2.1
2.6
V
DD
[V]
3.1
3.6
ai18221b
68/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
60
Figure 18. Typical pull-up resistance R
PU
vs V
DD
with V
IN
=V
SS
55
-40°C
25°C
85°C
50
45
40
35
30
1.8
2 2.2
2.4
2.6
V
DD
[V]
2.8
3 3.2
3.4
3.6
ai18222b
Figure 19. Typical pull-up current I pu
vs V
DD
with V
IN
=V
SS
120
100
80
-40°C
25°C
85°C
60
40
20
0
1.8
1.95
2.1
2.25
2.4
2.55
2.7
2.85
3 3.15
3.3
3.45
3.6
V
DD
[V] ai18223b
DS9178 Rev 4 69/96
87
Electrical parameters STM8L051F3
Output driving current
Subject to general operating conditions for V
DD and T
A
unless otherwise specified.
Table 36. Output driving current (high sink ports)
I/O
Type
Symbol Parameter Conditions Min Max Unit
V
V
OL
(1)
OH
(2)
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
I
IO
= +2 mA,
V
DD
= 3.0 V
I
IO
= +2 mA,
V
DD
= 1.8 V
-
-
I
IO
= +10 mA,
V
DD
= 3.0 V
I
IO
= -2 mA,
V
DD
= 3.0 V
-
V
DD
-0.45
I
IO
= -1 mA,
V
DD
= 1.8 V
I
IO
= -10 mA,
V
DD
= 3.0 V
V
V
DD
DD
-0.45
-0.7
0.45
0.45
0.7
-
-
-
1. The I
IO
current sunk must always respect the absolute maximum rating specified in
IO
(I/O ports and control pins) must not exceed I
VSS
.
2. The I
IO
current sourced must always respect the absolute maximum rating specified in Table 13: Current
IO
(I/O ports and control pins) must not exceed I
VDD
.
V
V
V
V
V
V
Table 37. Output driving current (true open drain ports)
I/O
Type
Symbol Parameter Conditions Min Max
V
OL
(1)
Output low level voltage for an I/O pin
I
IO
= +3 mA,
V
DD
= 3.0 V
I
IO
= +1 mA,
V
DD
= 1.8 V
-
0.45
0.45
1. The I
IO
current sunk must always respect the absolute maximum rating specified in
IO
(I/O ports and control pins) must not exceed I
VSS
.
Unit
V
Table 38. Output driving current (PA0 with high sink LED driver capability)
I/O
Type
Symbol Parameter Conditions Min Max
V
OL
(1) Output low level voltage for an I/O pin
I
IO
= +20 mA,
V
DD
= 2.0 V
0.45
1. The I
IO
current sunk must always respect the absolute maximum rating specified in
IO
(I/O ports and control pins) must not exceed I
VSS
.
Unit
V
70/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
Figure 20. Typ. V
OL
@ V
DD ports)
= 3.0 V (high sink
1
0.75
0.5
0.25
-40°C
25°C
85°C
0
0 2 4 6 8 10
I
OL
[mA]
12 14 16 18 20 ai18226V2
Figure 21. Typ. V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 1
-40°C
25°C
85°C
OL
@ V
DD ports)
= 1.8 V (high sink
2 3 4
I
OL
[mA]
5 6 7 8 ai18227V2
Figure 22. Typ. V
OL
@ V
DD
= 3.0 V (true open drain ports)
0.5
0.4
-40°C
25°C
85°C
0.3
0.2
0.1
0
0 1 2 3
I
OL
[mA]
4 5 6 7 ai18228V2
Figure 24. Typ. V
DD -
V
OH
@ V sink ports)
DD
= 3.0 V (high
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0 2
-40°C
25°C
85°C
4 6 8 10
I
OH
[mA]
12 14 16 18 20 ai12830V2
Figure 23. Typ. V
OL
@ V
DD
= 1.8 V (true open drain ports)
0.5
0.4
0.3
0.2
0.1
0
0
-40°C
25°C
85°C
1 2 3
I
OL
[mA]
4 5 6 7 ai18229V2
Figure 25. Typ. V
DD -
V
OH
@ V
DD
= 1.8 V (high sink ports)
0.5
0.4
-40°C
25°C
85°C
0.3
0.2
0.1
0
0 1 2 3
I
OH
[mA]
4 5 6 7 ai18231V2
DS9178 Rev 4 71/96
87
Electrical parameters STM8L051F3
NRST pin
Subject to general operating conditions for V
DD
and T
A
unless otherwise specified.
Symbol
V
IL(NRST)
V
IH(NRST)
V
OL(NRST)
Table 39. NRST pin characteristics
Parameter
NRST input low level voltage
(1)
Conditions
-
-
I
OL
= 2 mA for 2.7 V ≤
DD
3.6 V
I
OL
= 1.5 mA for V
DD
< 2.7 V
Min
V
SS
1.4
-
-
V
HYST
NRST input hysteresis
-
10%V
DD
(2)
Typ
-
-
-
-
-
Max
0.8
V
DD
0.4
-
R
PU(NRST)
NRST pull-up equivalent resistor
V
F(NRST)
V
NF(NRST)
NRST input filtered pulse
(3)
NRST input not filtered pulse
1. Guaranteed by characterization results.
2. 200 mV min.
3. Data guaranteed by design, not tested in production.
-
-
30
-
300
45
-
-
60
50
-
Unit
V mV k Ω ns
Figure 26. Typical NRST pull-up resistance R
PU
vs V
DD
60
55
-40°C
25°C
85°C
50
45
40
35
30
1.8
2 2.2
2.4
2.6
2.8
V
DD
[V]
3 3.2
3.4
3.6
ai18224b
72/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
120
Figure 27. Typical NRST pull-up current I pu
vs V
DD
100
-40°C
25°C
85°C
80
60
40
20
0
1.8
1.95 2.1
2.25 2.4
2.55 2.7
2.85
3 3.15 3.3
3.45 3.6
V
DD
[V] ai18225b
The reset network shown in Figure 28
protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the V
IL(NRST) in
Table 39 . Otherwise the reset is not taken into account internally.
max. level specified
For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, attention must be paid to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. The minimum recommended capacity is 10 nF.
Figure 28. Recommended NRST pin configuration
V
DD
R
PU
EXTERNAL
RESET
CIRCUIT
(Optional)
0.1 µF
NRST
Filter
INTERNAL RESET
STM8
DS9178 Rev 4 73/96
87
Electrical parameters STM8L051F3
SPI1 - Serial peripheral interface
Unless otherwise specified, the parameters given in
Table 40 are derived from tests
performed under ambient temperature, f
SYSCLK
frequency and V
DD
supply voltage conditions summarized in
. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Symbol Parameter
Table 40. SPI1 characteristics
Conditions
(1)
Min Max Unit t su(NSS)
(2) t h(NSS)
t t w(SCKH)
w(SCKL)
t f
SCK
1/t c(SCK) t
t dis(SO)
t t t t t v(SO)
t su(MI)
su(SI)
t t r(SCK) t f(SCK)
h(SI)
h(SO)
SPI1 clock frequency
SPI1 clock rise and fall time
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode f
Master mode,
MASTER
= 8 MHz, f
SCK
= 4 MHz
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
4 x 1/f
0
0
-
SYSCLK
80
105
30
3
15
0
-
30
-
-
15
1
8
8
30
145
-
-
-
-
-
-
3x 1/f
SYSCLK
-
60
20
-
-
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.
4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.
MHz ns
74/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
Figure 29. SPI1 timing diagram - slave mode and CPHA=0
Figure 30. SPI1 timing diagram - slave mode and CPHA=1
(1)
NSS input t
SU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1 t w(SCKH) t w(SCKL) t a(SO)
MISO
OUTPUT
MOSI
INPUT t su(SI) t v(SO)
MSB OUT t h(SI)
MSB IN t c(SCK) t h(SO)
BIT6 OUT
BIT 1 IN t h(NSS) t r(SCK) t f(SCK) t dis(SO)
LSB OUT
LSB IN ai14135b
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD
.
DS9178 Rev 4 75/96
87
Electrical parameters
Figure 31. SPI1 timing diagram - master mode (1)
STM8L051F3
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD
.
76/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
Note:
I2C - Inter IC control interface
Subject to general operating conditions for V
DD
, f
SYSCLK
, and T
A
unless otherwise specified.
The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below:
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL).
Symbol
Table 41. I2C characteristics
Parameter
Standard mode
I2C
Min
(2)
Max
Fast mode I2C
(1)
Min
Max
t w(SCLL) t w(SCLH) t su(SDA) t h(SDA)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)
SDA and SCL rise time
SDA and SCL fall time
START condition hold time t su(STA)
Repeated START condition setup time t su(STO)
C b
STOP condition setup time t w(STO:STA)
STOP to START condition time (bus free)
Capacitive load for each bus line
4.7
4.0
250
0
-
-
4.0
4.7
4.0
4.7
-
-
-
-
-
1000
300
-
-
-
-
400
1. f
SYSCLK
must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz).
2. Data based on standard I2C protocol requirement, not tested in production.
1.3
0.6
100
0
0.6
0.6 -
0.6
1.3
-
-
-
900
300
300
-
-
-
-
-
-
400
Unit
μ s ns
μ s
μ s
μ s pF
For speeds around 200 kHz, the achieved speed can have a ± 5% tolerance
For other speed ranges, the achieved speed can have a ± 2% tolerance
The above variations depend on the accuracy of the external components used.
DS9178 Rev 4 77/96
87
Electrical parameters STM8L051F3
Figure 32. Typical application with I2C bus and timing diagram 1)
1. Measurement points are done at CMOS levels: 0.3 x V
DD
and 0.7 x V
DD
78/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
In the following table, data is based on characterization results, not tested in production, unless otherwise specified.
Symbol
Table 42. Reference voltage characteristics
Parameter Conditions Min Typ Max.
T
V
I
C t
I
REFOUT
t
I
I
REFINT
S_VREFINT
(1)(2)
BUF
REFINT out
REFOUT
VREFINT
ACC
STAB
STAB
VREFINT
VREFINT
VREFINT
Internal reference voltage consumption
ADC sampling time when reading the internal reference voltage
Internal reference voltage buffer consumption (used for ADC)
Reference voltage output
Internal reference voltage lowpower buffer consumption
Buffer output current
(4)
Reference voltage output load
Internal reference voltage startup time
Internal reference voltage buffer
Accuracy of V
REFINT
stored in the
VREFINT_Factory_CONV byte (5)
Stability of V
REFINT temperature
over
Stability of V
REFINT temperature
over
Stability of V
REFINT hours after 1000
-40 °C
0 °C ≤ T
-
-
-
-
-
-
-
-
-
-
≤
°C
A
-
T
≤
A
≤ 85
50 °C
-
-
-
1.202
-
-
-
-
-
-
-
-
-
(3)
1.4
5
13.5
1.224
730
-
-
2
-
-
20
-
-
-
10
25
1
50
TBD
1. Defined when ADC output reaches its final value ±1/2LSB
2. Data guaranteed by design.
3. Tested in production at V
DD
= 3 V ±10 mV.
4. To guaranty less than 1% V
REFOUT deviation.
5. Measured at V
DD
= 3 V ±10 mV. This value takes into account V
DD
accuracy and ADC conversion accuracy.
1200
3
10
± 5
50
20
Unit
µA
µs
µA
V nA
µA pF ms
µs mV ppm/°C ppm/°C ppm
In the following table, data is guaranteed by design, not tested in production.
DS9178 Rev 4 79/96
87
Electrical parameters STM8L051F3
Symbol
V
DDA
Analog supply voltage
V
REF+
Reference supply voltage
V
REF-
I
VDDA
Lower reference voltage
Current on the V
DDA input pin
Table 43. ADC1 characteristics
Min Typ
-
2.4 V ≤ V
DDA
≤ 3.6 V
1.8 V ≤ V
DDA
≤ 2.4 V
-
-
I
VREF+
-
Current on the V
REF+ input pin
f
V
R
C
AIN
T
A
AIN
ADC
ADC
Conversion voltage range
Temperature range
External resistance on
V
AIN
Internal sample and hold capacitor
ADC sampling clock frequency
-
-
-
-
-
-
2.4 V ≤ V
DDA
≤ 3.6 V without zooming
1.8 V ≤ V
DDA
≤ 2.4 V with zooming
V
AIN
on all slow channels
f
CONV f
TRIG t t
LAT t
S conv
12-bit conversion rate
External trigger frequency
External trigger latency
Sampling time
12-bit conversion time t t
WKUP
IDLE
(5) t
VREFINT
Wakeup time from OFF state
Time before a new conversion
Internal reference voltage startup time
-
V
AIN
on slow channels
V
DDA
< 2.4 V
V
AIN
on slow channels
2.4 V ≤ V
DDA
≤ 3.6 V
-
16 MHz
-
T
A
= +25 °C
T
A
= +70 °C
-
1.8
2.4
-
-
-
0
(2)
-
-
-40
-
-
0.320
0.320
-
-
-
0.86
0.41
-
-
-
-
1000
400
-
-
-
-
-
-
-
-
-
V
DDA
V
SSA
16
-
-
-
-
-
-
-
-
12 + t
S
1
Max
3.6
V
DDA
1450
700
(peak)
(1)
450
(average)
V
REF+
85
50
(3) t conv
3.5
-
-
-
16
8
760
(4)
-
3
1
(6)
refer to
µA
µA
-
°C k Ω pF
MHz
MHz kHz
1/f
ADC
1/f
SYSCLK
µs
µs
1/f
ADC
µs
µs s ms ms
Unit
V
V
V
V
µA
80/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
1. The current consumption through V
REF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps
2. V
REF-
or V
DDA
must be tied to ground.
3. Guaranteed by design.
4. Minimum sampling and conversion time is reached for maximum Rext = 0.5 k Ω
.
5. The time between 2 conversions, or between ADC ON and the first conversion must be lower than t
IDLE.
6. The t
IDLE
maximum value is ∞ on the “Z” revision code of the device.
DS9178 Rev 4 81/96
87
Electrical parameters STM8L051F3
In the following three tables, data is guaranteed by characterization result, not tested in production.
Symbol
DNL
INL
TUE
Offset
Gain
Table 44. ADC1 accuracy with V
DDA
= 3.3 V to 2.5 V
Parameter Conditions Typ Max
Differential non linearity
Integral non linearity
Total unadjusted error
Offset error
Gain error f
ADC
= 16 MHz f
ADC
= 8 MHz f
ADC
= 4 MHz f
ADC
= 16 MHz f
ADC
= 8 MHz f
ADC
= 4 MHz f
ADC
= 16 MHz f
ADC
= 8 MHz f
ADC
= 4 MHz f
ADC
= 16 MHz f
ADC
= 8 MHz f
ADC
= 4 MHz f
ADC
= 16 MHz f
ADC
= 8 MHz f
ADC
= 4 MHz
1.2
1.2
2.2
1.8
1.8
1.5
1
0.7
1
1
1
1.2
1 1.5
1.8
1.7
3.0
2.5
2.3
2
1.5
1.2
1.6
1.6
1.5
2
Unit
LSB
LSB
Symbol
DNL
INL
TUE
Offset
Gain
Symbol
DNL
INL
TUE
Offset
Gain
Table 45. ADC1 accuracy with V
DDA
= 2.4 V to 3.6 V
Parameter Typ Max
Differential non linearity
Integral non linearity
Total unadjusted error
Offset error
Gain error
1
1.7
2
1
1.5
2
3
4
2
3
Table 46. ADC1 accuracy with V
DDA
= V
REF+
= 1.8 V to 2.4 V
Parameter Typ Max Unit
Differential non linearity
Integral non linearity
Total unadjusted error
Offset error
Gain error
3
2
2
1
2
5
3
3
2
3
LSB
LSB
LSB
LSB
LSB
Unit
LSB
LSB
LSB
LSB
LSB
82/96 DS9178 Rev 4
STM8L051F3
Figure 33. ADC1 accuracy characteristics
Electrical parameters
Figure 34. Typical connection diagram using the ADC
V
AIN
R
AIN
(1)
AINx
C parasitic
(2)
V DD
V
T
0.6V
V T
0.6V
IL± 50nA
STM8
Sample and hold ADC converter
R ADC
12-bit converter
C
ADC
(1) ai17090f
1. Refer to Table 47 for the values of R
AIN
and C
ADC
.
2. C parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 this, f
ADC pF). A high C
should be reduced.
parasitic
value will downgrade conversion accuracy. To remedy
Figure 35. Maximum dynamic current consumption on V
REF+ conversion
supply pin during ADC
Sampling
(n cycles)
Conversion (12 cycles)
ADC clock
I ref+
700 μA
300 μA
MS46324V1
DS9178 Rev 4 83/96
87
Electrical parameters STM8L051F3
Ts (cycles)
48
96
192
384
16
24
4
9
1. Guaranteed by design.
0.25
0.5625
1
1.5
12
24
3
6
Ts
(µs)
Table 47. R
AIN
max for f
ADC
= 16 MHz (1)
R
AIN
max (kohm)
Slow channels
2.4 V < V
DDA
< 3.6 V
Not allowed
0.8
2.0
3.0
6.8
15.0
32.0
50.0
1.8 V < V
DDA
< 2.4 V
Not allowed
Not allowed
0.8
1.8
4.0
10.0
25.0
50.0
General PCB design guidelines
Power supply decoupling should be performed as shown in
or
, depending on whether V
REF+
is connected to V
DDA
or not. Good quality ceramic 10 nF capacitors should be used. They should be placed as close as possible to the chip.
Figure 36. Power supply and reference decoupling (V
REF+ not connected to V
DDA
)
STM8L
V
REF+
External reference
1 μF // 10 nF
Supply
1 μF // 10 nF
V
DDA
V
SSA
/V
REFai17031c
84/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
Figure 37. Power supply and reference decoupling (V
REF+ connected to V
DDA
)
STM8L
V
REF+
/V
DDA
Supply
1 μF // 10 nF
V
REF-
/V
SSA ai17032d
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
• ESD : Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000 standard.
• FTB : A burst of fast transient voltage (positive and negative) is applied to V
DD
and V
SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000 standard.
A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Prequalification trials
DS9178 Rev 4 85/96
87
Electrical parameters STM8L051F3
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Symbol Parameter
Table 48. EMS data
Conditions
Level/
Class
V
FESD
Voltage limits to be applied on any I/O pin to induce a functional disturbance
V
DD
= 3.3 V, T
A
= +25 °C, f
CPU
= 16 MHz, conforms to IEC 61000
3B
4A
V
EFTB
Fast transient voltage burst limits to be applied through 100 pF on
V
DD
and V
SS pins to induce a functional disturbance
V
DD
= 3.3 V, T
A
= +25 °C, f
CPU
= 16 MHz, conforms to IEC 61000
Using HSI
Using HSE
2B
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm IEC61967-2 which specifies the board and the loading of each pin.
Table 49. EMI data (1)
Max vs.
Symbol Parameter Conditions
Monitored frequency band
Unit
S
EMI
Peak level
V
T
DD
A
= 3.6 V,
= +25 °C,
LQFP32 conforming to
IEC61967-2
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
16 MHz
-3
9
4
2 dB μ V
-
1. Not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: human body model and charge device model. This test conforms to the
JESD22-A114A/A115A standard.
86/96 DS9178 Rev 4
STM8L051F3 Electrical parameters
Symbol
Table 50. ESD absolute maximum ratings
Ratings Conditions
Maximum value
(1)
V
ESD(HBM)
V
ESD(CDM)
Electrostatic discharge voltage
(human body model)
Electrostatic discharge voltage
(charge device model)
1. Guaranteed by characterization results.
T
A
= +25 °C
2000
500
Unit
V
Static latch-up
• LU : 3 complementary static tests are required on 6 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.
Symbol
LU
Table 51. Electrical sensitivities
Parameter
Static latch-up class
Class
II
DS9178 Rev 4 87/96
87
Package characteristics STM8L051F3
9.1 ECOPACK
®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
88/96 DS9178 Rev 4
STM8L051F3
9.2 Package mechanical data
Package characteristics
Figure 38. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package outline
D
20
PIN 1
IDENTIFICATION aaa C
A
1
11
10
E1 E
SEATING
PLANE
C e
A2
0.25 mm
GAUGE PLANE
A1 L
L1 k c b
YA_ME_V3
1. Drawing is not to scale.
Table 52. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data millimeters inches
(1)
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
A1
A2 b c
D
(2)
E
E1
(3) e
L
L1 k aaa
4.300
-
0.450
-
0°
-
-
0.050
0.800
0.190
0.090
6.400
6.200
4.400
0.650
0.600
1.000
-
-
-
-
1.000
-
-
6.500
6.400
4.500
-
0.750
-
8°
0.100
1.200
0.150
1.050
0.300
0.200
6.600
6.600
0.1693
-
0.0177
-
0°
-
-
0.0020
0.0315
0.0075
0.0035
0.2520
0.2441
0.1732
0.0256
0.0236
0.0394
-
-
-
-
0.0394
-
-
0.2559
0.2520
0.1772
-
0.0295
-
8°
0.0039
0.0472
0.0059
0.0413
0.0118
0.0079
0.2598
0.2598
DS9178 Rev 4 89/96
93
Package characteristics STM8L051F3
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side.
Figure 39. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package footprint
0.25
6.25
20 11
1.35
0.25
7.10 4.40
1
1. Dimensions are expressed in millimeters.
0.40
0.65
10
1.35
YA_FP_V1
90/96 DS9178 Rev 4
STM8L051F3 Package characteristics
Device marking for TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm,
0.65 mm pitch
The following figure gives an example of topside marking orientation versus pin 1/ball A1 identifier location.
Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.
Figure 40. Device marking for TSSOP20 – 20-lead thin shrink small outline,
6.5 x 4.4 mm, 0.65 mm pitch example
Product identification
8L051F3P6
Y WW R
Unmarkable surface
PIN1 reference
Date code
Additional information
MSv17034v1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS9178 Rev 4 91/96
93
Package characteristics STM8L051F3
The maximum chip junction temperature (T
Jmax
) must never exceed the values given in
Table 15: General operating conditions on page 48
.
The maximum chip-junction temperature, T
Jmax the following equation:
, in degree Celsius, may be calculated using
T
Jmax
= T
Amax
+ (P
Dmax
x Θ
JA
)
Where:
• T
Amax
is the maximum ambient temperature in ° C
• Θ
JA
is the package junction-to-ambient thermal resistance in ° C/W
• P
Dmax
is the sum of P
INTmax
and P
I/Omax
(P
Dmax
= P
INTmax
+ P
I/Omax
)
• P
INTmax
is the product of I
DD and internal power.
V
DD
, expressed in Watts. This is the maximum chip
• P
I/Omax
Where:
represents the maximum power dissipation on output pins
P
I/Omax
= Σ (V
OL
*I
OL
) + Σ ((V
DD taking into account the actual V the application.
-V
OH
OL
/I
)*I
OL
OH and
),
V
OH
/I
OH
of the I/Os at low and high level in
Symbol
Table 53. Thermal characteristics (1)
Parameter Value
Θ
JA
Thermal resistance junction-ambient
TSSOP20
110
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.
Unit
°C/W
92/96 DS9178 Rev 4
STM8L051F3 Ordering information
Figure 41. Low density value line STM8L051F3 ordering information scheme
Example: STM8 L 051 F 3 P 6
Product class
STM8 microcontroller
Family type
L = Low power
Sub-family type
051 = Ultra-low-power
Pin count
F = 20 pins
Program memory size
3 = 8 Kbytes
Package
P = TSSOP
Temperature range
6 = – 40 to 85 °C
For a list of available options (such as memory size, package) and orderable part numbers or for further information on any aspect of this device, please contact the ST sales office nearest to you.
DS9178 Rev 4 93/96
93
Revision history STM8L051F3
Date
01-Aug-2012
26-Mar-2014
04-Jul-2017
Revision
Table 54. Document revision history
Changes
1
2
3
Initial release.
Updated TSS0P20 package information
Updated pin name related to pin1 and 2 inside Table 4: STM8L051F3 pin description
Updated inside
Table 10: Option byte addresses
OPT5 default factory of BOR to 0x00
Updated
– All document to refer to specific RPN instead to the whole Value line when relevant to make content clearer
– Document’s title
– Footnotes were standardized on Section 8: Electrical parameters
– Figure on Features on the cover page
–
–
–
Section 2.2: Ultra-low-power continuum
–
Section 8.2: Absolute maximum ratings
–
Section 9.3: TSSOP20 package information
–
Figure 1: STM8L051F3 block diagram
–
Figure 2: STM8L051F3 clock tree diagram
–
Figure 5: Pin loading conditions
–
–
Figure 8: Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz
–
Figure 9: Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1)
–
Figure 10: Typ. IDD(LPR) vs. VDD (LSI clock source)
–
Figure 11: Typ. IDD(LPW) vs. VDD (LSI clock source)
–
Figure 13: LSE oscillator circuit diagram
–
Figure 15: Typical LSI frequency vs. VDD
–
Figure 16: Typical VIL and VIH vs VDD (high sink I/Os)
–
Figure 17: Typical VIL and VIH vs VDD (true open drain I/Os)
–
Figure 18: Typical pull-up resistance R
–
Figure 19: Typical pull-up current I pu
–
Figure 29: SPI1 timing diagram - slave mode and CPHA=0
–
Figure 30: SPI1 timing diagram - slave mode and CPHA=1
–
Figure 34: Typical connection diagram using the ADC
–
Figure 35: Maximum dynamic current consumption on V
REF+ pin during ADC conversion
94/96 DS9178 Rev 4
STM8L051F3 Revision history
Date
04-Jul-2017
07-Sep-2018
Revision
Table 54. Document revision history
Changes
3
(Cont.)
Updated (continuation):
–
Figure 37: Power supply and reference decoupling (VREF+ connected to VDDA)
–
Figure 38: TSSOP20 – 20-lead thin shrink small outline, 6.5 x
4.4 mm, 0.65 mm pitch, package outline
–
Figure 39: TSSOP20 – 20-lead thin shrink small outline, 6.5 x
4.4 mm, 0.65 mm pitch, package footprint
–
Table 25: Current consumption under external reset
4
Added
–
–
Updated:
–
12-bit ADC up to 1 Msps/10 channels
feature on cover page
–
Section 3.8: Analog-to-digital converter
–
Table 4: STM8L051F3 pin description
–
Table 7: General hardware register map
–
Table 43: ADC1 characteristics
–
– Added introduction to following sections:
Section 3.2: Central processing unit STM8
Section 3.3: Reset and supply management
Section 3.13: Communication interfaces
Section 3.15: Development support
Section 5: Memory and register map
Section 6: Interrupt vector mapping
Section 8: Electrical parameters
Section 8.3.1: General operating conditions
Section 8.3.2: Embedded reset and power control block characteristics
DS9178 Rev 4 95/96
95
STM8L051F3
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
96/96 DS9178 Rev 4
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