STMicroelectronics ILPS22QS Datasheet
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ILPS22QS
Datasheet
Dual full-scale, 1260 hPa and 4060 hPa, absolute digital output barometer with embedded Qvar electrostatic sensor
Product status link
ILPS22QS
Product summary
Order code
Temp. range [°C]
Package
Packing
ILPS22QSTR
-40 to +105
HLGA-10L
(2.0 x 2.0 x 0.73 mm)
Tape and reel
Product resources
TN0018 (Design and soldering)
Product labels
Features
• Selectable dual full-scale absolute pressure range
– Mode 1: 260 ~ 1260 hPa
– Mode 2: 260 ~ 4060 hPa
• Current consumption down to 1.8 µA
• Absolute pressure accuracy: 0.5 hPa
• Low pressure sensor noise: 0.34 Pa
• High-performance TCO: 0.45 Pa/°C
• Embedded temperature compensation
• Extended temperature range from -40 to +105 °C
• 24-bit pressure data output
• ODR from 1 Hz to 200 Hz
• SPI, I²C or MIPI I3C SM interfaces
• Supports 1.08 V digital interface
• Embedded FIFO
• Embedded analog hub for processing analog input data
• Embedded Qvar for detecting electric charge variation
• Interrupt functions: data-ready, FIFO flags, pressure thresholds
• Supply voltage: 1.7 to 3.6 V
• High shock survivability: 22,000 g
• Small and thin package
• ECOPACK lead-free compliant
Applications
• Industrial applications
• Gas and water metering
• Weather station equipment
• Altimeters and barometers for outdoor devices
• Smart filters
• Ventilators and CPAP equipment
• Man-down detection
Description
The ILPS22QS is an ultra-compact piezoresistive absolute pressure sensor which functions as a digital output barometer, supporting dual full-scale up to userselectable 4060 hPa. The device delivers ultra-low pressure noise with very low power consumption and operates over an extended temperature range from -40 °C to +105 °C.
The ILPS22QS comprises a sensing element and an IC interface which communicates over I²C, MIPI I3C SM or SPI interfaces from the sensing element to the application and supports 1.2 V digital interface as well. The sensing element, which detects absolute pressure, consists of a suspended membrane manufactured using a dedicated process developed by ST.
DS13431 - Rev 2 - December 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
ILPS22QS
The ILPS22QS embeds an analog hub sensing functionality which is able to connect an analog input and convert it to a digital signal for embedded processing. In addition, an embedded Qvar (electric charge variation detection) channel can be enabled for sensing in applications such as water leakage detection, tap, double tap, long press, and L/R - R/L swipe.
The ILPS22QS is available in a full-mold, holed LGA package (HLGA). The package is holed to allow external pressure to reach the sensing element.
DS13431 - Rev 2 page 2/58
1
ILPS22QS
Block diagrams
Block diagrams
Figure 1. Device architecture block diagram
Temperature
Sensor
MUX
Analog
Front-End
ADC
Digital
Logic
I
2
C
MIPI I3C
SM
SPI
Sensing Element
Analog Input / Qvar
Sensor Bias Voltage and Current Bias Clock and timing
Analog
Front-End
ADC
AVG
Filter
Figure 2. Digital logic
Pressure
Compensation
Temperature
Compensation
LP Filter
EN_LPFP
1
0
P
OUT
T
OUT
FIFO
Output
Registers
Output
Registers
I 2 C
MIPI I3C SM
SPI
DS13431 - Rev 2 page 3/58
2
Pin description
Figure 3. Pin connections (bottom view)
1 2
VDD
GND
GND_IO
10
9
8
7 6
3
4
5
RES
SDA/SDI/SDO
AH2/QVAR2
ILPS22QS
Pin description
Pin number
1
2
3
4
5
6
9
10
7
8
Name
Vdd_IO
SCL
SPC
RES
SDA
SDI
SDO
AH2/QVAR2
CS
AH1/QVAR1
GND_IO
GND
VDD
Table 1. Pin description
Function
Power supply for I/O pins
I²C / MIPI I3C SM serial clock (SCL)
SPI serial port clock (SPC)
Connect to GND
I²C / MIPI I3C SM serial data (SDA)
3-wire SPI serial data input (SDI)
3-wire serial data output (SDO)
Connect to GND if analog input / Qvar sensing is not needed.
Enables SPI
I²C and MIPI I3C SM / SPI mode selection
(1: SPI idle mode / I²C and MIPI I3C SM communication enabled;
0: SPI communication mode / I²C and MIPI I3C SM disabled)
Connect to GND if analog input / Qvar sensing is not needed.
0 V supply
0 V supply
Power supply
DS13431 - Rev 2 page 4/58
ILPS22QS
Mechanical and electrical specifications
3
Mechanical and electrical specifications
3.1
Mechanical characteristics
VDD = 1.8 V, T = 25 °C, unless otherwise noted.
Table 2. Pressure and temperature sensor characteristics
Symbol Parameter
Pressure sensor characteristics
PT op
Operating temperature range
P op
Operating pressure range
Mode 1
Mode 2
P bits
Pressure output data
P
P sens
AccRel
Pressure sensitivity
Mode 1
Mode 2
Relative pressure accuracy (2)
Mode 1
Mode 2
Test condition
T =25 °C
P= 800 ~ 1100 hPa
P = 2060 ~ 4060 hPa
Min.
-40
260
260
24
4096
2048
±0.015
±1
Max.
+105
1260
4060
Unit
°C hPa bits
LSB/hPa hPa
P
AccT
P noise
Absolute pressure accuracy
Mode 1
Mode 2
Refer to
Mode1
Mode 2
Refer to
P = 660 ~ 1260
T = -20 ~ 65 °C
T = -40 ~ 105 °C
P = 1260 ~ 4060 hPa
T = 0 ~ 65 °C
T = -40 ~ 105 °C
T = 25 °C
±0.5
±1
±0.28%
±0.37%
0.34
0.57
hPa
Pa
ODR
Pres
50
75
100
200
10
25
1
4
Hz
TCO
Temperature coefficient offset
Mode 1
Mode 2
P_drift Soldering drift
P = 660 ~ 1160 hPa, T = -20 ~ +65 °C
P = 2060 ~ 3060 hPa, T = 0 ~ +45 °C
±0.45
±3.5
±0.5
Pa/°C hPa
DS13431 - Rev 2 page 5/58
DS13431 - Rev 2
ILPS22QS
Mechanical characteristics
Symbol Parameter
Temperature sensor characteristics
T op
T sens
T acc
Operating temperature range
Temperature sensitivity
Temperature absolute accuracy
Test condition Min.
-40
100
Max.
+105
Unit
°C
LSB/°C
ODR
T
Output temperature data rate (4)
T = 0 to 80 °C ±1.5
50
75
100
200
10
25
1
4
°C
Hz
1. Typical specifications are not guaranteed.
2. By design, the typ. value is defined based on characterization data with 10 hPa pressure interval in mode 1 and 100 hPa pressure interval in mode 2.
3. Pressure noise RMS evaluated in a controlled environment, based on the average standard deviation of 50 measurements with AVG = 512, BW = ODR/9.
4. Output data rate is configured acting on ODR[3:0] in
Table 3. Absolute pressure accuracy at different full-scale modes
Full-scale mode
Mode 1 (full scale up to 1260 hPa)
Mode 2 (full scale up to 4060 hPa)
Condition
P = 660 ~ 1260 & T = -20 ~ 65 °C
P = 660 ~ 1260 & T = -40 ~ 105 °C
P = 1260 ~ 2060 & T = 0 ~ 65 °C
P = 1260 ~ 2060 & T = -40 ~ 105 °C
P = 2060 ~ 3060 & T = 0 ~ 65 °C
P = 2060 ~ 3060 & T = -40 ~ 105 °C
P = 3060 ~ 4060 & T = 0 ~ 65 °C
P = 3060 ~ 4060 & T = -40 ~ 105 °C
Typ. absolute pressure accuracy [hPa]
±0.5 hPa
±1 hPa
±0.15% of input pressure
±0.23% of input pressure
±0.21% of input pressure
±0.25% of input pressure
±0.28% of input pressure
±0.37% of input pressure page 6/58
3.2
ILPS22QS
Electrical characteristics
Electrical characteristics
VDD = 1.8 V, T = 25 °C, unless otherwise noted.
Table 4. Electrical characteristics - pressure and temperature
Symbol Parameter Test condition
VDD Supply voltage
Vdd_IO IO supply voltage
Idd
@ 1 Hz one-shot
AVG = 4 by disabling AH and Qvar (2)
AVG = 4 by enabling AH and Qvar
Supply current for pressure acquisition
@ 1 Hz one-shot
AVG = 128 by disabling AH and Qvar
AVG = 128 by enabling AH and Qvar
Supply current for Qvar (enabling AH and Qvar) AVG = 32 and ODR = 25 Hz
Max. Unit
1.7
1.08
1.8
4.3
9.2
11.7
46.5
3.6
V
3.6
V
µA
IddPdn
Power-down current by disabling AH and
Power-down current by enabling AH and Qvar
1
3.6
µA
1. Typical specifications are not guaranteed.
2. To disable AH and Qvar in order to save power consumption, 00h must be written in register 5Fh when the device is powered on. AH2/QVAR2 (pin 5) and AH1/QVAR1 (pin 7) must be connected to GND.
Table 5. Electrical parameters of Qvar (@Vdd = 1.8 V, T = 25 °C)
Parameter
Offset (shorted inputs)
Noise (shorted inputs)
Qvar gain
CMRR
Input impedance
Input range
1. Depending on ODR and AVG, refer to Table 6
Typ.
0.02
0.2
438k
64
±18
Unit mV
μV
LSB/mV dB
MΩ mV
Input impedance [MΩ]
AVG
32
64
128
512
4
8
16
Table 6. Input impedance of Qvar
1
21.6
21.6
21.5
21.4
21.2
20.9
19.1
4
21.5
21.4
21.2
20.9
20.3
19.1
14.1
10
21.4
21.2
20.7
19.9
18.5
16.2
9.3
R
IN
(ODR, AVG) [MΩ]
ODR [Hz]
25 50
21.1
20.5
19.6
17.9
15.3
11.8
5.0
20.5
19.6
17.9
15.3
11.8
8.1
2.8
75
20.0
18.7
16.5
13.3
9.6
6.2
2.0
100
19.6
17.9
15.3
11.8
8.1
5.0
1.5
200
17.9
15.3
11.8
8.1
5.0
2.8
0.8
DS13431 - Rev 2 page 7/58
ILPS22QS
Electrical characteristics
Symbol
DC input characteristics
Parameter
Vil
Vih
Low-level input voltage
(Schmitt buffer)
High-level input voltage
(Schmitt buffer)
DC output characteristics
Vol Low-level output voltage
Voh High-level output voltage
Table 7. DC characteristics
Condition
-
-
Min.
-
0.7 * Vdd_IO
-
Vdd_IO - 0.2
Typ.
-
-
-
-
Max.
Unit
0.3 * Vdd_IO
-
V
V
0.2
-
V
V
DS13431 - Rev 2 page 8/58
3.3
3.3.1
ILPS22QS
Communication interface characteristics
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and T
OP
.
Table 8. SPI slave timing values
Symbol
SPI clock frequency
CS setup time
SDI input hold time
SDO valid output time
Parameter
Max
Unit t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)
SPI clock cycle
CS hold time
SDI input setup time
SDO output hold time
SDO output disable time
Min
100
6
8
5
15
9
10
50
50 ns
MHz ns
1. Values are evaluated at 10 MHz clock frequency for SPI with 3 wires, based on characterization results, not tested in production.
2. Recommended to set max SPI clock 8 MHz to ≤50 Hz ODR.
Figure 4. SPI slave timing diagram
Note: Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports.
DS13431 - Rev 2 page 9/58
3.3.2
Note:
ILPS22QS
Communication interface characteristics
I²C - inter-IC control interface
Subject to general operating conditions for Vdd and T
OP
.
Table 9. I²C slave timing values
Symbol Parameter
I²C fast mode
Min Max
Min Max f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST) t su(SR) t su(SP) t w(SP:SR)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
START/REPEATED START condition hold time
REPEATED START condition setup time
STOP condition setup time
0
1.3
0.6
100
0
0.6
0.6
0.6
400
0.9
0
0.5
0.26
50
0
0.26
0.26
0.26
1000
Bus free time between STOP and START condition
Data valid time
Data valid acknowledge time
1.3
0.9
0.9
0.5
0.45
0.45
C
B
Capacitive load for each bus line 400
1. Data based on standard I²C protocol requirement, not tested in production.
2. Data for I²C fast mode and I²C fast mode+ have been validated by characterization, not tested in production.
550
Unit kHz
µs ns
µs pF
Figure 5. I²C slave timing diagram
REPEATED
START
START
SDA t su(SR) t w(SP:SR)
START t su(SDA) t h(SDA) t su(SP)
STOP
SCL t h(ST) t w(SCLL) t w(SCLH)
Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports.
DS13431 - Rev 2 page 10/58
3.4
Note:
ILPS22QS
Absolute maximum ratings
Absolute maximum ratings
Stress above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Vdd
Vdd_IO
Vin
P
T
STG
ESD
Table 10. Absolute maximum ratings
Ratings
Supply voltage
I/O pins supply voltage
Input voltage on any control pin
Overpressure
Storage temperature range
Electrostatic discharge protection
Supply voltage on any pin should never exceed 4.8 V.
Maximum value
-0.3 to 4.8
-0.3 to 4.8
-0.3 to Vdd_IO +0.3
2
-40 to +125
2 (HBM)
Unit
V
V
V
MPa
°C kV
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
DS13431 - Rev 2 page 11/58
4
4.1
4.2
4.3
ILPS22QS
Functionality
Functionality
The ILPS22QS is a high-resolution, digital output pressure sensor packaged in an HLGA full-mold package. The complete device includes a sensing element based on a piezoresistive Wheatstone bridge approach, and an IC interface which communicates a digital signal from the sensing element to the application.
Sensing element
An ST proprietary process is used to obtain a silicon membrane for MEMS pressure sensors. This silicon membrane is surrounded by a silicon spring structure and it contributes to isolate the membrane from mechanical and thermal stress in applications. When pressure is applied, the membrane deflection induces an imbalance in the Wheatstone bridge piezoresistances whose output signal is converted by the IC interface.
IC interface
The complete measurement chain is composed of a low-noise amplifier which converts the resistance unbalance of the MEMS sensors (pressure and temperature) into an analog voltage using an analog-to-digital converter.
The pressure and temperature data may be accessed through an I²C/MIPI I3C SM device particularly suitable for direct interfacing with a microcontroller.
/SPI interface thus making the
The ILPS22QS features a data-ready signal which indicates when a new set of measured pressure and temperature data are available, thus simplifying data synchronization in the digital system that uses the device.
Factory calibration
Thetrimming values are stored inside the device in a non-volatile structure. When the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation which allows the device to be used without requiring any further calibration.
DS13431 - Rev 2 page 12/58
4.4
ILPS22QS
Interpreting pressure readings
Interpreting pressure readings
The pressure data are stored in 3 registers: PRESS_OUT_H (2Ah)
,
PRESS_OUT_L (29h) , and PRESS_OUT_XL
. The value is expressed as a 24-bit signed number (in 2’s complement).
To obtain the pressure in hPa, take the complete 24-bit word and then divide by the sensitivity 4096
LSB/hPa when the FS_MODE bit is 0 (in mode 1, full scale is up to 1260 hPa) or divide by the sensitivity 2096 LSB/hPa when the FS_MODE bit is 1 (in mode 2, full scale is up to 4060 hPa).This
same interpretation is applied to pressure readings when FIFO is enabled and the pressure data
are stored in 3 registers: FIFO_DATA_OUT_PRESS_XL (78h)
,
FIFO_DATA_OUT_PRESS_L (79h) , and
.
Figure 6. Pressure readings
(1)
Pressure Value = PRESS_OUT_H 2Aℎ & PRESS_OUT_L 29ℎ & PRESS_OUT_XL 28ℎ = 3FF58Dℎ = 4191629 LSB signed decimal
(2)
When FS_MODE bit = 0 ( CTRL_REG2 (11h)
), for full scale up to 1260 hPa:
When FS_MODE bit = 1 ( CTRL_REG2 (11h)
), for full scale up to 4060 hPa:
DS13431 - Rev 2 page 13/58
4.5
ILPS22QS
Interpreting temperature readings
Interpreting temperature readings
The temperature data are stored in 2 registers:
.
The value is expressed as 2’s complement. To obtain the temperature in °C, take the two’s complement of the complete 16-bit word and then divide by the sensitivity 100 LSB/°C.
Figure 7. Temperature readings
TEMP_OUT_H
0 0 0 0 1 0 0 1
TEMP_OUT_L
1 1 0 0 0 1 0 0
Temperature value (LSB) = TEMP_OUT_H (2Ch) & TEMP_OUT_L (2Bh)
= 09C4 = 2500 LSB (decimal signed)
Temperature (°C) =
Temperature Value (LSB)
Sensitivity
=
2500 LSB
100 LSB/°C
= 25.00°C
DS13431 - Rev 2 page 14/58
5
ILPS22QS
FIFO
FIFO
•
•
•
•
•
The ILPS22QS embeds 128 slots of 24-bit data FIFO to store the pressure output values. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work according to six different modes:
•
Bypass mode
FIFO mode
Continuous (dynamic-stream) mode
Continuous (dynamic-stream)-to-FIFO mode
Bypass-to-continuous (dynamic-stream)
Bypass-to-FIFO mode
and each mode is selected by the TRIG_MODES bit and F_MODE[1:0] bits in
FIFO_CTRL (14h) . Programmable
FIFO threshold status, FIFO overrun events and the number of unread samples stored are available in the
registers.
(FIFO_WTM_IA) goes to '1' when the number of unread samples ( FIFO_STATUS1 (25h)
(FSS[7:0]) is greater than or equal to WTM[6:0] in FIFO_WTM (15h) . If FIFO_WTM (15h)
(WTM[6:0]) is equal to 0,
(FIFO_WTM_IA) stays at '0'.
(FIFO_OVR_IA) is equal to '1' if a FIFO slot is overwritten.
(FSS[7:0]) contains stored data levels of unread samples; when FSS[7:0] is equal to
‘00000000’, FIFO is empty; when FSS[7:0] is equal to ‘10000000’, FIFO is full and the unread samples are 128.
DS13431 - Rev 2 page 15/58
5.1
ILPS22QS
Bypass mode
Bypass mode
In bypass mode ( FIFO_CTRL (14h)
(TRIG_MODES and F_MODE[1:0] = ‘000’ or ‘100’), the FIFO is not operational and it remains empty.
Switching to bypass mode is also used to reset the FIFO. Passing through bypass mode is mandatory when switching between different FIFO buffer operating modes.
As described in the next figure, for each channel only the first address is used. When new data is available, the older data is overwritten.
Figure 8. Bypass mode
P i
P
0
P
1
P
2 empty
P
127
DS13431 - Rev 2 page 16/58
5.2
ILPS22QS
FIFO mode
FIFO mode
In FIFO mode ( FIFO_CTRL (14h)
(TRIG_MODES and F_MODE[1:0] = ‘001’) data from the output
PRESS_OUT_XL (28h) , PRESS_OUT_L (29h) , and PRESS_OUT_H (2Ah)
are stored in the FIFO until it is full.
To reset FIFO content, in order to select bypass mode the value '000' must be written in
(TRIG_MODE & F_MODE[1:0]). After this reset command it is possible to restart FIFO mode by writing the value
'001' in
(TRIG_MODE & F_MODE[1:0]).
The FIFO buffer memorizes 128 levels of data, but the depth of the FIFO can be resized/reduced by setting
(STOP_ON_WTM) bit. If the STOP_ON_WTM bit is set to '1', FIFO depth is limited to
FIFO_WTM (15h) (WTM[6:0]) data.
Figure 9. FIFO mode
P i
P
0
P
1
P
2
P
127
DS13431 - Rev 2 page 17/58
5.3
ILPS22QS
Continuous (dynamic-stream) mode
Continuous (dynamic-stream) mode
In Continuous (dynamic-stream) mode (
(TRIG_MODES and F_MODE[1:0] = ‘011’) after emptying the FIFO, the first new sample that arrives becomes the first to be read in a subsequent read burst. In this way, the number of new data available in FIFO does not depend on the previous read.
In continuous (dynamic-stream) mode FIFO_STATUS1 (25h)
(FSS[7:0]) is the number of new pressure samples available in the FIFO buffer.
Continuous (dynamic-stream) mode is intended to be used to read
(FSS[7:0]) samples when it is not possible to guarantee reading data within 1/ODR time period.
Figure 10. Continuous (Dynamic-Stream) mode
DS13431 - Rev 2 page 18/58
5.4
ILPS22QS
Bypass-to-FIFO mode
Bypass-to-FIFO mode
In bypass-to-FIFO mode
FIFO_CTRL (14h) (TRIG_MODES and F_MODE[1:0] = ‘101’), FIFO behavior switches
FIFO behaves like in bypass mode. Once the
INT_SOURCE (24h) (IA) bit rises to '1', FIFO behavior switches and
keeps behaving like in FIFO mode.
An interrupt generator has to be set to the desired configuration through INTERRUPT_CFG (0Bh)
.
Figure 11. Bypass-to-FIFO mode
P i P i
P
0
P
1
P
2
P
0
P
1
P
2 empty
P
127
P
127
Bypass mode
Trigger event
FIFO mode
DS13431 - Rev 2 page 19/58
5.5
ILPS22QS
Bypass-to-continuous (dynamic-stream) mode
Bypass-to-continuous (dynamic-stream) mode
In bypass-to-continuous (dynamic-stream) mode (
(TRIG_MODES and F_MODE[1:0] = ‘110’),
FIFO operates in bypass mode until it switches to continuous (dynamic-stream) mode behavior when
(IA) rises to '1', then FIFO behavior keeps behaving like in continuous (dynamic-stream) mode.
An interrupt generator has to be set to the desired configuration through INTERRUPT_CFG (0Bh)
.
Figure 12. Bypass-to-continuous (dynamic-stream) mode
P i P i
P
0
P
1
P
2
P
0
P
1
P
2 empty
P
127
P
126
P
127
Bypass mode
Trigger event
Dynamic-stream mode
DS13431 - Rev 2 page 20/58
5.6
ILPS22QS
Continuous (dynamic-stream)-to-FIFO mode
Continuous (dynamic-stream)-to-FIFO mode
In continuous (dynamic-stream)-to-FIFO mode (
(TRIG_MODES and F_MODE[1:0] = ‘111’), data are stored in FIFO and FIFO operates in continuous (dynamic-stream) mode behavior until it switches to
FIFO mode behavior when INT_SOURCE (24h) (IA) rises to '1'.
An interrupt generator has to be set to the desired configuration through INTERRUPT_CFG (0Bh)
.
Figure 13. Continuous (dynamic-stream)-to-FIFO mode
P i
P i
P
0
P
1
P
2
P
126
P
127
P
0
P
1
P
2
P
127
5.7
Dynamic-stream mode FIFO mode
Trigger event
Retrieving data from FIFO
FIFO data is read through FIFO_DATA_OUT_PRESS (78h, 79h and 7Ah).
The read address is automatically updated by the device and it rolls back to 78h when register 7Ch is reached. In order to read all FIFO levels in a multiple byte read, 384 bytes (3 output registers with 128 levels) must be read.
DS13431 - Rev 2 page 21/58
6
Application hints
VDD
Figure 14. ILPS22QS electrical connections (top view)
GND_IO
GND
C1
Vdd_IO
SCL/SPC
1
2
10 9 8
GND
7
6
AH1/QVAR1
CS
3 4 5
ILPS22QS
Application hints
DS13431 - Rev 2
GND GND
Figure 15. AH (analog hub) / Qvar external connections to pin 5, pin 7
Electrode 1
AH1/QVAR1 (Pin 7)
R1
D1
AH2/QVAR2 (Pin 5)
C1
R2
Electrode 2
D2
Name
C1
R1,R2
D1,D2
Value
10nF
500 Ohm
ESD Diode*
*ST ESDALCL5-1BM2 is referenced as an ST catalog product but other similar features of ESD diodes also can be used.
page 22/58
Note:
ILPS22QS
Application hints
The device power supply must be provided through the VDD line; a power supply decoupling capacitor C1
(100 nF) must be placed as near as possible to the supply pins of the device. The C1 capacitor can be tied to
VDD and Vdd_IO, but it is recommended to use 2 capacitors, one on each VDD and Vdd_IO line, in case VDD are Vdd_IO are separate. Depending on the application, an additional capacitor of 4.7 µF could be placed on the
VDD line.
If AH (analog hub) / Qvar is not used, it is recommended to connect both pin 5 and pin 7 to GND.
Qvar external connections to pin 5, pin 7
.
The functionality of the device and the measured data outputs are selectable and accessible through the I²C, MIPI
I3C SM , SPI interface. When using the I²C and MIPI I3C SM , CS must be tied to Vdd_IO.
All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to
this condition the measurement chain is powered off.
To guarantee proper power-off of the device, it is recommended to maintain the duration of the VDD line to GND for at least 10 ms.
Figure 16. ILPS22QS power-off sequence
VDD
0.7 V
Min.10 ms
Time
VDD rising / falling time: 10 µs ~ 100 ms
VDD must be lower than 0.7 V for at least 10 ms during power-off sequence for correct POR
DS13431 - Rev 2 page 23/58
6.1
6.2
6.3
ILPS22QS
Analog hub (AH) / Qvar functions
Analog hub (AH) / Qvar functions
The ILPS22QS embeds an analog hub sensing functionality which is able to connect an analog input and convert it to a digital signal as output. In addition, Qvar sensing with external electrodes can be used for user interfaces like water leakage detection, tap, double tap, long press, and L/R - R/L swipe.
Refer to application note AN5755 for additional details.
The input impedance between QVAR1 (pin 7) and QVAR2 (pin 5) of ILPS22QS depends on the AVG and ODR
configuration in Table 6. Input impedance of Qvar
.
Power-saving tip for the pressure sensor, disabling the analog hub (AH) / Qvar feature
The analog hub (AH) / Qvar feature is enabled by default and this feature causes slightly higher power consumption during operating and power-down modes to support AH/Qvar functions. Thus, it is recommended to use the following procedure to save power consumption in case the application doesn't need the AH/Qvar feature.
How to save power consumption? First of all, AH1/QVAR1 (pin 7) and AH2/QVAR2 (pin 5) must be connected to GND on the PCB (hardware design). Second, the application must write 00h in the 5Fh register whenever the application is powered on. Following this procedure, the device operates only in pressure sensor mode, disabling
AH/Qvar to achieve lower power consumption as described in
Table 4. Electrical characteristics - pressure and temperature .
Soldering information
The HLGA package is compliant with the ECOPACK standard and it is qualified for soldering heat resistance according to JEDEC J-STD-020.
For land pattern and soldering recommendations, consult technical note TN0018 available on www.st.com
.
DS13431 - Rev 2 page 24/58
ILPS22QS
Digital interfaces
7
Digital interfaces
7.1
7.2
Serial interfaces
The registers embedded in the ILPS22QS may be accessed through either the I²C, MIPI I3C SM or SPI serial interfaces. The latter operates in 3-wire SPI interface mode.
The serial interfaces are mapped to the same pins. To select/exploit the I²C interface, the CS line must be tied high (i.e. connected to Vdd_IO).
Pin name
CS
SCL/SPC
SDA
SDI/SDO
Table 11. Serial interface pin description
Pin description
Enables SPI
I²C and MIPI I3C SM / SPI mode selection
(1: SPI idle mode / I²C and MIPI I3C SM communication enabled;
0: SPI communication mode / I²C and MIPI I3C SM disabled)
I²C / MIPI I3C SM serial clock (SCL)
SPI serial port clock (SPC)
I²C / MIPI I3C SM serial data (SDA)
3-wire serial data input/output (SDI/SDO)
I²C serial interface (CS = high)
The ILPS22QS I²C is a bus slave. The I²C is employed to write data into registers whose content can also be read back.
The relevant I²C terminology is given in the following table.
Table 12. I²C terminology
Term Description
Transmitter The device which sends data to the bus
Receiver
Master
Slave
The device which receives data from the bus
The device which initiates a transfer, generates clock signals and terminates a transfer
The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines have to be connected to Vdd_IO through pull-up resistors.
The I²C interface is compliant with fast mode+ (1 MHz) I²C standards as well as with normal mode.
DS13431 - Rev 2 page 25/58
ILPS22QS
I²C serial interface (CS = high)
7.2.1
I²C operation
The transaction on the bus is started through a start (ST) signal. A start condition is defined as a high to low transition on the data line while the SCL line is held high. After the master has transmitted this, the bus is considered busy. The next data byte transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.
The 7-bit slave address (SAD) associated to the ILPS22QS is 1011100b = 5Ch.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.
The I²C embedded inside the ASIC behaves like a slave device and the following protocol must be adhered to.
After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK),
an 8-bit subaddress is transmitted (SUB). The IF_ADD_INC bit in CTRL_REG2 (11h)
enables subaddress auto increment (IF_ADD_INC is '1' by default), so if IF_ADD_INC = '1' the SUB (subaddress) is automatically increased to allow multiple data read/write.
The slave address is completed with a read/write bit. If the bit is ‘1’ (read), a repeated start (SR) condition must be issued after the two subaddress bytes; if the bit is ‘0’ (write) the master transmits to the slave with direction unchanged. The following table explains how the SAD+read/write bit pattern is composed, listing all the possible configurations.
Command
Read
Write
Table 13. SAD+read/write patterns
SAD[6:0]
1011100
1011100
R/W
1
0
10111001 (B9h)
10111000 (B8h)
SAD+R/W
Master
Slave
Master
Slave
ST
ST
Table 14. Transfer when master is writing one byte to slave
SAD+ W SUB DATA
SAK SAK
Table 15. Transfer when master is writing multiple bytes to slave
SAD+ W SUB DATA DATA
SAK SAK SAK
SAK
SAK
SP
SP
Master
Slave
ST
Table 16. Transfer when master is receiving (reading) one byte of data from slave
SAD+ W SUB SR SAD+ R
SAK SAK SAK DATA
NMAK SP
Master
Slave
ST
Table 17. Transfer when master is receiving (reading) multiple bytes of data from slave
SAD+
W
SUB SR
SAD+
R
MAK MAK
SAK SAK SAK DATA DATA DATA
NMAK SP
DS13431 - Rev 2 page 26/58
ILPS22QS
I²C serial interface (CS = high)
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a slave receiver does not acknowledge the slave address (that is, it is not able to receive because it is performing some real-time function), the data line must be kept high by the slave. The master can then abort the transfer. A low to high transition on the SDA line while the SCL line is high is defined as a stop condition. Each data transfer must be terminated by the generation of a stop (SP) condition.
In thepresented communication format MAK is master acknowledge and NMAK is no master acknowledge.
DS13431 - Rev 2 page 27/58
7.3
ILPS22QS
SPI bus interface (CS = low)
SPI bus interface (CS = low)
The ILPS22QS SPI is a bus slave. The SPI allows writing to and reading from the registers of the device.
The serial interface interacts with the application using only the 3-wire SPI which is available with CS , SPC ,
SDI/SDO .
Figure 17. SPI read protocol
The SPI read command is performed with 16 clock pulses. The multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.
bit0 :READ bit. The value is 1.
bit1-7 :address AD(6:0). This is the address field of the indexed register.
bit8-15 :data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit16-...
:data DO(...-8). Further data in multiple byte reads.
Figure 18. Multiple byte SPI read protocol (2-byte example)
DS13431 - Rev 2 page 28/58
7.3.1
ILPS22QS
SPI bus interface (CS = low)
SPI write in 3-wire mode
Figure 19. SPI write protocol
CS
SPC
SDI/O
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
The SPI write command is performed with 16 clock pulses. The multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
bit0 :WRITE bit. The value is 0.
bit1-7 :address AD(6:0). This is the address field of the indexed register.
bit8-15 :data DI(7:0) (write mode). This is the data that is written in the device (MSb first).
bit16-...
:data DI(...-8). Further data in multiple byte writes.
Figure 20. Multiple byte SPI write protocol (2-byte example)
CS
SPC
SDI/O
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
DS13431 - Rev 2 page 29/58
7.3.2
ILPS22QS
SPI bus interface (CS = low)
SPI read in 3-wire mode
.
Figure 21. SPI read protocol in 3-wire mode
CS
SPC
SDI/O
RW
AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI read command is performed with 16 clock pulses: bit0 :READ bit. The value is 1.
bit1-7 :address AD(6:0). This is the address field of the indexed register.
bit8-15 :data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode.
DS13431 - Rev 2 page 30/58
7.4
7.4.1
ILPS22QS
MIPI I3CSM slave interface
MIPI I3C SM slave interface
•
•
•
•
•
•
•
•
•
•
•
•
The ILPS22QS interface includes an MIPI I3C SM SDR only slave interface (compliant with release 1.1 of the specification) with MIPI I3C SM SDR embedded features:
• CCC command
Direct CCC communication (SET and GET)
Broadcast CCC communication
Private communications
Private read and write for single byte
Multiple read and write
In-band interrupt request
Slave reset pattern
Group address
Full range Vdd_IO support
Asynchronous modes 0 and 1
Synchronous mode
Error detection and recovery methods (S0-S6)
In order to disable the I3C block, I2C_I3C_DIS = 1 must be written in
.
MIPI I3C
SM
CCC supported commands
The list of MIPI I3C SM CCC commands supported by the device is detailed in the following table.
SETDASA
ENEC
DISEC
ENTAS0
SETXTIME
0x87
0x80 / 0x00
0x81/ 0x01
0x82 / 0x02
0x98 / 0x28
Table 18. MIPI I3C SM CCC commands
Command Command code Default
ENTDAA 0x07
Description
DAA procedure
Assign dynamic address using static address 0x6B/0x6A depending on SDO pin
Slave activity control (direct and broadcast)
Slave activity control (direct and broadcast)
Enter activity state (direct and broadcast)
Timing information exchange
GETXTIME 0x99
0x07
0x00
0x0C
0x92
Timing information exchange
RSTDAA
SETMWL
SETMRL
SETNEWDA
0x06
0x89 / 0x08
0x8A / 0x09
0x88
Reset the assigned dynamic address (broadcast only)
Define maximum write length during private write (direct and broadcast)
Define maximum read length during private read (direct and broadcast)
Change dynamic address
GETMWL
GETMRL
0x8B
0x8C
0x00
0x08
(2 byte)
0x00
0x10
0x05
(3 byte)
Get maximum write length during private write
Get maximum read length during private read
DS13431 - Rev 2 page 31/58
7.5
ILPS22QS
Overview of anti-spike filter management
Command Command code Default
GETPID
GETBCR
GETDCR
GETSTATUS
GETMXDS
GETCAPS
SETGRPA
RSTGRPA
RSTACT
0x8D
0x8E
0x8F
0x90
0x94
0x95
0x9B
0x2C/0x9C
0x9A/0x2A
Description
0x00
0x00
(2 byte)
0x08
0x60
0x00
0x11
0x18
0x00
0x02
0x08
0x00
0xB4
0x90
0x0B
0x02
0x08
0x00
0xB4
0x10
0x0B
SDO = 1
SDO = 0
0x07
(1 byte)
Bus characteristics register
0x62 default MIPI I3C SM device characteristics register
Status register
Return maximum write and read speed
Provide information about device capabilities and supported extended features
Group address assignment command
Reset the group address
Configure slave reset action
Overview of anti-spike filter management
The device acts as a standard I²C target as long as it has an I²C static address. The device is capable of detecting and disabling the I²C anti-spike filter after detecting the broadcast address (7'h7E/W). In order to guarantee proper behavior of the device, the I3C master must emit the first START, 7'h7E/W at open-drain speed using I²C fast mode plus reference timing.
After detecting the broadcast address, the device can receive the I3C dynamic address following the I3C pushpull timing. If the device is not assigned a dynamic address, then the device will continue to operate as an I²C device with no anti-spike filter. For the case in which the host decides to keep the device as I²C with anti-spike filter, there is a configuration required to keep the anti-spike filter active. This configuration is done by writing the
ASF_ON bit to '1' in the
register. This configuration forces the anti-spike filter to always be turned on instead of being managed by the communication on the bus.
DS13431 - Rev 2 page 32/58
8
ILPS22QS
Register mapping
Register mapping
The following table provides a quick overview of the 8-bit registers embedded in the device.
Name
Reserved
INTERRUPT_CFG
THS_P_L
THS_P_H
IF_CTRL
WHO_AM_I
CTRL_REG1
CTRL_REG2
CTRL_REG3
Reserved
FIFO_CTRL
FIFO_WTM
REF_P_L
REF_P_H
Reserved
I3C_IF_CTRL
RPDS_L
RPDS_H
Reserved
INT_SOURCE
FIFO_STATUS1
FIFO_STATUS2
STATUS
PRESSURE_OUT_XL
PRESSURE_OUT_L
PRESSURE_OUT_H
TEMP_OUT_L
TEMP_OUT_H
Reserved
FIFO_DATA_OUT_PRESS_XL
FIFO_DATA_OUT_PRESS_L
FIFO_DATA_OUT_PRESS_H
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
Register address
Hex
19
1A
1B
1C-23
24
12
13
14
15
16
17
18
00 – 0A
0B
0C
0D
0E
0F
10
11
2A
2B
2C
2D - 77
78
79
7A
25
26
27
28
29
Table 19. Registers address map
Type
R/W
R/W
R
R
R/W
R/W
R/W
Default
Hex
Function and comment
Output
Output
Output
Output
Output
-
Output
Output
Output
00h
B4h
00h
10h
-
00h
00h
00h
Reserved
Interrupt register
Pressure threshold registers
Interface control register
Who am I
Control registers
01h
-
00h
00h
00h
00h
-
Reserved
FIFO configuration registers
Reference pressure registers
80h
00h
00h
Reserved
Interface configuration register
Pressure offset registers
Reserved
Output Interrupt register
Output
FIFO status registers
Output
Output Status register
Pressure output registers
Temperature output registers
Reserved
FIFO pressure output registers
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
DS13431 - Rev 2 page 33/58
ILPS22QS
Register mapping
To guarantee the proper behavior of the device, all register addresses not listed in the above table must not be accessed and the content stored in those registers must not be changed.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
DS13431 - Rev 2 page 34/58
ILPS22QS
Register description
9
Register description
The device contains a set of registers which are used to control its behavior and to retrieve pressure and temperature data. The register address, made up of 7 bits, is used to identify them and to read/write the data through the serial interface.
9.1
7
AUTOREFP
INTERRUPT_CFG (0Bh)
Interrupt mode for pressure acquisition configuration (R/W)
6 5 4 3
RESET_ARP AUTOZERO RESET_AZ -
2
LIR
1
PLE
0
PHE
AUTOREFP
RESET_ARP
AUTOZERO
RESET_AZ
LIR
PLE
PHE
Enable AUTOREFP function. Default value: 0
(0: normal mode; 1: AUTOREFP enabled)
Reset AUTOREFP function. Default value: 0
(0: normal mode; 1: reset AUTOREFP function)
Enable AUTOZERO function. Default value: 0
(0: normal mode; 1: AUTOZERO enabled)
Reset AUTOZERO function. Default value: 0
(0: normal mode; 1: reset AUTOZERO function)
Latch interrupt request to the
INT_SOURCE (24h) register. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
Enable interrupt generation on pressure low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on pressure value lower than preset threshold)
Enable interrupt generation on pressure high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on pressure value higher than preset threshold)
It is enabled when either the PHE bit or PLE bit (or both bits) is set to '1'. Then, the differential pressure can be compared to a user-defined threshold stored in the 15-bit THS_P (0Ch and 0Dh) registers.
The threshold pressure value defined by the user is a 15-bit unsigned value in a 16-bit register composed of
The value is:
THS_P (15-bit unsigned) = Desired interrupt threshold (hPa) x 16 for FS_mode 1 (up to 1260 hPa)
THS_P (15-bit unsigned) = Desired interrupt threshold (hPa) x 8 for FS_mode 2 (up to 4060 hPa)
The PHE and PLE bits in INTERRUPT_CFG (0Bh) enable the differential pressure interrupt generation on the positive or negative event respectively.
The differential interrupt must be used with AUTOREFP or AUTOZERO mode.
DS13431 - Rev 2 page 35/58
ILPS22QS
THS_P_L (0Ch)
P_DIFF_IN
Figure 22. “Threshold-based” interrupt event
Threshold positive value
Threshold negative value
Positive
Negative
•
•
To enable the AUTOZERO mode, the AUTOZERO bit must be set to '1' and then the measured pressure value
is used as the reference and stored in the register REF_P ( REF_P_L (16h)
,
REF_P_H (17h) ). From this point
on, the output pressure value (
PRESS_OUT_XL (28h) , PRESS_OUT_L (29h) , PRESS_OUT_H (2Ah) ) is updated
with the difference between the measured pressure and REF_P.
P_DIFF_IN = measured pressure - REF_P
PRESS_OUT = measured pressure - REF_P
After the first conversion, the AUTOZERO bit is automatically set back to '0'. In order to return back to normal mode, the RESET_AZ bit in the INTERRUPT_CFG (0Bh) register has to be set to '1'. This also resets the content of the REF_P registers to 0.
AUTOREFP mode allows using the pressure differential for the generation of the interrupt keeping the output pressure registers PRESS_OUT (
PRESS_OUT_XL (28h) , PRESS_OUT_L (29h)
,
comparing REF_P. If the AUTOREFP bit is set to '1', the measured output pressure is used as the reference in the
register REF_P ( REF_P_L (16h)
,
REF_P_H (17h) ) for interrupt generation with following:
• P_DIFF_IN = measured pressure - REF_P
The output registers PRESS_OUT (28h, 29h and 2Ah) are not changed by REF_P and shows as follows.
• PRESS_OUT = measured pressure
After the first conversion, the AUTOREFP bit is automatically set to '0'. In order to return back to normal mode, the
RESET_ARP bit has to be set to '1'.
9.2
7
THS7
THS_P_L (0Ch)
User-defined threshold value for pressure interrupt event (Least significant bits) (R/W)
6 5 4 3 2
THS6 THS5 THS4 THS3 THS2
1
THS1
0
THS0
THS[7:0]
This register contains the low part of threshold value for pressure interrupt generation.
Default value: 00h
The threshold value for pressure interrupt generation is a 15-bit unsigned right-justified value composed of
and THS_P_L (0Ch).The value is expressed as:
THS_P (15-bit unsigned) = Desired interrupt threshold (hPa) x 16 for FS_mode 1 (up to 1260 hPa)
THS_P (15-bit unsigned) = Desired interrupt threshold (hPa) x 8 for FS_mode 2 (up to 4060 hPa)
To enable the interrupt event based on this user-defined threshold, the PHE bit or PLE bit (or both bits) in
INTERRUPT_CFG (0Bh) has to be enabled.
DS13431 - Rev 2 page 36/58
ILPS22QS
THS_P_H (0Dh)
9.3
7
-
THS_P_H (0Dh)
User-defined threshold value for pressure interrupt event (Most significant bits) (R/W)
6 5 4 3 2
THS14 THS13 THS12 THS11 THS10
1
THS9
I2C_I3C_DIS
EN_SPI_READ
SDA_PU_EN
CS_PU_DIS
Disable I²C and I3C digital interfaces. Default value: 0
(0: enable I²C and I3C digital interfaces; 1: disable I²C and I3C digital interfaces)
Enable SPI read mode. This bit must be set to 1 before using SPI 3-wire interface. Default value: 0
(0: disable SPI read for 3-wire SPI; 1: enable SPI read for 3-wire SPI)
Enable pull-up on the SDA pin. Default value: 0
(0: SDA pin pull-up disconnected; 1: SDA pin with pull-up)
Disable pull-up on CS pin. Default value: 0
(0: CS pin with internal pull-up; 1: CS pin pull-up disconnected)
9.5
7
1
WHO_AM_I (0Fh)
Device Who am I
6 5
0 1
4
1
3
0
2
1
1
0
0
THS8
THS[14:8]
Default value: 00h
9.4
7
0
IF_CTRL (0Eh)
Interface control register (R/W)
6 5 4
I2C_I3C_DIS EN_SPI_READ SDA_PU_EN
3
0
2
0
1
CS_PU_DIS
0
-
0
0
DS13431 - Rev 2 page 37/58
ILPS22QS
CTRL_REG1 (10h)
9.6
7
0
CTRL_REG1 (10h)
Control register 1 (R/W)
6 5
ODR3 ODR2
4
ODR1
3
ODR0
2
AVG2
1
AVG1
0
AVG0
ODR[3:0]
AVG[2:0]
ODR[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
Output data rate selection. Default value: 0000
Average selection. Default value: 000
Table 20. Output data rate bit configurations
ODR of pressure, temperature, and Qvar
Power-down / one-shot
1 Hz
4 Hz
10 Hz
25Hz
50 Hz
75 Hz
100 Hz
200 Hz
AVG[2:0]
000
001
010
011
100
101
111
Table 21. Averaging selection
Averaging of pressure, temperature, and Qvar
4
8
16
32
64
128
512
The power consumption of the ILPS22QS mainly depends on the selected ODR (Output Data Rate) and on the selected resolution. The user can select the desired ODR and the oversampling frequency for pressure measurements in the CTRL_REG1 (10h) register. The ODR[3:0] bits are dedicated to the ODR selection, while the AVG[2:0] bits are used to configure the resolution.
DS13431 - Rev 2 page 38/58
ILPS22QS
CTRL_REG1 (10h)
AVG
512
128
64
32
16
8
4
The following table summarizes the current consumption of all the ASIC resolution modes.
Table 22. Power consumption for pressure acquisition
One-shot mode
Current consumption (μA)
@ 1 Hz
31.1
9.2
5.5
3.6
2.7
2
1.8
ODR max
25
75
100
200
300
400
500
1 Hz
Continuous mode – current consumption (μA) vs. ODR
4 Hz 10 Hz 25 Hz 50 Hz 75 Hz
32.8
126.8
314.4
10 35.6
86.7
6.3
4.4
3.5
2.7
2.5
20.4
12.8
9
6
5
48.7
29.8
20.2
12.6
10.2
783.8
214.3
119.4
71.9
48.2
29.1
23.2
-
427
237.2
142.2
94.8
56.5
44.7
-
639.8
355
212.6
141.4
84.2
66.2
100 Hz
-
-
472.8
282.9
188
111.5
87.8
200 Hz
AVG
512
128
64
32
16
8
4
Table 23. Power consumption for Qvar acquisition
One-shot mode
Current consumption (μA)
@ 1 Hz
21.9
8.6
6.5
5.4
4.8
4.3
4.2
ODR max
25
75
100
200
300
400
500
Continuous mode – current consumption (μA) vs. ODR
1 Hz 4 Hz 10 Hz 25 Hz
22.6
76.4
9.3
24.1
7.2
6.1
15.4
11.1
5.5
5
4.9
8.9
6.9
6.4
184.5
53.9
32.1
21.3
15.7
10.7
9.3
458.6
128.4
73.6
46.5
32.8
20
16.6
50 Hz 75 Hz
-
253.4
143.2
88.6
61.4
35.8
28.9
-
379
213.1
131
90
51.4
41.2
100 Hz
-
-
283.1
173.4
118.7
67.1
53.5
200 Hz
-
-
-
343.4
233.4
130.2
102.7
The noise performance of pressure in ILPS22QS is also defined as depending on the ODR and selected resolution and its performance is a trade-off between the power consumption and resolution. The noise performance is indicated in the following table.
AVG
512
128
64
32
16
8
4
1. LPF1 filter is disabled.
ODR/2
0.59
0.9
1.20
1.64
2.30
3.12
4.26
Table 24. Noise performance of pressure
FS = 1260 hPa
Pressure noise (Pa rms
)
ODR/4
0.44
0.67
0.86
1.16
1.63
2.18
2.87
ODR/9
0.34
0.48
0.64
0.87
1.18
1.60
2.20
ODR/2
1.16
2.15
2.98
4.14
5.86
8.11
11.3
FS = 4060 hPa
Pressure noise (Pa rms
)
ODR/4
0.85
1.48
2.05
2.89
4.11
5.73
7.82
ODR/9
0.64
1.11
1.55
2.10
2.97
4.23
5.81
-
-
-
564.4
374
221.7
174
DS13431 - Rev 2 page 39/58
ILPS22QS
CTRL_REG1 (10h)
When the ODR bits are set to '0000', the device is in Power-down mode . When the device is in power-down mode, almost all internal blocks of the device are switched off to minimize power consumption. The digital interface is still active to allow communication with the device. The content of the configuration registers is preserved and output data registers are not updated, therefore keeping the last data sampled in memory before going into power-down mode.
If the ONESHOT bit in CTRL_REG2 (11h)
is set to '1', one-shot mode is triggered and a new acquisition starts when it is required. Enabling this mode is possible only if the device was previously in power-down mode (ODR bits set to '0000'). Once the acquisition is completed and the output registers updated, the device automatically enters in power-down mode. ONESHOT bit self-clears itself.
When the ODR bits are set to a value different than '0000', the device is in continuous mode and automatically acquires a set of data (pressure and temperature) at the frequency selected through the ODR[3:0] bits.
DS13431 - Rev 2 page 40/58
ILPS22QS
CTRL_REG2 (11h)
9.7
7
BOOT
CTRL_REG2 (11h)
Control register 2 (R/W)
6 5
FS_Mode LFPF_CFG
4
EN_LPFP
3
BDU
2
SWRESET
1
-
0
ONESHOT
BOOT
FS_Mode
LFPF_CFG
EN_LPFP
BDU
SWRESET
ONESHOT
Reboots memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
Full-scale selection. Default value: 0
(0: mode 1, full scale up to 1260 hPa; 1: mode 2, full scale up to 4060 hPa)
Low-pass filter configuration. Default value: 0
(0: ODR/4; 1: ODR/9)
Enables low-pass filter on pressure data. Default value: 1
(0: disable, 1: enable)
Block data update. Default value: 0
(0: continuous update;
1: output registers not updated until MSB and LSB have been read)
Software reset. Default value: 0
(0: normal mode; 1: software reset).
The bit is self-cleared when the reset is completed.
Enables one-shot mode. Default value: 0
(0: idle mode; 1: a new dataset is acquired)
1. To guarantee the correct behavior of the BDU feature, PRESS_OUT_H (2Ah) must be the last address
read.
The BOOT bit is used to refresh the content of the internal registers stored in the Non-Volatile memory block. At device power-up, the content of the Non-Volatile memory block is transferred to the internal registers related to the trimming functions to allow correct behavior of the device itself. If for any reason the content of the trimming registers is modified, it is sufficient to use this bit to restore the correct values. When the BOOT bit is set to '1', the content of the internal Non-Volatile memory is copied into the corresponding internal registers and is used to calibrate the device. These values are factory trimmed and they are different for every device. They allow the correct behavior of the device and normally they should not be changed. At the end of the boot process, the
BOOT bit is set again to '0' by hardware. The BOOT bit takes effect immediately after it is set to 1.
The ONESHOT bit is used to start a new conversion when the ODR[3:0] bits in CTRL_REG1 (10h)
are set to '0000'. Writing a '1' to ONESHOT triggers a single measurement of pressure and temperature. Once the measurement is done, the ONESHOT bit will self-clear, the new data are available in the output registers, and the
bits are updated.
DS13431 - Rev 2 page 41/58
ILPS22QS
CTRL_REG3 (12h)
9.8
7
AH_QVAR_EN
CTRL_REG3 (12h)
Control register 3 (R/W)
6 5
0 0
4
0
3
0
2
0
1
0
0
IF_ADD_INC
AH_QVAR_EN
Enables AH (analog hub) / Qvar functions. Default : 0
(0: disable; 1: enable)
IF_ADD_INC
Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI). Default value: 1
(0: disable, 1: enable)
The AH_QVAR_EN bit enables the AH (analog hub) and Qvar functions. The network of external connections and electrodes must be designed in the final application if these functions need to be enabled. Refer to
(analog hub) / Qvar external connections to pin 5, pin 7 .
The IF_ADD_INC bit enables the address to be automatically incremented during a multiple byte access with a serial interface (SPI or I²C).
9.9
7
0
FIFO_CTRL (14h)
FIFO control register (R/W)
6
0
5
0
4
0
3
STOP_ON_WTM
2
TRIG_MODES
1
F_MODE1
0
F_MODE0
STOP_ON_WTM
TRIG_MODES
F_MODE[1:0]
Stop-on-FIFO watermark. Enables FIFO watermark level use. Default value: 0
(0: disable; 1: enable)
Enables triggered FIFO modes. Default value: 0
Selects triggered FIFO modes. Default value: 00
.
TRIG_MODES x
0
0
1
1
1
Table 25. FIFO mode selection
F_MODE[1:]
00
01
1x
01
10
11
Mode
Bypass
FIFO mode
Continuous (Dynamic-Stream)
Bypass-to-FIFO
Bypass-to-Continuous (Dynamic-Stream)
Continuous (Dynamic-Stream)-to-FIFO
The STOP_ON_WTM bit enables the use of the FIFO watermark level: when the number of samples in FIFO is
equal to the watermark level (set using the WTM[6:0] bits in FIFO_WTM (15h)
) then FIFO is full.
The TRIG_MODES bit enables the triggered FIFO modes.
The F_MODE[1:0] bits select one of the FIFO modes, as described in
Output pressure data are read through
DS13431 - Rev 2 page 42/58
ILPS22QS
FIFO_WTM (15h)
9.10
7
0
FIFO_WTM (15h)
FIFO threshold setting register (R/W)
6 5
WTM6 WTM5
4
WTM4
3
WTM3
2
WTM2
1
WTM1
0
WTM0
WTM[6:0] FIFO threshold. Watermark level setting. Default value: 0000000
9.11
7
REFL7
REF_P_L (16h)
Reference pressure LSB data (R)
6 5
REFL6 REFL5
4
REFL4
3
REFL3
REFL[7:0]
Thisregister contains the low part of the reference pressure value.
Default value: 00000000
The reference pressure value is 16-bit data and it is composed of REF_P_H (17h)
and REF_P_L (16h). The value is expressed as 2’s complement.
The reference pressure value is stored and used when the AUTOZERO or AUTOREFP function is enabled.
Please refer to the
INTERRUPT_CFG (0Bh) register description.
9.12
7
REFL15
REF_P_H (17h)
Reference pressure MSB data (R)
6 5
REFL14 REFL13
4
REFL12
3
REFL11
2
REFL10
1
REFL9
0
REFL8
REFL[15:8]
Thisregister contains the high part of the reference pressure value.
Default value: 00000000
2
REFL2
1
REFL1
0
REFL0
DS13431 - Rev 2 page 43/58
ILPS22QS
I3C_IF_CTRL_ADD (19h)
9.13
7
1
I3C_IF_CTRL_ADD (19h)
Control register (R/W)
6 5
0 ASF_ON
4
0
3
0
2
0
1
I3C_Bus_
Avb_Sel1
0
I3C_Bus_
Avb_Sel0
ASF_ON
I3C_Bus_Avb_Sel[1:0]
Enable anti-spike filters. Default value: 0
(0: anti-spike filters are managed by protocol and turned off after the broadcast address;
1: anti-spike filters on SCL and SDA lines are always enabled)
These bits are used to select the bus available time when I3C IBI is used.
Default value: 00
(00: bus available time equal to 50 µsec;
01: bus available time equal to 2 µsec;
10: bus available time equal to 1 msec;
11: bus available time equal to 25 msec)
9.14
7
RPDS7
RPDS_L (1Ah)
Pressure offset (LSB data)
6 5
RPDS6 RPDS5
4
RPDS4
3
RPDS3
2
RPDS2
1
RPDS1
0
RPDS0
RPDS[7:0]
Thisregister contains the low part of the pressure offset value.
Default value: 00000000
The pressure offset value is 16-bit data that can be used to implement one-point calibration (OPC) after soldering.
This value is composed of
and RPDS_L (1Ah). The value is expressed as 2’s complement.
The customer can perform a one-point calibration after soldering (recommended) and the offset coefficient can be stored for OPC in register RPDS (1Ah, 1Bh). These stored offset values are directly added to the compensated pressure data in the block diagram below. To give better flexibility to the user, the OPC value can be written twice in the same register map.
Figure 23. One-point calibration
DS13431 - Rev 2 page 44/58
ILPS22QS
RPDS_H (1Bh)
9.15
7
RPDS15
RPDS_H (1Bh)
Pressure offset (MSB data)
6 5
RPDS14 RPDS13
4
RPDS12
3
RPDS11
2
RPDS10
1
RPDS9
0
RPDS8
RPDS[15:8]
This register contains the high part of the pressure offset value.
Default value: 00000000
9.16
7
BOOT_ON
INT_SOURCE (24h)
Interrupt source (read only) register for differential pressure. A read at this address clears the INT_SOURCE register itself.
6 5 4 3 2 1 0
0 0 0 0 IA PL PH
BOOT_ON
IA
PL
PH
Indication that Boot (reboot) phase is running.
(0: boot phase not running; 1: boot phase is running)
Interrupt active.
(0: no interrupt has been generated;
1: one or more interrupt events have been generated).
Differential pressure Low.
(0: no interrupt has been generated;
1: low differential pressure event has occurred).
Differential pressure High.
(0: no interrupt has been generated;
1: high differential pressure event has occurred).
9.17
7
FSS7
FIFO_STATUS1 (25h)
FIFO status register (read only)
6 5
FSS6 FSS5
4
FSS4
3
FSS3
FSS[7:0]
FIFO stored data level, number of unread samples stored in FIFO.
(00000000: FIFO empty; 10000000: FIFO full, 128 unread samples)
2
FSS2
1
FSS1
0
FSS0
DS13431 - Rev 2 page 45/58
ILPS22QS
FIFO_STATUS2 (26h)
9.18
7
FIFO_STATUS2 (26h)
FIFO status register (read only)
6 5
FIFO_WTM_IA FIFO_OVR_IA FIFO_FULL_IA
T_OR
P_OR
T_DA
P_DA
4
-
3
-
2
-
FIFO_WTM_IA
FIFO_OVR_IA
FIFO_FULL_IA
FIFO threshold (watermark) status. Default value: 0
(0: FIFO filling is lower than treshold level;
1: FIFO filling is equal or higher than treshold level).
FIFO overrun status. Default value: 0
(0: FIFO is not completely full;
1: FIFO is full and at least one sample in the FIFO has been overwritten).
FIFO full status. Default value: 0
(0: FIFO is not completely filled;
1: FIFO is completely filled, no samples overwritten)
9.19
7
-
STATUS (27h)
Status register (read only)
6 5
T_OR
4
P_OR
3
-
2
-
Temperature data overrun.
(0: no overrun has occurred;
1: a new data for temperature has overwritten the previous data)
Pressure data overrun.
(0: no overrun has occurred;
1: new data for pressure has overwritten the previous data)
Temperature data available.
(0: new data for temperature is not yet available;
1: a new temperature data is generated)
Pressure data available.
(0: new data for pressure is not yet available;
1: a new pressure data is generated)
This register is updated every ODR cycle.
1
-
0
-
1
T_DA
0
P_DA
DS13431 - Rev 2 page 46/58
ILPS22QS
PRESS_OUT_XL (28h)
9.20
7
POUT7
PRESS_OUT_XL (28h)
Either pressure output or AH/Qvar output value LSB data (read only)
6 5 4 3
POUT6 POUT5 POUT4 POUT3
2
POUT2
1
POUT1
0
POUT0
POUT[7:0] This register contains the low part of the pressure or AH/Qvar output value.
The pressure output value is a 24-bit data that contains the measured pressure. It is composed of
PRESS_OUT_H (2Ah) , PRESS_OUT_L (29h)
and PRESS_OUT_XL (28h). The value is expressed as 2’s complement.
The output pressure register PRESS_OUT is provided as the difference between the measured pressure and the content of the register RPDS (1Ah, 1Bh).
Please refer to Section 4.4 Interpreting pressure readings
for additional information.
9.21
7
POUT15
PRESS_OUT_L (29h)
Either pressure output or AH/Qvar output value middle data (read only)
6 5 4 3
POUT14 POUT13 POUT12 POUT11
2
POUT10
1
POUT9
0
POUT8
POUT[15:8]
This register contains the mid part of the pressure or AH/Qvar output value.
.
9.22
7
POUT23
PRESS_OUT_H (2Ah)
Either pressure output or AH/Qvar output value MSB data (read only)
6
POUT22
5
POUT21
4
POUT20
3
POUT19
2
POUT18
1
POUT17
0
POUT16
POUT[23:16]
This register contains the high part of the pressure or AH/Qvar output value.
9.23
7
TOUT7
TEMP_OUT_L (2Bh)
Temperature output value LSB data (read only)
6 5 4
TOUT6 TOUT5 TOUT4
3
TOUT3
2
TOUT2
1
TOUT1
TOUT[7:0] This register contains the low part of the temperature output value.
The temperature output value is 16-bit data that contains the measured temperature. It is composed of
, and TEMP_OUT_L (2Bh). The value is expressed as 2’s complement.
This register contains the temperature value and the resolution is: 1LSB = 0.01 °C.
0
TOUT0
DS13431 - Rev 2 page 47/58
9.24
7
TOUT15
TEMP_OUT_H (2Ch)
Temperature output value MSB data (read only)
6 5 4
TOUT14 TOUT13 TOUT12
3
TOUT11
2
TOUT10
TOUT[15:8] Thisregister contains the high part of the temperature output value.
9.25
7
FIFO_P7
FIFO_DATA_OUT_PRESS_XL (78h)
Either FIFO pressure or AH/Qvar output LSB data (read only)
6 5 4 3
FIFO_P6 FIFO_P5 FIFO_P4 FIFO_P3
2
FIFO_P2
FIFO_P[7:0] Pressure or AH/Qvar LSB data in FIFO buffer
9.26
7
FIFO_P15
FIFO_DATA_OUT_PRESS_L (79h)
Either FIFO pressure or AH/Qvar output middle data (read only)
6 5 4 3
FIFO_P14 FIFO_P13 FIFO_P12 FIFO_P11
2
FIFO_P10
1
TOUT9
1
FIFO_P1
0
TOUT8
0
FIFO_P0
1
FIFO_P9
0
FIFO_P8
FIFO_P[15:8] Pressure or AH/Qvar middle data in FIFO buffer
9.27
7
FIFO_P23
FIFO_DATA_OUT_PRESS_H (7Ah)
Either FIFO pressure or AH/Qvar output MSB data (read only)
6
FIFO_P22
5
FIFO_P21
4
FIFO_P20
3
FIFO_P19
2
FIFO_P18
1
FIFO_P17
0
FIFO_P16
FIFO_P[23:16] Pressure or AH/Qvar MSB data in FIFO buffer
ILPS22QS
TEMP_OUT_H (2Ch)
DS13431 - Rev 2 page 48/58
10
10.1
ILPS22QS
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
HLGA-10L package information
Figure 24. HLGA-10L (2.0 x 2.0 x 0.73 mm typ.) package outline and mechanical dimensions
Pin 1
L
B
Sensing area
H 0.5
1
2x (0.1)
Pin 1
A
0.91
0.31
C
(10x) 0.25
±0.05
0.15
C A B
0.05
C
L e
ITEM n g t h [ L
W i d t h [ W
]
]
H e i g h t [ H ]
Dimensions are in millimeter unless otherwise specified
General Tolerance is +/-0.1mm unless otherwise specified
OUTER DIMENSIONS
DIMENSION [mm]
2
0 .
8
2 m a x
TOLERANCE [mm]
± 0 .
1
± 0 .
1
/
DM00386636_1
DS13431 - Rev 2 page 49/58
10.2
ILPS22QS
HLGA-10L packing information
HLGA-10L packing information
0.30±0.05
Figure 25. Carrier tape information for HLGA-10L package
4.00
2.00±0.05 SEE NOTE 2
4.00 SEE NOTE 1
1.50 +
0.1
0.0
1.00 MIN
R 0.20 MAX
Bo
A A
B
1.75±0.10
5.50±0.05
SEE NOTE 2
12.00 +-
0.3
0.1
Ko
SECTION B-B
0.13
0.13
DETAIL D
SCALE 6:1
SCALE 12 : 1
R0.25
Ao
SECTION A-A
SCALE 1:1
DIM
Ao 2.20
Bo 2.20
Ko 1.00
±
0.05
0.05
0.10
NOTES:
1.
2.
3.
10 SPROCKET HOLE PITCH CUMULATIVE TOLERANCE ±0.2
POCKET POSITION RELATIVE TO SPROCKET HOLE MEASURED AS TRUE POSITION OF POCKET, NOT
POCKET HOLE.
Ao AND Bo ARE MEASURED ON A PLANE AT A DISTANCE "R" ABOVE THE BOTTOM OF THE POCKET.
Figure 26. HLGA-10L package orientation in carrier tape
B
DS13431 - Rev 2 page 50/58
DS13431 - Rev 2
ILPS22QS
HLGA-10L packing information
A
Figure 27. Reel information for carrier tape of HLGA-10L package
T
40mm min.
Access hole at slot location
B
C
D N
Full radius
G measured at hub
Tape slot in core for tape start
2.5mm min. width
Table 26. Reel dimensions for carrier tape of HLGA-10L package
Reel dimensions (mm)
A (max)
B (min)
C
D (min)
N (min)
G
T (max)
330
1.5
13 ±0.25
20.2
60
12.4 +2/-0
18.4
page 51/58
ILPS22QS
Revision history
Date
01-Oct-2021
22-Dec-2021 2
Table 27. Document revision history
Version
1
Changes
Initial release
Added Qvar functionality
Updated Idd in Table 4. Electrical characteristics - pressure and temperature
and added
Table 5. Electrical parameters of Qvar (@Vdd = 1.8 V, T = 25 °C)
and
Table 6. Input impedance of Qvar
Updated GETPID command in Table 18. MIPI I3C SM CCC commands
Updated Section 6 Application hints , added Figure 15. AH (analog hub) /
Qvar external connections to pin 5, pin 7
, added
Added
Table 23. Power consumption for Qvar acquisition
Minor textual updates
DS13431 - Rev 2 page 52/58
ILPS22QS
Contents
Contents
Power-saving tip for the pressure sensor, disabling the analog hub (AH) / Qvar feature . . . 24
DS13431 - Rev 2 page 53/58
ILPS22QS
Contents
DS13431 - Rev 2 page 54/58
ILPS22QS
Contents
DS13431 - Rev 2 page 55/58
ILPS22QS
List of tables
List of tables
DS13431 - Rev 2 page 56/58
ILPS22QS
List of figures
List of figures
DS13431 - Rev 2 page 57/58
ILPS22QS
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13431 - Rev 2 page 58/58
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