STMicroelectronics LPS27HHTW Datasheet
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LPS27HHTW
Datasheet
MEMS pressure sensor: 260-1260 hPa absolute digital output barometer with embedded temperature sensor in water-resistant package
Product status link
LPS27HHTW
Product summary
Order code
Temp. range [°C]
Package
Packing
LPS27HHTWTR
-40 to +85°C
CCLGA-10L
Tape and reel
Product label
Features
• Pressure sensor with water-resistant package
• Potting gel and grounded metal cap
• 260 to 1260 hPa absolute pressure range
• Current consumption down to 4 µA
• Absolute pressure accuracy: 0.5 hPa
• Low pressure sensor noise: 0.7 Pa
• Temperature accuracy: ±1.5 °C
• Embedded temperature compensation
• 24-bit pressure data output
• ODR from 1 Hz to 200 Hz
• SPI, I²C or MIPI I3C SM interfaces
• Embedded FIFO
• Interrupt functions: Data-Ready, FIFO flags, pressure thresholds
• Supply voltage: 1.7 to 3.6 V
• ECOPACK lead-free compliant
Applications
• Altimeters and barometers for portable devices
• GPS applications
• Weather station equipment
• Sport watches
• e-cigarettes
• Water depth monitoring
• Gas metering
Description
The LPS27HHTW is an ultra-compact piezoresistive absolute pressure sensor which functions as a digital output barometer. The device also embeds a temperature sensor to monitor ambient temperature. The LPS27HHTW comprises a sensing element and an IC interface which communicates through I²C, MIPI I3C SM or SPI from the sensing element to the application.
The sensing element, which detects absolute pressure, consists of a suspended membrane manufactured using a dedicated process developed by ST.
The LPS27HHTW is available in a ceramic LGA package with metal lid. It is guaranteed to operate over a temperature range extending from -40 °C to +85 °C.
The package is holed to allow external pressure to reach the sensing element. Gel inside the IC protects the electrical components from water and the metal cap is grounded electrically for better ESD robustness.
DS13489 - Rev 1 - January 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
LPS27HHTW
Block diagrams
Block diagrams
Figure 1. Device architecture block diagram
Temperature
Sensor
MUX
Analog
Front-End
ADC
Digital
Logic
I
2
C
MIPI I3C
SM
SPI
Sensing Element
Analog
Front-End
Sensor Bias
ADC
Voltage and Current Bias Clock and timing
Digital
LP Filter
LPF0
Figure 2. Digital logic
Pressure
Compensation
Temperature
Compensation
Digital
LP Filter
LPF1
EN_LPFP
1
Pout
0
Output
Registers
Tout FIFO
I 2 C
MIPI I3C SM
SPI
DS13489 - Rev 1 page 2/55
2
Pin description
Figure 3. Pin connections (bottom view)
1 2
VDD
GND
GND
10
9
8
GND
7 6
3
4
5
RES
SDA/SDI/SDO
SDO/SA0
LPS27HHTW
Pin description
DS13489 - Rev 1
Pin number
1
2
3
4
5
6
9
10
7
8
Table 1. Pin description
Name Function
Vdd_IO
SCL
SPC
Reserved
SDA
SDI
SDI/SDO
SDO
SA0
CS
Power supply for I/O pins
I²C / MIPI I3C SM serial clock (SCL)
SPI serial port clock (SPC)
Connect to GND
I²C / MIPI I3C SM serial data (SDA)
4-wire SPI serial data input (SDI)
3-wire serial data input/output (SDI/SDO)
4-wire SPI serial data output (SDO)
I²C least significant bit of the device address (SA0)
MIPI I3C SM least significant bit of the static address (SA0)
SPI enable
I²C and MIPI I3C SM / SPI mode selection
(1: SPI idle mode / I²C and MIPI I3C SM communication enabled;
0: SPI communication mode / I²C and MIPI I3C SM disabled)
INT_DRDY Interrupt or Data-Ready
GND 0 V supply
GND
VDD
0 V supply
Power supply page 3/55
LPS27HHTW
Mechanical and electrical specifications
3
Mechanical and electrical specifications
3.1
Mechanical characteristics
VDD = 1.8 V, T = 25 °C, unless otherwise noted.
Table 2. Pressure and temperature sensor characteristics
Test condition Symbol
Pressure sensor characteristics
Parameter
PT op
P op
P bits
P sens
P
AccRel
Operating temperature range
Operating pressure range
Pressure output data
Pressure sensitivity
Relative accuracy over pressure (2)
P
AccT
P noise
Absolute accuracy over temperature
RMS pressure sensing noise (3)
P= 800 - 1100 hPa, T = 25 °C
P = 860 ~ 1160 hPa, T = 25 ~ 65°C
P = 260 ~ 1260 hPa, T = 0 ~ 65 °C with embedded filter and at T = 25 °C
Min.
-40
260
ODR
Pres
Pressure output data rate
TCO
P_longterm
Temperature coefficient offset
Pressure accuracy, long-term stability
P_drift Soldering drift
Temperature sensor characteristics
Operating temperature range T op
T acc
T sens
Temperature absolute accuracy
Temperature sensitivity
P = 860 ~ 1160 hPa, T = -20 ~ +65 °C
25 ~ 65 °C
-40
24
4096
±0.025
±0.5
±1
0.007
75
100
200
1
10
25
50
0.75
1
±0.5
ODR
T
Temperature output data rate
±1.5
100
1
10
25
50
75
100
200
1. Typical specifications are not guaranteed.
2. By design, the typ. value is defined based characterization data with 10 hPa pressure interval.
3. Pressure noise RMS evaluated in a controlled environment, based on the average standard deviation of 50 measurements with LOW_NOISE_EN = 1, EN_LPFP = 1, LPFP_CFG = 1.
4. Output data rate is configured acting on ODR[2:0] in
Max.
+85
1260
+85
Unit
°C hPa bits
LSB/hPa hPa hPa hPa RMS
Hz
Pa/°C hPa/year hPa
°C
°C
LSB/°C
Hz
DS13489 - Rev 1 page 4/55
3.2
LPS27HHTW
Electrical characteristics
Electrical characteristics
VDD = 1.8 V, T = 25 °C, unless otherwise noted.
Symbol
VDD Supply voltage
Vdd_IO IO supply voltage
Parameter
Table 3. Electrical characteristics
Test condition
Idd Supply current
@ ODR 1 Hz
LOW_NOISE_EN = 0
@ ODR 1 Hz
LOW_NOISE_EN = 1
IddPdn Supply current in power-down mode
1. Typical specifications are not guaranteed.
Min.
1.7
1.7
4
Max.
3.6
Vdd+0.1
Unit
V
V
µA
12
0.9
µA
Table 4. DC characteristics
Symbol Parameter
DC input characteristics
Vil
Vih
Low-level input voltage (Schmitt buffer)
High-level input voltage (Schmitt buffer)
DC output characteristics
Vol Low-level output voltage
Voh High-level output voltage
Condition Min.
0.7 * Vdd
Vdd - 0.2
Typ.
Max.
0.3 * Vdd
0.2
Unit
V
V
V
V
DS13489 - Rev 1 page 5/55
3.3
3.3.1
LPS27HHTW
Communication interface characteristics
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and T
OP
.
Table 5. SPI slave timing values
Symbol
SPI clock frequency
CS setup time
SDI input hold time
SDO valid output time
Parameter
Max.
Unit t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)
SPI clock cycle
CS hold time
SDI input setup time
SDO output hold time
SDO output disable time
Min.
100
6
8
5
15
9
10
50
50 ns
MHz ns
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.
2. Recommended to set max SPI clock 8 MHz to ≤50 Hz ODR.
Figure 4. SPI slave timing diagram
DS13489 - Rev 1
Note: Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports.
page 6/55
3.3.2
LPS27HHTW
Communication interface characteristics
I²C - inter-IC control interface
Subject to general operating conditions for Vdd and T
OP
.
Table 6. I²C slave timing values
Symbol Parameter
Min.
Max
0 100 f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST) t su(SR) t su(SP) t w(SP:SR)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
START condition hold time
Repeated START condition setup time
STOP condition setup time
Bus free time between STOP and START condition
1. Data based on standard I²C protocol requirement, not tested in production.
4.7
4.0
250
0
4
4.7
4
4.7
3.45
Figure 5. I²C slave timing diagram
100
0
0.6
0.6
I²C fast mode
Min.
Max.
0 400
1.3
0.6
0.6
1.3
0.9
Unit kHz
µs ns
µs
µs
REPEATED
START
START
SDA t su(SR) t w(SP:SR)
START t su(SDA) t h(SDA) t su(SP)
STOP
SCL t h(ST) t w(SCLL) t w(SCLH)
Note: Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports.
DS13489 - Rev 1 page 7/55
3.4
LPS27HHTW
Absolute maximum ratings
Absolute maximum ratings
Stress above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Vdd
Vdd_IO
Vin
P
(water)
T
STG
ESD
Table 7. Absolute maximum ratings
Ratings
Supply voltage
I/O pins supply voltage
Input voltage on any control pin
Overpressure
Storage temperature range
Electrostatic discharge protection
Note: Supply voltage on any pin should never exceed 4.8 V.
Maximum value
-0.3 to 4.8
-0.3 to 4.8
-0.3 to Vdd_IO +0.3
1
-40 to +125
2 (HBM)
Unit
V
V
V
MPa
°C kV
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
DS13489 - Rev 1 page 8/55
4
4.1
4.2
4.3
LPS27HHTW
Functionality
Functionality
The LPS27HHTW is a high-resolution, digital output pressure sensor packaged in a CCLGA package with metal lid. The complete device includes a sensing element based on a piezoresistive Wheatstone bridge approach, and an IC interface which communicates a digital signal from the sensing element to the application.
Sensing element
An ST proprietary process is used to obtain a silicon membrane for MEMS pressure sensors. When pressure is applied, the membrane deflection induces an imbalance in the Wheatstone bridge piezoresistances whose output signal is converted by the IC interface.
IC interface
The complete measurement chain is composed of a low-noise amplifier which converts the resistance unbalance of the MEMS sensors (pressure and temperature) into an analog voltage using an analog-to-digital converter.
The pressure and temperature data may be accessed through an I²C/MIPI I3C SM device particularly suitable for direct interfacing with a microcontroller.
/SPI interface thus making the
The LPS27HHTW features a Data-Ready signal which indicates when a new set of measured pressure and temperature data are available, thus simplifying data synchronization in the digital system that uses the device.
Factory calibration
The trimming values are stored inside the device in a non-volatile structure. When the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation which allows the device to be used without requiring any further calibration.
DS13489 - Rev 1 page 9/55
4.4
LPS27HHTW
Device structure
Device structure
The LPS27HHTW has a unique cylindrical package solution with a full metal lid assembled on ceramic substrate and this cylindrical package provides an easy assembly with O-rings in the end user’s application.
Figure 6. LPS27HHTW internal structure
This structure (
) is designed and verified to resist water pressure up to 10 ATM and the potting gel in the
LPS27HHTW has been proven to protect electronic components from long-term exposure to harsh environments such as water mixed with chlorine, bromine, commercial washing detergent and fuels, solvents and chemicals.
It also provides excellent low-stress encapsulation performance for sensitive electronic components from severe environmental conditions such as high temperature and humidity, refer to the properties of the gel which are given in the following table.
Table 8. Potting gel properties
Properties
Permeability g/m²·24 hr
Hardness (penetration) based on ASTM D1403
Ultra-low Young's modulus
TCE (Thermal Coefficient of Expansion)
Potting gel
7
70
Less than 0.01 GPa
300 ppm/°C
DS13489 - Rev 1 page 10/55
4.5
LPS27HHTW
Interpreting pressure readings
Interpreting pressure readings
The pressure data are stored in 3 registers: PRESS_OUT_H (2Ah)
,
PRESS_OUT_L (29h) , and PRESS_OUT_XL
. The value is expressed as a 24-bit signed number (in 2’s complement).
To obtain the pressure in hPa, take the complete 24-bit word and then divide by the sensitivity 4096 LSB/ hPa. This same interpretation is applied to pressure readings when FIFO is enabled and the pressure
data are stored in 3 registers: FIFO_DATA_OUT_PRESS_XL (78h) ,
, and
.
Figure 7. Pressure readings
Pressure Value LSB = PRESS_OUT_H 2Aℎ & PRESS_OUT_L 29ℎ & PRESS_OUT_XL
28ℎ = 3FF58Dℎ = 4191629 LSB signed decimal
4.6
Interpreting temperature readings
The temperature data are stored in 2 registers:
TEMP_OUT_H (2Ch) and TEMP_OUT_L (2Bh)
.
The value is expressed as 2’s complement. To obtain the temperature in °C, take the two’s complement of the complete 16-bit word and then divide by the sensitivity 100 LSB/°C. This same interpretation is applied to temperature readings when FIFO is enabled and the temperature data are stored in 2 registers:
FIFO_DATA_OUT_TEMP_H (7Ch) and FIFO_DATA_OUT_TEMP_L (7Bh) .
Figure 8. Temperature readings
TEMP_OUT_H
0 0 0 0 1 0 0 1
TEMP_OUT_L
1 1 0 0 0 1 0 0
Temperature Value (LSB) = TEMP_OUT_H (2Ch) & TEMP_OUT_L (2Bh)
= 09C4 = 2500 LSB (decimal signed)
Temperature (°C) =
Temperature Value (LSB)
Sensitivity
=
2500 LSB
100 LSB/°C
= 25.00°C
(1)
(2)
DS13489 - Rev 1 page 11/55
5
LPS27HHTW
FIFO
FIFO
•
•
•
•
•
The LPS27HHTW embeds 128 slots of 40-bit data FIFO to store the pressure and temperature output values.
This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work according to six different modes:
•
Bypass mode
FIFO mode
Continuous (Dynamic-Stream) mode
Continuous (Dynamic-Stream)-to-FIFO mode
Bypass-to-Continuous (Dynamic-Stream)
Bypass-to-FIFO mode
and each mode is selected by the TRIG_MODES bit and F_MODE[1:0] bits in
FIFO_CTRL (13h) . Programmable
FIFO threshold status, FIFO overrun events and the number of unread samples stored are available in the
FIFO_STATUS1 (25h) and FIFO_STATUS2 (26h)
registers and can be set to generate dedicated interrupts on the
INT_DRDY pad using the
FIFO_STATUS2 (26h) (FIFO_WTM_IA) goes to '1' when the number of unread samples ( FIFO_STATUS1 (25h)
(FSS[7:0]) is greater than or equal to WTM[6:0] in FIFO_WTM (14h) . If FIFO_WTM (14h)
(WTM[6:0]) is equal to 0,
(FIFO_WTM_IA) stays at '0'.
(FIFO_OVR_IA) is equal to '1' if a FIFO slot is overwritten.
(FSS[7:0]) contains stored data levels of unread samples; when FSS[7:0] is equal to
‘00000000’, FIFO is empty; when FSS[7:0] is equal to ‘10000000’, FIFO is full and the unread samples are 128.
DS13489 - Rev 1 page 12/55
5.1
LPS27HHTW
Bypass mode
Bypass mode
In Bypass mode (
FIFO_CTRL (13h) (TRIG_MODES and F_MODE[1:0] = ‘000’ or ‘100’), the FIFO is not
operational and it remains empty.
Switching to Bypass mode is also used to reset the FIFO. Passing through Bypass mode is mandatory when switching between different FIFO buffer operating modes.
As described in the next figure, for each channel only the first address is used. When new data is available, the older data is overwritten.
Figure 9. Bypass mode
P
i
,T
i
P
0
P
1
P
2
T
0
T
1
T
2
empty
P
127
T
127
DS13489 - Rev 1 page 13/55
5.2
LPS27HHTW
FIFO mode
FIFO mode
In FIFO mode ( FIFO_CTRL (13h)
(TRIG_MODES and F_MODE[1:0] = ‘001’) data from the output
PRESS_OUT_XL (28h) , PRESS_OUT_L (29h)
,
PRESS_OUT_H (2Ah) , TEMP_OUT_L (2Bh) , and
are stored in the FIFO until it is full.
(TRIG_MODE & F_MODE[1:0]). After this reset command it is possible to restart FIFO mode by writing the value
'001' in
(TRIG_MODE & F_MODE[1:0]).
The FIFO buffer memorizes 128 levels of data, but the depth of the FIFO can be resized/reduced by setting
(STOP_ON_WTM) bit. If the STOP_ON_WTM bit is set to '1', FIFO depth is limited to
FIFO_WTM (14h) (WTM[6:0]) data.
Figure 10. FIFO mode
P
i
,T
i
P
0
P
1
P
2
T
0
T
1
T
2
P
127
T
127
DS13489 - Rev 1 page 14/55
5.3
LPS27HHTW
Continuous (Dynamic-Stream) mode
Continuous (Dynamic-Stream) mode
In Continuous (Dynamic-Stream) mode ( FIFO_CTRL (13h) (TRIG_MODES and F_MODE[1:0] = ‘011’) after
emptying the FIFO, the first new sample that arrives becomes the first to be read in a subsequent read burst. In this way, the number of new data available in FIFO does not depend on the previous read.
In Continuous (Dynamic-Stream) mode
FIFO_STATUS1 (25h) (FSS[7:0]) is the number of new pressure and
temperature samples available in the FIFO buffer.
Continuous (Dynamic-Stream) is intended to be used to read
(FSS[7:0]) samples when it is not possible to guarantee reading data within 1/ODR time period.
Also, a FIFO threshold interrupt on the INT_DRDY pad through CTRL_REG3 (12h)
(INT_F_WTM) can be enabled in order to read data from the FIFO and leave free memory slots for incoming data.
Figure 11. Continuous (Dynamic-Stream) mode
DS13489 - Rev 1 page 15/55
5.4
LPS27HHTW
Bypass-to-FIFO mode
Bypass-to-FIFO mode
In Bypass-to-FIFO mode (
FIFO_CTRL (13h) (TRIG_MODES and F_MODE[1:0] = ‘101’), FIFO behavior switches
FIFO behaves like in Bypass mode. Once the INT_SOURCE (24h)
(IA) bit rises to '1', FIFO behavior switches and keeps behaving like in FIFO mode.
An interrupt generator has to be set to the desired configuration through INTERRUPT_CFG (0Bh)
.
Figure 12. Bypass-to-FIFO mode
P i
,T i P i
,T i
P
0
P
1
P
2
T
0
T
1
T
2
P
0
P
1
P
2
T
0
T
1
T
2 empty
P
127
T
127
P
127
T
127
Bypass Mode
Trigger event
FIFO Mode
DS13489 - Rev 1 page 16/55
5.5
LPS27HHTW
Bypass-to-Continuous (Dynamic-Stream) mode
Bypass-to-Continuous (Dynamic-Stream) mode
In Bypass-to-Continuous (Dynamic-Stream) mode (
(TRIG_MODES and F_MODE[1:0] = ‘110’),
FIFO operates in Bypass mode until it switches to Continuous (Dynamic-Stream) mode behavior when
(IA) rises to '1', then FIFO behavior keeps behaving like in Continuous (Dynamic-Stream) mode.
An interrupt generator has to be set to the desired configuration through INTERRUPT_CFG (0Bh)
.
Figure 13. Bypass-to-Continuous (Dynamic-Stream) mode
P i
,T i P i
,T i
P
0
P
1
P
2
T
0
T
1
T
2
P
0
P
1
P
2
T
0
T
1
T
2 empty
P
127
T
127
P
126
P
127
T
126
T
127
Bypass Mode
Trigger event
Dynamic-Stream Mode
DS13489 - Rev 1 page 17/55
5.6
LPS27HHTW
Continuous (Dynamic-Stream)-to-FIFO mode
Continuous (Dynamic-Stream)-to-FIFO mode
In Continuous (Dynamic-Stream)-to-FIFO mode ( FIFO_CTRL (13h) (TRIG_MODES and F_MODE[1:0] = ‘111’),
data are stored in FIFO and FIFO operates in Continuous (Dynamic-Stream) mode behavior until it switches to
FIFO mode behavior when INT_SOURCE (24h) (IA) rises to '1'.
An interrupt generator has to be set to the desired configuration through INTERRUPT_CFG (0Bh)
.
Figure 14. Continuous (Dynamic-Stream)-to-FIFO mode
P i
,T i
P i
,T i
P
0
P
1
P
2
T
0
T
1
T
2
P
126
P
127
T
126
T
127
P
0
P
1
P
2
T
0
T
1
T
2
P
127
T
127
5.7
Dynamic-Stream Mode FIFO Mode
Trigger event
Retrieving data from FIFO
FIFO data is read through FIFO_DATA_OUT_PRESS (78h, 79h and 7Ah) and FIFO_DATA_OUT_TEMP (7Bh,
7Ch).
The read address is automatically updated by the device and it rolls back to 78h when register 7Ch is reached. In order to read all FIFO levels in a multiple byte read, 640 bytes (5 output registers by 128 levels) must be read.
DS13489 - Rev 1 page 18/55
6
Application hints
Figure 15. LPS27HHTW electrical connections (top view)
LPS27HHTW
Application hints
DS13489 - Rev 1
The device power supply must be provided through the VDD line; a power supply decoupling capacitor C1 (100 nF) must be placed as near as possible to the supply pads of the device. The C1 capacitor can be tied to VDD and Vdd_IO, but it is recommended to use 2 capacitors, one on each VDD and Vdd_IO line, in case VDD are
Vdd_IO are separate. Depending on the application, an additional capacitor of 4.7 µF could be placed on the VDD line.
The functionality of the device and the measured data outputs are selectable and accessible through the I²C, MIPI
I3C SM , SPI interface. When using the I²C and MIPI I3C SM , CS must be tied to Vdd_IO.
All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to
this condition the measurement chain is powered off.
Note: To guarantee proper power-off of the device, it is recommended to maintain the duration of the VDD line to
GND for at least 10 ms.
page 19/55
VDD
Figure 16. LPS27HHTW power-off sequence
LPS27HHTW
Soldering information
6.1
0.2V
Min.10ms
Time
VDD Rising / Falling time : 10 µs ~ 100 ms
VDD must be lower than 0.2 V for at least 10 ms during power-off sequence for correct POR
Soldering information
The CCLGA package is compliant with the ECOPACK standard and it is qualified for soldering heat resistance according to JEDEC J-STD-020.
DS13489 - Rev 1 page 20/55
LPS27HHTW
Digital interfaces
7
Digital interfaces
7.1
7.2
Serial interfaces
The registers embedded in the LPS27HHTW may be accessed through either the I²C, MIPI I3C SM or SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I²C interface, the CS line must be tied high (i.e. connected to Vdd_IO).
Pin name
CS
SCL/SPC
SDA
SDI
SDI/SDO
SDO
SA0
Table 9. Serial interface pin description
Pin description
SPI enable
I²C/SPI mode selection
(1: SPI idle mode / I²C communication enabled; 0: SPI communication mode / I²C disabled)
I²C serial clock (SCL)
SPI serial port clock (SPC)
I²C serial data (SDA)
4-wire SPI serial data input (SDI)
3-wire serial data input /output (SDI/SDO)
SPI serial data output (SDO)
I²C less significant bit of the device address (SA0)
I²C serial interface (CS = high)
The LPS27HHTW I²C is a bus slave. The I²C is employed to write data into registers whose content can also be read back.
The relevant I²C terminology is given in the following table.
Table 10. I²C terminology
Term
Transmitter The device which sends data to the bus
Receiver
Master
Slave
The device which receives data from the bus
Description
The device which initiates a transfer, generates clock signals and terminates a transfer
The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines have to be connected to Vdd_IO through pull-up resistors.
The I²C interface is compliant with fast mode (400 kHz) I²C standards as well as with the normal mode.
DS13489 - Rev 1 page 21/55
LPS27HHTW
I²C serial interface (CS = high)
7.2.1
Master
Slave
Master
Slave
I²C operation
The transaction on the bus is started through a START (ST) signal. A start condition is defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After the master has transmitted this, the bus is considered busy. The next data byte transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.
The 7-bit slave address (SAD) associated to the LPS27HHTW is 101110xb. The SDO/SA0 pad can be used to modify the less significant bit of the device address. If the SA0 pad is connected to voltage supply, LSb is ‘1’ (7-bit address 1011101b=5Dh), otherwise if the SA0 pad is connected to ground, the LSb value is ‘0’ (7-bit address
1011100b=5Ch). This solution permits connecting and addressing two different LPS27HHTW devices to the same
I²C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.
The I²C embedded inside the ASIC behaves like a slave device and the following protocol must be adhered to.
After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK), an
8-bit sub-address will be transmitted (SUB): the 7 LSB represent the actual register address while the MSB has no meaning. The IF_ADD_INC bit in
enables sub-address auto increment (IF_ADD_INC is '1' by default), so if IF_ADD_INC = '1' the SUB (sub-address) will be automatically increased to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged.
Table 11 explains how the SAD+read/write bit pattern is composed, listing all the possible
configurations.
Command
Read
Write
Read
Write
SAD[6:1]
101110
101110
101110
101110
Table 11. SAD+Read/Write patterns
SAD[0] = SA0
0
0
1
1
R/W
1
0
1
0
SAD+R/W
10111001 (B9h)
10111000 (B8h)
10111011 (BBh)
10111010 (BAh)
Master
Slave
ST
ST
Table 12. Transfer when master is writing one byte to slave
SAD + W SUB DATA
SAK SAK
Table 13. Transfer when master is writing multiple bytes to slave
SAD + W SUB DATA
SAK SAK SAK
DATA
SAK
SAK
SP
SP
ST
Table 14. Transfer when master is receiving (reading) one byte of data from slave
SAD + W SUB SR SAD + R
SAK SAK SAK DATA
NMAK SP
DS13489 - Rev 1 page 22/55
LPS27HHTW
SPI bus interface (CS = low)
Master
Slave
Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
ST SAD+W SUB SR SAD+R MAK MAK
SAK SAK SAK DATA DATA DATA
NMAK SP
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function), the data line must be kept HIGH by the slave. The master can then abort the transfer. A LOW-to-HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is no master acknowledge.
7.3
SPI bus interface (CS = low)
The LPS27HHTW SPI is a bus slave. The SPI allows writing to and reading from the registers of the device.
The serial interface interacts with the application using 4 wires: CS , SPC , SDI and SDO .
Figure 17. Read and write protocol
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and returns to high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .
Both the read register and write register commands are completed in 16 clock pulses or multiples of 8 in the case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23,...) starts at the last falling edge of SPC just before the rising edge of CS.
bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip will drive SDO at the start of bit 8.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data
DO(7:0) (read mode). This is the data that is read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods are added. When the IF_ADD_INC bit is 0, the address used to read/write data remains the same for every block. When the IF_ADD_INC bit is 1, the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
DS13489 - Rev 1 page 23/55
7.3.1
SPI read
Figure 18. SPI read protocol
LPS27HHTW
SPI bus interface (CS = low)
The SPI read command is performed with 16 clock pulses. The multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit 16-...
: data DO(...-8). Further data in multiple byte reads.
Figure 19. Multiple byte SPI read protocol (2-byte example)
DS13489 - Rev 1 page 24/55
7.3.2
LPS27HHTW
SPI bus interface (CS = low)
SPI write
Figure 20. SPI write protocol
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
The SPI write command is performed with 16 clock pulses. The multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : WRITE bit. The value is 0.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written in the device (MSb first).
bit 16-...
: data DI(...-8). Further data in multiple byte writes.
Figure 21. Multiple byte SPI write protocol (2-byte example)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
DS13489 - Rev 1 page 25/55
7.3.3
LPS27HHTW
SPI bus interface (CS = low)
SPI read in 3-wire mode
Figure 22. SPI read protocol in 3-wire mode
CS
SPC
SDI/O
RW
AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode.
DS13489 - Rev 1 page 26/55
LPS27HHTW
MIPI I3CSM slave interface
7.4
7.4.1
MIPI I3C SM slave interface
•
•
•
•
•
•
•
The LPS27HHTW interface includes a MIPI I3C SM SDR only slave interface with MIPI I3C SM SDR embedded features:
CCC command
Direct CCC communication (SET and GET)
Broadcast CCC communication
Private communications
Private read and write for single byte
Multiple read and write
In-band interrupt and hot-join requests
MIPI I3C
SM
CCC supported commands
The list of MIPI I3C SM CCC commands supported by the device is detailed in the following table.
Command
ENEC
RSTDAA
DISEC
ENTAS0
ENTAS1
ENTAS2
ENTAS3
SETMWL
SETMRL
SETDASA
SETNEWDA
GETMWL
GETMRL
GETPID
GETBCR
GETDCR
GETSTATUS
Table 16. MIPI I3C
SM
CCC commands
Command code Default Description
0x80 / 0x00 Slave activity control (direct and broadcast)
0x86 / 0x06
0x81/ 0x01
Reset the assigned dynamic address (direct and broadcast)
Slave activity control (direct and broadcast)
0x82 / 0x02
0x83 / 0x03
0x84 / 0x04
0x85 / 0x05
Enter activity state (direct and broadcast)
Enter activity state (direct and broadcast)
Enter activity state (direct and broadcast)
Enter activity state (direct and broadcast)
0x89 / 0x08
0x8A / 0x09
0x00
0x08
0x00
0x10
0x04
Define maximum write length during private write (direct and broadcast)
Define maximum read length during private read (direct and broadcast)
0x87
0x88
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
Assign dynamic address using static address (0x5C/0x5D depending on the SDO level)
Change dynamic address
0x00
0x08
0x00
0x10
0x04
Get maximum write length during private write
Get maximum read length during private read
0x02
0x08
0x00
0xB3
0x00
0x00
Device ID register
0x07 Bus characteristics register
0x62 DCR
Status register
DS13489 - Rev 1 page 27/55
Command
GETMXDS
GETXTIME
Command code Default Description
0x94
0x99
0x00
0x20
0x07
0x04
0x0A
0x64
Return max data speed
Get exchange time information
LPS27HHTW
MIPI I3CSM slave interface
DS13489 - Rev 1 page 28/55
7.5
LPS27HHTW
I²C/MIPI I3CSM coexistence in LPS27HHTW
I²C/MIPI I3C SM coexistence in LPS27HHTW
In the LPS27HHTW, the SDA and SCL lines are common to both I²C and MIPI I3C SM . The I²C bus requires anti-spike filters on the SDA and SCL pins that are not compatible with MIPI I3C SM timing.
The device can be connected to both I²C and MIPI I3C
SM
or only to the MIPI I3C
SM
bus depending on the connection of the INT1 pin when the device is powered up:
• INT_DRDY pin floating (internal pull-down): I²C/MIPI I3C SM both active, see
– I²C case: INT_DRDY pin is by default an input with pull-down. If I²C is used, INT_DRDY must be left unconnected or eventually pulled down during device initialization. After power-on, during device configuration, the INT_DRDY pin can be programmed as an interrupt output pin and it is recommended to set bit I3C_disable to '1'.
– I3C case: INT_DRDY pin is by default an input with pull-down. If I3C is used and the INT_DRDY pin is unconnected, dynamic address assignment must be performed using I²C Fast Mode Plus Timing (max
1 MHz clock). After dynamic address assignment, I3C can be used in full speed mode.
• INT_DRDY pin connected to Vdd_IO: only MIPI I3C SM
– Only I3C: INT_DRDY pin is by default an input with pull-down. If INT_DRDY is set to Vdd_IO, I3C slave is selected and device can be initialized at full speed through the SETDASA command. If the I3C bus is available for more than 10 msec and the device is not yet addressed, a hot join request is performed
(SDA line kept to ground from slave) and the master must manage the request. After device address assignment, a private write can be performed to disconnect the INT_DRDY pull-down.
Figure 23. I²C and MIPI I3C SM both active (INT_DRDY pin not connected)
INT1 pin not connected
I²C/I3C both active
I²C/I3C
(both active)
I²C bus case I3C bus case
Master sends
I²C r/w
Master assigns DA to the slave
(1)
Master resets
DA
Slave performs requested r/w
I3C private R/W with and without 7Eh
CCC commands
Slave event management
Error detection and recovery
1.
Address assignment (SETDASA) must be performed with I²C Fast Mode Plus Timing. When the slave is addressed, the I²C slave is disabled and the timing is compatible with MIPI I3C SM specifications.
DS13489 - Rev 1 page 29/55
LPS27HHTW
I²C/MIPI I3CSM coexistence in LPS27HHTW
Figure 24. Only MIPI I3C SM active (INT_DRDY pin connected to Vdd_IO)
INT1 pin connected to Vdd_IO
Only I3C active
I²C/I3C I3C bus case
Dynamic
Address
Assignment
(1)
Master resets
DA
I3C private R/W with and without 7Eh
CCC commands
Slave event management
Error detection and recovery
1.
When the slave is MIPI I3C SM only, the I²C slave is always disabled. The address can be assigned using
MIPI I3C SM SDR timing.
DS13489 - Rev 1 page 30/55
8
LPS27HHTW
Register mapping
Register mapping
Name
Reserved
INTERRUPT_CFG
THS_P_L
THS_P_H
IF_CTRL
WHO_AM_I
CTRL_REG1
CTRL_REG2
CTRL_REG3
FIFO_CTRL
FIFO_WTM
REF_P_L
REF_P_H
Reserved
RPDS_L
RPDS_H
Reserved
INT_SOURCE
FIFO_STATUS1
FIFO_STATUS2
STATUS
PRESS_OUT_XL
PRESS_OUT_L
PRESS_OUT_H
TEMP_OUT_L
TEMP_OUT_H
Reserved
LPFP_RES
Reserved
FIFO_DATA_OUT_PRESS_XL
FIFO_DATA_OUT_PRESS_L
FIFO_DATA_OUT_PRESS_H
FIFO_DATA_OUT_TEMP_L
FIFO_DATA_OUT_TEMP_H
The following table provides a quick overview of the 8-bit registers embedded in the device.
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
Table 17. Registers address map
Type
R/W
R/W
R
2D - 3B
3C
3D - 77
78
79
7A
7B
7C
2A
2B
2C
27
28
29
19
1A - 23
24
25
26
Register
Address
Hex
00 - 0A
16
17
18
13
14
15
0E
0F
10
0B
0C
0D
11
12
Default
00000000
00000000
00000000
00000000
-
00000000
00000000
-
Output
Output
Output
Binary
-
00000000
00000000
00000000
00000000
10110011
00000000
00010000
00000000
Output
Output
Output
Output
Output
Output
-
Output
-
Output
Output
Output
Output
Output
Function and comment
Reserved
Interrupt register
Pressure threshold registers
Interface control register
Who am I
Control registers
FIFO configuration register
Reference pressure registers
Pressure offset registers
Reserved
Interrupt register
FIFO status registers
Status register
Pressure output registers
Temperature output registers
Reserved
Low-pass filter reset register
Reserved
FIFO pressure output registers
FIFO temperature output registers
DS13489 - Rev 1 page 31/55
LPS27HHTW
Register mapping
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
To guarantee the proper behavior of the device, all register addresses not listed in the above table must not be accessed and the content stored in those registers must not be changed.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
DS13489 - Rev 1 page 32/55
LPS27HHTW
Register description
9
Register description
The device contains a set of registers which are used to control its behavior and to retrieve pressure and temperature data. The register address, made up of 7 bits, is used to identify them and to read/write the data through the serial interface.
9.1
7
AUTOREFP
INTERRUPT_CFG (0Bh)
Interrupt mode for pressure acquisition configuration (R/W)
6 5 4 3
RESET_ARP AUTOZERO RESET_AZ DIFF_EN
2
LIR
1
PLE
0
PHE
AUTOREFP
RESET_ARP
AUTOZERO
RESET_AZ
DIFF_EN
LIR
PLE
PHE
Enable AUTOREFP function. Default value: 0
(0: normal mode; 1: AUTOREFP enabled)
Reset AUTOREFP function. Default value: 0
(0: normal mode; 1: reset AUTOREFP function)
Enable AUTOZERO function. Default value: 0
(0: normal mode; 1: AUTOZERO enabled)
Reset AUTOZERO function. Default value: 0
(0: normal mode; 1: reset AUTOZERO function)
Enable interrupt generation. Default value: 0
(0: interrupt generation disabled; 1: interrupt generation enabled)
Latch interrupt request to the
INT_SOURCE (24h) register. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
Enable interrupt generation on pressure low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on pressure value lower than preset threshold)
Enable interrupt generation on pressure high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on pressure value higher than preset threshold)
It is enabled when the DIFF_EN bit in the INTERRUPT_CFG (0Bh) register is set to '1' and either PHE bit or PLE bit (or both bits) = '1'. Then, the differential pressure can be compared to a user-defined threshold stored in the
15-bit THS_P (0Ch and 0Dh) registers.
The threshold pressure value defined by the user is a 15-bit unsigned value in the 16-bit register composed of
THS_P_L (0Ch) and THS_P_H (0Dh)
. The value is:
THS_P (15-bit unsigned) = Desired Interrupt threshold (hPa) x 16
The PHE and PLE bits in INTERRUPT_CFG (0Bh) enable the differential pressure interrupt generation on the positive or negative event respectively.
The differential interrupt must be used with AUTOREFP or AUTOZERO mode.
DS13489 - Rev 1 page 33/55
DS13489 - Rev 1
LPS27HHTW
INTERRUPT_CFG (0Bh)
P_DIFF_IN
Figure 25. “Threshold-based” interrupt event
Threshold positive value
Threshold negative value
Positive
Negative
•
•
To enable the AUTOZERO mode, the AUTOZERO bit must be set to '1' and then the measured pressure value
is used as the reference and stored in the register REF_P ( REF_P_L (15h)
,
REF_P_H (16h) ). From this point
on, the output pressure value (
PRESS_OUT_XL (28h) , PRESS_OUT_L (29h) ,
PRESS_OUT_H (2Ah) ) is updated
with the difference between the measured pressure and REF_P.
P_DIFF_IN = measured pressure - REF_P
PRESS_OUT = measured pressure - REF_P
After the first conversion, the AUTOZERO bit is automatically set back to '0'. In order to return back to normal mode, the RESET_AZ bit in the INTERRUPT_CFG (0Bh) register has to be set to '1'. This also resets the content of the REF_P registers to 0.
AUTOREFP mode allows using the pressure differential for the generation of the interrupt keeping the output pressure registers PRESS_OUT (
PRESS_OUT_XL (28h) , PRESS_OUT_L (29h)
,
comparing REF_P. If the AUTOREFP bit is set to '1', the measured output pressure is used as the reference in the
register REF_P ( REF_P_L (15h)
,
REF_P_H (16h) ) for interrupt generation with following:
• P_DIFF_IN = measured pressure - REF_P
The output registers PRESS_OUT (28h, 29h and 2Ah) are not changed by REF_P and shows as follows.
• PRESS_OUT = measured pressure
After the first conversion, the AUTOREFP bit is automatically set to '0'. In order to return back to normal mode, the
RESET_ARP bit has to be set to '1' page 34/55
LPS27HHTW
THS_P_L (0Ch)
9.2
7
THS7
THS_P_L (0Ch)
User-defined threshold value for pressure interrupt event (least significant bits) (R/W)
6 5 4 3 2
THS6 THS5 THS4 THS3 THS2
1
THS1
0
THS0
THS[7:0] This register contains the low part of threshold value for pressure interrupt generation. Default value: 00h
The threshold value for pressure interrupt generation is a 15-bit unsigned right-justified value composed of
and THS_P_L (0Ch).The value is expressed as:
THS_P (15-bit unsigned) = Desired interrupt threshold (hPa) x 16
has to be enabled.
9.3
7
-
THS_P_H (0Dh)
User-defined threshold value for pressure interrupt event (most significant bits) (R/W)
6 5 4 3 2
THS14 THS13 THS12 THS11 THS10
1
THS9
0
THS8
THS[14:8]
This register contains the high part of threshold value for pressure interrupt generation. Default value: 00h
9.4
7
INT_EN_I3C
IF_CTRL (0Eh)
Interface control register (R/W)
6 5
0 0
4
SDA_PU_EN
3 2 1 0
SDO_PU_EN PD_DIS_INT1 I3C_DISABLE I2C_DISABLE
INT_EN_I3C
SDA_PU_EN
SDO_PU_EN
PD_DIS_INT1
I3C_DISABLE
I2C_DISABLE
Enable INT1 pad with MIPI I3C SM . If the INT_EN_I3C bit is set, the INT1 pad is polarized as OUT. Default value: 0
(0: INT1 disabled with MIPI I3C SM ; 1: INT1 enabled with MIPI I3C SM )
Enable pull-up on the SDA pin. Default value: 0
(0: SDA pin pull-up disconnected; 1: SDA pin with pull-up)
Enable pull-up on the SDO pin. Default value: 0
(0: SDO pin pull-up disconnected; 1: SDO pin with pull-up)
Disable pull down on the INT1 pin. Default value: 0
(0: INT1 pin with pull-down; 1: INT1 pin pull-down disconnected)
Disable MIPI I3C SM interface. Default value: 0
(0: MIPI I3C SM enabled; 1: MIPI I3C SM disabled)
Disable I²C interface. Default value: 0
(0: I²C enabled; 1: I²C disabled)
1. I3C_DISABLE bit disables the MIPI I3C SM communication protocol.
2. I2C_DISABLE bit disables the I²C interface, by default both SPI and I²C interfaces are enabled.
DS13489 - Rev 1 page 35/55
LPS27HHTW
WHO_AM_I (0Fh)
9.5
7
1
WHO_AM_I (0Fh)
Device Who am I
6 5
0 1
9.6
7
0
CTRL_REG1 (10h)
Control register 1 (R/W)
6 5
ODR2 ODR1
4
1
3
0
2
0
1
1
0
1
4
ODR0
3
EN_LPFP
2
LPFP_CFG
1
BDU
0
SIM
ODR[2:0]
EN_LPFP
LPFP_CFG
BDU
SIM
Output data rate selection. Default value: 000
.
Enable low-pass filter on pressure data when Continuous mode is used. Default value: 0
(0: Low-pass filter disabled; 1: Low-pass filter enabled)
LPFP_CFG: Low-pass configuration register. Default value: 0
.
Block data update. Default value: 0
(0: continuous update;
1: output registers not updated until MSB and LSB have been read)
SPI Serial Interface Mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
Table 18. Output data rate bit configurations
ODR[2:0]
100
101
111
000
001
010
011
1. This option disables the low-noise mode automatically.
Temperature, Pressure (Hz)
One-shot
1 Hz
10 Hz
25 Hz
50 Hz
75 Hz
100 Hz
200 Hz
When the ODR bits are set to '000', the device is in Power-down mode . When the device is in power-down mode, almost all internal blocks of the device are switched off to minimize power consumption. The I²C interface is still active to allow communication with the device. The content of the configuration registers is preserved and output data registers are not updated, therefore keeping the last data sampled in memory before going into power-down mode.
If the ONE_SHOT bit in
CTRL_REG2 (11h) is set to '1',
One-shot mode is triggered and a new acquisition starts when it is required. Enabling this mode is possible only if the device was previously in power-down mode (ODR bits set to '000'). Once the acquisition is completed and the output registers updated, the device automatically enters in power-down mode. ONE_SHOT bit self-clears itself.
DS13489 - Rev 1 page 36/55
LPS27HHTW
CTRL_REG2 (11h)
When the ODR bits are set to a value different than '000', the device is in Continuous mode and automatically acquires a set of data (pressure and temperature) at the frequency selected through the ODR[2:0] bits.
Once the additional low-pass filter has been enabled through the EN_LPFP bit, it is possible to configure the device bandwidth acting on the LPFP_CFG bit. See
for low-pass filter configurations.
EN_LPFP
0
1
1
LPFP_CFG x
0
1
Table 19. Low-pass filter configurations
Additional low-pass filter status
Disabled
Enabled
Enabled
Device bandwidth
ODR/2
ODR/9
ODR/20
The BDU bit is used to inhibit the update of the output registers until both upper and lower (and XLOW) register parts are read. In default mode (BDU = ‘0’) the output register values are updated continuously. If for any reason it is not sure to read faster than the output data rate, it is recommended to set the BDU bit to ‘1’. In this way, the content of the output registers is not updated until MSB, LSB and XLSB have been read which avoids reading values related to different sample times.
9.7
7
BOOT
CTRL_REG2 (11h)
Control register 2 (R/W)
6
INT_H_L
5
PP_OD
4
IF_ADD_INC
3
0
2
SWRESET
1
LOW_NOISE_EN
0
ONE_SHOT
BOOT
INT_H_L
PP_OD
IF_ADD_INC
SWRESET
LOW_NOISE_EN
ONE_SHOT
Reboots memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
Interrupt active-high, active-low. Default value: 0
(0: active high; 1: active low)
Push-pull/open-drain selection on interrupt pad. Default value: 0
(0: push-pull; 1: open-drain)
Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI).
Default value: 1
(0: disable; 1: enable)
Software reset. Default value: 0
(0: normal mode; 1: software reset).
The bit is self-cleared when the reset is completed.
Enables low noise (used only if ODR is lower than 100 Hz). Default value: 0
(0: low-current mode; 1: low-noise mode)
Enables one-shot. Default value: 0
(0: idle mode; 1: a new dataset is acquired)
The BOOT bit is used to refresh the content of the internal registers stored in the Flash memory block. At device power-up, the content of the Flash memory block is transferred to the internal registers related to the trimming functions to allow correct behavior of the device itself. If for any reason the content of the trimming registers is modified, it is sufficient to use this bit to restore the correct values. When the BOOT bit is set to '1', the content of the internal Flash is copied into the corresponding internal registers and is used to calibrate the device. These values are factory trimmed and they are different for every device. They allow the correct behavior of the device and normally they should not be changed. At the end of the boot process, the BOOT bit is set again to '0' by hardware. The BOOT bit takes effect immediately after it is set to 1.
DS13489 - Rev 1 page 37/55
DS13489 - Rev 1
LPS27HHTW
CTRL_REG2 (11h)
INT_H_L selects an interrupt active-high/low value.
PP_OD selects push-pull/open-drain on the interrupt pad.
The IF_ADD_INC bit enables the address to be automatically incremented during a multiple byte access with a serial interface (SPI or I²C).
The SWRESET bit resets the volatile registers to default value ‘0’. It returns to ‘0’ by hardware.
LOW_NOISE_EN is disabled by default and must be changed when the device is in power-down mode. It enables low-noise mode but can be used when the ODR is lower than 100 Hz. If ODR = 100 Hz or ODR = 200 Hz, this option is automatically switched off and the value of the low-noise enable bit is ignored.
LOW_NOISE_EN mode is enabled to have less RMS noise and the best performance is achieved with
LOW_NOISE_EN set to 1 and filter at ODR/20. Depending on the application, the LOW_NOISE_EN bit can be enabled (low-noise mode) or disabled (low-current mode) to have less RMS noise or less power consumption
(refer to the following table).
Mode
Low noise
Low current
Table 20. RMS noise and power consumption
Additional low-pass filter status
Disabled
Enabled
Enabled
Disabled
Enabled
Enabled
Device bandwidth
ODR/9
ODR/20
ODR/9
ODR/20
RMS noise [Pa]
5.6
3.2
2.1
1.8
1
0.7
Supply current
@ ODR = 1 Hz [µA]
4
4
4
12
12
12
The ONE_SHOT bit is used to start a new conversion when the ODR[2:0] bits in
to '000'. Writing a '1' in ONE_SHOT triggers a single measurement of pressure and temperature. Once the measurement is done, the ONE_SHOT bit will self-clear, the new data are available in the output registers, and
the STATUS (27h) bits are updated.
page 38/55
LPS27HHTW
CTRL_REG3 (12h)
9.8
7
0
CTRL_REG3 (12h)
Control register 3 - INT_DRDY pin control register (R/W)
6 5 4 3
0 INT_F_FULL INT_F_WTM INT_F_OVR
2
DRDY
1
INT_S1
0
INT_S0
INT_F_FULL
INT_F_WTM
INT_F_OVR
DRDY
INT_S[1:0]
FIFO full flag on INT_DRDY pin. Default value: 0
(0: FIFO empty; 1: FIFO full - 128 unread samples)
FIFO threshold (watermark) status on INT_DRDY pin. Default value: 0
(0: FIFO is lower than FTH level; 1: FIFO is equal to or higher than FTH level)
FIFO overrun status on INT_DRDY pin. Default value: 0
(0: not overwritten; 1: at least one sample in the FIFO has been overwritten)
Data-ready signal on INT_DRDY pin. Default value: 0
(0: disable; 1: enable)
Data signal on INT_DRDY pin control bits. Default value: 00
Table 21. Interrupt configurations
INT_S1 INT_S0
0 0
0
1
1
1
0
1
INT_DRDY pin configuration
Data signal (in order of priority: DRDY or INT_F_WTM or INT_F_OVR or INT_F_FULL)
Pressure high (P_high)
Pressure low (P_low)
Pressure low OR high
Figure 26. Interrupt events on INT_DRDY pin
New data set is available
FIFO Threshold (Watermark)
FIFO Overrun
FIFO Full
CTRL_REG3 (@12h)
DRDY
INT_F_WTM
INT_F_OVR
INT_F_FULL
INT_S[1:0]
Pressure higher than threshold
Pressure lower than threshold
10
11
00
01 INT_DRDY pin
DS13489 - Rev 1 page 39/55
LPS27HHTW
FIFO_CTRL (13h)
9.9
7
0
FIFO_CTRL (13h)
FIFO control register (R/W)
6
0
5
0
4
0
3
STOP_ON_WTM
2
TRIG_MODES
1
F_MODE1
STOP_ON_WTM
TRIG_MODES
F_MODE[1:0]
Stop-on-FIFO watermark. Enables FIFO watermark level use. Default value: 0
(0: disable; 1: enable)
Enables triggered FIFO modes. Default value: 0
Selects triggered FIFO modes. Default value: 00
.
9.10
7
0
TRIG_MODES
1
1
1 x
0
0
Table 22. FIFO mode selection
F_MODE[1:0]
01
10
11
00
01
1x
Mode
Bypass
FIFO mode
Continuous (Dynamic-Stream)
Bypass-to-FIFO
Bypass-to-Continuous (Dynamic-Stream)
Continuous (Dynamic-Stream)-to-FIFO
The STOP_ON_WTM bit enables the use of the FIFO watermark level: when the number of samples in FIFO is
equal to the watermark level (set using the WTM[4:0] bits in FIFO_WTM (14h)
) then FIFO is full.
The TRIG_MODES bit enables the triggered FIFO modes.
The F_MODE[1:0] bits select one of the FIFO modes as described in
.
Output data (pressure and temperature) are read through
FIFO_DATA_OUT_PRESS_XL (78h) ,
FIFO_DATA_OUT_PRESS_L (79h) , FIFO_DATA_OUT_PRESS_H (7Ah) , FIFO_DATA_OUT_TEMP_L (7Bh)
and
FIFO_DATA_OUT_TEMP_H (7Ch) ; both single read and multiple read operations can be used.
FIFO_WTM (14h)
FIFO threshold setting register (R/W)
6 5
WTM6 WTM5
4
WTM4
3
WTM3
2
WTM2
1
WTM1
0
WTM0
WTM[6:0] FIFO threshold. Watermark level setting. Default value: 0000000
0
F_MODE0
DS13489 - Rev 1 page 40/55
LPS27HHTW
REF_P_L (15h)
9.11
7
REFL7
REF_P_L (15h)
Reference pressure LSB data (R)
6 5
REFL6 REFL5
4
REFL4
3
REFL3
2
REFL2
1
REFL1
0
REFL0
REFL[7:0] This register contains the low part of the reference pressure value. Default value: 00000000
The Reference pressure value is 16-bit data and it is composed of
REF_P_H (16h) and REF_P_L (15h). The
value is expressed as 2’s complement.
The reference pressure value is stored and used when the AUTOZERO or AUTOREFP function is enabled.
Please refer to the
INTERRUPT_CFG (0Bh) register description.
9.12
7
REFL15
REF_P_H (16h)
Reference pressure MSB data (R)
6 5
REFL14 REFL13
4
REFL12
3
REFL11
2
REFL10
1
REFL9
0
REFL8
REFL[15:8] This register contains the high part of the reference pressure value. Default value: 00000000
9.13
7
RPDS7
RPDS_L (18h)
Pressure offset (LSB data)
6 5
RPDS6 RPDS5
4
RPDS4
3
RPDS3
2
RPDS2
1
RPDS1
0
RPDS0
RPDS[7:0] This register contains the low part of the pressure offset value. Default value: 00000000
The pressure offset value is 16-bit data that can be used to implement one-point calibration (OPC) after soldering.
This value is composed of
RPDS_H (19h) and RPDS_L (18h). The value is expressed as 2’s complement.
9.14
7
RPDS15
RPDS_H (19h)
Pressure offset (MSB data)
6 5
RPDS14 RPDS13
4
RPDS12
3
RPDS11
2
RPDS10
1
RPDS9
0
RPDS8
RPDS[15:8]
This register contains the high part of the pressure offset value. Default value: 00000000
Refer to
DS13489 - Rev 1 page 41/55
9.15
7
BOOT_ON
INT_SOURCE (24h)
Interrupt source (read only)
6 5
0 0
4
0
3
0
BOOT_ON
IA
PL
PH
Indication of Boot phase.
(0: Boot phase has ended;
1: Boot phase is running).
Interrupt active.
(0: no interrupt has been generated;
1: one or more interrupt events have been generated).
Differential pressure Low.
(0: no interrupt has been generated;
1: low differential pressure event has occurred).
Differential pressure High.
(0: no interrupt has been generated;
1: high differential pressure event has occurred).
9.16
7
FSS7
FIFO_STATUS1 (25h)
FIFO status register (read only)
6 5
FSS6 FSS5
4
FSS4
3
FSS3
2
IA
2
FSS2
FSS[7:0]
FIFO stored data level, number of unread samples stored in FIFO.
(00000000: FIFO empty; 10000000: FIFO full, 128 unread samples)
9.17
7
FIFO_STATUS2 (26h)
FIFO status register (read only)
6 5
FIFO_WTM_IA FIFO_OVR_IA FIFO_FULL_IA
4
-
3
-
FIFO_WTM_IA
FIFO_OVR_IA
FIFO_FULL_IA
2
-
FIFO threshold (watermark) status. Default value: 0
(0: FIFO filling is lower than treshold level;
1: FIFO filling is equal or higher than treshold level).
FIFO overrun status. Default value: 0
(0: FIFO is not completely full;
1: FIFO is full and at least one sample in the FIFO has been overwritten).
FIFO full status. Default value: 0
(0: FIFO is not completely filled;
1: FIFO is completely filled, no samples overwritten)
1
-
1
PL
1
FSS1
LPS27HHTW
INT_SOURCE (24h)
0
PH
0
FSS0
0
-
DS13489 - Rev 1 page 42/55
LPS27HHTW
STATUS (27h)
9.18
7
-
STATUS (27h)
Status register (read only)
6 5
T_OR
4
P_OR
3
-
2
-
1
T_DA
0
P_DA
T_OR
P_OR
T_DA
P_DA
Temperature data overrun.
(0: no overrun has occurred;
1: a new data for temperature has overwritten the previous data)
Pressure data overrun.
(0: no overrun has occurred;
1: new data for pressure has overwritten the previous data)
Temperature data available.
(0: new data for temperature is not yet available;
1: a new temperature data is generated)
Pressure data available.
(0: new data for pressure is not yet available;
1: a new pressure data is generated)
This register is updated every ODR cycle.
9.19
7
POUT7
PRESS_OUT_XL (28h)
Pressure output value LSB data (read only)
6 5 4
POUT6 POUT5 POUT4
3
POUT3
2
POUT2
1
POUT1
0
POUT0
POUT[7:0] This register contains the low part of the pressure output value.
The pressure output value is a 24-bit data that contains the measured pressure. It is composed of
and PRESS_OUT_XL (28h). The value is expressed as 2’s complement.
The output pressure register PRESS_OUT is provided as the difference between the measured pressure and the content of the register RPDS (18h, 19h)*.
Please refer to Section 4.5 Interpreting pressure readings
for additional info.
*DIFF_EN = '0', AUTOZERO = '0', AUTOREFP = '0'
9.20
7
POUT15
PRESS_OUT_L (29h)
Pressure output value middle data (read only)
6 5 4
POUT14 POUT13 POUT12
3
POUT11
2
POUT10
1
POUT9
0
POUT8
POUT[15:8]
This register contains the mid part of the pressure output value. Refer to PRESS_OUT_XL (28h) .
DS13489 - Rev 1 page 43/55
9.21
7
POUT23
PRESS_OUT_H (2Ah)
Pressure output value MSB data (read only)
6 5 4
POUT22 POUT21 POUT20
3
POUT19
2
POUT18
1
POUT7
0
POUT16
POUT[23:16] This register contains the high part of the pressure output value. Refer to
9.22
7
TOUT7
TEMP_OUT_L (2Bh)
Temperature output value LSB data (read only)
6 5 4
TOUT6 TOUT5 TOUT4
3
TOUT3
2
TOUT2
1
TOUT1
0
TOUT0
TOUT[7:0] This register contains the low part of the temperature output value.
The temperature output value is 16-bit data that contains the measured temperature. It is composed of
and TEMP_OUT_L (2Bh). The value is expressed as 2’s complement.
9.23
7
TOUT15
TEMP_OUT_H (2Ch)
Temperature output value MSB data (read only)
6 5 4
TOUT14 TOUT13 TOUT12
3
TOUT11
2
TOUT10
1
TOUT9
0
TOUT8
TOUT[15:8] This register contains the high part of the temperature output value.
9.24
LPFP_RES (3Ch)
Low-pass filter reset (read only)
If the LPFP is active, in order to avoid the transitory phase, the filter can be reset by reading this register before generating pressure measurements.
9.25
7
FIFO_P7
FIFO_DATA_OUT_PRESS_XL (78h)
FIFO pressure output LSB data (read only)
6
FIFO_P6
5
FIFO_P5
4
FIFO_P4
3
FIFO_P3
2
FIFO_P2
1
FIFO_P1
0
FIFO_P1
FIFO_P[7:0] Pressure LSB data in FIFO buffer
LPS27HHTW
PRESS_OUT_H (2Ah)
DS13489 - Rev 1 page 44/55
9.26
7
FIFO_P15
FIFO_DATA_OUT_PRESS_L (79h)
FIFO pressure output middle data (read only)
6 5 4
FIFO_P14 FIFO_P13 FIFO_P12
3
FIFO_P11
2
FIFO_P10
1
FIFO_P9
0
FIFO_P8
FIFO_P[15:8] Pressure middle data in FIFO buffer
9.27
7
FIFO_P23
FIFO_DATA_OUT_PRESS_H (7Ah)
FIFO pressure output MSB data (read only)
6 5 4
FIFO_P22 FIFO_P21 FIFO_P20
3
FIFO_P19
2
FIFO_P18
1
FIFO_P17
0
FIFO_P16
FIFO_P[23:16] Pressure MSB data in FIFO buffer
9.28
7
FIFO_T7
FIFO_DATA_OUT_TEMP_L (7Bh)
FIFO temperature output LSB data (read only)
6 5 4
FIFO_T6 FIFO_T5 FIFO_T4
3
FIFO_T3
2
FIFO_T2
FIFO_T[7:0] Temperature LSB data in FIFO buffer
9.29
7
FIFO_T15
FIFO_DATA_OUT_TEMP_H (7Ch)
Temperature LSB data in FIFO buffer
6
FIFO_T14
5
FIFO_T13
4
FIFO_T12
3
FIFO_T11
2
FIFO_T10
1
FIFO_T1
1
FIFO_T9
0
FIFO_T0
0
FIFO_T8
FIFO_T[15:8] Temperature MSB data in FIFO buffer
LPS27HHTW
FIFO_DATA_OUT_PRESS_L (79h)
DS13489 - Rev 1 page 45/55
10
10.1
LPS27HHTW
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
CCLGA-10L package information
Figure 27. CCLGA - 10L (2.7 x 2.7 x 1.7 typ. mm) package outline and mechanical data
L e
ITEM n g t h [
W i d t h
L ]
[ W ]
H e i g h t [ H ]
Dimensions are in millimeter unless otherwise specified
General Tolerance is +/-0.10mm unless otherwise specified
OUTER DIMENSIONS
DIMENSION [mm]
2 .
7
2 .
7
1 .
8 5 M A X
TOLERANCE [mm]
± 0 .
1 5
± 0 .
1
/
5
DM00492423_1
DS13489 - Rev 1 page 46/55
10.2
LPS27HHTW
CCLGA-10L packing information
CCLGA-10L packing information
Figure 28. Carrier tape information for CCLGA-10L package
Figure 29. Package orientation in carrier tape
DS13489 - Rev 1 page 47/55
DS13489 - Rev 1
LPS27HHTW
CCLGA-10L packing information
A
Figure 30. Reel information for carrier tape of CCLGA-10L package
T
40mm min.
Access hole at slot location
B
C
D N
Full radius
G measured at hub
Tape slot in core for tape start
2.5mm min. width
Table 23. Reel dimensions for carrier tape of CCLGA-10L package
Reel dimensions (mm)
A (max)
B (min)
C
D (min)
N (min)
G
T (max)
330
1.5
13 ±0.25
20.2
60
12.4 +2/-0
18.4
page 48/55
LPS27HHTW
Contents
Contents
DS13489 - Rev 1 page 49/55
LPS27HHTW
Contents
DS13489 - Rev 1 page 50/55
LPS27HHTW
Contents
DS13489 - Rev 1 page 51/55
LPS27HHTW
List of tables
List of tables
DS13489 - Rev 1 page 52/55
LPS27HHTW
List of figures
List of figures
DS13489 - Rev 1 page 53/55
Revision history
Date
12-Jan-2021
Version
1
Table 24. Document revision history
Changes
Initial release
LPS27HHTW
DS13489 - Rev 1 page 54/55
LPS27HHTW
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13489 - Rev 1 page 55/55
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