STMicroelectronics LPS22HH Datasheet
Advertisement
Advertisement
LPS22HH
High-performance MEMS nano pressure sensor:
260-1260 hPa absolute digital output barometer
Datasheet
-
production data
HLGA-10L
(2.0 x 2.0 x 0.73 mm)
Applications
Altimeters and barometers for portable devices
GPS applications
Weather station equipment
Sport watches
e-cigarettes
Drones
Gas metering
Features
260 to 1260 hPa absolute pressure range
Current consumption down to 4 μ A
Absolute pressure accuracy: 0.5 hPa
Low pressure sensor noise: 0.65 Pa
High-performance TCO: 0.65 Pa/°C
Embedded temperature compensation
24-bit pressure data output
ODR from 1 Hz to 200 Hz
SPI, I²C or MIPI I3C
SM interfaces
Embedded FIFO
Interrupt functions: Data-Ready, FIFO flags, pressure thresholds
Supply voltage: 1.7 to 3.6 V
High shock survivability: 22,000 g
Small and thin package
ECOPACK
®
lead-free compliant
Description
The LPS22HH is an ultra-compact piezoresistive absolute pressure sensor which functions as a digital output barometer. The device comprises a sensing element and an IC interface which communicates through I²C, MIPI I3C SM or SPI from the sensing element to the application.
The sensing element, which detects absolute pressure, consists of a suspended membrane manufactured using a dedicated process developed by ST.
The LPS22HH is available in a full-mold, holed
LGA package (HLGA). It is guaranteed to operate over a temperature range extending from -40 °C to +85 °C. The package is holed to allow external pressure to reach the sensing element.
Order code
LPS22HHTR
Table 1. Device summary
Temperature range [°C] Package
-40 to +85°C HLGA-10L
Packing
Tape and reel
February 2019
This is information on a product in full production.
DocID030890 Rev 2 1/59 www.st.com
Contents
Contents
2/59
LPS22HH
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 9
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
I²C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Interpreting pressure readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Interpreting temperature readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Continuous (Dynamic-Stream) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bypass-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bypass-to-Continuous (Dynamic-Stream) mode . . . . . . . . . . . . . . . . . . . 22
Continuous (Dynamic-Stream)-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . 23
Retrieving data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DocID030890 Rev 2
LPS22HH Contents
SPI bus interface (CS = low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SM
slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CCC supported commands . . . . . . . . . . . . . . . . . . . . . . . . 33
coexistence in LPS22HH . . . . . . . . . . . . . . . . . . . . . . . . 35
INTERRUPT_CFG (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FIFO_STATUS1 (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
FIFO_STATUS2 (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PRESS_OUT_XL (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PRESS_OUT_L (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PRESS_OUT_H (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DocID030890 Rev 2 3/59
59
Contents
LPS22HH
TEMP_OUT_L (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
TEMP_OUT_H (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
FIFO_DATA_OUT_PRESS_XL (78h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
FIFO_DATA_OUT_PRESS_L (79h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
FIFO_DATA_OUT_PRESS_H (7Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
FIFO_DATA_OUT_TEMP_L (7Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
FIFO_DATA_OUT_TEMP_H (7Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
HLGA-10L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HLGA-10L packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4/59 DocID030890 Rev 2
LPS22HH
List of tables
List of tables
Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 28
Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 28
CCC commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DocID030890 Rev 2 5/59
59
List of figures
List of figures
LPS22HH
SM both active (INT_DRDY pin not connected) . . . . . . . . . . . . . . . . . . . . 35
SM active (INT_DRDY pin connected to VDD_IO). . . . . . . . . . . . . . . . . . . . . 36
HLGA-10L (2.0 x 2.0 x 0.73 mm typ.) package outline and mechanical dimensions . . . . . 55
6/59 DocID030890 Rev 2
LPS22HH Block diagrams
Figure 1. Device architecture block diagram dĞŵƉĞƌĂƚƵƌĞ
^ĞŶƐŽƌ
Dhy
ŶĂůŽŐ
&ƌŽŶƚͲŶĚ ŝŐŝƚĂů
>ŽŐŝĐ
/ Ϯ
D/W//ϯ ^D
^W/
^ĞŶƐŝŶŐůĞŵĞŶƚ
ŶĂůŽŐ
&ƌŽŶƚͲŶĚ
^ĞŶƐŽƌŝĂƐ sŽůƚĂŐĞĂŶĚƵƌƌĞŶƚŝĂƐ ůŽĐŬĂŶĚƚŝŵŝŶŐ
ŝŐŝƚĂů
>W&ŝůƚĞƌ
>W&Ϭ
Figure 2. Digital logic ŝŐŝƚĂů
>W&ŝůƚĞƌ
>W&ϭ
WƌĞƐƐƵƌĞ
ŽŵƉĞŶƐĂƚŝŽŶ
Eͺ>W&W ϭ
WŽƵƚ
Ϭ
KƵƚƉƵƚ
ZĞŐŝƐƚĞƌƐ dĞŵƉĞƌĂƚƵƌĞ
ŽŵƉĞŶƐĂƚŝŽŶ dŽƵƚ &/&K
/ Ϯ
D/W//ϯ ^D
^W/
DocID030890 Rev 2 7/59
59
Pin description LPS22HH
Figure 3. Pin connections (bottom view)
9''
*1'
*1'
5(6
6'$6',6'2
6'26$
8/59
Pin number
1
2
3
4
5
6
7
8
9
10
Name
Vdd_IO
SCL
SPC
Reserved
SDA
SDI
SDI/SDO
SDO
SA0
CS
Table 2. Pin description
Function
Power supply for I/O pins
I²C / MIPI I3C
SM serial clock (SCL)
SPI serial port clock (SPC)
Connect to GND
I²C / MIPI I3C
SM
serial data (SDA)
4-wire SPI serial data input (SDI)
3-wire serial data input/output (SDI/SDO)
4-wire SPI serial data output (SDO)
I²C least significant bit of the device address (SA0)
MIPI I3C
SM
least significant bit of the static address (SA0)
SPI enable
I²C and MIPI I3C
SM
/ SPI mode selection
(1: SPI idle mode / I²C and MIPI I3C
SM
communication enabled;
0: SPI communication mode / I²C and MIPI I3C
SM disabled)
INT_DRDY Interrupt or Data-Ready
GND
GND
VDD
0 V supply
0 V supply
Power supply
DocID030890 Rev 2
LPS22HH
3
Mechanical and electrical specifications
Mechanical and electrical specifications
P sens
VDD = 1.8 V, T = 25 °C, unless otherwise noted.
Symbol
Table 3. Pressure and temperature sensor characteristics
Parameter
Pressure sensor characteristics
Test condition Min.
Typ.
(1)
PT op
P op
P bits
Operating temperature range
Operating pressure range
Pressure output data
-40
260
24
Pressure sensitivity 4096
P
AccRel
P
AccT
P noise
ODR
Pres
Relative accuracy over pressure
(2)
P = 800 - 1100 hPa
T = 25 °C
Absolute accuracy over temperature P op
, T = -20 to 80°C
RMS pressure sensing noise
(3) with embedded filter and at T = 25 °C
Pressure output data rate
(4)
±0.025
±0.5
0.0065
1
10
25
50
75
100
200
TCO Temperature coefficient offset
P = 660 ~ 1160 hPa,
T = -20 ~ +65 °C
±0.65
P_longterm
P_drift
Pressure accuracy, long-term stability
(5)
Soldering drift
Temperature sensor characteristics
T op
T sens
T acc
Operating temperature range
Temperature sensitivity
Temperature absolute accuracy T = 0 to 80°C
-40
±0.33
±0.5
ODR
T
Output temperature data rate
100
±1.5
1
10
25
50
75
100
200
Max.
+85
1260
+85
Unit
Hz
Pa/°C hPa/year hPa
°C
LSB/°C
°C
Hz
°C hPa bits
LSB/ hPa hPa hPa hPa
RMS
DocID030890 Rev 2 9/59
59
Mechanical and electrical specifications LPS22HH
1. Typical specifications are not guaranteed.
2. By design, the typ. value is defined based characterization data with 10 hPa pressure interval.
3. Pressure noise RMS evaluated in a controlled environment, based on the average standard deviation of 50 measurements with LOW_NOISE_EN = 1, EN_LPFP = 1, LPFP_CFG = 1.
4. Output data rate is configured acting on ODR[2:0] in
5. Typ. value is defined considering a 5-year life cycle of the final application.
VDD = 1.8 V, T = 25 °C, unless otherwise noted.
Symbol Parameter
VDD Supply voltage
Vdd_IO IO supply voltage
Table 4. Electrical characteristics
Test condition Min.
1.7
1.7
Idd Supply current
@ ODR 1 Hz
LOW_NOISE_EN = 0
@ ODR 1 Hz
LOW_NOISE_EN = 1
IddPdn
Supply current in power-down mode
1. Typical specifications are not guaranteed.
Typ.
(1)
Max.
Unit
3.6
V
Vdd+0.1
V
4
μ A
12
0.9
μ A
Symbol Parameter
DC input characteristics
Vil
Vih
Low-level input voltage
(Schmitt buffer)
High-level input voltage
(Schmitt buffer)
DC output characteristics
Vol Low-level output voltage
Voh High-level output voltage
Table 5. DC characteristics
Condition Min.
-
-
0.8 * Vdd_IO
-
Vdd_IO - 0.2
Typ.
-
-
-
-
Max.
0.2 * Vdd_IO V
V
0.2
-
Unit
V
V
10/59 DocID030890 Rev 2
LPS22HH Mechanical and electrical specifications
3.3
3.3.1
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and T
OP
.
Table 6. SPI slave timing values
Value
(1)
Symbol Parameter Unit
Min Max t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)
SPI clock cycle
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
100
6
8
5
15
9
10
(2)
50
50 ns
MHz ns
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.
2. Recommended to set max SPI clock 8 MHz to ≤ 50 Hz ODR.
Figure 4. SPI slave timing diagram
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
DocID030890 Rev 2 11/59
59
Mechanical and electrical specifications
3.3.2 I²C - inter-IC control interface
Subject to general operating conditions for Vdd and T
OP
.
Symbol Parameter (1)
Table 7. I²C slave timing values
I²C standard mode
(1)
Min Max f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
0
4.7
4.0
250
0
100
3.45
t su(SR)
START condition hold time
Repeated START condition setup time
4
4.7
t su(SP)
STOP condition setup time 4 t w(SP:SR)
Bus free time between STOP and START condition
4.7
1. Data based on standard I²C protocol requirement, not tested in production.
Figure 5. I²C slave timing diagram
Min
0
1.3
0.6
100
0
0.6
I²C fast mode
Max
400
0.9
0.6
0.6
1.3
LPS22HH
μ s
Unit kHz
μ s ns
μ s
6'$
67$57
W
VX65
W
Z6365
5(3($7('
67$57
67$57
W
VX6'$
W
K6'$
W
VX63
6723
6&/
Note:
W
K67
W
Z6&//
W
Z6&/+
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
12/59 DocID030890 Rev 2
LPS22HH
3.4
Mechanical and electrical specifications
Absolute maximum ratings
Stress above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Table 8. Absolute maximum ratings
Ratings
Vdd Supply voltage
Vdd_IO I/O pins supply voltage
Vin Input voltage on any control pin
P Overpressure
T
STG
Storage temperature range
ESD Electrostatic discharge protection
Maximum value
-0.3 to 4.8
-0.3 to 4.8
-0.3 to Vdd_IO +0.3
2
-40 to +125
2.5 (HBM)
Unit
V
V
V
MPa
°C kV
Note: Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
DocID030890 Rev 2 13/59
59
Functionality
4 Functionality
LPS22HH
The LPS22HH is a high-resolution, digital output pressure sensor packaged in an HLGA fullmold package. The complete device includes a sensing element based on a piezoresistive
Wheatstone bridge approach, and an IC interface which communicates a digital signal from the sensing element to the application.
An ST proprietary process is used to obtain a silicon membrane for MEMS pressure sensors. When pressure is applied, the membrane deflection induces an imbalance in the
Wheatstone bridge piezoresistances whose output signal is converted by the IC interface.
The complete measurement chain is composed of a low-noise amplifier which converts the resistance unbalance of the MEMS sensors (pressure and temperature) into an analog voltage using an analog-to-digital converter.
The pressure and temperature data may be accessed through an I²C/MIPI I3C SM /SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller.
The LPS22HH features a Data-Ready signal which indicates when a new set of measured pressure and temperature data are available, thus simplifying data synchronization in the digital system that uses the device.
The trimming values are stored inside the device in a non-volatile structure. When the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation which allows the device to be used without requiring any further calibration.
14/59 DocID030890 Rev 2
LPS22HH
4.4
Functionality
Interpreting pressure readings
The pressure data are stored in 3 registers: PRESS_OUT_H (2Ah) , PRESS_OUT_L (29h)
,
and PRESS_OUT_XL (28h) . The value is expressed as a 24-bit signed number (in 2’s
complement).
To obtain the pressure in hPa, take the complete 24-bit word and then divide by the sensitivity 4096 LSB/hPa. This same interpretation is applied to pressure readings when
FIFO is enabled and the pressure data are stored in 3 registers:
FIFO_DATA_OUT_PRESS_XL (78h) , FIFO_DATA_OUT_PRESS_L (79h)
, and
Figure 6. Pressure readings
Equation 1
3UHVVXUH9DOXH/6% 35(66B287B+$K 35(66B287B/K 35(66B287B;/K
))'K /6%VLJQHGGHFLPDO
Equation 2
3UHVVXUHK3D
3UHVVXUH9DOXH/6%
6HQVLWLYLW\
/6%
/6%K3D
K3$
DocID030890 Rev 2 15/59
59
Functionality
4.5
LPS22HH
Interpreting temperature readings
The temperature data are stored in 2 registers: TEMP_OUT_H (2Ch)
and
.
The value is expressed as 2’s complement. To obtain the temperature in °C, take the two’s complement of the complete 16-bit word and then divide by the sensitivity 100 LSB/°C. This same interpretation is applied to temperature readings when FIFO is enabled and the temperature data are stored in 2 registers:
FIFO_DATA_OUT_TEMP_H (7Ch) and
Figure 7. Temperature readings
7(03B287B+ 7(03B287B/
7HPSHUDWXUH9DOXH/6% 7(03B287B+&K 7(03B287B/%K
& /6%GHFLPDOVLJQHG
7HPSHUDWXUH&
7HPSHUDWXUH 9DOXH /6%
6HQVLWLYLW\
/6%
/6%&
&
16/59 DocID030890 Rev 2
LPS22HH
5 FIFO
FIFO
The LPS22HH embeds 128 slots of 40-bit data FIFO to store the pressure and temperature output values. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work according to six different modes:
Bypass mode
FIFO mode
Continuous (Dynamic-Stream) mode
Continuous (Dynamic-Stream)-to-FIFO mode
Bypass-to-Continuous (Dynamic-Stream)
Bypass-to-FIFO mode
The FIFO buffer is enabled when a configuration different from all bits '0' are written in
FIFO_CTRL (13h) and each mode is selected by the TRIG_MODES bit and F_MODE[1:0]
bits in
. Programmable FIFO threshold status, FIFO overrun events and the number of unread samples stored are available in the
FIFO_STATUS2 (26h) registers and can be set to generate dedicated interrupts on the
INT_DRDY pad using the
FIFO_STATUS2 (26h) (FIFO_WTM_IA) goes to '1' when the number of unread samples
(FSS[7:0]) is greater than or equal to WTM[6:0] in
(14h) . If FIFO_WTM (14h) (WTM[6:0]) is equal to 0,
FIFO_STATUS2 (26h) (FIFO_WTM_IA)
stays at '0'.
FIFO_STATUS2 (26h) (FIFO_OVR_IA) is equal to '1' if a FIFO slot is overwritten.
FIFO_STATUS1 (25h) (FSS[7:0]) contains stored data levels of unread samples; when
FSS[7:0] is equal to ‘00000000’, FIFO is empty; when FSS[7:0] is equal to ‘10000000’,
FIFO is full and the unread samples are 128.
DocID030890 Rev 2 17/59
59
FIFO LPS22HH
In Bypass mode (
(TRIG_MODES and F_MODE[1:0] = ‘000’ or ‘100’), the
FIFO is not operational and it remains empty.
Switching to Bypass mode is also used to reset the FIFO. Passing through Bypass mode is mandatory when switching between different FIFO buffer operating modes.
As described in the next figure, for each channel only the first address is used. When new data is available, the older data is overwritten.
Figure 8. Bypass mode
3
L
7
L
3
3
3
7
7
7
HPSW\
3 7
18/59 DocID030890 Rev 2
LPS22HH FIFO
In FIFO mode (
(TRIG_MODES and F_MODE[1:0] = ‘001’) data from the output
PRESS_OUT_XL (28h) , PRESS_OUT_L (29h) , PRESS_OUT_H (2Ah) ,
TEMP_OUT_L (2Bh) , and TEMP_OUT_H (2Ch) are stored in the FIFO until it is full.
To reset FIFO content, in order to select Bypass mode the value '000' must be written in
(TRIG_MODE & F_MODE[1:0]). After this reset command it is possible to restart FIFO mode by writing the value '001' in
F_MODE[1:0]).
The FIFO buffer memorizes 128 levels of data, but the depth of the FIFO can be
resized/reduced by setting the FIFO_CTRL (13h) (STOP_ON_WTM) bit. If the
STOP_ON_WTM bit is set to '1', FIFO depth is limited to
FIFO_WTM (14h) (WTM[6:0]) data.
Figure 9. FIFO mode
3
L
7
L
3
3
3
7
7
7
3 7
DocID030890 Rev 2 19/59
59
FIFO
5.3
LPS22HH
Continuous (Dynamic-Stream) mode
In Continuous (Dynamic-Stream) mode (
(TRIG_MODES and
F_MODE[1:0] = ‘011’) after emptying the FIFO, the first new sample that arrives becomes the first to be read in a subsequent read burst. In this way, the number of new data available in FIFO does not depend on the previous read.
In Continuous (Dynamic-Stream) mode FIFO_STATUS1 (25h)
(FSS[7:0]) is the number of new pressure and temperature samples available in the FIFO buffer.
Continuous (Dynamic-Stream) is intended to be used to read
(FSS[7:0]) samples when it is not possible to guarantee reading data within 1/ODR time period.
Also, a FIFO threshold interrupt on the INT_DRDY pad through
(INT_F_WTM) can be enabled in order to read data from the FIFO and leave free memory slots for incoming data.
Figure 10. Continuous (Dynamic-Stream) mode
20/59 DocID030890 Rev 2
LPS22HH FIFO
In Bypass-to-FIFO mode (
(TRIG_MODES and F_MODE[1:0] = ‘101’),
FIFO behavior switches when the
INT_SOURCE (24h) (IA) bit rises for the first time. When
the
INT_SOURCE (24h) (IA) bit is equal to '0', FIFO behaves like in Bypass mode. Once the
INT_SOURCE (24h) (IA) bit rises to '1', FIFO behavior switches and keeps behaving like in
FIFO mode.
An interrupt generator has to be set to the desired configuration through
.
Figure 11. Bypass-to-FIFO mode
3
L
7
L 3
L
7
L
3
3
3
7
7
7
3
3
3
7
7
7
HPSW\
3 7 3 7
%\SDVV0RGH
7ULJJHUHYHQW
),)20RGH
DocID030890 Rev 2 21/59
59
FIFO
5.5
LPS22HH
Bypass-to-Continuous (Dynamic-Stream) mode
In Bypass-to-Continuous (Dynamic-Stream) mode (
FIFO_CTRL (13h) (TRIG_MODES and
F_MODE[1:0] = ‘110’), FIFO operates in Bypass mode until it switches to Continuous
(Dynamic-Stream) mode behavior when
(IA) rises to '1', then FIFO behavior keeps behaving like in Continuous (Dynamic-Stream) mode.
An interrupt generator has to be set to the desired configuration through
.
Figure 12. Bypass-to-Continuous (Dynamic-Stream) mode
3
L
7
L 3
L
7
L
3
3
3
7
7
7
3
3
3
7
7
7
HPSW\
3 7
3
3
7
7
%\SDVV0RGH
7ULJJHUHYHQW
'\QDPLF6WUHDP0RGH
22/59 DocID030890 Rev 2
LPS22HH
5.6
FIFO
Continuous (Dynamic-Stream)-to-FIFO mode
In Continuous (Dynamic-Stream)-to-FIFO mode (
FIFO_CTRL (13h) (TRIG_MODES and
F_MODE[1:0] = ‘111’), data are stored in FIFO and FIFO operates in Continuous (Dynamic-
Stream) mode behavior until it switches to FIFO mode behavior when
(IA) rises to '1'.
An interrupt generator has to be set to the desired configuration through
.
Figure 13. Continuous (Dynamic-Stream)-to-FIFO mode
3
L
7
L
3
L
7
L
3
3
3
7
7
7
3
3
3
7
7
7
3
3
7
7
3 7
'\QDPLF6WUHDP0RGH ),)20RGH
7ULJJHUHYHQW
5.7 Retrieving data from FIFO
FIFO data is read through FIFO_DATA_OUT_PRESS (78h, 79h and 7Ah) and
FIFO_DATA_OUT_TEMP (7Bh, 7Ch).
The read address is automatically updated by the device and it rolls back to 78h when register 7Ch is reached. In order to read all FIFO levels in a multiple byte read, 640 bytes
(5 output registers by 128 levels) must be read.
DocID030890 Rev 2 23/59
59
Application hints
Figure 14. LPS22HH electrical connections (top view)
LPS22HH
Note:
The device power supply must be provided through the VDD line; a power supply decoupling capacitor C1 (100 nF) must be placed as near as possible to the supply pads of the device. The C1 capacitor can be tied to VDD and VDDIO, but it is recommended to use
2 capacitors, one on each VDD and VDDIO line, in case VDD are VDDIO are separate.
Depending on the application, an additional capacitor of 4.7 μ F could be placed on VDD line.
The functionality of the device and the measured data outputs are selectable and accessible through the I²C, MIPI I3C SM , SPI interface. When using the I²C and MIPI I3C SM , CS must be tied to Vdd_IO.
All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to
Figure 14 ). It is possible to remove VDD while maintaining
Vdd_IO without blocking the communication bus, in this condition the measurement chain is powered off.
To guarantee proper power-off of the device, it is recommended to maintain the duration of the VDD line to GND for at least 10 ms.
24/59 DocID030890 Rev 2
LPS22HH
9''
Figure 15. LPS22HH power-off sequence
Application hints
9
0LQPV
7LPH
9''5LVLQJ)DOOLQJWLPHVaPV
9''PXVWEHORZHUWKDQ9IRUDWOHDVWPVGXULQJSRZHURIIVHTXHQFHIRUFRUUHFW325
The HLGA package is compliant with the ECOPACK ® standard and it is qualified for soldering heat resistance according to JEDEC J-STD-020.
DocID030890 Rev 2 25/59
59
Digital interfaces LPS22HH
The registers embedded in the LPS22HH may be accessed through either the I²C, MIPI
I3C
SM
or SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I²C interface, the
CS line must be tied high (i.e. connected to Vdd_IO).
Pin name
CS
SCL/SPC
SDA
SDI
SDI/SDO
SDO
SAO
Table 9. Serial interface pin description
Pin description
SPI enable
I²C/SPI mode selection
(1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C serial clock (SCL)
SPI serial port clock (SPC)
I²C serial data (SDA)
4-wire SPI serial data input (SDI)
3-wire serial data input /output (SDI/SDO)
4-wire SPI serial data output (SDO)
I²C less significant bit of the device address (SA0)
26/59
The LPS22HH I²C is a bus slave. The I²C is employed to write data into registers whose content can also be read back.
The relevant I²C terminology is given in
Term
Table 10. I²C terminology
Description
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master The device which initiates a transfer, generates clock signals and terminates a transfer
Slave The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines have to be connected to Vdd_IO through pull-up resistors.
The I²C interface is compliant with fast mode (400 kHz) I²C standards as well as with the normal mode.
DocID030890 Rev 2
LPS22HH Digital interfaces
The transaction on the bus is started through a START (ST) signal. A start condition is defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After the master has transmitted this, the bus is considered busy. The next data byte transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave.
When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.
The 7-bit slave address (SAD) associated to the LPS22HH is 101110xb. The SDO / SA0 pad can be used to modify the less significant bit of the device address. If the SA0 pad is connected to voltage supply, LSb is ‘1’ (7-bit address 1011101b=5Dh), otherwise if the SA0 pad is connected to ground, the LSb value is ‘0’ (7-bit address 1011100b=5Ch). This solution permits connecting and addressing two different LPS22HH devices to the same I²C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.
The I²C embedded inside the ASIC behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK), an 8-bit sub-address will be transmitted (SUB): the
7 LSB represent the actual register address while the MSB has no meaning. The
IF_ADD_INC bit in
CTRL_REG2 (11h) enables sub-address auto increment (IF_ADD_INC
is '1' by default), so if IF_ADD_INC = '1' the SUB (sub-address) will be automatically increased to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged.
SAD+read/write bit pattern is composed, listing all the possible configurations.
Command
Read
Write
Read
Write
Table 11. SAD+Read/Write patterns
SAD[6:1] SAD[0] = SA0 R/W
101110
101110
101110
101110
0
0
1
1
1
0
1
0
SAD+R/W
10111001 (B9h)
10111000 (B8h)
10111011 (BBh)
10111010 (BAh)
Master
Slave
Table 12. Transfer when master is writing one byte to slave
ST SAD + W SUB DATA
SAK SAK SAK
SP
DocID030890 Rev 2 27/59
59
Digital interfaces LPS22HH
Master
Slave
ST
Table 13. Transfer when master is writing multiple bytes to slave
SAD + W SUB DATA DATA
SAK SAK SAK SAK
SP
Master
Table 14. Transfer when master is receiving (reading) one byte of data from slave
ST SAD + W SUB SR SAD + R NMAK
Slave SAK SAK SAK DATA
SP
Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP
Slave SAK SAK SAK DATA DATA DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit
(MSb) first. If a receiver cannot receive another complete byte of data until it has performed some other functions, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function), the data line must be kept HIGH by the slave. The master can then abort the transfer. A LOW-to-HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is no master acknowledge.
28/59 DocID030890 Rev 2
LPS22HH
7.3
Digital interfaces
SPI bus interface (CS = low)
The LPS22HH SPI is a bus slave. The SPI allows writing to and reading from the registers of the device.
The serial interface interacts with the application using 4 wires: CS , SPC , SDI and SDO .
Figure 16. Read and write protocol
&6
63&
6',
5:
$' $' $' $' $' $' $'
', ', ', ', ', ', ', ',
6'2
'2 '2 '2 '2 '2 '2 '2 '2
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and returns to high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .
Both the read register and write register commands are completed in 16 clock pulses or multiples of 8 in the case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23,...) starts at the last falling edge of SPC just before the rising edge of CS .
bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip will drive SDO at the start of bit 8.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods are added. When the
IF_ADD_INC bit is 0, the address used to read/write data remains the same for every block.
When the IF_ADD_INC bit is 1, the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
DocID030890 Rev 2 29/59
59
Digital interfaces
Figure 17. SPI read protocol
LPS22HH
The SPI read command is performed with 16 clock pulses. The multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit 16-...
: data DO(...-8). Further data in multiple byte reads.
Figure 18. Multiple byte SPI read protocol (2-byte example)
30/59 DocID030890 Rev 2
LPS22HH Digital interfaces
Figure 19. SPI write protocol
&6
63&
6',
5:
$' $' $' $' $' $' $'
', ', ', ', ', ', ', ',
The SPI write command is performed with 16 clock pulses. The multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : WRITE bit. The value is 0.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written in the device (MSb first).
bit 16-...
: data DI(...-8). Further data in multiple byte writes.
Figure 20. Multiple byte SPI write protocol (2-byte example)
&6
63&
6',
5:
$' $' $' $' $' $' $'
', ', ', ', ', ', ', ', ',',',',',',', ',
DocID030890 Rev 2 31/59
59
Digital interfaces
7.3.3 SPI read in 3-wire mode
LPS22HH
A 3-wire mode is entered by setting bit SIM to ‘1’ (SPI serial interface mode selection) in
Figure 21. SPI read protocol in 3-wire mode
&6
63&
6',2
5:
$' $' $' $' $' $'
'2 '2 '2 '2 '2 '2 '2 '2
The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
32/59 DocID030890 Rev 2
LPS22HH Digital interfaces
SM
slave interface
The LPS22HH interface includes a MIPI I3C
SM
SDR embedded features:
SDR only slave interface with MIPI I3C
SM
CCC command
Direct CCC communication (SET and GET)
Broadcast CCC communication
Private communications
Private read and write for single byte
Multiple read and write
In-band interrupt and hot-join requests
SM
CCC supported commands
The list of MIPI I3C SM table.
CCC commands supported by the device is detailed in the following
Command
ENEC
RSTDAA
DISEC
ENTAS0
ENTAS1
ENTAS2
ENTAS3
SETMWL
SETMRL
SETDASA
SETNEWDA
GETMWL
GETMRL
Table 16. MIPI I3C SM CCC commands
Command code
Default Description
0x80 / 0x00
0x86 / 0x06
0x81 / 0x01
0x82 / 0x02
0x83 / 0x03
0x84 / 0x04
0x85 / 0x05
0x89 / 0x08
0x8A / 0x09
0x00
0x08
0x00
0x10
0x04
Slave activity control (direct and broadcast)
Reset the assigned dynamic address
(direct and broadcast)
Slave activity control (direct and broadcast)
Enter activity state (direct and broadcast)
Enter activity state (direct and broadcast)
Enter activity state (direct and broadcast)
Enter activity state (direct and broadcast)
Define maximum write length during private write
(direct and broadcast)
Define maximum read length during private read
(direct and broadcast)
0x87
0x88
Assign dynamic address using static address
(0x5C / 0x5D depending on the SDO level)
Change dynamic address
0x8B
0x8C
0x00
0x08
0x00
0x10
0x04
Get maximum write length during private write
Get maximum read length during private read
DocID030890 Rev 2 33/59
59
Digital interfaces
Command
GETPID
GETBCR
GETDCR
GETSTATUS
GETMXDS
GETXTIME
Table 16. MIPI I3C SM CCC commands (continued)
Command code
Default Description
0x8D
0x8E
0x8F
0x90
0x02
0x08
0x00
0xB3
0x00
0x00
0x07
0x62
Device ID register
Bus characteristics register
DCR
Status register
0x94
0x99
0x00
0x20
0x07
0x04
0x0A
0x64
Return max data speed
Get exchange time information
LPS22HH
34/59 DocID030890 Rev 2
LPS22HH Digital interfaces
SM
coexistence in LPS22HH
In the LPS22HH, the SDA and SCL lines are common to both I²C and MIPI I3C
SM
. The I²C bus requires anti-spike filters on the SDA and SCL pins that are not compatible with MIPI
I3C
SM
timing.
The device can be connected to both I²C and MIPI I3C
SM
or only to the MIPI I3C
SM
bus depending on the connection of the INT1 pin when the device is powered up:
INT_DRDY pin floating (internal pull-down): I²C/MIPI I3C SM
– I²C case: INT_DRDY pin is by default an input with pull-down. If I²C is used,
INT_DRDY must be left unconnected or eventually pulled down during device initialization. After power-on, during device configuration, the INT_DRDY pin can be programmed as an interrupt output pin and it is recommended to set bit
I3C_disable to '1'.
– I3C case: INT_DRDY pin is by default an input with pull-down. If I3C is used and the INT_DRDY pin is unconnected, dynamic address assignment must be performed using I²C Fast Mode Plus Timing (max 1 MHz clock). After dynamic address assignment, I3C can be used in full speed mode.
INT_DRDY pin connected to VDD_IO: only MIPI I3C
SM
– Only I3C: INT_DRDY pin is by default an input with pull-down. If INT_DRDY is set to Vdd_IO, I3C slave is selected and device can be initialized at full speed through the SETDASA command. If the I3C bus is available for more than 10 msec and the device is not yet addressed, a hot join request is performed (SDA line kept to ground from slave) and the master must manage the request. After device address assignment, a private write can be performed to disconnect the
INT_DRDY pull-down.
Figure 22. I²C and MIPI I3C SM both active (INT_DRDY pin not connected)
INT_DRDY pin not connected
I²C/MIPI I3C SM both active
I²C/MIPI I3C SM
(both active)
I²C bus case MIPI I3C SM bus case
Master sends
I²C r/w
Master assigns DA to the slave
(1)
Master resets
DA
Slave performs requested r/w
MIPI I3C SM
7EhCCC commands
Slave event management
Error detection and recovery
1. Address assignment (SETDASA) must be performed with I²C Fast Mode Plus Timing. When the slave is addressed, the I²C slave is disabled and the timing is compatible with MIPI I3C
SM specifications.
DocID030890 Rev 2 35/59
59
Digital interfaces LPS22HH
Figure 23. Only MIPI I3C SM active (INT_DRDY pin connected to VDD_IO)
INT_DRDY pin connected to VDD_IO
Only MIPI I3C SM active
I²C/MIPI I3C SM MIPI I3C SM bus case
Dynamic
Address
Assignment (1)
Master resets
DA
MIPI I3C SM private R/W with and without
7Eh CCC commands
Slave event management
Error detection and recovery
1. When the slave is MIPI I3C
SM
MIPI I3C
SM
SDR timing.
only, the I²C slave is always disabled. The address can be assigned using
36/59 DocID030890 Rev 2
LPS22HH Register mapping
Reserved
INTERRUPT_CFG
THS_P_L
THS_P_H
IF_CTRL
WHO_AM_I
CTRL_REG1
CTRL_REG2
CTRL_REG3
FIFO_CTRL
FIFO_WTM
REF_P_L
REF_P_H
Reserved
RPDS_L
RPDS_H
Reserved
INT_SOURCE
FIFO_STATUS1
FIFO_STATUS2
STATUS
PRESSURE_OUT_XL
PRESSURE_OUT_L
PRESSURE_OUT_H
TEMP_OUT_L
TEMP_OUT_H
Reserved
FIFO_DATA_OUT_PRESS_XL
FIFO_DATA_OUT_PRESS_L
FIFO_DATA_OUT_PRESS_H
provides a quick overview of the 8-bit registers embedded in the device.
Name
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Table 17. Registers address map
Register address Default
Type
Binary
R/W
R/W
R
R
R
Hex
2A
2B
2C
2D - 77
78
79
7A
26
27
28
29
19
1A-23
24
25
15
16
17
18
11
12
13
14
00 – 0A
0B
0C
0D
0E
0F
10
Function and comment
Output
Output
Output
Output
Output
-
Output
Output
Output
Reserved
00000000 Interrupt register
00000000
Pressure threshold registers
00000000
00000000 Interface control register
10110011 Who am I
00000000
00010000
00000000
Control registers
00000000 FIFO configuration register
00000000
00000000
00000000
Reference pressure registers
-
00000000
00000000
-
Reserved
Pressure offset registers
Reserved
Output Interrupt register
Output
FIFO status registers
Output
Output Status register
Pressure output registers
Temperature output registers
Reserved
FIFO pressure output registers
DocID030890 Rev 2 37/59
59
Register mapping LPS22HH
Name
FIFO_DATA_OUT_TEMP_L
FIFO_DATA_OUT_TEMP_H
Table 17. Registers address map (continued)
Register address Default
Type
Binary
R
R
Hex
7B
7C
Output
Output
Function and comment
FIFO temperature output registers
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
To guarantee the proper behavior of the device, all register addresses not listed in the above table must not be accessed and the content stored in those registers must not be changed.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
38/59 DocID030890 Rev 2
LPS22HH Register description
The device contains a set of registers which are used to control its behavior and to retrieve pressure and temperature data. The register address, made up of 7 bits, is used to identify them and to read/write the data through the serial interface.
Interrupt mode for pressure acquisition configuration (R/W)
7 6 5
AUTOREFP RESET_ARP AUTOZERO
4
RESET_AZ
3
DIFF_EN
2
LIR
1
PLE
AUTOREFP Enable AUTOREFP function. Default value: 0
(0: normal mode; 1: AUTOREFP enabled)
RESET_ARP Reset AUTOREFP function. Default value: 0
(0: normal mode; 1: reset AUTOREFP function)
AUTOZERO Enable AUTOZERO function. Default value: 0
(0: normal mode; 1: AUTOZERO enabled)
RESET_AZ Reset AUTOZERO function. Default value: 0
(0: normal mode; 1: reset AUTOZERO function)
DIFF_EN Enable interrupt generation. Default value: 0
(0: interrupt generation disabled; 1: interrupt generation enabled)
LIR
PLE
Latch interrupt request to the
INT_SOURCE (24h) register. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
Enable interrupt generation on pressure low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on pressure value lower than preset threshold)
PHE Enable interrupt generation on pressure high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on pressure value higher than preset threshold)
0
PHE
Referring to
Figure 24: “Threshold-based” interrupt event , the LPS22HH can be set by the
user to support the interrupt function when P_DIFF_IN (defined below) is higher or lower than the threshold value stored in
THS_P_L (0Ch) and THS_P_H (0Dh) .
It is enabled when the DIFF_EN bit in INTERRUPT_CFG (0Bh) register is set to '1' and
either PHE bit or PLE bit (or both bits) = '1'. Then, the differential pressure can be compared to a user-defined threshold stored in the 15-bit THS_P (0Ch and 0Dh) registers.
The threshold pressure value defined by the user is a 15-bit unsigned value in a 16-bit
register composed of THS_P_L (0Ch) and THS_P_H (0Dh)
The value is:
THS_P (15-bit unsigned) = Desired Interrupt threshold (hPa) x 16
The PHE and PLE bits in
INTERRUPT_CFG (0Bh) enable the differential pressure interrupt
generation on the positive or negative event respectively.
The differential interrupt must be used with AUTOREFP or AUTOZERO mode. Please refer to the application note (AN5209: Section 8. Interrupt modes) for further details.
DocID030890 Rev 2 39/59
59
Register description
3B',))B,1
Figure 24. “Threshold-based” interrupt event
7KUHVKROGSRVLWLYHYDOXH
7KUHVKROGQHJDWLYHYDOXH
3RVLWLYH
1HJDWLYH
LPS22HH
To enable the AUTOZERO mode, the AUTOZERO bit must be set to '1' and then the measured pressure value is used as the reference and stored in the register REF_P
( REF_P_L (15h) , REF_P_H (16h) ). From this point on, the output pressure value
( PRESS_OUT_XL (28h) , PRESS_OUT_L (29h) , PRESS_OUT_H (2Ah) ) is updated with
the difference between the measured pressure and REF_P.
– P_DIFF_IN = measured pressure - REF_P
– PRESS_OUT = measured pressure - REF_P
After the first conversion, the AUTOZERO bit is automatically set back to '0'. In order to
return back to normal mode, the RESET_AZ bit in the INTERRUPT_CFG (0Bh) register has
to be set to '1'. This also resets the content of the REF_P registers to 0.
AUTOREFP mode allows using the pressure differential for the generation of the interrupt keeping the output pressure registers PRESS_OUT (
PRESS_OUT_L (29h) , PRESS_OUT_H (2Ah) ) without comparing REF_P. If the
AUTOREFP bit is set to '1', the measured output pressure is used as the reference in the
register REF_P ( REF_P_L (15h) , REF_P_H (16h) ) for interrupt generation with following:
– P_DIFF_IN = measured pressure - REF_P
The output registers PRESS_OUT (28h, 29h and 2Ah) are not changed by REF_P and shows as follows.
– PRESS_OUT = measured pressure
After the first conversion, the AUTOREFP bit is automatically set to '0'. In order to return back to normal mode, the RESET_ARP bit has to be set to '1'
40/59 DocID030890 Rev 2
LPS22HH Register description
User-defined threshold value for pressure interrupt event (Least significant bits) (R/W)
7
THS7
THS[7:0]
6
THS6
5
THS5
4
THS4
3
THS3
2
THS2
1
THS1
0
THS0
This register contains the low part of threshold value for pressure interrupt generation.
Default value: 00h
The threshold value for pressure interrupt generation is a 15-bit unsigned right-justified value composed of
THS_P_H (0Dh) and THS_P_L (0Ch) .The value is expressed as:
THS_P (15-bit unsigned) = Desired interrupt threshold (hPa) x 16
To enable the interrupt event based on this user-defined threshold, the DIFF_EN bit in
INTERRUPT_CFG (0Bh) must be set to '1', the PHE bit or PLE bit (or both bits) in
INTERRUPT_CFG (0Bh) has to be enabled.
User-defined threshold value for pressure interrupt event (Most significant bits) (R/W)
7
-
6
THS14
5
THS13
4
THS12
3
THS11
2
THS10
1
THS9
0
THS8
THS[14:8]
This register contains the high part of threshold value for pressure interrupt generation.
.
Default value: 00h
DocID030890 Rev 2 41/59
59
Register description LPS22HH
Interface control register (R/W)
7
INT_EN_I3C
6
0
5
0
4 3 2 1 0
SDA_PU_EN SDO_PU_EN PD_DIS_INT1 I3C_DISABLE I2C_DISABLE
INT_EN_I3C
SDA_PU_EN
SDO_PU_EN
PD_DIS_INT1
I3C_DISABLE
(1)
Enable INT1 pad with MIPI I3C
SM polarized as OUT. Default value: 0
. If the INT_EN_I3C bit is set, the INT1 pad is
(0: INT1 disabled with MIPI I3C
SM
; 1: INT1 enabled with MIPI I3C
SM
)
Enable pull-up on the SDA pin. Default value: 0
(0: SDA pin pull-up disconnected; 1: SDA pin with pull-up)
Enable pull-up on the SDO pin. Default value: 0
(0: SDO pin pull-up disconnected; 1: SDO pin with pull-up)
Disable pull down on the INT1 pin. Default value: 0
(0: INT1 pin with pull-down; 1: INT1 pin pull-down disconnected)
Disable MIPI I3C
SM interface. Default value: 0
(0: MIPI I3C
SM enabled; 1: MIPI I3C
SM disabled)
I2C_DISABLE
(2)
Disable I²C interface. Default value: 0
(0: I²C enabled; 1: I²C disabled)
1. I3C_DISABLE bit disables the MIPI I3C
SM communication protocol.
2. I2C_DISABLE bit disables the I²C interface, by default both SPI and I²C interfaces are enabled.
Device Who am I
7
1
6
0
5
1
4
1
3
0
2
0
1
1
0
1
42/59 DocID030890 Rev 2
LPS22HH Register description
Control register 1 (R/W)
7
0
6
ODR2
5
ODR1
4
ODR0
3
EN_LPFP
2
LPFP_CFG
1
BDU
0
SIM
ODR[2:0]
EN_LPFP Enable low-pass filter on pressure data when Continuous mode is used.
Default value: 0
(0: Low-pass filter disabled; 1: Low-pass filter enabled)
LPFP_CFG LPFP_CFG: Low-pass configuration register. Default value: 0
.
BDU
(1)
Block data update. Default value: 0
(0: continuous update;
1: output registers not updated until MSB and LSB have been read)
SIM
Output data rate selection. Default value: 000
.
SPI Serial Interface Mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
1. To guarantee the correct behavior of BDU feature,
must be the last address read.
Table 18. Output data rate bit configurations
ODR[2:0] Temperature, Pressure
000
001
010
011
100
101
110
(1)
111
(1)
1. This option disables the low-noise mode automatically.
One-shot
1 Hz
10 Hz
25 Hz
50 Hz
75 Hz
100 Hz
200 Hz
When the ODR bits are set to '000', the device is in Power-down mode . When the device is in power-down mode, almost all internal blocks of the device are switched off to minimize power consumption. The I²C interface is still active to allow communication with the device.
The content of the configuration registers is preserved and output data registers are not updated, therefore keeping the last data sampled in memory before going into power-down mode.
If the ONE_SHOT bit in
CTRL_REG2 (11h) is set to '1',
One-shot mode is triggered and a new acquisition starts when it is required. Enabling this mode is possible only if the device was previously in power-down mode (ODR bits set to '000'). Once the acquisition is completed and the output registers updated, the device automatically enters in power-down mode. ONE_SHOT bit self-clears itself.
DocID030890 Rev 2 43/59
59
Register description LPS22HH
When the ODR bits are set to a value different than '000', the device is in Continuous mode and automatically acquires a set of data (pressure and temperature) at the frequency selected through the ODR[2:0] bits.
Once the additional low-pass filter has been enabled through the EN_LPFP bit, it is possible to configure the device bandwidth acting on the LPFP_CFG bit. See
filter configurations.
EN_LPFP
0
1
1
Table 19. Low-pass filter configurations
LPFP_CFG Additional low-pass filter status x
0
1
Disabled
Enabled
Enabled
Device bandwidth
ODR/2
ODR/9
ODR/20
The BDU bit is used to inhibit the update of the output registers until both upper and lower
(and XLOW) register parts are read. In default mode (BDU = ‘0’) the output register values are updated continuously. If for any reason it is not sure to read faster than the output data rate, it is recommended to set the BDU bit to ‘1’. In this way, the content of the output registers is not updated until MSB, LSB and XLSB have been read which avoids reading values related to different sample times.
44/59 DocID030890 Rev 2
LPS22HH Register description
Control register 2 (R/W)
7
BOOT
6
INT_H_L
5
PP_OD
4
IF_ADD_INC
3
0
2 1 0
SWRESET LOW_NOISE_EN ONE_SHOT
BOOT
INT_H_L
PP_OD
IF_ADD_INC
SWRESET
Reboots memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
Interrupt active-high, active-low. Default value: 0
(0: active high; 1: active low)
Push-pull/open-drain selection on interrupt pad. Default value: 0
(0: push-pull; 1: open-drain)
Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI). Default value: 1
(0: disable; 1: enable)
Software reset. Default value: 0
(0: normal mode; 1: software reset).
The bit is self-cleared when the reset is completed.
LOW_NOISE_EN Enables low noise (used only if ODR is lower than 100 Hz). Default value: 0
(0: low-current mode; 1: low-noise mode)
ONE_SHOT Enables one-shot. Default value: 0
(0: idle mode; 1: a new dataset is acquired)
The BOOT bit is used to refresh the content of the internal registers stored in the Flash memory block. At device power-up, the content of the Flash memory block is transferred to the internal registers related to the trimming functions to allow correct behavior of the device itself. If for any reason the content of the trimming registers is modified, it is sufficient to use this bit to restore the correct values. When the BOOT bit is set to '1', the content of the internal Flash is copied into the corresponding internal registers and is used to calibrate the device. These values are factory trimmed and they are different for every device. They allow the correct behavior of the device and normally they should not be changed. At the end of the boot process, the BOOT bit is set again to '0' by hardware. The BOOT bit takes effect immediately after it is set to 1.
INT_H_L selects an interrupt active-high/low value.
PP_OD selects push-pull/open-drain on the interrupt pad.
The IF_ADD_INC bit enables the address to be automatically incremented during a multiple byte access with a serial interface (SPI or I²C).
The SWRESET bit resets the volatile registers to default value ‘0’. It returns to ‘0’ by hardware.
DocID030890 Rev 2 45/59
59
Register description LPS22HH
LOW_NOISE_EN is disabled by default and must be changed when the device is in powerdown mode. It enables low-noise mode but can be used when the ODR is lower than
100 Hz. If ODR = 100 Hz or ODR = 200 Hz, this option is automatically switched off and the value of the low-noise enable bit is ignored.
LOW_NOISE_EN mode is enabled to have less RMS noise and the best performance is achieved with LOW_NOISE_EN set to 1 and filter at ODR/20. Depending on the application, the LOW_NOISE_EN bit can be enabled (low-noise mode) or disabled (low-current mode) to have less RMS noise or less power consumption (refer to the following table).
Mode
Low noise
Low current
Table 20. RMS noise and power consumption
Additional low-pass filter status
Device bandwidth RMS noise [Pa]
Supply current
@ ODR = 1 Hz [ μ A]
Disabled
Enabled
Enabled
Disabled
Enabled
Enabled
ODR/9
ODR/20
ODR/9
ODR/20
1.7
0.9
0.65
4.5
2.6
1.7
4
4
4
12
12
12
The ONE_SHOT bit is used to start a new conversion when the ODR[2:0] bits in
CTRL_REG1 (10h) are set to '000'. Writing a '1' in ONE_SHOT triggers a single
measurement of pressure and temperature. Once the measurement is done, the
ONE_SHOT bit will self-clear, the new data are available in the output registers, and the
bits are updated.
46/59 DocID030890 Rev 2
LPS22HH Register description
Control register 3 - INT_DRDY pin control register (R/W)
7
0
6
0
5 4 3
INT_F_FULL INT_F_WTM INT_F_OVR
2
DRDY
1
INT_S1
0
INT_S0
INT_F_FULL FIFO full flag on INT_DRDY pin. Default value: 0
(0: FIFO empty; 1: FIFO full - 128 unread samples)
INT_F_WTM FIFO threshold (watermark) status on INT_DRDY pin. Default value: 0
(0: FIFO is lower than FTH level; 1: FIFO is equal to or higher than FTH level)
INT_F_OVR FIFO overrun status on INT_DRDY pin. Default value: 0
(0: not overwritten; 1: at least one sample in the FIFO has been overwritten)
DRDY Data-ready signal on INT_DRDY pin. Default value: 0
(0: disable; 1: enable)
INT_S[1:0] Data signal on INT_DRDY pin control bits. Default value: 00
Refer to
.
INT_S1 INT_S0
0
0
1
1
0
1
0
1
Table 21. Interrupt configurations
INT_DRDY pin configuration
Data signal (in order of priority: DRDY or INT_F_WTM or INT_F_OVR or
INT_F_FULL)
Pressure high (P_high)
Pressure low (P_low)
Pressure low OR high
Figure 25. Interrupt events on INT_DRDY pin dZ>ͺZ'ϯ;ΛϭϮŚͿ
EĞǁĚĂƚĂƐĞƚŝƐĂǀĂŝůĂďůĞ
&/&KdŚƌĞƐŚŽůĚ;tĂƚĞƌŵĂƌŬͿ
&/&KKǀĞƌƌƵŶ
&/&K&Ƶůů
WƌĞƐƐƵƌĞŚŝŐŚĞƌƚŚĂŶƚŚƌĞƐŚŽůĚ
WƌĞƐƐƵƌĞůŽǁĞƌƚŚĂŶƚŚƌĞƐŚŽůĚ
/Edͺ^ϭ͗Ϭ
ϬϬ
Ϭϭ ϭϬ ϭϭ
/EdͺZzƉŝŶ
DocID030890 Rev 2 47/59
59
Register description
9.9 FIFO_CTRL (13h)
FIFO control register (R/W)
LPS22HH
7
0
6
0
5
0
4
0
3 2 1
STOP_ON_WTM TRIG_MODES F_MODE1
0
F_MODE0
STOP_ON_WTM Stop-on-FIFO watermark. Enables FIFO watermark level use. Default value: 0
(0: disable; 1: enable)
TRIG_MODES
F_MODE[1:0]
Enables triggered FIFO modes. Default value: 0
Selects triggered FIFO modes. Default value: 00
Refer to
TRIG_MODES
0
1 x
0
1
1
Table 22. FIFO mode selection
F_MODE[1:]
00
01
1x
01
10
11
Mode
Bypass
FIFO mode
Continuous (Dynamic-Stream)
Bypass-to-FIFO
Bypass-to-Continuous (Dynamic-Stream)
Continuous (Dynamic-Stream)-to-FIFO
The STOP_ON_WTM bit enables the use of the FIFO watermark level: when the number of samples in FIFO is equal to the watermark level (set using the WTM[4:0] bits in
) then FIFO is full.
The TRIG_MODES bit enables the triggered FIFO modes.
The F_MODE[1:0] bits select one of the FIFO modes, as described in
Output data (pressure and temperature) are read through FIFO_DATA_OUT_PRESS_XL
,
,
and
FIFO_DATA_OUT_TEMP_H (7Ch) ; both single
read and multiple read operations can be used.
48/59 DocID030890 Rev 2
LPS22HH Register description
FIFO threshold setting register (R/W)
7
0
WTM[6:0]
6
WTM6
5
WTM5
4
WTM4
3
WTM3
2
WTM2
1
WTM1
FIFO threshold. Watermark level setting. Default value: 0000000
0
WTM0
Reference pressure LSB data (R)
7
REFL7
REFL[7:0]
6
REFL6
5
REFL5
4
REFL4
3
REFL3
2
REFL2
1
REFL1
This register contains the low part of the reference pressure value.
Default value: 00000000
0
REFL0
The Reference pressure value is 16-bit data and it is composed of REF_P_H (16h) and
. The value is expressed as 2’s complement.
The reference pressure value is stored and used when the AUTOZERO or AUTOREFP
function is enabled. Please refer to the INTERRUPT_CFG (0Bh) register description.
Reference pressure MSB data (R)
7
REFL15
6
REFL14
5
REFL13
4
REFL12
3
REFL11
2
REFL10
1
REFL9
REFL[15:8] This register contains the high part of the reference pressure value.
Default value: 00000000
0
REFL8
DocID030890 Rev 2 49/59
59
Register description LPS22HH
Pressure offset (LSB data)
7
RPDS7
RPDS[7:0]
6
RPDS6
5
RPDS5
4
RPDS4
3
RPDS3
2
RPDS2
This register contains the low part of the pressure offset value.
Default value: 00000000
1
RPDS1
0
RPDS0
The pressure offset value is 16-bit data that can be used to implement one-point calibration
(OPC) after soldering. This value is composed of RPDS_H (19h) and RPDS_L (18h)
. The value is expressed as 2’s complement.
Pressure offset (MSB data)
7
RPDS15
6
RPDS14
5
RPDS13
4
RPDS12
3
RPDS11
2
RPDS10
RPDS[15:8] This register contains the high part of the pressure offset value.
Refer to
RPDS_L (18h) . Default value: 00000000
1
RPDS9
0
RPDS8
Interrupt source (read only)
7
BOOT_ON
BOOT_ON
6
0
IA
PL
PH
5
0
4
0
3
0
2
IA
Indication of Boot phase.
(0: Boot phase has ended;
1: Boot phase is running).
Interrupt active.
(0: no interrupt has been generated;
1: one or more interrupt events have been generated).
Differential pressure Low.
(0: no interrupt has been generated;
1: low differential pressure event has occurred).
Differential pressure High.
(0: no interrupt has been generated;
1: high differential pressure event has occurred).
1
PL
0
PH
50/59 DocID030890 Rev 2
LPS22HH Register description
FIFO status register (read only)
7
FSS7
FSS[7:0]
6
FSS6
5
FSS5
4
FSS4
3
FSS3
2
FSS2
1
FSS1
FIFO stored data level, number of unread samples stored in FIFO.
(00000000: FIFO empty; 10000000: FIFO full, 128 unread samples)
0
FSS0
FIFO status register (read only)
7 6 5
FIFO_WTM_IA FIFO_OVR_IA FIFO_FULL_IA
FIFO_WTM_IA
FIFO_OVR_IA
FIFO_FULL_IA
4
-
3
-
2
-
1
-
FIFO threshold (watermark) status. Default value: 0
(0: FIFO filling is lower than treshold level;
1: FIFO filling is equal or higher than treshold level).
FIFO overrun status. Default value: 0
(0: FIFO is not completely full;
1: FIFO is full and at least one sample in the FIFO has been overwritten).
FIFO full status. Default value: 0
(0: FIFO is not completely filled;
1: FIFO is completely filled, no samples overwritten)
0
-
Status register (read only)
7
--
6
--
5
T_OR
4
P_OR
3
--
2
--
T_OR Temperature data overrun.
(0: no overrun has occurred;
1: a new data for temperature has overwritten the previous data)
P_OR Pressure data overrun.
(0: no overrun has occurred;
1: new data for pressure has overwritten the previous data)
T_DA Temperature data available.
(0: new data for temperature is not yet available;
1: a new temperature data is generated)
P_DA Pressure data available.
(0: new data for pressure is not yet available;
1: a new pressure data is generated)
1
T_DA
This register is updated every ODR cycle.
DocID030890 Rev 2
0
P_DA
51/59
59
Register description LPS22HH
Pressure output value LSB data (read only)
7
POUT7
POUT[7:0]
6
POUT6
5
POUT5
4
POUT4
3
POUT3
2
POUT2
This register contains the low part of the pressure output value.
1
POUT1
0
POUT0
The pressure output value is a 24-bit data that contains the measured pressure. It is
composed of PRESS_OUT_H (2Ah) , PRESS_OUT_L (29h) and PRESS_OUT_XL (28h) .
The value is expressed as 2’s complement.
The output pressure register PRESS_OUT is provided as the difference between the measured pressure and the content of the register RPDS (18h, 19h)*.
Please refer to
Section 4.4: Interpreting pressure readings for additional info.
*DIFF_EN = '0', AUTOZERO = '0', AUTOREFP = '0'
Pressure output value middle data (read only)
7
POUT15
6
POUT14
5
POUT13
4
POUT12
3
POUT11
2
POUT10
POUT[15:8]
This register contains the mid part of the pressure output value.
1
POUT9
0
POUT8
Pressure output value MSB data (read only)
7
POUT23
6
POUT22
5
POUT21
4
POUT20
3
POUT19
2
POUT18
POUT[23:16]
This register contains the high part of the pressure output value.
Refer to
1
POUT17
0
POUT16
52/59 DocID030890 Rev 2
LPS22HH Register description
Temperature output value LSB data (read only)
7
TOUT7
TOUT[7:0]
6
TOUT6
5
TOUT5
4
TOUT4
3
TOUT3
2
TOUT2
1
TOUT1
This register contains the low part of the temperature output value.
0
TOUT0
The temperature output value is 16-bit data that contains the measured temperature. It is
composed of TEMP_OUT_H (2Ch) , and TEMP_OUT_L (2Bh) . The value is expressed as
2’s complement.
Temperature output value MSB data (read only)
7
TOUT15
6
TOUT14
5
TOUT13
4
TOUT12
3
TOUT11
2
TOUT10
1
TOUT9
TOUT[15:8] This register contains the high part of the temperature output value.
0
TOUT8
FIFO pressure output LSB data (read only)
7
FIFO_P7
FIFO_P[7:0]
6
FIFO_P6
5
FIFO_P5
4
FIFO_P4
3
FIFO_P3
Pressure LSB data in FIFO buffer
2
FIFO_P2
1
FIFO_P1
0
FIFO_P0
FIFO pressure output middle data (read only)
7
FIFO_P15
FIFO_P[15:8]
6
FIFO_P14
5
FIFO_P13
4
FIFO_P12
3
FIFO_P11
Pressure middle data in FIFO buffer
2
FIFO_P10
1
FIFO_P9
0
FIFO_P8
DocID030890 Rev 2 53/59
59
Register description LPS22HH
FIFO pressure output MSB data (read only)
7
FIFO_P23
FIFO_P[23:16]
6
FIFO_P22
5
FIFO_P21
4
FIFO_P20
3
FIFO_P19
Pressure middle data in FIFO buffer
2
FIFO_P18
1
FIFO_P17
0
FIFO_P16
FIFO temperature output LSB data (read only)
7
FIFO_T7
FIFO_T[7:0]
6
FIFO_T6
5
FIFO_T5
4
FIFO_T4
3
FIFO_T3
Temperature LSB data in FIFO buffer
2
FIFO_T2
1
FIFO_T1
0
FIFO_T0
FIFO temperature output MSB data (read only)
7
FIFO_T15
FIFO_T[15:8]
6
FIFO_T14
5
FIFO_T13
4
FIFO_T12
3
FIFO_T11
Temperature MSB data in FIFO buffer
2
FIFO_T10
1
FIFO_T9
0
FIFO_T8
54/59 DocID030890 Rev 2
LPS22HH Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
10.1 HLGA-10L package information
Figure 26. HLGA-10L (2.0 x 2.0 x 0.73 mm typ.) package outline and mechanical dimensions
3LQ
/
%
6HQVLQJDUHD
+
[
3LQ
$
&
[
& $ %
&
/ H
,7(0
Q J W K > / @
: L G W K
+ H L J K W
> : @
> + @
'LPHQVLRQVDUHLQPLOOLPHWHUXQOHVVRWKHUZLVHVSHFLILHG
*HQHUDO7ROHUDQFHLVPPXQOHVVRWKHUZLVHVSHFLILHG
287(5',0(16,216
',0(16,21>PP@
P D [
72/(5$1&(>PP@
'0B
DocID030890 Rev 2 55/59
59
Package information
10.2 HLGA-10L packing information
Figure 27. Carrier tape information for HLGA-10L package
6((127(
6((127( 0,1
50$;
$ $
LPS22HH
%
6((127(
%R
6(&7,21%%
.R
'(7$,/'
6&$/(
6&$/(
5
$R
6(&7,21$$
',0
6&$/(
$R
%R
.R
127(6
6352&.(7+2/(3,7&+&808/$7,9(72/(5$1&(
32&.(7326,7,215(/$7,9(726352&.(7+2/(0($685('$6758(326,7,212)32&.(7127
32&.(7+2/(
$R$1'%R$5(0($685('21$3/$1($7$',67$1&(5$%29(7+(%277202)7+(32&.(7
%
Figure 28. HLGA-10L package orientation in carrier tape
56/59 DocID030890 Rev 2
LPS22HH
$
Package information
Figure 29. Reel information for carrier tape of HLGA-10L package
7
PPPLQ
$FFHVVKROHDW
VORWORFDWLRQ
%
&
' 1
)XOOUDGLXV
*PHDVXUHGDWKXE
7DSHVORW
LQFRUHIRU
WDSHVWDUW
PPPLQZLGWK
Table 23. Reel dimensions for carrier tape of HLGA-10L package
Reel dimensions (mm)
A (max)
B (min)
C
D (min)
N (min)
G
T (max)
330
1.5
13 ±0.25
20.2
60
12.4 +2/-0
18.4
DocID030890 Rev 2 57/59
59
Revision history LPS22HH
Date
22-Aug-2018
04-Feb-2019
Revision
Table 24. Document revision history
Changes
1
2
Initial release
Updated description of SETDASA in Table 16: MIPI I3C
Updated text concerning BOOT bit in CTRL_REG2 (11h)
Updated bit 7 in INT_SOURCE (24h)
Updated Figure 27: Carrier tape information for HLGA-10L package
58/59 DocID030890 Rev 2
LPS22HH
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DocID030890 Rev 2 59/59
59
Download
Public link updated
The public link to your chat has been updated. You may view and manage your chat links after registration here.
Document public link
Advertisement