STMicroelectronics LPS33HW Datasheet

. Programmable FIFO threshold status,

FIFO overrun events and the number of unread samples stored are available in the

CTRL_REG3 (12h) register.

INT_DRDY pad using the

( FIFO_STATUS (26h) (FSS5:0)) is greater than or equal to WTM[4:0] in

(FTH_FIFO) goes to '1' when the number of unread samples

FIFO_CTRL (14h) . If

FIFO_CTRL (14h) (WTM4:0) is equal to 0,

FIFO_STATUS (26h) (FTH_FIFO) goes to '0'.

(OVRN) is equal to '1' if a FIFO slot is overwritten.

(FSS5:0) contains stored data levels of unread samples; when

FSS[5:0] is equal to '000000' FIFO is empty, when FSS[5:0] is equal to '100000' FIFO is full and the unread samples are 32.

To guarantee the switching into and out of FIFO mode, discard the first sample acquired.

In Bypass mode (

(FMODE2:0)=000), the FIFO is not operational and it remains empty.

Bypass mode is also used to reset the FIFO when in FIFO mode.

As described in the next figure, for each channel only the first address is used. When new data is available, the older data is overwritten.

Figure 6. Bypass mode

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LPS33HW FIFO

In FIFO mode (

(FMODE2:0) = 001) data from the output PRESS_OUT_H

(2Ah) , PRESS_OUT_L (29h) ,

TEMP_OUT_L (2Bh) are stored in the FIFO until it is overwritten.

and

TEMP_OUT_H (2Ch) ,

To reset FIFO content, Bypass mode the value '000' must be written in

FIFO_CTRL

(14h)

(FMODE2:0). After this reset command it is possible to restart FIFO mode writing the value '001' in

FIFO_CTRL (14h) (FMODE2:0).

FIFO buffer memorizes 32 levels of data but the depth of the FIFO can be resized by setting the

CTRL_REG2 (11h) (STOP_ON_FTH) bit. If the STOP_ON_FTH bit is set to '1', FIFO

depth is limited to

FIFO_CTRL (14h) (WTM4:0) + 1 data.

A FIFO threshold interrupt can be enabled (F_OVR bit in CTRL_REG3 (12h)

in order to be raised when the FIFO is filled to the level specified by the WTM4:0 bits of

FIFO_CTRL

(14h)

. When a FIFO threshold interrupt occurs, the first data has been overwritten and the

FIFO stops collecting data from the input pressure and temperature.

Figure 7. FIFO mode

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FIFO LPS33HW

Stream mode ( FIFO_CTRL (14h) (FMODE2:0) = 010) provides continuous FIFO update: as

new data arrive, the older is discarded.

Once the entire FIFO has been read, the last data read still remains in the FIFO and hence once a new sample is acquired, the

FIFO_STATUS (26h) (FSS5:0) value rises from 0 to 2.

An overrun interrupt can be enabled,

CTRL_REG3 (12h) (F_OVR) = '1', in order to inform

when the FIFO is full and eventually read its content all at once. If an overrun occurs, the oldest sample in FIFO is overwritten, so if the FIFO was empty, the lost sample has already been read.

Figure 8. Stream mode

In the latter case reading all FIFO content before an overrun interrupt has occurred, the first data read is equal to the last already read in the previous burst, so the number of new data available in FIFO depends on the previous reading.

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LPS33HW FIFO

In Dynamic-Stream mode ( FIFO_CTRL (14h)

(FMODE2:0) = 110) after emptying the FIFO, the first new sample that arrives becomes the first to be read in a subsequent read burst. In this way the number of new data available in FIFO does not depend on the previous reading.

In Dynamic-Stream mode

FIFO_STATUS (26h) (FSS5:0) is the number of new pressure and

temperature samples available in the FIFO buffer.

Stream Mode is intended to be used to read all 32 samples of FIFO within an ODR after receiving an overrun signal.

Dynamic-Stream is intended to be used to read

Also, a FIFO threshold interrupt on the INT_DRDY pad through CTRL_REG3 (12h) (F_FTH)

(FSS5:0) samples when it is not possible to guarantee reading data within an ODR.

can be enabled in order to read data from the FIFO and leave free memory slots for incoming data.

Figure 9. Dynamic-Stream mode

DocID030522 Rev 1 19/50

FIFO LPS33HW

In Stream-to-FIFO mode (

FIFO_CTRL (14h) (FMODE2:0) = 011), FIFO behavior changes

according to the

INT_SOURCE (25h) (IA) bit. When INT_SOURCE (25h) (IA) bit is equal to

'1', FIFO operates in FIFO mode. When the INT_SOURCE (25h) (IA) bit is equal to '0', FIFO

operates in Stream mode.

An interrupt generator can be set to the desired configuration through

INTERRUPT_CFG

INTERRUPT_CFG (0Bh) (LIR) bit should be set to '1' in order to have latched interrupt.

The

Figure 10. Stream-to-FIFO mode

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LPS33HW FIFO

In Bypass-to-Stream mode (

FIFO_CTRL (14h) (FMODE2:0) = '100'), data measurement

storage inside FIFO operates in Stream mode when INT_SOURCE (25h) (IA) is equal to

'1',otherwise FIFO content is reset (Bypass mode).

An interrupt generator can be set to the desired configuration through

INTERRUPT_CFG

INTERRUPT_CFG (0Bh) (LIR) bit should be set to '1' in order to have latched interrupt.

The

Figure 11. Bypass-to-Stream mode

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FIFO LPS33HW

In Bypass-to-FIFO mode (

(FMODE2:0) = '111'), data measurement storage inside FIFO operates in FIFO mode when

INT_SOURCE (25h)

(IA) is equal to '1', otherwise FIFO content is reset (Bypass mode).

An interrupt generator can be set to the desired configuration through

INTERRUPT_CFG

INTERRUPT_CFG (0Bh) (LIR) bit should be set to '1' in order to have latched interrupt.

The

Figure 12. Bypass-to-FIFO mode

4.8 Retrieving data from FIFO

FIFO data is read from PRESS_OUT_H (2Ah) , PRESS_OUT_L (29h) ,

PRESS_OUT_XL

(28h)

and

TEMP_OUT_H (2Ch) , TEMP_OUT_L (2Bh) .

Each time data is read from the FIFO, the oldest data are placed in the

PRESS_OUT_H

(2Ah) , PRESS_OUT_L (29h) ,

PRESS_OUT_XL (28h) ,

TEMP_OUT_H (2Ch)

and

TEMP_OUT_L (2Bh) registers and both single-read and read-burst operations can be used.

The reading address is automatically updated by the device and it rolls back to 28h when register 2Ch is reached. In order to read all FIFO levels in a multiple byte reading, 160 bytes

(5 output registers by 32 levels) must be read.

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LPS33HW Application hints

9''

Figure 13. LPS33HW electrical connections (top view)

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The device power supply must be provided through the VDD line; a power supply decoupling capacitor C1 (100 nF) must be placed as near as possible to the supply pads of the device. Depending on the application, an additional capacitor of 4.7 μ F could be placed on the VDD line.

The functionality of the device and the measured data outputs are selectable and accessible through the I²C/SPI interface. When using the I 2

C, CS must be tied to Vdd_IO.

All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to

Figure 13 ). It is possible to remove VDD while maintaining

Vdd_IO without blocking the communication bus, in this condition the measurement chain is powered off.

The CCLGA package is compliant with the ECOPACK ® standard and it is qualified for soldering heat resistance according to JEDEC J-STD-020.

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Digital interfaces LPS33HW

The registers embedded in the LPS33HW may be accessed through both the I²C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode.

The serial interfaces are mapped onto the same pads. To select/exploit the I²C interface, the

CS line must be tied high (i.e. connected to Vdd_IO).

Pin name

SCL/SPC

SDA

SDI

SDI/SDO

SDO

SAO

Table 9. Serial interface pin description

Pin description

SPI enable

I²C/SPI mode selection

(1: SPI idle mode / I

C communication enabled;

0: SPI communication mode / I

C disabled)

I²C serial clock (SCL)

SPI serial port clock (SPC)

I²C serial data (SDA)

4-wire SPI serial data input (SDI)

3-wire serial data input /output (SDI/SDO)

SPI serial data output (SDO)

I²C less significant bit of the device address (SA0)

6.2 I

C serial interface (CS = High)

The LPS33HW I²C is a bus slave. The I²C is employed to write data into registers whose content can also be read back.

The relevant I²C terminology is given in

Table 10.

Term

Table 10. I

C terminology

Description

Transmitter The device which sends data to the bus

Receiver The device which receives data from the bus

Master The device which initiates a transfer, generates clock signals and terminates a transfer

Slave The device addressed by the master

There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines have to be connected to Vdd_IO through pull-up resistors.

The I²C interface is compliant with fast mode (400 kHz) I²C standards as well as with the normal mode.

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LPS33HW Digital interfaces

6.2.1 I

C operation

The transaction on the bus is started through a START (ST) signal. A start condition is defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next data byte transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.

The slave address (SAD) associated to the LPS33HW is 101110xb. The SDO / SA0 pad can be used to modify the less significant bit of the device address. If the SA0 pad is connected to voltage supply, LSb is ‘1’ (address 1011101b), otherwise if the SA0 pad is connected to ground, the LSb value is ‘0’ (address 1011100b). This solution permits to connect and address two different LPS33HW devices to the same I²C lines.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.

The I 2 C embedded inside the ASIC behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK), an 8-bit sub-address will be transmitted (SUB): the

7 LSB represent the actual register address while the MSB has no meaning. The

IF_ADD_INC bit in

CTRL_REG2 (11h) enables sub-address auto increment (IF_ADD_INC

is '1' by default), so if IF_ADD_INC = '1' the SUB (sub-address) will be automatically increased to allow multiple data read/write.

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged.

Table 11 explains how the

SAD+read/write bit pattern is composed, listing all the possible configurations.

Command

Read

Write

Read

Write

Table 11. SAD+Read/Write patterns

SAD[6:1] SAD[0] = SA0 R/W

101110

SAD+R/W

10111001 (B9h)

10111000 (B8h)

10111011 (BBh)

10111010 (BAh)

Master

Slave

Table 12. Transfer when master is writing one byte to slave

ST SAD + W SUB DATA

SAK SAK SAK

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Digital interfaces LPS33HW

Master

Slave

Table 13. Transfer when master is writing multiple bytes to slave

SAD + W SUB DATA DATA

SAK SAK SAK SAK

Master

Table 14. Transfer when master is receiving (reading) one byte of data from slave

ST SAD + W SUB SR SAD + R NMAK

Slave SAK SAK SAK DATA

Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP

Slave SAK SAK SAK DATA DATA DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit

(MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other functions, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be kept HIGH by the slave. The master can then abort the transfer. A LOW-to-HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In order to read multiple bytes incrementing the register address, it is necessary to assert the most significant bit of the sub-address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of the first register to be read.

In the presented communication format MAK is Master acknowledge and NMAK is no master acknowledge.

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LPS33HW Digital interfaces

6.3 SPI interface

The LPS33HW SPI is a bus slave. The SPI allows writing to and reading from the registers of the device.

The serial interface interacts with the application using 4 wires: CS , SPC , SDI and SDO .

Figure 14. Read and write protocol

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CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and returns to high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and

SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .

Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in the case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23,...) starts at the last falling edge of SPC just before the rising edge of CS .

bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip will drive SDO at the start of bit 8.

bit 1-7 : address AD(6:0). This is the address field of the indexed register.

bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

In multiple read/write commands further blocks of 8 clock periods are added. When the

IF_ADD_INC bit is 0, the address used to read/write data remains the same for every block.

When the IF_ADD_INC bit is 1, the address used to read/write data is incremented at every block.

The function and the behavior of SDI and SDO remain unchanged.

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Digital interfaces LPS33HW

Figure 15. SPI read protocol

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The SPI read command is performed with 16 clock pulses. The multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : READ bit. The value is 1.

bit 1-7 : address AD(6:0). This is the address field of the indexed register.

bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

bit 16-...

: data DO(...-8). Further data in multiple byte reads.

Figure 16. Multiple byte SPI read protocol (2-byte example)

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28/50 DocID030522 Rev 1

LPS33HW Digital interfaces

Figure 17. SPI write protocol

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The SPI write command is performed with 16 clock pulses. The multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : WRITE bit. The value is 0.

bit 1-7 : address AD(6:0). This is the address field of the indexed register.

bit 8-15 : data DI(7:0) (write mode). This is the data that is written in the device (MSb first).

bit 16-...

: data DI(...-8). Further data in multiple byte writes.

Figure 18. Multiple byte SPI write protocol (2-byte example)

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Digital interfaces

6.3.3 SPI read in 3-wire mode

LPS33HW

A 3-wire mode is entered by setting bit SIM to ‘1’ (SPI serial interface mode selection) in

CTRL_REG1 (10h) .

Figure 19. SPI read protocol in 3-wire mode

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The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.

bit 1-7 : address AD(6:0). This is the address field of the indexed register.

bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

A multiple read command is also available in 3-wire mode.

30/50 DocID030522 Rev 1

LPS33HW Register mapping

Table 16

provides a quick overview of the 8-bit registers embedded in the device.

Name

Table 16. Registers address map

Type

Register

Address

Default

Function and comment

Hex Binary

Reserved

INTERRUPT_CFG

THS_P_L

R/W

THS_P_H R/W

Reserved -

WHO_AM_I

CTRL_REG1

CTRL_REG2

CTRL_REG3

R/W

Reserved -

FIFO_CTRL R/W

REF_P_XL

REF_P_L

R/W

REF_P_H

RPDS_L

RPDS_H

RES_CONF

Reserved

INT_SOURCE

FIFO_STATUS

STATUS

R/W

PRESS_OUT_XL

PRESS_OUT_L

PRESS_OUT_H

TEMP_OUT_L

TEMP_OUT_H

Reserved

LPFP_RES

00000000

10110001

00000000

00010000

00000000

Output

00 - 0A

1B - 24

2D - 32

Reserved

Interrupt register

Pressure threshold registers

Reserved

Who am I

Control registers

Reserved

FIFO configuration register

Reference pressure registers

Pressure offset registers

Resolution register

Reserved

Interrupt register

FIFO status register

Status register

Pressure output registers

Temperature output registers

Reserved

Filter reset register

DocID030522 Rev 1 31/50

Register mapping LPS33HW

Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.

To guarantee the proper behavior of the device, all register addresses not listed in the above table must not be accessed and the content stored in those registers must not be changed.

The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.

32/50 DocID030522 Rev 1

LPS33HW Register description

The device contains a set of registers which are used to control its behavior and to retrieve pressure and temperature data. The register address, made up of 7 bits, is used to identify them and to read/write the data through the serial interface.

AUTORIFP

Interrupt configuration

RESET_ARP

AUTOZERO

RESET_AZ

DIFF_EN

LIR

PLE

PHE

AUTORIFP AUTORIFP: Enable AutoRifP function. Default value: 0

(0: normal mode; 1: AutoRifP enabled)

RESET_ARP Reset AutoRifP function. Default value: 0

(0: normal mode; 1: reset AutoRifP function)

AUTOZERO Enable Autozero. Default value: 0

(0: normal mode; 1: Autozero enabled)

RESET_AZ Reset Autozero function. Default value: 0

(0: normal mode; 1: reset Autozero function)

DIFF_EN Enable interrupt generation. Default value: 0

(0: interrupt generation disabled; 1: interrupt generation enabled)

LIR

PLE

PHE

Latch interrupt request to the INT_SOURCE register. Default value: 0

(0: interrupt request not latched; 1: interrupt request latched)

Enable interrupt generation on differential pressure low event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured differential pressure value lower than preset threshold)

Enable interrupt generation on differential pressure high event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured differential pressure value higher than preset threshold)

To generate an interrupt event based on a user-defined threshold, the DIFF_EN bit must be

set to '1' and the threshold values stored in THS_P_L (0Ch)

and

THS_P_H (0Dh)

When DIFF_EN = '1', the PHE bit or PLE bit (or both bits) has to be enabled. The PHE and

PLE bits enable the interrupt generation on the positive or negative event respectively.

When DIFF_EN is enabled and AUTOZERO or AUTORIFP is enabled, the defined pressure threshold values in THS_P (0Ch, 0Dh) is compared with:

P_DIFF_IN = measured pressure - pressure reference

The value of the pressure reference is assigned depending on the AUTOZERO and

AUTORIFP modes given in the next two paragraphs.

DocID030522 Rev 1 33/50

Register description LPS33HW

Figure 20. “Threshold-based” interrupt event

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If the AUTOZERO bit is set to '1', the measured pressure is used as a reference on the register REF_P (15h, 16h and 17h). From that point on, the output pressure registers

PRESS_OUT (

PRESS_OUT_H (2Ah) , PRESS_OUT_L (29h) and

register REF_P (15h, 16h and 17h). The output registers PRESS_OUT ( PRESS_OUT_H

) are updated and the same value is also used for the interrupt generation:

– PRESS_OUT = measured pressure - REF_P

After the first conversion the AUTOZERO bit is automatically set to '0'. To return back to normal mode, the RESET_AZ bit has to be set to '1'. This resets also the content of the

REF_P registers.

If the AUTORIFP bit is set to '1', the measured pressure is used as a reference on the

(2Ah) , PRESS_OUT_L (29h) and

PRESS_OUT_XL (28h) ) show the difference between the

measured pressure and the content of the RPDS registers (18h and 19h):

– PRESS_OUT = measured pressure - RPDS*256

After the first conversion the AUTORIFP bit is automatically set to '0'. To return back to normal mode, the RESET_ARP bit has to be set to '1'.

THS7

Least significant bits of the threshold value for pressure interrupt generation.

THS6

THS5

THS4

THS3

THS2

THS1

THS0

THS[7:0] This register contains the low part of threshold value for pressure interrupt generation.

The threshold value for pressure interrupt generation is a 16-bit unsigned right-justified value composed of

THS_P_H (0Dh) and

THS_P_L (0Ch) . The value is expressed as:

Interrupt threshold (hPA) = (THS_P) / 16.

To enable the interrupt event based on this user-defined threshold, the DIFF_EN bit in

INTERRUPT_CFG (0Bh) must be set to '1', the PHE bit or PLE bit (or both bits) in

INTERRUPT_CFG (0Bh) has to be enabled.

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LPS33HW Register description

THS15

Most significant bits of the threshold value for pressure interrupt generation.

THS14

THS13

THS12

THS11

THS10

THS9

THS[15:8]

THS8

This register contains the high part of threshold value for pressure interrupt generation. Refer to

THS_P_L (0Ch) .

Device Who am I

Control register 1

0 (1)

ODR2

ODR1

ODR0

1. This bit must be set to ‘0’ for proper operation of the device.

EN_LPFP

LPFP_CFG

BDU

SIM

ODR[2:0]

EN_LPFP

Output data rate selection. Default value: 000

Refer to

Table 17

Enable low-pass filter on pressure data. Default value: 0

(0: Low-pass filter disabled; 1: Low-pass filter enabled)

LPFP_CFG Low-pass configuration register. Default value: 0

Refer to

Table 18

BDU

(1)

Block data update. Default value: 0

(0: continuous update;

1: output registers not updated until MSB and LSB have been read)

SIM SPI Serial Interface Mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface)

1. To guarantee the correct behavior of the BDU feature, PRESS_OUT_H (2Ah)

must be the last address read.

DocID030522 Rev 1 35/50

Register description LPS33HW

ODR2

ODR1

Table 17. Output data rate bit configurations

ODR0 Pressure (Hz) Temperature (Hz)

Power-down / One-shot mode enabled

1 Hz 1 Hz

10 Hz

25 Hz

10 Hz

25 Hz

50 Hz

75 Hz

50 Hz

75 Hz

When the ODR bits are set to '000' the device is in Power-down mode . When the device is in power-down mode, almost all internal blocks of the device are switched off to minimize power consumption. The I 2 C interface is still active to allow communication with the device. The content of the configuration registers is preserved and output data registers are not updated, therefore keeping the last data sampled in memory before going into power-down mode.

If the ONE_SHOT bit in CTRL_REG2 (11h)

is set to '1', One-shot mode is triggered and a new acquisition starts when it is required. Enabling this mode is possible only if the device was previously in power-down mode (ODR bits set to '000'). Once the acquisition is completed and the output registers updated, the device automatically enters in powerdown mode. The ONE_SHOT bit self-clears itself.

When the ODR bits are set to a value different than '000', the device is in Continuous mode and automatically acquires a set of data (pressure and temperature) at the frequency selected through the ODR[2:0] bits.

Once the additional low-pass filter has been enabled through the EN_LPFP bit, it is possible to configure the device bandwidth acting on the LPFP_CFG bit. See

Table 18 for low-pass

filter configurations.

EN_LPFP

Table 18. Low-pass filter configurations

LPFP_CFG Additional low-pass filter status x

Disabled

Enabled

Device bandwidth

ODR/2

ODR/9

ODR/20

The BDU bit is used to inhibit the update of the output registers between the reading of the upper and lower register parts. In default mode (BDU = ‘0’), the lower and upper register parts are updated continuously. When the BDU is activated (BDU = ‘1’), the content of the

output registers is not updated until PRESS_OUT_H (2Ah) is read, avoiding the reading of

values related to different samples.

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LPS33HW Register description

Control register 2

BOOT

FIFO_EN

STOP_ON_FTH

IF_ADD_INC

1. This bit must be set to ‘0’ for proper operation of the device

I2C_DIS

SWRESET

(1)

ONE_SHOT

BOOT

FIFO_EN

Reboot memory content. Default value: 0

(0: normal mode;

1: reboot memory content). The bit is self-cleared when the BOOT is completed.

FIFO enable. Default value: 0

(0: disable; 1: enable)

STOP_ON_FTH Stop on FIFO threshold. Enable FIFO watermark level use. Default value: 0

(0: disable; 1: enable)

IF_ADD_INC

(1)

C or SPI). Default value: 1

(0: disable; 1: enable)

I2C_DIS Disable I

(0: I

C interface. Default value: 0

C enabled;1: I

C disabled)

SWRESET

ONE_SHOT

Software reset. Default value: 0

(0: normal mode; 1: software reset).

The bit is self-cleared when the reset is completed.

One-shot enable. Default value: 0

(0: idle mode; 1: a new dataset is acquired)

1. It is recommend to use a single-byte read (with IF_ADD_INC = 0) when output data registers are acquired without using the FIFO. If a read of the data occurs during the refresh of the output data register, it is recommended to set the BDU bit to ‘1’ in

CTRL_REG1 (10h) in order to avoid mixing data.

The BOOT bit is used to refresh the content of the internal registers stored in the Flash memory block. At device power-up the content of the Flash memory block is transferred to the internal registers related to the trimming functions to allow correct behavior of the device itself. If for any reason the content of the trimming registers is modified, it is sufficient to use this bit to restore the correct values. When the BOOT bit is set to ‘1’, the content of the internal Flash is copied inside the corresponding internal registers and is used to calibrate the device. These values are factory trimmed and they are different for every device. They allow correct behavior of the device and normally they should not be changed. At the end of the boot process the BOOT bit is set again to ‘0’ by hardware. The BOOT bit takes effect after one ODR clock cycle.

SWRESET

is the software reset bit. The following device registers ( INTERRUPT_CFG

THS_P_H (0Dh) , CTRL_REG1 (10h)

, THS_P_L (0Ch) ,

CTRL_REG2 (11h) ,

CTRL_REG3 (12h) ,

FIFO_CTRL (14h) ,

REF_P_XL (15h) , REF_P_L (16h) , REF_P_H

(17h)

) are reset to the default value if the SWRESET bit is set to '1'. The SWRESET bit returns back to '0' by hardware.

The ONE_SHOT bit is used to start a new conversion when the ODR[2,0] bits in

CTRL_REG1 (10h) are set to ‘000’. Writing a ‘1’ in ONE_SHOT triggers a single

measurement of pressure and temperature. Once the measurement is done, the

ONE_SHOT bit will self-clear, the new data are available in the output registers, and the

STATUS (27h)

bits are updated.

DocID030522 Rev 1 37/50

Register description LPS33HW

INT_H_L

Control register 3 - INT_DRDY pin control register

PP_OD

F_FSS5

F_FTH

F_OVR

DRDY

INT_S2

INT_S1

INT_H_L

PP_OD

F_FSS5

F_FTH

F_OVR

DRDY

INT_S[2:1]

Interrupt active-high/low. Default value: 0

(0: active high; 1: active low)

Push-pull/open-drain selection on interrupt pads. Default value: 0

(0: push-pull; 1: open drain)

FIFO full flag on INT_DRDY pin. Default value: 0

(0: disable; 1: enable)

FIFO threshold (watermark) status on INT_DRDY pin. Default value: 0

(0: disable; 1: enable)

FIFO overrun interrupt on INT_DRDY pin. Default value: 0

(0: disable; 1: enable)

Data-ready signal on INT_DRDY pin. Default value: 0

(0: disable; 1: enable)

Data signal on INT_DRDY pin control bits. Default value: 00

Refer to

Table 19

INT_S2

INT_S1

Table 19. Interrupt configurations

INT_DRDY pin configuration

Data signal (in order of priority: DRDY or F_FTH or F_OVR or

F_FSS5

Pressure high (P_high)

Pressure low (P_low)

Pressure low OR high

38/50 DocID030522 Rev 1

LPS33HW

Figure 21. Interrupt events on INT_DRDY pin

Register description

8.8

F_MODE2

FIFO_CTRL (14h)

FIFO control register

F_MODE1

F_MODE0

WTM4

WTM3

WTM2

F_MODE[2:0] FIFO mode selection. Default value: 000

Refer to

Table 20

and Section 4 for additional details.

WTM[4:0] FIFO watermark level selection.

WTM1

Table 20. FIFO mode selection

F_MODE2 F_MODE1 F_MODE0 FIFO mode selection

Bypass mode

FIFO mode

Stream mode

Stream-to-FIFO mode

Bypass-to-Stream mode

Reserved

Dynamic-Stream mode

Bypass-to-FIFO mode

WTM0

DocID030522 Rev 1 39/50

Register description LPS33HW

REFL7

Reference pressure (LSB data)

REFL6

REFL5

REFL4

REFL3

REFL2

REFL1

REFL0

REFL[7:0] This register contains the low part of the reference pressure value.

The reference pressure value is 24-bit data and is composed of

REF_P_H (17h)

REF_P_L

(16h)

and

REF_P_XL (15h) . The value is expressed as 2’s complement.

The reference pressure value is used when the AUTOZERO or AUTORIFP function is

enabled (refer to CTRL_REG3 (12h) ) and for the Autozero function (refer to the

INTERRUPT_CFG (0Bh) ).

REFL15

Reference pressure (middle part)

REFL14

REFL13

REFL12

REFL11

REFL10

REFL9

REFL8

REFL[15:8] This register contains the mid part of the reference pressure value.

Refer to

REF_P_XL (15h) .

REFL23

Reference pressure (MSB part)

REFL22

REFL21

REFL20

REFL19

REFL18

REFL17

REFL16

REFL[23:16] This register contains the high part of the reference pressure value.

Refer to

REF_P_XL (15h) .

40/50 DocID030522 Rev 1

LPS33HW Register description

RPDS7

Pressure offset (LSB data)

RPDS6

RPDS5

RPDS[7:0]

RPDS4

RPDS3

RPDS2

RPDS1

This register contains the low part of the pressure offset value.

RPDS0

If, after the soldering of the component, a residual offset is still present, it can be removed with a one-point calibration.

After soldering, the measured offset can be stored in the RPDS_H (19h) and RPDS_L (18h)

registers and automatically subtracted from the pressure output registers: the output pressure register PRESS_OUT (28h, 29h and 2Ah) is provided as the difference between the measured pressure and the content of the register 256*RPDS (18h, 19h)*.

*DIFF_EN = '0', AUTOZERO = '0', AUTORIFP = '0'

RPDS15

Pressure offset (MSB data)

RPDS14

RPDS13

RPDS12

RPDS11

RPDS10

RPDS9

RPDS[15:8] This register contains the high part of the pressure offset value.

Refer to

RPDS_L (18h) .

RPDS8

Low-power mode configuration

0 (1)

1. These bits must be set to ‘0’ for proper operation of the device.

2. The content of this bit must not be modified for proper operation of the device

0 (1)

1 reserved (2)

LC_EN

(1)

Low-current mode enable. Default: 0

(0: normal mode (low-noise mode); 1: low-current mode).

1. The LC_EN bit must be changed only with the device in power down and not during operation. Once the

LC_EN bit is configured, it affects both One-shot mode and Continuous mode.

DocID030522 Rev 1 41/50

Register description

Interrupt source

BOOT_STATUS

BOOT_STATUS If ‘1’ indicates that the Boot (Reboot) phase is running.

IA Interrupt active.

(0: no interrupt has been generated;

1: one or more interrupt events have been generated).

Differential pressure Low.

(0: no interrupt has been generated;

1: Low differential pressure event has occurred).

Differential pressure High.

(0: no interrupt has been generated;

1: High differential pressure event has occurred).

LPS33HW

FTH_FIFO

FIFO status

OVR

FTH_FIFO

FSS5

FSS4

FSS3

FSS2

FSS1

FSS0

OVR

FSS[5:0]

FIFO threshold status.

(0: FIFO filling is lower than the threshold level,

1: FIFO filling is equal or higher than the threshold level).

FIFO overrun status.

(0: FIFO is not completely full;

1: FIFO is full and at least one sample in the FIFO has been overwritten).

FIFO stored data level.

(000000: FIFO empty, 100000: FIFO is full and has 32 unread samples).

Table 21. FIFO_STATUS example: OVR/FSS details

FTH OVRN FSS5 FSS4 FSS3 FSS2 FSS1 FSS0 Description

(1)

...

(1)

FIFO empty

1 unread sample

32 unread samples

At least one sample has been overwritten

1. When the number of unread samples in FIFO is greater than the threshold level set in register

FIFO_CTRL

(14h) , FTH value is ‘1’.

42/50 DocID030522 Rev 1

LPS33HW Register description

Status register

T_OR

P_OR

T_DA

P_DA

P_OR

T_DA

Temperature data overrun.

(0: no overrun has occurred;

1: a new data for temperature has overwritten the previous one)

Pressure data overrun.

(0: no overrun has occurred;

1: new data for pressure has overwritten the previous one)

Temperature data available.

(0: new data for temperature is not yet available;

1: new data for temperature is available)

Pressure data available.

(0: new data for pressure is not yet available;

1: new data for pressure is available)

This register is updated every ODR cycle.

P_DA

POUT7

Pressure output value (LSB)

POUT6

POUT5

POUT4

POUT3

POUT2

POUT1

POUT0

POUT[7:0] This register contains the low part of the pressure output value.

The pressure output value is 24-bit data that contains the measured pressure. It is

composed of PRESS_OUT_H (2Ah) , PRESS_OUT_L (29h) and

PRESS_OUT_XL (28h) .

The value is expressed as 2’s complement.

The output pressure register PRESS_OUT is provided as the difference between the measured pressure and the content of the register RPDS (18h, 19h)*.

Please refer to

Section 3.4: Interpreting pressure readings for additional info.

*DIFF_EN = '0', AUTOZERO = '0', AUTORIFP = '0'

DocID030522 Rev 1 43/50

Register description LPS33HW

POUT15

Pressure output value (mid part)

POUT14

POUT13

POUT12

POUT11

POUT10

POUT9

POUT[15:8]

This register contains the mid part of the pressure output value. Refer to

POUT8

POUT23

Pressure output value (MSB)

POUT22

POUT21

POUT20

POUT19

POUT18

POUT17

POUT[23:16]

This register contains the high part of the pressure output value.

Refer to