STMicroelectronics LPS22HB Datasheet
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LPS22HB
MEMS nano pressure sensor: 260-1260 hPa absolute
digital output barometer
Datasheet
-
production data
Applications
Altimeters and barometers for portable devices
GPS applications
Weather station equipment
Sport watches
HLGA-10L
(2.0 x 2.0 x 0.76 mm)
Features
260 to 1260 hPa absolute pressure range
Current consumption down to 3 μ A
High overpressure capability: 20x full-scale
Embedded temperature compensation
24-bit pressure data output
16-bit temperature data output
ODR from 1 Hz to 75 Hz
SPI and I²C interfaces
Embedded FIFO
Interrupt functions: Data Ready, FIFO flags, pressure thresholds
Supply voltage: 1.7 to 3.6 V
High shock survivability: 22,000 g
Small and thin package
ECOPACK
®
lead-free compliant
Description
The LPS22HB is an ultra-compact piezoresistive absolute pressure sensor which functions as a digital output barometer. The device comprises a sensing element and an IC interface which communicates through I 2 C or SPI from the sensing element to the application.
The sensing element, which detects absolute pressure, consists of a suspended membrane manufactured using a dedicated process developed by ST.
The LPS22HB is available in a full-mold, holed
LGA package (HLGA). It is guaranteed to operate over a temperature range extending from -40 °C to +85 °C. The package is holed to allow external pressure to reach the sensing element.
Order code
LPS22HBTR
Table 1. Device summary
Temperature range [°C] Package
-40 to +85°C HLGA-10L
Packing
Tape and reel
June 2017
This is information on a product in full production.
DocID027083 Rev 6 1/49 www.st.com
Contents
Contents
2/49
LPS22HB
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interpreting pressure readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Dynamic-Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bypass-to-Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bypass-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Retrieving data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DocID027083 Rev 6
LPS22HB Contents
C serial interface (CS = High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
INTERRUPT_CFG (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FIFO_STATUS (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PRESS_OUT_XL (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PRESS_OUT_L (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PRESS_OUT_H (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
TEMP_OUT_L (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
TEMP_OUT_H (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Contents
LPS22HB
HLGA-10L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4/49 DocID027083 Rev 6
LPS22HB
List of tables
List of tables
C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 27
Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 27
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List of figures
List of figures
LPS22HB
C slave timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
HLGA-10L (2.0 x 2.0 x 0.76 mm typ.) package outline and mechanical dimensions . . . . . 47
6/49 DocID027083 Rev 6
LPS22HB
Figure 1. Device architecture block diagram
Block diagrams
Figure 2. Digital logic
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Pin description LPS22HB
Figure 3. Pin connections (bottom view)
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8/49 DocID027083 Rev 6
LPS22HB Pin description
Pin number
1
2
3
4
5
6
7
8
9
10
Name
Vdd_IO
SCL
SPC
Reserved
SDA
SDI
SDI/SDO
SDO
SA0
CS
INT_DRDY
GND
GND
VDD
Table 2. Pin description
Function
Power supply for I/O pins
I
2
C serial clock (SCL)
SPI serial port clock (SPC)
Connect to GND
I
2
C serial data (SDA)
4-wire SPI serial data input (SDI)
3-wire serial data input/output (SDI/SDO)
4-wire SPI serial data output (SDO)
I
2
C less significant bit of the device address (SA0)
SPI enable
I
2
C/SPI mode selection
(1: SPI idle mode / I
2
C communication enabled;
0: SPI communication mode / I
2
C disabled)
Interrupt or Data Ready
0 V supply
0 V supply
Power supply
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Mechanical and electrical specifications
3 Mechanical and electrical specifications
LPS22HB
VDD = 1.8 V, T = 25 °C, unless otherwise noted.
Symbol
Table 3. Pressure and temperature sensor characteristics
Parameter
Pressure sensor characteristics
PT op
PT full
P op
P bits
Operating temperature range
Full accuracy temperature range
Operating pressure range
Pressure output data
P sens
Pressure sensitivity
Test condition Min.
-40
0
260
Typ.
(1)
24
4096
Max.
+85
+65
1260
Unit
P
AccRel
P
P
AccT noise
Relative accuracy over pressure
Absolute accuracy over temperature
RMS pressure sensing noise
(3)
P = 800 - 1100 hPa
T = 25 °C
P op
T = 0 to 65 °C
After OPC
(2)
P op
T = 0 to 65 °C no OPC
with embedded filtering
±0.1
±0.1
±1
0.0075
hPa hPa hPa
RMS
ODR
Pres
Pressure output data rate
(4)
1
10
25
50
75
Hz
Temperature sensor characteristics
T op
T sens
T acc
ODR
T
Operating temperature range
Temperature sensitivity
Temperature absolute accuracy
Output temperature data rate
T = 0 to 65 °C
-40
100
±1.5
1
10
25
50
75
+85 °C
LSB/°C
°C
Hz
1. Typical specifications are not guaranteed.
2. OPC: One-Point Calibration, see RPDS_L (18h)
,
3. Pressure noise RMS evaluated in a controlled environment, based on the average standard deviation of 50 measurements at highest ODR and with LC_EN bit = 0, EN_LPFP = 1, LPFP_CFG = 1.
4. Output data rate is configured acting on ODR[2:0] in
°C
°C hPa bits
LSB/ hPa
10/49 DocID027083 Rev 6
LPS22HB Mechanical and electrical specifications
VDD = 1.8 V, T = 25 °C, unless otherwise noted.
Symbol
VDD Supply voltage
Vdd_IO IO supply voltage
Table 4. Electrical characteristics
Parameter Test condition Min.
1.7
1.7
Idd Supply current
@ ODR 1 Hz
LC_EN bit = 0
@ ODR 1 Hz
LC_EN bit = 1
IddPdn
Supply current in power-down mode
1. Typical specifications are not guaranteed.
Typ.
(1)
Max.
3.6
Vdd+0.1
Unit
V
V
12
μ A
3
1 μ A
Symbol Parameter
DC input characteristics
Vil
Vih
Low-level input voltage
(Schmitt buffer)
High-level input voltage
(Schmitt buffer)
DC output characteristics
Vol Low-level output voltage
Voh High-level output voltage
Table 5. DC characteristics
Condition Min.
-
-
0.8 * Vdd_IO
-
Vdd_IO - 0.2
Typ.
-
-
-
-
Max.
0.2 * Vdd_IO V
V
0.2
-
Unit
V
V
DocID027083 Rev 6 11/49
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Mechanical and electrical specifications
3.3
3.3.1
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and T
OP
.
Table 6. SPI slave timing values
Value
(1)
Symbol Parameter
Min Max t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)
SPI clock cycle
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
100
6
8
5
15
9
10
50
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.
LPS22HB
Unit ns
MHz ns
Figure 4. SPI slave timing diagram
Note:
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Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
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LPS22HB Mechanical and electrical specifications
3.3.2 I
2
C - inter-IC control interface
Subject to general operating conditions for Vdd and T
OP
.
Symbol Parameter (1)
Table 7. I 2 C slave timing values
I²C standard mode
(1)
Min Max f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
START condition hold time
0
4.7
4.0
250
0
4
100
3.45
t su(SR)
Repeated START condition setup time
4.7
t su(SP)
STOP condition setup time 4 t w(SP:SR)
Bus free time between STOP and START condition
4.7
1. Data based on standard I
2
C protocol requirement, not tested in production.
Figure 5. I 2 C slave timing diagram
Min
0
1.3
0.6
100
0
0.6
I²C fast mode
Max
400
0.9
0.6
0.6
1.3
μ s
Unit kHz
μ s ns
μ s
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Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
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Mechanical and electrical specifications
3.4 Absolute maximum ratings
LPS22HB
Stress above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Table 8. Absolute maximum ratings
Ratings
Vdd Supply voltage
Vdd_IO I/O pins supply voltage
Vin Input voltage on any control pin
P Overpressure
T
STG
Storage temperature range
ESD Electrostatic discharge protection
Maximum value
-0.3 to 4.8
-0.3 to 4.8
-0.3 to Vdd_IO +0.3
2
-40 to +125
2 (HBM)
Unit
V
V
V
MPa
°C kV
Note: Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
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LPS22HB
4 Functionality
Functionality
The LPS22HB is a high-resolution, digital output pressure sensor packaged in an HLGA fullmold package. The complete device includes a sensing element based on a piezoresistive
Wheatstone bridge approach, and an IC interface which communicates a digital signal from the sensing element to the application.
An ST proprietary process is used to obtain a silicon membrane for MEMS pressure sensors. When pressure is applied, the membrane deflection induces an imbalance in the
Wheatstone bridge piezoresistances whose output signal is converted by the IC interface.
The complete measurement chain is composed of a low-noise amplifier which converts the resistance unbalance of the MEMS sensors (pressure and temperature) into an analog voltage using an analog-to-digital converter.
The pressure and temperature data may be accessed through an I²C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller.
The LPS22HB features a Data-Ready signal which indicates when a new set of measured pressure and temperature data are available, thus simplifying data synchronization in the digital system that uses the device.
4.4
The trimming values are stored inside the device in a non-volatile structure. When the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation which allows the device to be used without requiring any further calibration.
Interpreting pressure readings
The pressure data are stored in 3 registers: PRESS_OUT_H (2Ah) , PRESS_OUT_L (29h)
,
and PRESS_OUT_XL (28h) . The value is expressed as 2’s complement.
To obtain the pressure in hPa, take the two’s complement of the complete word and then divide by 4096 LSB/hPa.
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Functionality
Figure 6. Pressure readings
LPS22HB
Equation 1
Equation 2
16/49 DocID027083 Rev 6
LPS22HB
5 FIFO
FIFO
The LPS22HB embeds 32 slots of 40-bit data FIFO to store the pressure and temperature output values. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work according to seven different modes: Bypass mode, FIFO mode, Stream mode, Dynamic-
Stream mode, Stream-to-FIFO mode, Bypass-to-Stream and Bypass-to-FIFO mode. The
FIFO buffer is enabled when the FIFO_EN bit in
CTRL_REG2 (11h) is set to '1' and each
mode is selected by the FIFO_MODE[2:0] bits in
. Programmable FIFO threshold status, FIFO overrun events and the number of unread samples stored are
available in the FIFO_STATUS (26h) register and can be set to generate dedicated
interrupts on the INT_DRDY pad using the
register.
(FTH_FIFO) goes to '1' when the number of unread samples
( FIFO_STATUS (26h) (FSS5:0)) is greater than or equal to WTM[4:0] in
.
If
FIFO_CTRL (14h) (WTM4:0) is equal to 0,
(FTH_FIFO) goes to '0'.
(OVRN) is equal to '1' if a FIFO slot is overwritten.
(FSS5:0) contains stored data levels of unread samples; when
FSS[5:0] is equal to '000000' FIFO is empty, when FSS[5:0] is equal to '100000' FIFO is full and the unread samples are 32.
To guarantee the switching into and out of FIFO mode, discard the first sample acquired.
In Bypass mode (
(FMODE2:0)=000), the FIFO is not operational and it remains empty.
Bypass mode is also used to reset the FIFO when in FIFO mode.
As described in the next figure, for each channel only the first address is used. When new data is available, the older data is overwritten.
Figure 7. Bypass mode
DocID027083 Rev 6 17/49
49
FIFO LPS22HB
In FIFO mode (
(FMODE2:0) = 001) data from the output
,
PRESS_OUT_L (29h) , PRESS_OUT_H (2Ah) and TEMP_OUT_L
(2Bh) , TEMP_OUT_H (2Ch) are stored in the FIFO until it is overwritten.
To reset FIFO content, in Bypass mode the value '000' must be written in
(FMODE2:0). After this reset command, it is possible to restart FIFO mode, writing the value '001' in
FIFO buffer memorizes 32 levels of data but the depth of the FIFO can be resized by setting the
CTRL_REG2 (11h) (STOP_ON_FTH) bit. If the STOP_ON_FTH bit is set to '1', FIFO
depth is limited to
FIFO_CTRL (14h) (WTM4:0) + 1 data.
A FIFO threshold interrupt can be enabled (F_OVR bit in CTRL_REG3 (12h)
in order to be raised when the FIFO is filled to the level specified by the WTM4:0 bits of
. When a FIFO threshold interrupt occurs, the first data has been overwritten and the
FIFO stops collecting data from the input pressure and temperature.
Figure 8. FIFO mode
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18/49 DocID027083 Rev 6
LPS22HB FIFO
Stream mode ( FIFO_CTRL (14h) (FMODE2:0) = 010) provides continuous FIFO update: as
new data arrive, the older is discarded.
Once the entire FIFO has been read, the last data read remains in the FIFO and hence once a new sample is acquired, the
(FSS5:0) value rises from 0 to 2.
An overrun interrupt can be enabled,
CTRL_REG3 (12h) (F_OVR) = '1', in order to inform
when the FIFO is full and eventually read its content all at once. If an overrun occurs, the oldest sample in FIFO is overwritten, so if the FIFO was empty, the lost sample has already been read.
Figure 9. Stream mode
In the latter case reading all FIFO content before an overrun interrupt has occurred, the first data read is equal to the last already read in the previous burst, so the number of new data available in FIFO depends on the previous reading.
DocID027083 Rev 6 19/49
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FIFO
5.4
LPS22HB
Dynamic-Stream mode
In Dynamic-Stream mode ( FIFO_CTRL (14h)
(FMODE2:0) = 110) after emptying the FIFO, the first new sample that arrives becomes the first to be read in a subsequent read burst. In this way, the number of new data available in FIFO does not depend on the previous reading.
In Dynamic-Stream mode
FIFO_STATUS (26h) (FSS5:0) is the number of new pressure and
temperature samples available in the FIFO buffer.
Stream Mode is intended to be used to read all 32 samples of FIFO within an ODR after receiving an overrun signal.
Dynamic-Stream is intended to be used to read
(FSS5:0) samples when it is not possible to guarantee reading data within an ODR.
Also, a FIFO threshold interrupt on the INT_DRDY pad through
can be enabled in order to read data from the FIFO and leave free memory slots for incoming data.
Figure 10. Dynamic-Stream mode
20/49 DocID027083 Rev 6
LPS22HB FIFO
In Stream-to-FIFO mode (
FIFO_CTRL (14h) (FMODE2:0) = 011), FIFO behavior changes
according to the INT_SOURCE(IA) bit. When the INT_SOURCE(IA) bit is equal to '1', FIFO operates in FIFO mode. When the INT_SOURCE(IA) bit is equal to '0', FIFO operates in
Stream mode.
An interrupt generator can be set to the desired configuration through
.
The
INTERRUPT_CFG (0Bh) (LIR) bit should be set to '1' in order to have latched interrupt.
Figure 11. Stream-to-FIFO mode
DocID027083 Rev 6 21/49
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FIFO LPS22HB
In Bypass-to-Stream mode (
FIFO_CTRL (14h) (FMODE2:0) = '100'), data measurement
storage inside FIFO operates in Stream mode when INT_SOURCE(IA) is equal to '1', otherwise FIFO content is reset (Bypass mode).
An interrupt generator can be set to the desired configuration through
.
The
INTERRUPT_CFG (0Bh) (LIR) bit should be set to '1' in order to have latched interrupt.
Figure 12. Bypass-to-Stream mode
22/49 DocID027083 Rev 6
LPS22HB FIFO
In Bypass-to-FIFO mode (
(FMODE2:0) = '111'), data measurement storage inside FIFO operates in FIFO mode when INT_SOURCE(IA) is equal to '1', otherwise FIFO content is reset (Bypass mode).
An interrupt generator can be set to the desired configuration through
.
The
INTERRUPT_CFG (0Bh) (LIR) bit should be set to '1' in order to have latched interrupt.
Figure 13. Bypass-to-FIFO mode
5.8 Retrieving data from FIFO
FIFO data is read from PRESS_OUT (Addr. reg 28h,29h,2Ah) and TEMP_OUT (Addr. reg
2Bh,2Ch).
Each time data is read from the FIFO, the oldest data are placed in the
,
PRESS_OUT_L (29h) , PRESS_OUT_H (2Ah) , TEMP_OUT_L (2Bh) and
TEMP_OUT_H (2Ch) registers and both single-read and read-burst operations can be
used.
The device automatically updates the reading address and it rolls back to 28h when register
2Ch is reached. In order to read all FIFO levels in multiple byte reading, 160 bytes (5 output registers by 32 levels) must be read.
DocID027083 Rev 6 23/49
49
Application hints
9''
Figure 14. LPS22HB electrical connections (top view)
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The device power supply must be provided through the VDD line; a power supply decoupling capacitor C1 (100 nF) must be placed as near as possible to the supply pads of the device. Depending on the application, an additional capacitor of 4.7 μ F could be placed on VDD line.
The functionality of the device and the measured data outputs are selectable and accessible through the I²C/SPI interface. When using the I 2 C, CS must be tied to Vdd_IO.
All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to
Figure 14 ). It is possible to remove VDD while maintaining
Vdd_IO without blocking the communication bus, in this condition the measurement chain is powered off.
The HLGA package is compliant with the ECOPACK ® standard, and it is qualified for soldering heat resistance according to JEDEC J-STD-020.
24/49 DocID027083 Rev 6
LPS22HB Digital interfaces
The registers embedded in the LPS22HB may be accessed through both the I²C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I²C interface, the
CS line must be tied high (i.e. connected to Vdd_IO).
Pin name
CS
SCL/SPC
SDA
SDI
SDI/SDO
SDO
SAO
Table 9. Serial interface pin description
Pin description
SPI enable
I²C/SPI mode selection (1: SPI idle mode / I
2
C communication enabled; 0: SPI communication mode / I
2
C disabled)
I²C serial clock (SCL)
SPI serial port clock (SPC)
I²C serial data (SDA)
4-wire SPI serial data input (SDI)
3-wire serial data input /output (SDI/SDO)
SPI serial data output (SDO)
I²C less significant bit of the device address (SA0)
7.2 I
2
C serial interface (CS = High)
The LPS22HB I²C is a bus slave. The I²C is employed to write data into registers whose content can also be read back.
The relevant I²C terminology is given in
Term
Table 10. I 2 C terminology
Description
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master The device which initiates a transfer, generates clock signals and terminates a transfer
Slave The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines have to be connected to Vdd_IO through pull-up resistors.
The I²C interface is compliant with fast mode (400 kHz) I²C standards as well as with the normal mode.
DocID027083 Rev 6 25/49
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Digital interfaces LPS22HB
7.2.1 I
2
C operation
The transaction on the bus is started through a START (ST) signal. A start condition is defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After the master has transmitted this, the bus is considered busy. The next data byte transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave.
When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.
The slave address (SAD) associated to the LPS22HB is 101110xb. The SDO / SA0 pad can be used to modify the less significant bit of the device address. If the SA0 pad is connected to voltage supply, LSb is ‘1’ (address 1011101b), otherwise if the SA0 pad is connected to ground, the LSb value is ‘0’ (address 1011100b). This solution permits connecting and addressing two different LPS22HB devices to the same I²C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.
The I 2 C embedded inside the ASIC behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK), an 8-bit sub-address will be transmitted (SUB): the
7 LSB represent the actual register address while the MSB has no meaning. The
IF_ADD_INC bit in
CTRL_REG2 (11h) enables sub-address auto increment (IF_ADD_INC
is '1' by default), so if IF_ADD_INC = '1' the SUB (sub-address) will be automatically increased to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged.
SAD+read/write bit pattern is composed, listing all the possible configurations.
Command
Read
Write
Read
Write
Table 11. SAD+Read/Write patterns
SAD[6:1] SAD[0] = SA0 R/W
101110
101110
101110
101110
0
0
1
1
1
0
1
0
SAD+R/W
10111001 (B9h)
10111000 (B8h)
10111011 (BBh)
10111010 (BAh)
Master
Slave
Table 12. Transfer when master is writing one byte to slave
ST SAD + W SUB DATA
SAK SAK SAK
SP
26/49 DocID027083 Rev 6
LPS22HB Digital interfaces
Master
Slave
ST
Table 13. Transfer when master is writing multiple bytes to slave
SAD + W SUB DATA DATA
SAK SAK SAK SAK
SP
Master
Table 14. Transfer when master is receiving (reading) one byte of data from slave
ST SAD + W SUB SR SAD + R NMAK
Slave SAK SAK SAK DATA
SP
Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP
Slave SAK SAK SAK DATA DATA DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit
(MSb) first. If a receiver cannot receive another complete byte of data until it has performed some other functions, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function), the data line must be kept HIGH by the slave. The master can then abort the transfer. A LOW-to-HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes incrementing the register address, it is necessary to assert the most significant bit of the sub-address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of the first register to be read.
In the presented communication format MAK is Master acknowledge and NMAK is no master acknowledge.
DocID027083 Rev 6 27/49
49
Digital interfaces LPS22HB
7.3 SPI interface
The LPS22HB SPI is a bus slave. The SPI allows writing to and reading from the registers of the device.
The serial interface interacts with the application using 4 wires: CS , SPC , SDI and SDO .
Figure 15. Read and write protocol
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CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and returns to high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .
Both the read register and write register commands are completed in 16 clock pulses or multiples of 8 in the case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23,...) starts at the last falling edge of SPC just before the rising edge of CS .
bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip will drive SDO at the start of bit 8.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods are added. When the
IF_ADD_INC bit is 0, the address used to read/write data remains the same for every block.
When the IF_ADD_INC bit is 1, the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
28/49 DocID027083 Rev 6
LPS22HB Digital interfaces
Figure 16. SPI read protocol
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The SPI read command is performed with 16 clock pulses. The multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit 16-...
: data DO(...-8). Further data in multiple byte reads.
Figure 17. Multiple byte SPI read protocol (2-byte example)
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DocID027083 Rev 6 29/49
49
Digital interfaces LPS22HB
Figure 18. SPI write protocol
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The SPI write command is performed with 16 clock pulses. The multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : WRITE bit. The value is 0.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written in the device (MSb first).
bit 16-...
: data DI(...-8). Further data in multiple byte writes.
Figure 19. Multiple byte SPI write protocol (2-byte example)
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30/49 DocID027083 Rev 6
LPS22HB
7.3.3
Digital interfaces
SPI read in 3-wire mode
A 3-wire mode is entered by setting bit SIM to ‘1’ (SPI serial interface mode selection) in
Figure 20. SPI read protocol in 3-wire mode
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The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
DocID027083 Rev 6 31/49
49
Register mapping LPS22HB
32/49
provides a quick overview of the 8-bit registers embedded in the device.
Name
Table 16. Registers address map
Type
Register
Address
Default
Hex Binary
Function and comment
Reserved 00 - 0A
INTERRUPT_CFG
THS_P_L
R/W
R/W
0B
0C
THS_P_H R/W 0D
Reserved 0E
WHO_AM_I
CTRL_REG1
CTRL_REG2
CTRL_REG3
R
R/W
R/W
R/W
0F
10
11
12
Reserved 13
FIFO_CTRL R/W 14
REF_P_XL
REF_P_L
R/W
R/W
15
16
REF_P_H
RPDS_L
RPDS_H
RES_CONF
Reserved
INT_SOURCE
FIFO_STATUS
STATUS
R/W
R/W
R/W
R/W
R
R
R
25
26
27
17
18
19
1A
1B - 24
PRESS_OUT_XL
PRESS_OUT_L
PRESS_OUT_H
TEMP_OUT_L
TEMP_OUT_H
Reserved
LPFP_RES
R
R
R
R
R
R
28
29
2A
2B
2C
2D - 32
33
-
00000000
00000000
00000000
-
10110001
00000000
00010000
00000000
-
00000000
00000000
00000000
00000000
00000000
00000000
00000000
output output output output output output output output
output
Reserved
Interrupt register
Pressure threshold registers
Reserved
Who am I
Control registers
Reserved
FIFO configuration register
Reference pressure registers
Pressure offset registers
Resolution register
Reserved
Interrupt register
FIFO status register
Status register
Pressure output registers
Temperature output registers
Reserved
Filter reset register
DocID027083 Rev 6
LPS22HB Register mapping
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
To guarantee the proper behavior of the device, all register addresses not listed in the above table must not be accessed and the content stored in those registers must not be changed.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
DocID027083 Rev 6 33/49
49
Register description LPS22HB
The device contains a set of registers which are used to control its behavior and to retrieve pressure and temperature data. The register address, made up of 7 bits, is used to identify them and to read/write the data through the serial interface.
Interrupt mode for pressure acquisition configuration.
7
AUTORIFP
6 5
RESET_ARP AUTOZERO
4
RESET_AZ
3
DIFF_EN
2
LIR
1
PLE
AUTORIFP Enable AUTORIFP: function. Default value: 0
(0: normal mode; 1: AutoRifP enabled)
RESET_ARP Reset AutoRifP function. Default value: 0
(0: normal mode; 1: reset AutoRifP function)
AUTOZERO Enable Autozero function. Default value: 0
(0: normal mode; 1: Autozero enabled)
RESET_AZ Reset Autozero function. Default value: 0
(0: normal mode; 1: reset Autozero function)
DIFF_EN Enable interrupt generation. Default value: 0
(0: interrupt generation disabled; 1: interrupt generation enabled)
LIR
PLE
PHE
Latch interrupt request to the
INT_SOURCE (25h) register. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
Enable interrupt generation on pressure low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on pressure value lower than preset threshold)
Enable interrupt generation on pressure high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on pressure value higher than preset threshold)
0
PHE
To generate an interrupt event based on a user-defined threshold, the DIFF_EN bit must be
set to '1' and the threshold values stored in THS_P_L (0Ch)
and
.
When DIFF_EN = '1', the PHE bit or PLE bit (or both bits) have to be enabled.
When DIFF_EN is enabled and AUTOZERO or AUTORIFP is enabled, the defined pressure threshold values in THS_P (0Ch, 0Dh) is compared with:
P_DIFF_IN = measured pressure - REF_P
34/49 DocID027083 Rev 6
LPS22HB
Figure 21. “Threshold based” interrupt event
Register description
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If the AUTOZERO bit is set to '1', the measured pressure is used as the reference in the register REF_P (15h, 16h and 17h). From that point on, the output pressure registers
PRESS_OUT (28h, 29h and 2Ah) are updated and the same value is also used for the interrupt generation:
– PRESS_OUT = measured pressure - REF_P
– P_DIFF_IN = measured pressure - REF_P
After the first conversion, the AUTOZERO bit is automatically set to '0'. To return back to normal mode, RESET_AZ bit has to be set to '1'. This resets also the content of the REF_P registers.
If the AUTORIFP bit is set to '1', the measured pressure is used as the reference in the register REF_P (15h, 16h and 17h). From that point on, the value used for the interrupt generation is the following:
– P_DIFF_IN = measured pressure - REF_P
The output registers PRESS_OUT (28h, 29h and 2Ah) show the difference between the measured pressure and the content of the RPDS registers (18h and 19h):
– PRESS_OUT = measured pressure - RPDS
After the first conversion, AUTORIFP bit is automatically set to '0'. To return back to normal mode, the RESET_ARP bit has to be set to '1'.
DocID027083 Rev 6 35/49
49
Register description LPS22HB
User-defined threshold value for pressure interrupt event (Least significant bits).
7
THS7
6
THS6
5
THS5
4
THS4
3
THS3
2
THS2
1
THS1
0
THS0
THS[7:0] This register contains the low part of threshold value for pressure interrupt generation.
The threshold value for pressure interrupt generation is a 16-bit unsigned right-justified value composed of
THS_P_H (0Dh) and THS_P_L (0Ch) .The value is expressed as:
Interrupt threshold (hPa) = ±THS_P / 16
To enable the interrupt event based on this user-defined threshold, the DIFF_EN bit in
INTERRUPT_CFG (0Bh) must be set to '1', the PHE bit or PLE bit (or both bits) in
INTERRUPT_CFG (0Bh) has to be enabled.
User-defined threshold value for pressure interrupt event (Most significant bits).
7
THS15
6
THS14
5
THS13
4
THS12
3
THS11
2
THS10
1
THS9
THS[15:8]
0
THS8
This register contains the high part of threshold value for pressure interrupt generation. Refer to
Device Who am I
7
1
6
0
5
1
4
1
3
0
2
0
1
0
0
1
36/49 DocID027083 Rev 6
LPS22HB Register description
Control register 1
7
0 (1)
6
ODR2
5
ODR1
4
ODR0
3
EN_LPFP
1. This bit must be set to ‘0’ for proper operation of the device.
2
LPFP_CFG
1
BDU
0
SIM
ODR[2:0]
EN_LPFP
Output data rate selection. Default value: 000
Refer to
.
Enable low-pass filter on pressure data when Continuous mode is used. Default value: 0
(0: Low-pass filter disabled; 1: Low-pass filter enabled)
LPFP_CFG LPFP_CFG: Low-pass configuration register. Default value:0
Refer to
.
BDU
(1)
Block data update. Default value: 0
(0: continuous update;
1: output registers not updated until MSB and LSB have been read
(2)
)
SIM SPI Serial Interface Mode selection.Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
1. To guarantee the correct behavior of BDU feature,
PRESS_OUT_H (2Ah) must be the last address read.
2. When I 2 C is used with BDU=1, the IF_ADD_INC bit has to be set to ‘0’ in
single-byte read of the output registers is allowed.
ODR2
0
1
1
0
0
0
ODR1
Table 17. Output data rate bit configurations
ODR0 Pressure (Hz) Temperature (Hz)
1
0
0
0
0
1
1
0
1
0
1
0
Power down / one-shot mode enabled
1 Hz
10 Hz
1 Hz
10 Hz
25 Hz
50 Hz
75 Hz
25 Hz
50 Hz
75 Hz
When the ODR bits are set to '000', the device is in Power-down mode . When the device is in power-down mode, almost all internal blocks of the device are switched off to minimize power consumption. The I 2 C interface is still active to allow communication with the device.
The content of the configuration registers is preserved and output data registers are not updated, therefore keeping the last data sampled in memory before going into power-down mode.
If the ONE_SHOT bit in
CTRL_REG2 (11h) is set to '1',
One-shot mode is triggered and a new acquisition starts when it is required. Enabling this mode is possible only if the device was previously in power-down mode (ODR bits set to '000'). Once the acquisition is completed and the output registers updated, the device automatically enters in power-down mode. ONE_SHOT bit self-clears itself.
DocID027083 Rev 6 37/49
49
Register description LPS22HB
When the ODR bits are set to a value different than '000', the device is in Continuous mode and automatically acquires a set of data (pressure and temperature) at the frequency selected through the ODR[2:0] bits.
Once the additional low-pass filter has been enabled through the EN_LPFP bit, it is possible to configure the device bandwidth acting on the LPFP_CFG bit. See
filter configurations.
EN_LPFP
0
1
1
Table 18. Low-pass filter configurations
LPFP_CFG Additional low-pass filter status x
0
1
Disabled
Enabled
Enabled
Device bandwidth
ODR/2
ODR/9
ODR/20
The BDU bit is used to inhibit the update of the output registers between the reading of upper, middle and lower register parts. In default mode (BDU = ‘0’), the lower and upper register parts are updated continuously. When the BDU is activated (BDU = ‘1’), the content of the output registers is not updated until
is read, avoiding the reading of values related to different samples.
38/49
Control register 2
7
BOOT
6
FIFO_EN
5 4
STOP_ON_FTH IF_ADD_INC
3
I2C_DIS
1. This bit must be set to ‘0’ for proper operation of the device
2
SWRESET
1
0 (1)
0
ONE_SHOT
BOOT
FIFO_EN
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content). The bit is self-cleared when the BOOT is completed.
FIFO enable. Default value: 0
(0: disable; 1: enable)
STOP_ON_FTH Stop on FIFO watermark. Enable FIFO watermark level use. Default value: 0
(0: disable; 1: enable)
IF_ADD_INC
(1)
I2C_DIS
Register address automatically incremented during a multiple byte access with a serial interface (I
2
C or SPI). Default value: 1
(0: disable; 1 enable)
Disable I
2
(0: I
2
C interface. Default value: 0
C enabled;1: I
2
C disabled)
SWRESET Software reset. Default value: 0
(0: normal mode; 1: software reset).
The bit is self-cleared when the reset is completed.
ONE_SHOT One-shot enable. Default value: 0
(0: idle mode; 1: a new dataset is acquired)
1. It is recommend to use a single-byte read (with IF_ADD_INC = 0) when output data registers are acquired without using the FIFO. If a read of the data occurs during the refresh of the output data register, it is recommended to set the BDU bit to ‘1’ in
CTRL_REG1 (10h) in order to avoid mixing data.
DocID027083 Rev 6
LPS22HB Register description
The BOOT bit is used to refresh the content of the internal registers stored in the Flash memory block. At device power-up, the content of the Flash memory block is transferred to the internal registers related to the trimming functions to allow correct behavior of the device itself. If for any reason the content of the trimming registers is modified, it is sufficient to use this bit to restore the correct values. When the BOOT bit is set to ‘1’, the content of the internal Flash is copied into the corresponding internal registers and is used to calibrate the device. These values are factory trimmed and they are different for every device. They allow the correct behavior of the device and normally they should not be changed. At the end of the boot process the BOOT bit is set again to ‘0’ by hardware. The BOOT bit takes effect after one ODR clock cycle.
SWRESET
is the software reset bit. The following device registers ( INTERRUPT_CFG
,
,
FIFO_CTRL (14h) , REF_P_XL (15h) ,
) are reset to the default value if the SWRESET bit is set to '1'. The SWRESET bit returns to '0' by hardware.
The ONE_SHOT bit is used to start a new conversion when the ODR[2:0] bits in
CTRL_REG1 (10h) are set to ‘000’. Writing a ‘1’ in ONE_SHOT triggers a single
measurement of pressure and temperature. Once the measurement is done, the
ONE_SHOT bit will self-clear, the new data are available in the output registers, and the
STATUS (27h) bits are updated.
Control register 3 - INT_DRDY pin control register
7
INT_H_L
6
PP_OD
5
F_FSS5
4
F_FTH
3
F_OVR
2
DRDY
1
INT_S2
0
INT_S1
INT_H_L
PP_OD
F_FSS5
F_FTH
F_OVR
DRDY
INT_S[2:1]
Interrupt active-high/low. Default value: 0
(0: active high; 1: active low)
Push-pull/open drain selection on interrupt pads. Default value: 0
(0: push-pull; 1: open drain)
FIFO full flag on INT_DRDY pin. Default value: 0
(0: disable; 1: enable)
FIFO watermark status on INT_DRDY pin. Default value: 0
(0: disable; 1: enable)
FIFO overrun interrupt on INT_DRDY pin. Default value: 0
(0: disable; 1: enable)
Data-ready signal on INT_DRDY pin. Default value: 0
(0: disable; 1: enable)
Data signal on INT_DRDY pin control bits. Default value: 00
Refer to
.
DocID027083 Rev 6 39/49
49
Register description
INT_S2 INT_S1
1
1
0
0
Table 19. Interrupt configurations
INT_DRDY pin configuration
0 Data signal (in order of priority: DRDY or F_FTH or F_OVR or F_FSS5
1 Pressure high (P_high)
0 Pressure low (P_low)
1 Pressure low OR high
Figure 22. Interrupt events on INT_DRDY pin
LPS22HB
40/49 DocID027083 Rev 6
LPS22HB
9.8 FIFO_CTRL (14h)
FIFO control register
7
F_MODE2
6
F_MODE1
5
F_MODE0
4
WTM4
3
WTM3
2
WTM2
F_MODE[2:0] FIFO mode selection. Default value: 000
Refer to
and Section 5 for additional details.
WTM[4:0] FIFO watermark level selection.
Register description
1
WTM1
0
WTM0
Table 20. FIFO mode selection
F_MODE2 F_MODE1 F_MODE0 FIFO mode selection
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bypass mode
FIFO mode
Stream mode
Stream-to-FIFO mode
Bypass-to-Stream mode
Reserved
Dynamic-Stream mode
Bypass-to-FIFO mode
Reference pressure (LSB data)
7
REFL7
6
REFL6
5
REFL5
4
REFL4
3
REFL3
2
REFL2
1
REFL1
0
REFL0
REFL[7:0] This register contains the low part of the reference pressure value.
The Reference pressure value is a 24-bit data and it is composed of
and
REF_P_XL (15h) . The value is expressed as 2’s complement.
The reference pressure value is used when AUTOZERO or AUTORIFP function is enabled.
Please refer to
INTERRUPT_CFG (0Bh) register description.
DocID027083 Rev 6 41/49
49
Register description LPS22HB
Reference pressure (middle part)
7
REFL15
6
REFL14
5
REFL13
REFL[15:8]
4
REFL12
3
REFL11
2
REFL10
1
REFL9
This register contains the mid part of the reference pressure value.
Refer to
0
REFL8
Reference pressure (MSB part)
7
REFL23
6
REFL22
5
REFL21
4
REFL20
3
REFL19
2
REFL18
1
REFL17
REFL[23:16] This register contains the high part of the reference pressure value.
Refer to
0
REFL16
Pressure offset (LSB data)
7
RPDS7
6
RPDS6
5
RPDS5
RPDS[7:0]
4
RPDS4
3
RPDS3
2
RPDS2
This register contains the low part of the pressure offset value.
1
RPDS1
0
RPDS0
The pressure offset value is 16-bit data that can be used to implement one-point calibration
(OPC) after soldering. This value is composed of RPDS_H (19h) and RPDS_L (18h)
. The value is expressed as 2’s complement.
42/49
Pressure offset (MSB data)
7
RPDS15
6
RPDS14
5
RPDS13
4
RPDS12
3
RPDS11
2
RPDS10
RPDS[15:8] This register contains the high part of the pressure offset value.
Refer to
1
RPDS9
0
RPDS8
DocID027083 Rev 6
LPS22HB Register description
Low-power mode configuration
7
0 (1)
6
0 (1)
5
0 (1)
4
0 (1)
3
0 (1)
2
0 (1)
1. These bits must be set to ‘0’ for proper operation of the device.
2. The content of this bit must not be modified for proper operation of the device
1 reserved (2)
LC_EN
(1)
Low current mode enable. Default 0
0: Normal mode (low-noise mode); 1: Low-current mode.
1. The LC_EN bit must be changed only with the device in power down and not during operation. Once
LC_EN bit is configured, it affects both One-shot mode and Continuous mode.
0
LC_EN
Interrupt source
7
BOOT_STATUS
6
0
5
0
4
0
3
0
2
IA
BOOT_STATUS If ‘1’ indicates that the Boot (Reboot) phase is running.
IA
PL
Interrupt active.
(0: no interrupt has been generated;
1: one or more interrupt events have been generated).
Differential pressure Low.
(0: no interrupt has been generated;
1: low differential pressure event has occurred).
PH Differential pressure High.
(0: no interrupt has been generated;
1: high differential pressure event has occurred).
1
PL
0
PH
DocID027083 Rev 6 43/49
49
Register description LPS22HB
FIFO status
7
FTH_FIFO
FTH_FIFO
6
OVR
OVR
FSS[5:0]
5
FSS5
4
FSS4
3
FSS3
2
FSS2
1
FSS1
FIFO watermark status.
(0: FIFO filling is lower than treshold level;
1: FIFO filling is equal or higher than treshold level).
FIFO overrun status.
(0: FIFO is not completely full;
1: FIFO is full and at least one sample in the FIFO has been overwritten).
FIFO stored data level.
(000000: FIFO empty, 100000: FIFO is full and has 32 unread samples).
0
FSS0
FTH
Table 21. FIFO_STATUS example: OVR/FSS details
OVRN FSS5 FSS4 FSS3 FSS2 FSS1 FSS0 Description
0
--
(1)
--
--
0
0
0
0
0
0
0
0
0
0
0
0
0
1
FIFO empty
1 unread sample
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
32 unread samples
At least one sample has been written
1. When the number of unread samples in FIFO is greater than the threshold level set in register
, the FTH value is ‘1’.
44/49 DocID027083 Rev 6
LPS22HB Register description
Status register
7
--
6
--
5
T_OR
4
P_OR
3
--
2
--
T_OR Temperature data overrun.
(0: no overrun has occurred;
1: a new data for temperature has overwritten the previous data)
P_OR Pressure data overrun.
(0: no overrun has occurred;
1: new data for pressure has overwritten the previous data)
T_DA Temperature data available.
(0: new data for temperature is not yet available;
1: a new temperature data is generated)
P_DA Pressure data available.
(0: new data for pressure is not yet available;
1: a new pressure data is generated)
1
T_DA
This register is updated every ODR cycle.
0
P_DA
Pressure output value (LSB)
7
POUT7
6
POUT6
5
POUT5
POUT[7:0]
4
POUT4
3
POUT3
2
POUT2
1
POUT1
This register contains the low part of the pressure output value.
0
POUT0
The pressure output value is a 24-bit data that contains the measured pressure. It is
composed of PRESS_OUT_H (2Ah) , PRESS_OUT_L (29h)
The value is expressed as 2’s complement.
The output pressure register PRESS_OUT is provided as the difference between the measured pressure and the content of the register RPDS (18h, 19h)*.
Please refer to
Section 4.4: Interpreting pressure readings for additional info.
*DIFF_EN = '0', AUTOZERO = '0', AUTORIFP = '0'
DocID027083 Rev 6 45/49
49
Register description LPS22HB
Pressure output value (mid part)
7
POUT15
6
POUT14
5
POUT13
4
POUT12
3
POUT11
2
POUT10
1
POUT9
POUT[15:8]
This register contains the mid part of the pressure output value. Refer to
0
POUT8
Pressure output value (MSB)
7
POUT23
6
POUT22
5
POUT21
4
POUT20
3
POUT19
2
POUT18
POUT[23:16]
This register contains the high part of the pressure output value.
Refer to
1
POUT17
0
POUT16
Temperature output value (LSB)
7
TOUT7
TOUT[7:0]
6
TOUT6
5
TOUT5
4
TOUT4
3
TOUT3
2
TOUT2
1
TOUT1
This register contains the low part of the temperature output value.
0
TOUT0
The temperature output value is 16-bit data that contains the measured temperature. It is
composed of TEMP_OUT_H (2Ch) , and TEMP_OUT_L (2Bh) . The value is expressed as
2’s complement.
Temperature output value (MSB)
7
TOUT15
6
TOUT14
5
TOUT13
4
TOUT12
3
TOUT11
2
TOUT10
1
TOUT9
TOUT[15:8] This register contains the high part of the temperature output value.
0
TOUT8
46/49
Low-pass filter reset register. If the LPFP is active, in order to avoid the transitory phase, the filter can be reset by reading this register before generating pressure measurements.
DocID027083 Rev 6
LPS22HB Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
10.1 HLGA-10L package information
Figure 23. HLGA-10L (2.0 x 2.0 x 0.76 mm typ.) package outline and mechanical dimensions
,7(0
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DocID027083 Rev 6 47/49
49
Revision history LPS22HB
Date
29-Oct-2014
05-May-2015
04-Sep-2015
15-Dec-2015
22-Nov-2016
29-Jun-2017
Table 22. Document revision history
Revision Changes
1
2
3
4
5
6
Initial release.
Datasheet status promoted from “Target specification” to
“Preliminary data”.
Updated: note 2 in Table 3: Pressure and temperature sensor characteristics, Section 4: FIFO, Table 20: FIFO mode selection and the following registers: FIFO_STATUS (26h), CTRL_REG1
(10h), CTRL_REG2 (11h), Section 9: Package mechanical data.
Datasheet status promoted from “Preliminary data” to “Production data”.
Updates: Table 1: Device summary , Sections: 4.2: IC interface , 4.3:
Factory calibration , 7.1: Serial interfaces , Table 17: Output data rate bit configurations and 9.17: STATUS (27h) .
Updated: Section 1: Block diagrams , Section 4.4: Interpreting pressure readings , Table 16: Registers address map , Figure 21 .
Added: TEMP_OUT_H (2Ch) and LPFP_RES (33h) .
Minor text changes.
Added footnote 2 to CTRL_REG1 (10h)
Minor textual updates
Updated Vol and Voh in
Updated
C slave timing values and Figure 5: I
Updated
Table 16: Registers address map
Added footnote
to IF_ADD_INC bit in
48/49 DocID027083 Rev 6
LPS22HB
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
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ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
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