STMicroelectronics VIPER31 Datasheet
Pubblicità
Pubblicità
VIPER31
Datasheet
Energy saving offline high voltage converter
~ AC
D
IN
R
IN
C
IN
C1
OVP
VCC DRAIN
FB
CONTROL
COMP UVP GND
VIPER31
R1
C3 R2
C2
L
OUT
D1
GND
Product status link
VIPER31
Product label
D
AUX
D2
V
OUT
C
OUT
GND
Features
• 800 V avalanche-rugged power MOSFET to cover ultra-wide VAC input range
• Embedded HV startup and sense FET
• Current mode PWM controller
• Drain current limit protection (OCP):
– 710 mA (VIPER317)
– 850 mA (VIPER318)
– 990 mA (VIPER319)
• Wide supply voltage range: 4.5 V to 30 V
– < 20 mW @ 230 V
AC
in no-load;
– < 430 mW @ 230 V
AC
, 25 0mW output load
• Jittered switching frequency reduces the EMI filter cost:
– 30 kHz ± 7% (type X)
– 60 kHz ± 7% (type L)
– 132 kHz ±7% (type H)
• Embedded E/A with 1.2 V reference
• Built-in soft-start for improved system reliability
• Protections with automatic restart:
– overload/short-circuit (OLP)
– thermal shutdown
– overvoltage
• Protections without automatic restart:
– pulse-skip protection to avoid flux runaway
– undervoltage/disable
– max. duty cycle
Application
• Low power SMPS for home appliances, home automation, industrial, consumers, lighting
• Low power adapters
Description
The VIPER31 device is a high-voltage converter that smartly integrates an 800
V avalanche rugged power MOSFET with PWM current-mode control. The 800 V breakdown allows extended input voltage range to be applied, as well as to reduce the size of the DRAIN snubber circuit. The IC can meet the most stringent energysaving standards as it has very low consumption and operates in pulse frequency modulation at light load. Overvoltage and undervoltage protections with separate and settable intervention thresholds are available at OVP and UVP pins respectively. UVP can also be used as a disabling input for the entire SMPS, with ultra-low residual input power consumption. Integrated HV startup, sense FET, error amplifier and oscillator with frequency jitter allow a complete application to be designed with a minimum component count. Flyback, buck and buck boost topologies are supported.
DS13285 - Rev 3 - November 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
1
VIPER31
Pin setting
Pin setting
GND
Figure 1. Connection diagram
DRAIN
N.C.
VCC
N. A.
UVP
OVP
FB
COMP
N. C.
N. C.
N. C.
N. C.
DRAIN
DRAIN
DRAIN
Table 1. Pin description
Pin number
Name
1
2
3
4
5
6
7
GND
N. C.
VCC
N.A.
UVP
OVP
FB
Function
Ground and MOSFET source.
Connection of both the source of the internal MOSFET and the return of the bias current of the device. All of the groundings of bias components must be tied to a trace going to this pin and kept separate from the pulsed current return.
Not connected.
When designing the PCB, this pin can be soldered to GND.
Controller Supply . An external storage capacitor has to be connected across this pin and GND. The pin, internally connected to the high-voltage current source, provides the VCC capacitor charging current at startup. A small bypass capacitor (0.1 μF typ.) in parallel, placed as close as possible to the IC, is also recommended, for noise filtering purposes.
Not available for user.
This pin is mechanically connected to the controller die pad of the frame. In order to improve noise immunity, it is highly recommended to connect it to GND.
Undervoltage Protection. If V
UVP
falls below the internal threshold V
UVP_th
(0.4 V typ.) for more than t
UVP_DEB
time (30 ms, typ.), the IC is disabled, and its consumption reduced to ultra-low values. When
V
UVP
rises above V
UVP_th,
the device waits for a t
UVP_REST
time interval (30 ms, typ.) then resumes switching. The pin can be used to realize an input undervoltage protection or as a disabling input for the entire SMPS, with ultra-low residual input power consumption. If the feature is not required, the pin must be left open, which excludes the function.
Overvoltage protection . If VOVP exceeds the internal threshold V
OVP_th
(4 V typ.) for more than t
OVP_DEB
time (250 μsec, typ.), the PWM is disabled in auto-restart for t
OVP_REST
(500 msec, typ.) until the OVP condition is removed, after that it restarts switching with soft-start phase. OVP pin can be used to realize an input overvoltage protection (or, in non-isolated topologies, an output overvoltage protection).
If the feature is not required, the pin must be connected to GND, which excludes the function.
Direct feedback . It is the inverting input of the internal transconductance E/A, internally referenced to
1.2 V with respect to GND. In non-isolated converter, the output voltage information is directly fed into the pin through a voltage divider. In primary regulation, the FB voltage divider is connected to the VCC. The
E/A is disabled if FB is connected to GND pin.
DS13285 - Rev 3 page 2/40
VIPER31
Pin setting
Pin number
Name Function
8
9 to 12
COMP
N.C.
13 to 16 DRAIN
Compensation . This is the output of the internal E/A. A compensation network is placed between this pin and GND to achieve stability and good dynamic performance of the control loop. In case of secondary feedback, the internal E/A must be disabled and the COMP directly driven by the optocoupler to control the DRAIN peak current setpoint.
Not connected.
These pins must be left floating in order to get a safe clearance distance.
MOSFET drain . The internal high-voltage current source sources current from these pins to charge the VCC capacitor at startup. The pins are mechanically connected to the internal metal PAD of the
MOSFET in order to facilitate heat dissipation. On the PCB, some copper areas under these pins decreases the total junction-to-ambient thermal resistance thus facilitating the power dissipation.
DS13285 - Rev 3 page 3/40
2
VIPER31
Electrical and thermal ratings
Electrical and thermal ratings
Table 2. Absolute maximum ratings
Symbol
V
DS
I
DRAIN
V
CC
Drain-to- source (ground) voltage
Pulsed drain current (pulse-width limited by SOA)
VCC voltage -0.3
Min.
800
3
Max.
30.5V
V
V
OVP
UVP
OVP voltage
UVP voltage
-0.3
-0.3
Internally
Internally
V
V
FB
COMP
FB voltage
COMP voltage
-0.3
-0.3
P
TOT
T
J
T
STG
Power Dissipation @ Tamb < 50°C
Junction Temperature operating range
Storage Temperature
-40
-55
1. stresses beyond those listed absolute maximum ratings may cause permanent damage to the device.
2. exposure to absolute-maximum-rated conditions for extended periods may affect the device reliability
3. by internal clamp between 4.75 V and 5.25 V or Vcc + 0.6 V, whichever is lower
4. the AMR value is intended when VCC ≥ 5 V, otherwise the value VCC + 0.3 V has to be considered.
5. when mounted on a standard single side FR4 board with 100 mm² (0.155² inch) of Cu (35 μm thick)
Internally
150
150
V
A
V
V
V
V
V
W
°C
°C
Unit
Table 3. Thermal data
Symbol Parameter
Max. value
SO16N
R
R
R
R
TH-JC
TH-JA
TH-JC
TH-JA
Thermal resistance junction to case (1)
(dissipated power = 1W)
Thermal resistance junction to ambient
(dissipated power = 1W)
Thermal resistance junction to case (2)
(dissipated power = 1W)
Thermal resistance junction to ambient
(dissipated power = 1W)
10
120
5
85
1. when mounted on a standard single side FR4 board with minimum copper area
2. when mounted on a standard single side FR4 board with 100mm² (0.155² inch) of Cu (35 μm thick)
Unit
°C/W
°C/W
°C/W
°C/W
DS13285 - Rev 3 page 4/40
Figure 2. R th_JA versus copper area
1.500
R thJA
/(R thJA
@ A = 100mm 2 )
1.375
1.250
1.125
1.000
0.875
0.750
0 25 50 75 100
A (mm 2 )
125 150 175 200 225
VIPER31
Electrical characteristics
2.1
Table 4. Avalanche characteristics
I
Symbol
AR
EAS
Parameter
Avalanche current
Single pulse avalanche energy
Condition
Repetitive and non-repetitive.
Pulse-width limited by T
Jmax
I
AS
= I
AR
,
V
DS
= 100 V,
Starting T
J
= 25°C
1. Parameter derived by characterization
Electrical characteristics
Tj = -40 to 125°C, V
CC
= 9 V (unless otherwise specified)
Min.
Symbol
V
BVDSS
Parameter
Breakdown voltage
I
DSS
Drain-source leakage current
I
OFF
R
DS(on)
OFF state drain current
Static drain-source
ON ‑ resistance
Table 5. Power section
Test condition
I
DRAIN
= 1 mA, V
COMP
= V
GND
,
T
J
= 25°C
V
DS
= 400 V, V
COMP
= V
GND
,
T
J
= 25°C
V
DRAIN
= max. rating,
V
COMP
= V
GND
, T
J
= 25°C
I
DRAIN
= 400 mA, T
J
= 25°C
I
DRAIN
= 400 mA, T
J
= 125°C
Typ.
Max.
1.15
A
Unit
3
Min.
800
Typ.
Max.
Unit
V
1
60
3.5
7 mJ
µA
µA
Ω
Ω
DS13285 - Rev 3 page 5/40
VIPER31
Electrical characteristics
Note:
Table 6. Supply section
Symbol Parameter
High-voltage startup current source
V
BVDSS_SU
Breakdown voltage of startup
MOSFET
T
J
= 25°C
Test condition
I
I
V
HV_START
Drain-source startup voltage
I
I
R
G
CH1
CH2
Startup resistor
V
FB
> V
FB_REF
,
V
DRAIN
= 400 V,
V
DRAIN
= 600 V
V
CC charging current at startup V
DRAIN
= 100V, V
CC
≤ 1V
V
CC
charging current
V
FB
> V
FB_REF
, V
DRAIN
= 100V
1V < V
CC
<V
CCon
IC supply and consumptions
V
CC
Operating voltage range
V
Ccon
V
V
Cson
Ccoff
VCC startup threshold
HV current source turn-on threshold
UVLO
V
CC falling q
CC
Quiescent current
Operating supply current, switching
Not switching,
V
FB
> V
FB_REF
X, L versions
H version
V
DS
F
= 150 V, V
OSC
= 30 kHz
COMP
= 1.2 V,
V
DS
F
= 150 V, V
OSC
= 60 kHz
COMP
= 1.2 V,
V
F
DS
= 150 V, V
COMP
= 1.2 V,
OSC
= 132 kHz
Min.
Typ.
Max.
Unit
800
24
V
V
54 MΩ 36 45
0.5
7.6
1
8.8
1.5
10 mA
4.5
7.5
4
3.75
8
4.25
4
1.25
30
8.5
4.5
4.25
0.35
0.48
1.7
1.5
2.25
2
2.8
V
V
V
V mA mA
1.
Current supplied only during the main MOSFET OFF time.
2.
Parameter assured by design and characterization.
DS13285 - Rev 3 page 6/40
DS13285 - Rev 3
VIPER31
Electrical characteristics
Table 7. Controller section
E/A
Symbol
V
FB_REF
V
FB_DIS
I
FB_PULL UP
Parameter
Reference voltage
E/A disable voltage
Pull-up current
Test condition
I
I
G
COMP1
COMP2
R
M
COMP(DYN)
Trans conductance
Max. source current
Max. sink current
Dynamic resistance
V
COMP
=1.5 V,
V
FB >VFBREF
V
COMP
=1.5 V,
V
FB
=0.5 V
V
FB
=2 V,
V
COMP
=1.5 V
V
COMP
=2.7 V,
V
FB
=G
ND
V
COMPH
V
COMPL
Current limitation threshold
PFM threshold
H
COMP
ΔV
COMP
/ΔI
DRAIN
VIPER31 7 *
VIPER31 8 *
VIPER31 9 *
I
I
I
OLP and timing
DLIM
2 f
Dlim_PFM
Drain current limitation
Power coefficient
I
DLIM_TYP
2 x F
OSC_TYP
Drain current limitation at light load
T
J
= 25°C , VIPER31 7 *
T
J
= 25°C , VIPER31 8 *
T
J
= 25°C , VIPER31 9 *
VIPER31 7
VIPER31 8
VIPER31 9
VIPER317L
VIPER317H
VIPER318X
VIPER318L
VIPER318H
VIPER319X
VIPER319L
VIPER319H
T
J
=25°C, V
COMP
=V
COMPL
VIPER31 7 *
T
J
=25°C, V
COMP
=V
COMPL
VIPER31 8
T
J
=25°C, V
COMP
=V
COMPL
VIPER31 9
Min.
13
2.75
0.6
3.8
3.2
2.9
Typ.
Max.
Unit
1.175
150
0.9
400
1.2
180
1
550
1.225
210
1.1
700
V mV
µA
µA/V
75
75
100
100
15
3.1
0.8
4.2
3.5
3.2
125 µA
125 µA
17
3.45
1
4,6
3.8
3.5
V/A kΩ
V
V
675
810
940
639
765
891
-10%
80
710
850
990
710
850
990
30.2
66.5
21.7
43.4
95.4
29.4
58.8
129.4
110
745
890
1040
781
935
1089 mA
+10% A 2 ·kHz
140
100
120
130
150
160 mA
180 page 7/40
DS13285 - Rev 3
VIPER31
Electrical characteristics
Symbol t
OVL t
OVL_max t
SS
Parameter
Overload delay time
Max. overload delay time
Soft-start time
Test condition
When in pulse skipping
Min.
45
5 t
ON_MIN
Minimum turn-on time
V
CC
=9 V,
V
COMP
=1 V,
V
FB
=V
FB_REF
250 t
RESTART
UVP
Restart time after fault 0.625
V
UVP_th
UVP threshold
V
CC
=9 V,
V
COMP
=1 V,
V
FB=VFB_REF
0.38
t t
I
UVP_pull- up
UVP_DEB
UVP_REST
UVP pull-up current
Debounce time before UVP tripping
Debounce time for restoring normal operation from UVP
Quiescient current during UVP Not switching, V
FB
>V
FB_REF
18.75
18.75
I q_DIS
OVP
V
OVP_th
Overvoltage protection threshold
V
CC
=9 V,
V
COMP
=1 V,
V
FB
=V
FB_REF
3.85
t t
OVP_DEB
OVP_REST
Debounce time before OVP tripping
Restart time after overvoltage protection tripping
156
312
Oscillator
F
OSC
F
OSC MIN
F
D
F
M
D
MAX
Switching frequency
Min. switching frequency
Modulation depth
Modulation frequency
T
J
=25ºC VIPER31*X
T
J
= 25ºC, VIPER31*L
T
J
= 25ºC, VIPER31*H
T
J
= 25ºC
27
54
119
13.5
T
SD
Max. duty cycle
Thermal shutdown protection
Thermal shutdown temperature threshold
70
150
1. Measured at Vin = 100 Vdc in Flyback topology, with 1.5 mH transformer primary inductance
2. See
Section 4.10 Pulse frequency modulation
3. See
4. Parameter assured by design and characterization.
Typ.
50
8
300
1
0.4
-1
30
30
0.25
4
250
500
30
60
132
15
±7·F
OSC
200
160
Max.
55
100
11
350
1.375
0.42
41.25
41.25
0.35
4.15
344
688
33
66
145
16.5
80
µs ms kHz
%
Hz
%
Unit ms ms ms ns s
V
V kHz
°C
µA ms ms mA page 8/40
VIPER31
Typical electrical characteristics
3 Typical electrical characteristics
Figure 3. I
DLIM
vs. T
J
1.2
I
DLIM
/(I
DLIM
@25°C)
1.1
1
0.9
0.8
-50 -25 0 25 50
T j
[°C]
75 100 125 150
Figure 4. F
OSC vs. T
J
1.1
F
OSC
/(F
OSC
@25°C)
1.05
1
0.95
0.9
-50 -25 0 25 50
T j
[°C]
75 100 125 150
Figure 5. V
HV_START
vs. T
J
1.2
V
HV_START
/(V
HV_START
@25°C)
1.1
1
0.9
0.8
-50 -25 0 25 50
T j
[°C]
75 100 125 150
Figure 7. Quiescent Current I q
vs. T
J
1.1
I q
/(I q
@25°C)
1.05
1
0.95
0.9
-50 -25 0 25 50
T j
[°C]
75 100 125 150
Figure 6. VF
B_REF
vs. T
J
1.05
V
FB_REF
/(V
FB_REF
@25°C)
1.025
1
0.975
0.95
-50 -25 0 25 50
T j
[°C]
75 100 125 150
Figure 8. Operating current I
CC
vs. T
J
1.2
I
CC
/(I
CC
@25°C)
1.1
1
0.9
0.8
-50 -25 0 25
T j
50
[°C]
75 100 125 150
DS13285 - Rev 3 page 9/40
Figure 9. I
CH1 vs. T
J
1.5
I
CH1
/(I
CH1
@25°C)
1.3
1.1
0.9
0.7
0.5
-50 -25 0 25 50
T j
[°C]
75 100 125 150
Figure 11. I
CH1
vs. V
DRAIN
1.1
I
CH1
/(I
CH1
@V
DRAIN
= 100V)
1.05
1
0.95
0.9
0 100 200 300 400
V
DRAIN
[V]
500 600 700 800
1.2
G
M
/(G
M
@25°C)
Figure 13. G
M
vs. T
J
1.1
1
0.9
0.8
-50 -25 0 25
T j
50
[°C]
75 100 125 150
VIPER31
Typical electrical characteristics
Figure 10. I
CH2
vs. T
J
1.2
I
CH2
/(I
CH2
@25°C)
1.1
1
0.9
0.8
-50 -25 0 25 50
T j
[°C]
75 100 125 150
Figure 12. I
CH2 vs. V
DRAIN
1.1
I
CH2
/(I
CH2
@V
DRAIN
=100V)
1.05
1
0.95
0.9
0 100 200 300
V
400
DRAIN
[V]
500 600 700 800
Figure 14. I
COMP
vs. T
J
1.1
I
COMP
/(I
COMP
@25°C)
1.05
1
0.95
0.9
-50 -25 0 25
T j
50
[°C]
75 100 125 150
DS13285 - Rev 3 page 10/40
VIPER31
Typical electrical characteristics
Figure 15. R
DSON
vs. T
J
2.50
R
DS(on)
/(R
DS(on)
@25°C)
1.00
0.50
2.00
1.50
0.00
-50 -25 0 25 50
T j
[°C]
75 100 125 150
Figure 17. Static drain-source on resistance
1.04
1
0.96
0.92
0.88
-50
Figure 19. V
BVDSS
vs. T
J
1.12
V
(BR)DSS
/ (V
(BR)DSS
@ 25 0 C)
1.08
0
I
D
= 1 mA
50
T
J
[°C]
100 150
1
0.5
Figure 16. R
DSON
1.5
R
DS(on)
/(R
DS(on)
@I
DRAIN
= 360mA)
vs. I
DRAIN
T = 25°C
0
0 50 100 150 200
I
DRAIN
[mA]
250 300 350 400
Figure 18. Power MOSFET C
OSS
vs. V
DS
@ V
GS
=0, f=1MHz
10000
C
OSS
[pF]
1000
100
10
1
0 1 10
V
DS
[V]
100 1000
4.8
4.4
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0.0
Figure 20. Output characteristic
I
DRAIN
[A]
4.0
8.0
12.0
16.0
-40°C
25°C
125°C
V
DS
[V]
DS13285 - Rev 3 page 11/40
10
I
D
[A]
Figure 21. SOA SO16N package
1
0.1
0.01
0.1
R
DS(on) limit
1 10 100 t p
= 1 m s t p
= 10 m s
1000 t p
= 100 m s t p
=
1 ms
V [V]
VIPER31
Typical electrical characteristics
2
1
0
-50
Figure 22. Maximum avalanche energy vs. Tj
4
E
AS
[mJ]
I
D
Single pulse,
= 1A, V
DD
= 50 V
3
0 50
T j
[°C]
100 150
DS13285 - Rev 3 page 12/40
4
4.1
4.2
VIPER31
General description
General description
Block diagram
COMP
FB
V
FB_REF
-
+
E/A
Figure 23. Block diagram
VCC
IC_DIS
I
CH*
I
HV
IC DISABLE
LOGIC
S
Q
R
REGULATOR
4V
Internal Supply bus
LIGHT LOAD PFM
SOFT START
I
DLIM ref
+
OCP
LEB
+
-
PWM
IC_DIS_SET IC_DIS_RESET
OCP t
UVP_DEB filter
JITTERED
OSCILLATOR
TURN ON
LOGIC t
OVL filter
UVLO VCC
VCC_clamp t
OVP_DEB filter t
UVP_REST filter
IC_DIS
OTP
HV DISABLE
LOGIC
S
R
Q
PROTECTION t
LOGIC
RESTART
OVP LOGIC t
OVP_REST
T
SD t
LOGIC
RESTART
V
UVP_th - V
OVP_th
R
SENSE
HV
Start up
DRAIN
V z
R
G
THERMAL
DIODE
(OTP)
UVP OVP
Typical power capability
Table 8. Typical power
Adapter
27 W
Vin: 230 V
AC
31 W
16 W
Vin: 85-265 V
19 W
AC
1. Typical continuous power in non-ventilated enclosed adapter measured at 50°C ambient.
2. Maximum practical continuous power in an open frame design at 50°C ambient, with adequate heat sinking.
GND
DS13285 - Rev 3 page 13/40
Figure 24. Typical deliverable output power vs. T
AMB
(Vin: 85-265V
AC
)
VIPER31
Primary MOSFET
4.3
4.4
Primary MOSFET
The primary switch is implemented with an avalanche rugged N-channel MOSFET with 800 V minimum breakdown voltage, V
BVDSS
, and 3.5 Ω maximum on-resistance, R
DS(on)
.
The sense-FET is embedded and allows a virtually lossless current sensing.
The MOSFET gate driver controls the gate current during both turn-on and turn-off in order to minimize common mode EMI. Under UVLO conditions the embedded pull-down circuit holds the gate low in order to ensure that the
MOSFET cannot be turned on accidentally.
High-voltage startup
The embedded high-voltage startup includes both the 800 V startup FET, whose gate is biased through the resistor R
G
, and the switchable HV current source, delivering the current I
HV
. The major portion of I
HV
, (I
CH
), charges the capacitor connected to VCC pin. A minor portion is sunk by the controller block.
Power on: at startup, as the voltage across the DRAIN pin exceeds the V
HV_START
threshold, the HV current source is turned on, charging linearly the VCC capacitor with the current I
CH2
(8.8 mA typ.). This charging current is reduced to I
CH1
(1 mA typ.) in case V
CC
is lower than 1 V (typical value), in order to limit IC power dissipation in case the pin is accidentally shorted to GND.
As V
CC
reaches the startup threshold, V
CCon
, the chip starts operating, the primary MOSFET is enabled to switch, the HV current source is disabled and the device is powered by the energy stored in the VCC capacitor. The IC can be supplied through a transformer auxiliary winding or, in case of not isolated topologies with V
OUT
≥ 5 V, directly from the converter’s output.
The supply operating range is from 4.5 V to 30.5 V. If VCC pin voltage exceeds 30.5 V (referred to V
GND
), the internal clamp could be reached, which causes the VIPER31 to stop switching.
This condition is potentially dangerous for the VIPER31 and must be avoided, by means of proper transformer design and/or external protection (zener diode between VCC and GND pins).
In normal operation the HV current source is always kept off by maintaining V
CC consumption is given by the power dissipated on R
G
only, calculated as follows:
above V
Cson
, so its residual
Equation 1
(1)
P
HV
(V
IN
) = V
IN
2 /R
G
DS13285 - Rev 3 page 14/40
VIPER31
Soft startup
At nominal input voltage (230 V
AC
), typical and worst-case consumptions are 2.4 mW and 3.0 mW respectively
(corresponding to R
G
_typ = 45 Mohm and R
G
_min = 36 Mohm). This means that, with a careful design, the overall no-load input power consumption of the application can be maintained very low (typically, below 10 mW
@230 V
AC
)
Power-off: when the IC is disconnected from the mains, or there is a mains interruption, for some time the converter keeps on working, powered by the energy stored in the input bulk capacitor. When it is discharged below a critical value, the converter is no longer able to keep the output voltage regulated. During the power down, when the DRAIN voltage becomes too low, the HV current source remains off and the IC is stopped as soon as V
CC
drops below the UVLO threshold, V
Ccoff
.
Figure 25. Power ON and power OFF
V
IN_DC
Power-off:
V
IN decreases
V
HV_START
Power-on:
HV current source enabled t
V
DRAIN
4.5
t
V
CC
V
CCon
V
CSon
V
CCoff
HV current source is disabled here
I
CH1
I
CH2
1V
HV current source is no more activated because of too low V
DRAIN
UVLO t
V
OUT
Power-on
Output regulation is lost here
Power-off t
Steady-state
Soft startup
The internal soft-start function of the VIPer31 progressively increases the cycle-by-cycle current limitation set point from zero up to I
DLIM
.
The soft-start time, t
SS
, which is internally set at 8 ms, is activated at any attempt of converter power-on and at any restart after a fault event.
The feature is used to reduce the stress of the power components and increase the reliability of the system.
DS13285 - Rev 3 page 15/40
4.6
4.7
VIPER31
Oscillator
I
DRAIN
I
DLIM
Figure 26. Soft startup
Soft start phase t
SS
Steady state time
V
COMP
V
COMPH time
V
OUT
V
OUT time
Oscillator
The IC embeds a fixed frequency oscillator with jittering feature. The switching frequency is modulated by approximately ±7%·F
OSC
at 200 Hz rate. The purpose of the jittering is to get a spread-spectrum action that distributes the energy of each harmonic of the switching frequency over a number of frequency bands, having the same energy on the whole but smaller amplitudes. This helps to reduce the conducted emissions, especially when measured with the average detection method or, which is the same, to pass the EMI tests with an input filter of smaller size with respect to the one that should be needed in absence of jittering feature. Three switching frequency options, F
OSC
, are available: 30 kHz (X type), 60 kHz (L type) and 132 kHz (H type).
Pulse skipping
The IC embeds a pulse skip circuit that operates in the following way:
•
•
Each time the DRAIN peak current exceeds I
DLIM
level within t
ON_MIN
, the next switching cycle is skipped.
The cycles can be skipped until the minimum switching frequency F
OSC_MIN
(15 kHz) is reached.
Each time the DRAIN peak current does not exceed I
DLIM
within t
ON_MIN
, the next switching cycle is restored. The cycles can be restored until the nominal switching frequency FOSC is reached.
The protection is intended in order to avoid the so called “flux runaway” condition often present at converter startup and due to the fact that the primary MOSFET, which is turned on by the internal oscillator, cannot be turned off before the minimum on-time.
During the on-time, the inductor is charged through the input voltage and, if it cannot be discharged by the same amount during the off-time, in every switching cycle there is a net increase of the average inductor current, that can reach dangerously high values until the output capacitor is not charged enough to ensure the inductor discharge rate needed for the volt-second balance. This condition is common at converter startup, because of the low output voltage.
In the following
Figure 27. Pulse skipping during startup the effect of pulse skipping feature on the DRAIN peak
current shape is shown (solid line), compared with the DRAIN peak current shape when pulse skipping feature is not implemented (dashed line). Providing more time for cycle-by-cycle inductor discharge when needed, this feature is effective in keeping low the maximum DRAIN peak current avoiding the flux runaway condition.
DS13285 - Rev 3 page 16/40
VIPER31
Direct feedback
V
OUT
V
OUT_nom
Figure 27. Pulse skipping during startup
I
DRAIN
I
DLIM time without pulse skipping with pulse skipping
4.8
4.9
4.10
time skipped cycles
Direct feedback
The IC embeds a transconductance type error amplifier (E/A) whose inverting input and output are FB and
COMP, respectively. The internal reference voltage of the E/A is V
FB_REF
(1.2 V typical value referred to GND).
In non-isolated topologies, a positive output voltage can be tightly set through a simple voltage divider applied among the output voltage terminal, FB and GND.
The E/A output is scaled down and fed into the PWM comparator, where it is compared to the voltage across the sense resistor in series to the sense-FET, thus setting the cycle-by-cycle drain current limitation.
An R-C network connected on the output of the error amplifier (COMP) is usually used to stabilize the overall control loop.
The FB is provided with an internal pull-up to prevent a wrong IC behavior when the pin is accidentally left floating.
The E/A is disabled if the FB voltage is lower than V
FB_DIS
(200 mV, typ).
Secondary feedback
When a secondary feedback is required, the internal E/A has to be disabled shorting FB to GND (V
FB
< V
FB_
D
IS
With this setting, COMP is internally connected to the parallel of a 100 uA current generator and the 15 kΩ (typ.)
).
R
COMP(DYN)
resistor, and the voltage across COMP is set by the current sunk.
This allows to set the output voltage value through an external error amplifier (TS431 or similar) placed on the secondary side, whose error signal is used to set the DRAIN peak current setpoint corresponding to the output power demand. If isolation is required, the error signal must be transferred through an optocoupler, with the phototransistor collector connected across COMP and GND.
Pulse frequency modulation
If the output load is decreased, the feedback loop reacts by lowering V
COMP,
which reduces the DRAIN peak current setpoint. The minimum value is I
DLIM_PFM
, corresponding to the V
COMPL
threshold.
If the load is further decreased, the DRAIN peak current value is maintained at I
DLIM_PFM
and some PWM cycles are skipped. This kind of operation is referred to as “pulse frequency modulation” (PFM), the number of the skipped cycles depending on the balance between the output power demand and the power transferred from the input. The result is an equivalent switching frequency which can go down to some hundreds Hz, thus reducing all the frequency-related losses.
DS13285 - Rev 3 page 17/40
VIPER31
Overload protection
4.11
This kind of operation, together with the extremely low IC quiescent current, allows very low input power consumption in no-load and light load, while the low DRAIN peak current value, I
DLIM_PFM
, prevents any audible noise which could arise from low switching frequency values. When the output load is increased, V
COMP increases and PFM is exited. V limitation (IDLIM).
COMP
reaches its maximum at V
COMPH
, corresponding to the DRAIN current
Overload protection
In order to manage the overload condition the IC embeds the following main blocks: the OCP comparator to turn off the power MOSFET when the drain current reaches its limit (I
DLIM
), the up and down OCP counter to define the turn-off delay time in case of continuous overload (t
OVL
= 50 ms typ.) and the timer to define the restart time after protection tripping (t
RESTART
= 1 sec, typ.).
In case of short-circuit or overload, the control level on the inverting input of the PWM comparator is greater than the reference level fed into the inverting input of the OCP comparator. As a result, the cycle-by-cycle turn off of the power switch is triggered by the OCP comparator instead of by the PWM comparator. Every cycle this condition is met, the OCP counter is incremented. If the fault condition persists for a time greater than t
OVL
(corresponding to the counter end-of-count), the protection is tripped, the PWM is disabled for t
RESTART
, then it resumes switching with soft-start and, if the fault is still present, it is disabled again after t
OVL
. The OLP management prevents the IC from being indefinitely operated at I
DLIM
and the low repetition rate of the restart attempts of the converter avoids overheating the IC in case of repeated fault events.
After the fault removal, the IC resumes working normally. If the fault is removed before the protection tripping
(before t
OVL
), the t
OVL
counter is decremented on a cycle-by-cycle basis down to zero and the protection is not tripped. If the fault is removed during t
RESTART resuming switching.
, the IC waits for the t
RESTART
period ot have elapsed before
In fault condition, V
CC
is kept between V which recharges the VCC capacitor to V
CSon
and V
CCon
by the periodical activation of the HV current source,
Ccon
any time the IC internal consumption discharges it to V
Cson
.
Overload applied
Figure 28. Overload protection
Overload removed V
CC
V
CCon
V
CSon
I
DRAIN
I
DLIM time
4.12
t
OVL t
OVL time t
RESTART t
RESTART t
SS t
SS
Undervoltage protection
If the voltage across the UVP pin (V
UVP
) falls below the internal threshold V
UVP_th
(0.4 V typ.) for a time greater than t
UVP_DEB
(30 ms, typ.), the IC is disabled and its consumption is reduced to ultra-low values (I q_DIS
).
When V
UVP rises above V
UVP_th
, the IC must wait t
UVP_REST
(30 ms, typ.) before resuming switching.
Both t
UVP_DEB
and t
UVP_REST
are intended to filter out possible noises/disturbances of the line, which could affect the correct operation of the function. They are obtained through two separate up/down counters:
DEB (REST) up/down counter has a deb_eoc (rest_eoc) end-of-count. The operation is illustrated in
If the counter starts from zero and counts always up, end-of-count is reached in a time interval t
UVP_DEB
(t
UVP_REST
).
DS13285 - Rev 3 page 18/40
DS13285 - Rev 3
VIPER31
Undervoltage protection
If V
UVP
falls below V
UVP_th
, the DEB counter is incremented. If V
UVP
increases above V
UVP
_th before uvp_eoc is reached, the counter is decremented. If the count goes back down to zero, a disturbance on the UVP pin is assumed and there is no consequence on the IC behavior.
If V
UVP
stays below V
UVP_th
until the counter reaches deb_eoc: the device is disabled; most of the internal blocks are turned off and the internal consumption is reduced to I q_DIS
; V
CC
is maintained between V
Cson
and V
Ccon by the periodical activation of the internal HV-current source; the DEB counter is reset. Of course, if during the count-up V
UVP
exceeds V
UVP_th for some time, the DEB counter is decremented during that time and the IC disable is delayed accordingly.
With IC disabled: if V
UVP
rises above V
UVP_th
, the REST counter is incremented, and when it reaches rest_eoc
(corresponding to t
UVP_REST
), the IC resumes switching. Of course, if during the count-up, V
UVP
falls below
V
UVP_th
for some time, the REST counter is decremented during that time and the IC re-enabling is delayed accordingly.
Figure 29. UVP timing
V
UVP
V
UVP
_th
V
DD
V
CCon
V
CSon
DEB counter deb_eoc
REST counter rest_eoc
< t
UVP_DEB t
UVP_DEB
I
DRAIN
IC disabled t
UVP_REST
Restart delay
IC re-enabled normal operation disabled with ultra-low consumption (I q_DIS
) normal operation
An input undervoltage protection can be easily realized connecting the rectified mains to UVP pin through a voltage divider, as shown in
Figure 30. Connection for input undervoltage protection/disable (isolated or nonisolated topologies)
.
page 19/40
DS13285 - Rev 3
VIPER31
Undervoltage protection
Figure 30. Connection for input undervoltage protection/disable (isolated or non-isolated topologies)
~ AC D
IN
C
IN
RH
Cs from V
AUX or V
OUT
OVP
VCC
VIPER31
DRAIN
CONTROL
FB
COMP UVP GND
GND
RL C1
R2
C2
If UVP function is not required, the UVP pin must be left floating. In this case, noise immunity of the pin is guaranteed by the internal pull-up I
UVP_pull-up
(1 uA, typ.) present in the UVP block.
If UVP function is required, RH value can be set arbitrarily, but some Mohms at least are recommended in order to minimize the power consumption of the UVP network. Then, if V in_UVP is the desired input undervoltage threshold, the value of RL can be found from the following formula:
Equation 2
(2)
RL =
VUVP_th
Vin_UVP − VUVP_th
RH
+ IUVP_pull − up
Equation 3
(3)
PUVP Vin =
Vin2
RH + RL
Thanks to the ultra-low consumption, the UVP pin can be used as an input to disable the SMPS from external, reaching the lowest input power consumption while the SMPS is still connected to the AC mains but not delivering power to its output.
The purpose of the UVP debounce time t
UVP_DEB
is also to guarantee some hold-up in case of a missing cycle of the input line, as illustrated in
Figure 31. Hold-up in case of input line missing cycles .
page 20/40
VIPER31
Overvoltage protection
V
BULK
Figure 31. Hold-up in case of input line missing cycles
1 missing cycle 2 missing cycles
V
UVP_th
V
UVP
I
DRAIN t
UVP_DEB t
UVP_DEB
IC disabled here
4.13
Overvoltage protection
If the voltage across OVP pin (V
OVP
) exceeds the internal threshold V
OVP_th
(4 V typ.) for a time greater than t
OVP_DEB
(250 us, typ.), the PWM is disabled in autorestart for t
OVP_REST
time (500 ms, typ.), until V
OVP
falls below V
OVP_th
.
The time interval t
OVP_DEB
is intended to filter out possible noises/disturbances of the line, which could affect the correct operation of the function, and is obtained through an up/down counter, where t
OVP_DEB
is the time the counter needs to reach its end-of-count (ovp_eoc) starting from zero and counting always up.
The operation is shown in Figure 32. OVP timing
. When V
OVP
exceeds V
OVP_th
, the up/down OVP counter is incremented.
If V
OVP
falls below V
OVP_th
before the OVP counter reaches ovp_eoc, the counter is decremented. If the count goes down to zero, a disturbance on the OVP pin is assumed and there is no consequence on the IC behavior.
t
If V
OVP stays above V
OVP_th
until the OVP counter reaches ovp_eoc: the PWM is disabled in autorestart for a
OVP_REST
time interval; the OVP counter is reset; V
CC
is maintained between V
Cson
and V
Ccon
by the periodical activation of the internal HV-current source. Of course, if during the count-up V
OVP
falls below V
OVP_th
for some time, during that time the counter is decremented and the PWM disable is delayed accordingly.
When V
OVP
drops below V
OVP_th
, the IC waits for the end of t
OVP_REST
, then restarts with soft-start phase.
DS13285 - Rev 3 page 21/40
DS13285 - Rev 3
Figure 32. OVP timing
V
OVP
_th
V
OVP
V
CCon
V
CSon
V
DD ovp_eoc
OVP count
GD
< t
OVP_DEB t
OVP_DEB t
OVP_REST t
OVP_DEB t
OVP_REST OVP check and
IC re-enabled
VIPER31
Overvoltage protection
OVP triggered and IC disabled
OVP check and
IC disabled
An input overvoltage protection can be easily realized connecting the rectified mains to OVP pin through a voltage
In case of non-isolated topologies, with the same principle an output overvoltage protection can be implemented, as shown in
Figure 34. Connection for output overvoltage protection (non-iso topologies)
.
If the OVP feature is not required, OVP pin must be connected to GND, which excludes the function.
If the OVP feature is required, RH value can be set arbitrarily, but some Mohms at least are recommended in order to minimize the power consumption of the OVP network. Then, if V in/out_OVP
is the desired input/output overvoltage threshold, the value of RL can be calculated from the following formula:
Equation 4
(4)
RL =
RH
Vin/out_OVP
VOVP_tℎ − 1
The power consumption of the OVP network at given Vin is expressed as:
Equation 5
(5)
POVP Vin =
Vin2
RH + RL in case of connection for input overvoltage protection and
Equation 6
(6)
POVP VOUT =
VOUT2
RH + RL in case of connection for output overvoltage protection.
page 22/40
VIPER31
Undervoltage and overvoltage protection
Figure 33. Connection for input overvoltage protection (iso/non-iso topologies)
~ AC D
IN
C
IN
RH
Cs from V
AUX or V
OUT
OVP
VCC
VIPER31
DRAIN
CONTROL
FB
COMP UVP GND
GND
RL C1
R2
C2
Figure 34. Connection for output overvoltage protection (non-iso topologies)
D
OUT
V
OUT
C
OUT
Cs from V
AUX or V
OUT
OVP
VCC
VIPER31
DRAIN
CONTROL
FB
COMP UVP GND
Rfb1 RH
GND
4.14
C1
R2
C2
Rfb2 RL
Undervoltage and overvoltage protection
If both undervoltage and overvoltage protections are required, they can be set independently from each other through a single voltage divider, as illustrated in the figure below.
DS13285 - Rev 3 page 23/40
DS13285 - Rev 3
VIPER31
Undervoltage and overvoltage protection
Figure 35. Connection for input and output overvoltage protections (iso/non-iso topologies)
~ AC D
IN from V
AUX or V
OUT
RH
C
IN
RM
Cs
OVP
VCC
VIPER31
DRAIN
CONTROL
FB
COMP UVP GND
GND
RL C1
R2
C2
The voltage divider equations are:
Equation 7
(7)
V in_UVP
=
VUVP tℎ
RL
− I
UVP_pull − up
· RH + RM + RL + RL · I
UVP_pull − up
Equation 8
(8)
V in_OVP
= V
OVP tℎ
−
RH
RH + RM + RL
· RL · I
UVP_pull − up
·
RH + RM + RL
RM + RL
Equation 7.a
(7.a)
V in_UVP
Equation 8.a
− I
UVP_pull − up
· RH + RL · I
UVP_pull − up
(8.a)
V in_OVP
V
OVP tℎ
− RL · I
UVP_pull − up
·
RH
RM + RL
Selecting arbitrarily the RH value, Equation
Equation 9
(9)
RL =
Vin_UVP + IUVP_pull − up · RH − Vin_UVP + IUVP_pull − up · RH
2 · IUVP_pull − up
2 − 4 · VUVP tℎ · IUVP_pull − up · RH
Equation 10 page 24/40
VIPER31
Thermal shutdown
4.15
(10)
RM = V
OVP tℎ
− RL · I
UVP_pull − up
·
RH
Vin_OVP
− RL
The power consumption of the UVP-OVP network at given Vin is expressed as:
Equation 11
(11)
P
UVP_OVP
V in
=
Vin
RH + RM + RL
As an example, if V in_UVP
and V in_OVP
design values are 50 Vdc and 450 Vdc respectively, and RH is set to 6
10 we have RL = 43 kohm, and RM = 60 kohm respectively, while from Equation 11
the power consumption of the network at 230 Vac is about 17 mW.
Thermal shutdown
The power MOSFET junction temperature is sensed during the on-time through a diode integrated into the HV section of the chip. If a junction temperature higher than the internal threshold TSD (160°C, typ.) is measured, the
PWM is disabled for t
RESTART
. In order to increase robustness against electromagnetic noises, the protection is triggered only if the condition is met for nth = 3 consecutive switching cycles.
After t
RESTART
, the IC resumes switching with soft-start phase: if a junction temperature above TSD is still measured for nth consecutive switching cycles, the protection is triggered and PWM is disabled again for t
RESTART
; otherwise normal operation is restored.
During t
RESTART
, V
CC is maintained between V
Cson
and V
Ccon
by the HV current source periodical activation.
Such a behavior is summarized in Figure 36. Thermal shutdown timing diagram
.
Figure 36. Thermal shutdown timing diagram
T
J
T
SD t
V
CC
V
CCon
V
CSon t
GD n < n th n = n th n = n th t t
RESTART t
RESTART
DS13285 - Rev 3 page 25/40
5
5.1
Application information
Typical schematics
~ AC
Figure 37. Flyback converter (non-isolated)
Daux
Din Rin
T
Dout
Ccl
Cout
Cin
Rcl
Cs
VCC
VIPER31
DRAIN
OVP
CONTROL
FB
COMP UVP GND
RH
Vout
GND
C1
R2
C2
RL
VIPER31
Application information
~ AC
GND1
Cs
Din
Figure 38. Flyback converter (isolated)
Rin T Dout
Cin Ccl
Cout
Rcl
Raux
Daux
VCC
VIPER31
DRAIN
OVP
FB
CONTROL
COMP UVP GND
OPTO
R3
R4
C2
RH
Vout
GND2
OPTO
C1
RL
DS13285 - Rev 3 page 26/40
DS13285 - Rev 3
~ AC
Din
Figure 39. Flyback converter (primary regulation)
Dout
Rin T
Ccl
Rcl
Cout
Vout
GND2
Cin
Cs
RH
RL
Daux
VCC
VIPER31
DRAIN
OVP
FB
CONTROL
COMP UVP GND
C2
C1
R2
GND1
~ AC
Din Rin
GND
Cin
Figure 40. Buck converter
Daux
VCC
VIPER31
DRAIN
OVP
FB
CONTROL
COMP UVP GND
Cs
RH
C3
RL
R2
C1
C2
D1
Lout
D2
Vout
Cout
GND
~ AC
Din Rin
Cin
Figure 41. Buck-boost converter
Daux
VCC
VIPER31
DRAIN
OVP
FB
CONTROL
COMP UVP GND
Cs
RH
RL
C3
D2
C1
D1
R2 C2
Cout
Lout
Vout
GND GND
VIPER31
Typical schematics page 27/40
5.2
VIPER31
Energy saving performances
Energy saving performances
The VIPer31 allows the design of applications compliant with the most stringent energy saving regulations. In order to show the typical performances achievable, the active mode average efficiency and the efficiency at
10% of the rated output power of a single output flyback converter using VIPer31 have been measured and are reported in Table 9. In addition, Figures 52 and 53 show no-load and light load consumptions.
Parameter
Flyback iso, 15V/1.2A
Table 9. Power supply efficiency, VOUT = 15 V
V
IN
115 V
AC
230 V
AC
10% output load efficiency [%]
83.2
77.4
Active mode average efficiency [%]
85.9
86.6
Pin @ no-load
[mW]
26.0
29.7
Figure 42. PIN versus VIN in no-load, VOUT = 15V
40
30
20
10
50 100 150 200
V
IN
[V
AC
]
250 300
DS13285 - Rev 3 page 28/40
DS13285 - Rev 3
Figure 43. PIN versus VIN in light-load, VOUT = 15V
450
400
350
300
250
P
OUT
= 250mW
200
150
100
50
0
50
P
OUT
= 50mW
P
OUT
= 25mW
100 150 200
V
IN
[V
AC
]
250
VIPER31
Energy saving performances
300 page 29/40
5.3
VIPER31
Layout guidelines and design recommendations
Layout guidelines and design recommendations
•
•
A proper printed circuit board layout is essential for correct operation of any switch-mode converter and this is true for the VIPer as well. The main reasons to have a proper PCB layout are to:
Provide clean signals to the IC, ensuring good immunity against external noises and switching noises
Reduce the electromagnetic interferences, both radiated and conducted, to pass more easily the EMC
When designing an SMPS using VIPer, the following basic rules should be considered:
•
•
•
•
•
•
Separating signal from power tracks: generally, traces carrying signal currents should run far from those carrying pulsed currents or with quickly swinging voltages. Signal ground traces should be connected to the
IC signal ground, GND, using a single “star point”, placed close to the IC. Power ground traces should be connected to the IC power ground, GND. The compensation network should be connected to the COMP, maintaining the trace to GND as short as possible. In case of two layer PCB, it is a good practice to route signal traces on one PCB side and power traces on the other side.
Filtering sensitive pins: some crucial points of the circuit need or may need filtering. A small highfrequency bypass capacitor to GND might be useful to get a clean bias voltage for the signal part of the
IC and protect the IC itself during EFT/ESD tests. A low ESL ceramic capacitor (a few hundreds pF up to
0.1 μF) should be connected across VCC and GND, placed as close as possible to the IC. With flyback topologies, when the auxiliary winding is used, it is suggested to connect the VCC capacitor on the auxiliary return and then to the main GND using a single track.
Keep power loops as confined as possible: minimize the area circumscribed by current loops where high pulsed currents flow, in order to reduce its parasitic self-inductance and the radiated electromagnetic field: this greatly reduces the electromagnetic interferences produced by the power supply during the switching. In a flyback converter the most critical loops are: the one including the input bulk capacitor, the power switch, the power transformer, the one including the snubber, the one including the secondary winding, the output rectifier and the output capacitor. In a buck converter the most critical loop is the one including the input bulk capacitor, the power switch, the power inductor, the output capacitor and the free-wheeling diode.
Reduce line lengths: any wire acts as an antenna. With the very short rise times exhibited by EFT pulses, any antenna has the capability of receiving high-voltage spikes. By reducing line lengths, the level of radiated energy that is received is reduced, and the resulting spikes from electrostatic discharges are lower.
This also keeps both resistive and inductive effects to a minimum. In particular, all of the traces carrying high currents, especially if pulsed (tracks of the power loops) should be as short and fat as possible.
Optimize track routing: as levels of pickup from static discharges are likely to be greater closer to the extremities of the board, it is wise to keep any sensitive lines away from these areas. Input and output lines often need to reach the PCB edge at some stage, but they can be routed away from the edge as soon as possible where applicable. Since vias are to be considered inductive elements, it is recommended to minimize their number in the signal path and avoid them when designing the power path.
Improve thermal dissipation: an adequate copper area has to be provided under the DRAIN pins as heat sink, while it is not recommended to place large copper areas on the GND.
DS13285 - Rev 3 page 30/40
DS13285 - Rev 3
VIPER31
Layout guidelines and design recommendations
~ AC D
IN
Figure 44. Recommended routing for flyback converter
R
IN
TR
D
OUT
C
IN C
CL
R
CL
D
AUX
C
OUT
V
OUT
GROUND
Cs
OPTO
R
OPTO
R
C
C
C
RH
DR.
DR.
DR. DR. N.C. N.C. N.C. N.C.
VIPER31
CONTROL
GND N.C.
VCC N.A. UVP OVP FB COMP
OPTO
C1
RL
~ AC D
IN
R
IN
Figure 45. Recommended routing for buck converter
C
IN
DR.
DR.
DR. DR. N.C. N.C. N.C. N.C.
VIPER31
CONTROL
GND N.C.
VCC N.A. UVP OVP FB COMP
Cc
D
AUX
Cs RH
C1
RL
L
OUT
D1
V
OUT
C
OUT
D
OUT
GROUND page 31/40
6
6.1
VIPER31
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
SO16N package information
Figure 46. SO16N package outline
DS13285 - Rev 3 page 32/40
Dim.
e h
L
E
E1 k ccc
A
A1
A2 b c
D
Table 10. SO16N mechanical data
Min.
mm
Typ.
0.1
1.25
0.31
0.17
9.8
5.8
3.8
0.25
0.4
0
9.9
6
3.9
1.27
VIPER31
SO16N package information
Max.
1.75
0.25
0.51
0.25
10
6.2
4
0.5
1.27
8
0.1
DS13285 - Rev 3 page 33/40
VIPER31
Order code
7 Order code
Order code
VIPER31 8 XDTR
VIPER31 9 XDTR
VIPER31 7 LDTR
VIPER31 8 LDTR
VIPER31 9 LDTR
VIPER31 7 HDTR
VIPER31 8 HDTR
VIPER31 9 HDTR
Table 11. Order code
I
DLIM
(OCP) typ
850 mA
9 90 mA
7 10 mA
85 0 mA
9 90 mA
7 10 mA
85 0 mA
9 90 mA
FOSC ± jitter
30 kHz ± 7%
60 kHz ± 7%
132 kHz ± 7%
Package
SO16N tape and reel
DS13285 - Rev 3 page 34/40
VIPER31
Revision history
Date
31-Mar-2020
8-Jun-2020
17-Nov-2020
2
3
Table 12. Document revision history
Version
1
Changes
Initial release.
; updated
figures in
Section 5.1 Typical schematics
; minor text update.
Added data for VIPER317/318/319 in Section Features , in
DS13285 - Rev 3 page 35/40
VIPER31
Contents
Contents
DS13285 - Rev 3 page 36/40
VIPER31
Contents
DS13285 - Rev 3 page 37/40
VIPER31
List of tables
List of tables
DS13285 - Rev 3 page 38/40
VIPER31
List of figures
List of figures
Figure 7. Quiescent Current I q
=0, f=1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 24. Typical deliverable output power vs. T
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DS13285 - Rev 3 page 39/40
VIPER31
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS13285 - Rev 3 page 40/40
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