STMicroelectronics L7980 Datasheet
Oglas
Oglas
L7980
2 A step-down switching regulator
VFQFPN8 3 x 3
HSOP8 exposed pad
Datasheet
-
production data
Industrial:
– PLD, PLA, FPGA, chargers
Networking: XDSL, modems, DC-DC modules
Computer:
– Optical storage, hard disk drive, printers, audio/graphic cards
LED driving
Features
2 A DC output current
4.5 V to 28 V input voltage
Output voltage adjustable from 0.6 V
250 kHz switching frequency, programmable up to 1 MHz
Internal soft-start and enable
Low dropout operation: 100% duty cycle
Voltage feed-forward
Zero load current operation
Overcurrent and thermal protection
VFQFPN 3 x 3 - 8L and HSOP8 package
Applications
Consumer:
– STB, DVD, DVD recorder, car audio, LCD
TV and monitors
Description
The L7980 device is a step-down switching regulator with a 2.5 A (minimum) current limited embedded Power MOSFET, so it is able to deliver up to 2 A current to the load depending on the application conditions.
The input voltage can range from 4.5 V to 28 V, while the output voltage can be set starting from
0.6 V to V
IN
.
Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz.
The QFN and the HSOP packages with exposed pad allow reducing the R thJA and 40 °C/W respectively.
down to 60 °C/W
Figure 1. Application circuit
May 2014
This is information on a product in full production.
DocID15181 Rev 6 1/42
www.st.com
Contents
Contents
L7980
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2
Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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L7980
Contents
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42
Pin settings
Figure 2. Pin connection (top view)
L7980
4/42
3
4
5
6
7
8
No.
1
2
Type
OUT
SYNCH
EN
COMP
FB
F
SW
GND
V
CC
Table 1. Pin description
Description
Regulator output
Master/slave synchronization. When it is left floating, a signal with a phase shift of half a period respect to the power turn on is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal, with zero phase shift.
Connecting together the SYNCH pin of two devices, the one with higher frequency works as master and the other one as slave; so the two powers turn on have a phase shift of half a period.
A logical signal (active high) enable the device. With EN higher than
1.2 V the device is ON and with EN is lower than 0.3 V the device is OFF.
Error amplifier output to be used for loop frequency compensation
Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.6 V. To have higher regulated voltages an external resistor divider is required from Vout to the FB pin.
The switching frequency can be increased connecting an external resistor from the FSW pin and ground. If this pin is left floating the device works at its free-running frequency of 250 kHz.
Ground
Unregulated DC input voltage
DocID15181 Rev 6
L7980 Maximum ratings
Symbol
Table 2. Absolute maximum ratings
Parameter
Vcc
OUT
Input voltage
Output DC voltage
F
SW
, COMP, SYNCH Analog pin
EN Enable pin
FB
P
TOT
T
J
T stg
Feedback voltage
Power dissipation at T
A
< 60 °C
VFQFPN
Junction temperature range
HSOP
Storage temperature range
Value
30
-0.3 to V
CC
-0.3 to 4
-0.3 to V
CC
-0.3 to 1.5
1.5.
2
-40 to 150
-55 to 150
Unit
V
W
°C
°C
Symbol
R thJA
Table 3. Thermal data
Parameter
Maximum thermal resistance junction ambient
(1)
VFQFPN
HSOP
1. Package mounted on demonstration board.
Value
60
40
Unit
°C/W
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42
Electrical characteristics L7980
Symbol
T
J
= 25 °C, V
CC
= 12 V, unless otherwise specified.
Table 4. Electrical characteristics
Parameter Test condition
V
CC
V
CCON
V
CCHYS
Operating input voltage range
Turn on V
CC
threshold
V
CC
UVLO hysteresis
R
DSON
MOSFET on resistance
I
LIM
Oscillator
Maximum limiting current
F
SW
Switching frequency
V
FSW
D
FSW pin voltage
Duty cycle
F
ADJ
Adjustable switching frequency
Dynamic characteristics
V
FB
Feedback voltage
I
I
Q
QST-BY
Enable
DC characteristics
Quiescent current
Total standby quiescent current
EN threshold voltage
EN current
Soft-start
T
SS
Soft-start duration
Error amplifier
V
CH
V
CL
I
O SOURCE
High level output voltage
Low level output voltage
Source COMP pin
(1)
(1)
(1)
(1)
(1)
R
FSW
= 33 k
4.5 V < V
CC
< 28 V
(1)
Duty cycle = 0, V
FB
= 0.8 V
Device OFF level
Device ON level
EN = V
CC
Min.
4.5
0.12
2.5
Values
Typ.
Max.
160
160
3.0
28
4.4
0.35
180
250
3.5
Unit
V m
A
225
220
0 100
0.593
0.6
0.607
1.2
FSW pin floating
F
SW
= 1 MHz, R
FSW
= 33 k
7.4
V
FB
< 0.6 V
V
FB
> 0.6 V
V
FB
= 0.5 V, V
COMP
= 1 V
3
250
1.254
1000
20
7.5
8.2
2
17
275
275
2.4
30
0.3
10
9.1
0.1
V mA
A
V
A ms
V mA
KHz
V
%
KHz
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L7980 Electrical characteristics
Table 4. Electrical characteristics (continued)
Values
Symbol Parameter Test condition Unit
I
O SINK
G
V
Sink COMP pin
Open loop voltage gain
Synchronization function
High input voltage
Low input voltage
Slave sink current
Master output amplitude
Output pulse width
Input pulse width
V
FB
(2)
= 0.7 V, V
COMP
V
SYNCH
I
SOURCE
= 2.9 V
= 4.5 mA
SYNCH floating
= 1 V
Min.
2
2.0
Typ.
Max.
25
100
0.7
110
3.3
1
0.9
mA dB
V mA
V ns
70
Protection
T
SHDN
Thermal shutdown 150
Hysteresis 30
1. Specification referred to T
J
from -40 to +125 °C. Specification in the -40 to +125 °C temperature range are assured by design, characterization and statistical correlation.
2. Guaranteed by design.
°C
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Functional description L7980
The L7980 device is based on a “voltage mode”, constant frequency control. The output voltage V
OUT
is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing an error signal that, compared to a fixed frequency sawtooth, controls the on and off time of the power switch.
The main internal blocks are shown in the block diagram in
. They are:
A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feed forward are implemented.
The soft-start circuitry to limit inrush current during the start-up phase.
The voltage mode error amplifier
The pulse width modulator and the relative logic circuitry necessary to drive the internal power switch.
The high-side driver for embedded P-channel Power MOSFET switch.
The peak current limit sensing block, to handle overload and short-circuit conditions.
A voltage regulator and internal reference. It supplies internal circuitry and provides a fixed internal reference.
A voltage monitor circuitry (UVLO) that checks the input and internal voltages.
A thermal shutdown block, to prevent thermal runaway.
Figure 3. Block diagram
PEAK
CURRENT
8/42
FSW
GND
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L7980 Functional description
5.1 Oscillator synchronization
shows the block diagram of the oscillator circuit. The internal oscillator provides
a constant frequency clock. Its frequency depends on the resistor externally connect to the
FSW pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be increased
by external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input voltage, the voltage feed forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see
.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the external resistor. In this way a frequency feed forward is implemented (
.b) in order to keep the PWM gain constant versus the switching frequency (see
for PWM gain expression).
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized connecting the SYNCH pin together. When SYNCH pins are connected, the device with higher oscillator frequency works as the master, so the slave device switches at the frequency of the master but with a delay of half a period. This minimizes the RMS current flowing through the input capacitor (see the L5988D datasheet).
Figure 4. Oscillator circuit block diagram
The device can be synchronized to work at higher frequency feeding an external clock signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(
.c). This changing has to be taken into account when the loop stability is studied.
To minimize the change of the PWM gain, the free running frequency should be set (with a resistor on the FSW pin) only slightly lower than the external clock frequency. This preadjusting of the frequency will change the sawtooth slope in order to get negligible the truncation of sawtooth, due to the external synchronization.
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Functional description L7980
Figure 5. Sawtooth: voltage and frequency feed forward; external synchronization
Figure 6. Oscillator frequency versus FSW pin resistor
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L7980 Functional description
5.2 Soft-start
The soft-start is essential to assure a correct and safe startup of the step-down converter. It avoids inrush current surge and makes the output voltage increases monothonically.
The soft-start is performed by a staircase ramp on the non inverting input (V
REF amplifier. So the output voltage slew rate is:
) of the error
Equation 1
SR
OUT
= SR
VREF
1 +
R1
R2
where SR
VREF
is the slew rate of the non inverting input, while R1and R2 is the resistor divider to regulate the output voltage (see
). The soft-start stair case consists of
64 steps of 9.5 mV each one, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So the soft-start time and then the output voltage slew rate depend on the switching frequency.
Figure 7. Soft-start scheme
Soft-start time results:
Equation 2
SS
TIME
=
Fsw
For example with a switching frequency of 250 kHz the SS
TIME
is 8 ms.
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Functional description
5.3 Error amplifier and compensation
L7980
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier so with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are the following:
Table 5. Uncompensated error amplifier characteristics
Parameter Value
Low frequency gain
GBWP
Slew rate
Output voltage swing
Maximum source/sink current
100 dB
4.5 MHz
7 V/
s
0 to 3.3 V
17 mA/25 mA
In continuous conduction mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. In case the zero introduced by the output capacitor helps to compensate the double pole of the LC filter a type II compensation network can be used. Otherwise, a type
III compensation network has to be used (see
compensation network selection).
Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe phase margin.
12/42
The L7980 device implements the overcurrent protection sensing current flowing through the Power MOSFET. Due to the noise created by the switching activity of the Power
MOSFET, the current sensing is disabled during the initial phase of the conduction time.
This avoids an erroneous detection of a fault condition. This interval is generally known as
“masking time” or “blanking time”. The masking time is about 200 ns.
When the overcurrent is detected, two different behaviors are possible depending on the operating condition.
1.
Output voltage in regulation. When the overcurrent is sensed, the Power MOSFET is switched off and the internal reference (V
REF
), that biases the non inverting input of the error amplifier, is set to zero and kept in this condition for a soft-start time (T
SS
, 2048 clock cycles). After this time, a new soft-start phase takes place and the internal
.a).
2. Soft-start phase. If the overcurrent limit is reached the Power MOSFET is turned off implementing the pulse by pulse overcurrent protection. During the soft-start phase, under overcurrent condition, the device can skip pulses in order to keep the output current constant and equal to the current limit. If at the end of the “masking time” the current is higher than the overcurrent threshold, the Power MOSFET is turned off and it will skip one pulse. If, at the next switching on at the end of the “masking time” the
DocID15181 Rev 6
L7980 Functional description
current is still higher than the threshold, the device will skip two pulses. This mechanism is repeated and the device can skip up to seven pulses. While, if at the end of the “masking time” the current is lower than the overcurrent threshold, the number of skipped cycles is decreased of one unit. At the end of soft-start phase the output voltage is in regulation and if the overcurrent persists the behavior explained above takes place (see
So the overcurrent protection can be summarized as an “hiccup” intervention when the output is in regulation and a constant current during the soft-start phase. If the output is shorted to ground when the output voltage is on regulation, the overcurrent is triggered and the device starts cycling with a period of 2048 clock cycles between “hiccup” (Power
MOSFET off and no current to the load) and “constant current” with very short on-time and with reduced switching frequency (up to one eighth of normal switching frequency). See
for short-circuit behavior.
Figure 8. Overcurrent protection strategy
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Functional description L7980
The enable feature allows to put in standby mode the device. With the EN pin lower than
0.3 V the device is disabled and the power consumption is reduced to less than 30 µA. With the EN pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an internal pull down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also V
CC
compatible.
The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C, the device restarts in normal operation. The sensing element is very close to the PDMOS area, so ensuring an accurate and fast temperature detection.
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L7980 Application informations
6.1 Input capacitor selection
The capacitor connected to the input has to be capable to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency.
So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 3
I
RMS
= I
O
D –
2
--------------+
D
2
-------
2
Where I
O
is the maximum DC output current, D is the duty cycle,
is the efficiency.
Considering
, this function has a maximum at D = 0.5 and it is equal to I
O
/2.
In a specific application the range of possible duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as:
Equation 4
D
MAX
=
V
V
INMIN
+
–
V
V
F
SW and
Equation 5
D
MIN
=
V
V
INMAX
+
–
V
V
SW
Where V
F
is the forward voltage on the freewheeling diode and V the internal PDMOS.
SW
is voltage drop across
The peak to peak voltage across the input capacitor can be calculated as:
Equation 6
V
PP
=
C
IN
I
O
F
SW
1 –
D
+
–
+
O where ESR is the equivalent series resistance of the capacitor.
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Application informations L7980
Given the physical dimension, ceramic capacitors can meet well the requirements of the input filter sustaining a higher input RMS current than electrolytic / tantalum types. In this case the equation of C
IN
as a function of the target V
PP
can be written as follows:
Equation 7
C
IN
=
V
PP
I
O
F
SW
1 –
D
+
–
neglecting the small ESR of ceramic capacitors.
Considering
= 1, this function has its maximum in D = 0.5, thus, given the maximum peak to peak input voltage (V
PP_MAX
), the minimum input capacitor (C
IN_MIN
) value is:
Equation 8
C
IN_MIN
=
I
O
PP_MAX
SW
Typically C
IN
is dimensioned to keep the maximum peak-peak voltage in the order of 1% of
V
INMAX
In
some multi layer ceramic capacitors suitable for this device are reported:
Manufacture
Taiyo Yuden
Table 6. Input MLCC capacitors
Series Cap value (
F)
UMK325BJ106MM-T
GMK325BJ106MN-T
GRM32ER71H475K
10
10
4.7
Rated voltage (V)
50
35
50 Murata
A ceramic bypass capacitor, as close to the VCC and GND pins as possible, so that additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability on the output voltage due to noise. The value of the bypass capacitor can go from 100 nF to
1 µF.
16/42
The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value in order to have the expected current ripple has to be selected.
The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current.
In the continuous current mode (CCM), the inductance value can be calculated by
:
Equation 9
I
L
=
V
IN
–
L
V
OUT
ON
=
V
L
+
V
F
OFF
Where T
ON
is the conduction time of the internal high-side switch and T
OFF
conduction time of the external diode [in CCM, F
SW
= 1 / (T
ON current ripple, at fixed Vout, is obtained at maximum T
OFF
to calculate minimum duty).
+ T
OFF
is the
)]. The maximum
that is at minimum duty cycle
DocID15181 Rev 6
L7980
6.3
Application informations
So fixing
I
L
= 20% to 30% of the maximum output current, the minimum inductance value can be calculated:
Equation 10
L
MIN
=
V
OUT
I
+
----------------------------
MAX
V
F
1 D
F
MIN
SW where F
SW
is the switching frequency, 1 / (T
ON
+ T
OFF
).
For example for V
OUT
= 5 V, V
IN inductance value to have
I
L
= 24 V, I
O
= 30% of I
O
= 2 A and F
SW
is about 28
H.
= 250 kHz the minimum
The peak current through the inductor is given by:
Equation 11
I
So if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. The higher is the inductor value, the higher is the average output current that can be delivered, without reaching the current limit.
In
some inductor part numbers are listed.
=
I
O
+
I
L
Manufacturer
Coilcraft
Wurth
SUMIDA
Table 7. Inductors
Series Inductor value (
H)
Saturation current (A)
MSS1038
MSS1048
MSS1060
PD Type L
PD Type M
PD4 Type X
CDRH6D226/HP
CDR10D48MN
3.8 to 10
12 to 22
22 to 47
8.2 to 15
2.2 to 4.7
22 to 47
1.5 to 3.3
6.6 to 12
3.9 to 6.5
3.84 to 5.34
5 to 6.8
3.75 to 6.25
4 to 6
2.6 to 3.5
3.6 to 5.2
4.1 to 5.7
Output capacitor selection
The current in the capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection.
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42
Application informations L7980
Equation 12
V
OUT
=
ESR
I
MAX
+
I
MAX
OUT
f
SW
Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi layer ceramic capacitor (MLCC) with very low ESR value.
The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. In
, it will be illustrated how to consider its effect in the
system stability.
For example with V
OUT order to have a
V
OUT
= 5 V, V
IN
= 0.01 · V
= 24 V,
I
OUT
L
= 0.6 A (resulting by the inductor value), in
, if the multi layer ceramic capacitor are adopted, 10 µF are needed and the ESR effect on the output voltage ripple can be neglected. In case of not negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value. So in case of 220 with ESR = 50 m
, the resistive component of the drop dominates and the voltage ripple is 33 mV
The output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. When the load transient slew rate exceeds the system bandwidth the output capacitor provides the current to the load. So if the high slew rate load transient is required by the application the output capacitor and system bandwidth have to be chosen in order to sustain the load transient.
In
some capacitor series are listed.
Manufacturer
MURATA
PANASONIC
SANYO
TDK
Series
GRM32
GRM31
ECJ
EEFCD
TPA/B/C
C3225
Table 8. Output capacitors
Cap value (
F)
Rated voltage (V)
22 to 100
10 to 47
10 to 22
10 to 68
100 to 470
22 to 100
6.3 to 25
6.3 to 25
6.3
6.3
4 to 16
6.3
ESR (m
)
< 5
< 5
< 5
15 to 55
40 to 80
< 5
18/42 DocID15181 Rev 6
L7980 Application informations
The compensation network has to assure stability and good dynamic performance. The loop of the L7980 is based on the voltage mode control. The error amplifier is a voltage operational amplifier with high bandwidth. So selecting the compensation network the E/A will be considered as ideal, that is, its bandwidth is much larger than the system one.
The transfer functions of PWM modulator and the output LC filter are studied (see
). The transfer function of the PWM modulator, from the error amplifier output
(COMP pin) to the OUT pin, results:
Equation 13
G
PW0
=
V
V s where V
S
is the sawtooth amplitude. As seen in
, the voltage feed forward generates a sawtooth amplitude directly proportional to the input voltage, that is:
Equation 14
V
S
=
IN
In this way the PWM modulator gain results constant and equals to:
Equation 15
G
PW0
=
V
V s
=
1
K
= 13
The synchronization of the device with an external clock provided trough the SYNCH pin can modify the PWM modulator gain (see
to understand how this gain changes
and how to keep it constant in spite of the external synchronization).
Figure 9. The error amplifier, the PWM modulation and the LC output filter
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42
Application informations
6.4.1
L7980
The transfer function on the LC filter is given by:
Equation 16
G
LC
=
1 +
2
f s
1 +
s
2
Q f
LC
+
2 s
f
LC
2 where:
Equation 17
f
LC
=
2
L C
OUT
1
+
R
OUT
f zESR
=
2
1
OUT
Equation 18
Q =
R
OUT
L C
OUT
OUT
R
R
OUT
OUT
+
E SR
ESR
-----------------------------------------------------------------------------------------, R
OUT
=
V
OUT
OUT
two different kind of network can compensate the loop. In
the two following paragraph the guidelines to select the Type II and Type III compensation network are illustrated.
Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect of the LC double pole, so increasing phase margin; then to place one pole in the origin to minimize the dc error on regulated output voltage; finally to place other poles far away the zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2
ESR C
OUT
< 1 / BW), the type
III compensation network is needed. Multi layer ceramic capacitors (MLCC) have very low
ESR (< 1 m
), with very high frequency zero, so type III network is adopted to compensate the loop.
the type III compensation network is shown. This network introduces two zeros
(f
Z1
, f
Z2
) and three poles (f
P0
, f
P1
, f
P2
). They are expressed as:
Equation 19
f
Z1
=
2
3
R
1
+ R
3
f
Z2
=
2
R
4
C
4
Equation 20
f
P0
= 0
f
P1
=
2
R
3
C
3
f
P2
=
2
R
4
C
4
C
4
+
C
5
C
5
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L7980 Application informations
Figure 10. Type III compensation network
In
the Bode diagram of the PWM and LC filter transfer function (G
PW0 and the open loop gain (G
LOOP
(f) = G
PW0
· G
LC
(f) · G
TYPEIII
(f)) are drawn.
· G
LC
(f))
Figure 11. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow:
1.
Choose a value for R
1
, usually between 1 k
and 5 k.
2. Choose a gain (R
4
/R
1
) in order to have the required bandwidth (BW), that means:
Equation 21
R
4
= f
LC
1 where K is the feed forward constant and 1 / K is equals to 13.
DocID15181 Rev 6 21/42
42
Application informations L7980
4
by placing the zero at 50% of the output filter double pole frequency (f
LC
):
Equation 22
C
4
=
R
1
4
LC
5
by placing the second pole at four times the system bandwidth (BW):
Equation 23
C
5
=
2
R
4
C
C
4
4
–
5. Set also the first pole at four times the system bandwidth and also the second zero at the output filter double pole:
Equation 24
R
3
=
R
---------------------------
f
LC
C
3
=
2
R
3
4 BW
The suggested maximum system bandwidth is equals to the switching frequency divided by
3.5 (F
SW
/3.5), anyway lower than 100 kHz if the F
SW
is set higher than 500 kHz.
For example with V
OUT
= 5 V, V
IN
= 24 V, I the type III compensation network is:
O
= 2 A, L = 27
H, C
OUT
= 22
F, ESR < 1 m,
Equation 25
R
1
= 4.99k
R
2
= 680
R
3
= 150
R
4
= 3.3k
C
3
= 4.7nF
C
4
= 22nF
C
5
= 220pF
22/42 DocID15181 Rev 6
L7980 Application informations
In
is shown the module and phase of the open loop gain. The bandwidth is about
54 kHz and the phase margin is 50°.
Figure 12. Open loop gain bode diagram with ceramic output capacitor
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2
ESR C
OUT
> 1 / BW), this zero helps stabilize the loop. Electrolytic capacitors show not negligible ESR (> 30 m
), so with this kind of output capacitor the type II network combined with the zero of the ESR allows stabilizing the loop.
DocID15181 Rev 6 23/42
42
Application informations
In
Figure 13. Type II compensation network
L7980
The singularities of the network are:
Equation 26
f
Z1
=
2
1
R
4
C
4
f
P0
= 0
f
P1
=
2
R
4
C
C
4
+
C
C
5
In
the Bode diagram of the PWM and LC filter transfer function [G
PW0 and the open loop gain [G
LOOP
(f) = G
PW0
· G
LC
(f) · G
TYPEII
(f)] are drawn.
· G
LC
(f)]
Figure 14. Open loop gain: module bode diagram
24/42 DocID15181 Rev 6
L7980 Application informations
The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow:
1.
Choose a value for R
1
, usually between 1 k
and 5 k, in order to have values of C4 and C5 not comparable with parasitic capacitance of the board.
2. Choose a gain (R
4
/ R
1
) in order to have the required bandwidth (BW), that means:
Equation 27
R
4
=
f
------------
LC
2
f
ESR
V
S
V
IN
1
Where f
ESR
is the ESR zero:
Equation 28
f
ESR
=
2
1
OUT and V
S
is the saw-tooth amplitude. The voltage feed forward keeps the ratio V
S
/V
IN
constant.
4
by placing the zero one decade below the output filter double pole:
Equation 29
C
4
=
4
LC
3
in order to place the second pole at four times the system bandwidth
(BW):
Equation 30
C
5
=
C
--------------------------------------------------------------
4 4
–
1
For example with V
OUT
= 5 V, V
IN
= 24 V, I the type II compensation network is:
O
= 2 A, L = 27
H, C
OUT
= 330
F, ESR = 50 m
Equation 31
R
1
= 1.1k
R
2
= 150
R
4
= 6.8k
C
4
= 82nF
C
5
= 82pF
In
is shown the module and phase of the open loop gain. The bandwidth is about
24 kHz and the phase margin is 48°.
DocID15181 Rev 6 25/42
42
Application informations L7980
Figure 15. Open loop gain bode diagram with electrolytic/tantalum output capacitor
26/42 DocID15181 Rev 6
L7980 Application informations
The thermal design is important to prevent the thermal shutdown of the device if junction temperature goes above 150 °C. The three different sources of losses within the device are: a) Conduction losses due to the not negligible R
DSon equal to:
of the power switch; these are
Equation 32
P
ON
= R
DSON
I
OUT
2
D
Where D is the duty cycle of the application and the maximum R
DSon
overtemperature is
300 m
. Note that the duty cycle is theoretically given by the ratio between V
OUT
and V
IN
, but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increases compared with the ideal case.
b) Switching losses due to Power MOSFET turn ON and OFF; these can be calculated as:
Equation 33
P
SW
= V
IN
I
OUT
T +
2
T
FALL
= V
IN
I
OUT
T
SW
F
SW
Where T
RISE
and T
FALL
are the overlap times of the voltage across the power switch (V
DS
) and the current flowing into it during turn ON and turn OFF phases, as shown in
T
SW
is the equivalent switching time. For this device the typical value for the equivalent switching time is 30 ns.
Equation 34
P
Q
= V
IN
I
Q where I
Q
is the quiescent current (I
Q
= 2.4 mA).
The junction temperature T
J
can be calculated as:
Equation 35
T
J
=
T
A
+
Rth
JA
P
TOT
Where T
A
is the ambient temperature and P
TOT
is the sum of the power losses just seen.
R thJA
is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount of heat. The Rth
JA
measured on the demonstration board described in the following paragraph is about 60 °C/W for the VFQFPN package and about 40 °C/W for the HSOP package.
DocID15181 Rev 6 27/42
42
Application informations
Figure 16. Switching losses
L7980
28/42
The PC board layout of switching DC/DC regulator is very important to minimize the noise injected in high impedance nodes and interferences generated by the high switching current loops.
In a step-down converter the input loop (including the input capacitor, the Power MOSFET and the free wheeling diode) is the most critical one. This is due to the fact that the high value pulsed current are flowing through it. In order to minimize the EMI, this loop has to be as short as possible.
The feedback pin (FB) connection to external resistor divider is a high impedance node, so the interferences can be minimized placing the routing of feedback node as far as possible from the high current paths. To reduce the pick up noise the resistor divider has to be placed very close to the device.
To filter the high frequency noise, a small bypass capacitor (220 nF - 1 µF) can be added as close as possible to the input voltage pin of the device.
Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane enhances the thermal performance of the converter allowing high power conversion.
DocID15181 Rev 6
L7980
In
Figure 17. Layout example
Application informations
DocID15181 Rev 6 29/42
42
Application informations
In
the demonstration board application circuit is shown.
Figure 18. Demonstration board application circuit (rev 1.0)
L7980
30/42
Reference
C4
C5
C6
R1
C1
C2
C3
R2
R3
R4
R5
D1
L1
Table 9. Component list (rev 1.0)
Part number Description
UMK325BJ106MM-T
GRM32ER61E226KE15
STPS3L40
MSS1038-103NL
10
F, 50 V
22
F, 25 V
2.2 nF, 50 V
22 nF, 50 V
220 pF, 50 V
470 nF, 50 V
4.99 k
, 1%, 0.1 W 0603
1.1 k
, 1%, 0.1 W 0603
220
, 1%, 0.1 W 0603
2.2 k
, 1%, 0.1 W 0603
100 k
1%, 0.1 W 0603
3 A DC, 40 V
10
H, 30%, 3.9 A,
DCR
MAX
= 35 m
Manufacturer
Taiyo Yuden
Murata
STMicroelectronics
Coilcraft
DocID15181 Rev 6
L7980 Application informations
Figure 19. PCB layout: L7980 and L7980A (component side)
Figure 20. PCB layout: L7980 and L7980A (bottom side)
Figure 21. PCB layout: L7980 and L7980A (front side)
DocID15181 Rev 6 31/42
42
Application informations L7980
Figure 22. Junction temperature vs. output current - V
IN
= 12 V
Figure 23. Junction temperature vs. output current - V
IN
= 5 V
Figure 24. Junction temperature vs. output current - V
IN
= 24 V
Figure 25. Efficiency vs. output current -
V
OUT
= 5 V
92
V
IN
=12V
V
IN
=18V
87
V
IN
=24V
82
Figure 26. Efficiency vs.output current -
V
OUT
= 3.3 V
95
90
V
IN
=5V
85
80
75
V
IN
=12V
V
IN
=24V
70
65
0.0
0.5
1.0
Io [A]
V
OUT
=3.3 V fsw=250 kHz
1.5
2.0
77
72
0.0
0.5
1.0
Io [A]
V
OUT
=5.0 V fsw=250 kHz
1.5
Figure 27. Efficiency vs. output current -
V
OUT
= 1.8 V
2.0
85
80
75
70
65
60
55
50
0.0
V
IN
=5V
V
IN
=12V
0.5
V
IN
=24V
1.0
Io [A]
V
OUT
=1.8 V fsw=250 kHz
1.5
2.0
32/42 DocID15181 Rev 6
L7980
Figure 28. Load regulation
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
Vcc=5V
Vcc=12V
Vcc=24V
2
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
5
0.5
1
Io [A]
1.5
Figure 30. Load transient: from 0.4 A to 2 A
Application informations
Figure 29. Line regulation
Io=1A
Io=2A
10 15
V
CC
[V]
20
Figure 31. Soft-start
25
I I
V
500mV/div
I I
Figure 32. Short-circuit behavior
I I
DocID15181 Rev 6 33/42
42
Application ideas L7980
The L7980 device can implement the step-up/down converter with a positive output voltage.
shows the schematic: one Power MOSFET and one Schottky diode are added to the standard buck topology to provide 12 V output voltage with input voltage from 4.5 V to
28 V.
Figure 33. Positive buck-boost regulator
34/42
The relationship between input and output voltage is:
Equation 36
V
OUT
= V
IN
So the duty cycle is:
Equation 37
D =
V
OUT
OUT
+ V
IN
The output voltage isn’t limited by the maximum operating voltage of the device (28 V), because the output voltage is sensed only through the resistor divider. The external Power
MOSFET maximum drain to source voltage must be higher than output voltage; the maximum gate to source voltage must be higher than the input voltage (in
, if V
IN higher than 16 V, the gate must be protected through the Zener diode and resistor)
is
The current flowing through the internal Power MOSFET is transferred to the load only during the OFF time, so according to the maximum DC switch current (2.0 A), the maximum output current for the buck boost topology can be calculated from
Equation 38
I
SW
=
I
------------- 2 A where I
SW
is the average current in the embedded Power MOSFET in the on time.
DocID15181 Rev 6
L7980 Application ideas
To chose the right value of the inductor and to manage transient output current, that for short time can exceed the maximum output current calculated by
current in the Power MOSFET has to be calculated. The peak current, showed in
, must be lower than the minimum current limit (3.7 A).
Equation 39
I
SW,PK
=
I
OUT
1 D
1 +
2
2.5A
r =
I
------------------------------------
OUT
V
OUT
L F
SW
–
2
Where r is defined as the ratio between the inductor current ripple and the inductor DC current:
So in the buck boost topology the maximum output current depends on the application conditions (firstly input and output voltage, secondly switching frequency and inductor value).
the maximum output current for the above configuration is depicted varying the
input voltage from 4.5 V to 28 V.
The dashed line considers a more accurate estimation of the duty cycles given by
, where power losses across diodes, external Power MOSFET, internal Power MOSFET
are taken into account.
Figure 34. Maximum output current according to max DC switch current (2.0 A):
V
O
= 12 V
Equation 40
D =
V
IN
– V
SW
V
– V
+
SWE
+
D
V
OUT
+ 2 V
D where V
D
is the voltage drop across diodes, V
Power MOSFET.
SW
and V
SWE
across the internal and external
DocID15181 Rev 6 35/42
42
Application ideas L7980
The L7980 device can implement the step-up/down converter with a negative output voltage.
shows the schematic to regulate -5 V: no further external components are added to the standard buck topology.
The relationship between input and output voltage is:
Equation 41
V
OUT
= –
V
IN
So the duty cycle is:
Equation 42
D =
V
OUT
V
OUT
V
IN
As in the positive one, in the inverting buck-boost the current flowing through the Power
MOSFET is transferred to the load only during the OFF time. So according to the maximum
DC switch current (2.0 A), the maximum output current can be calculated from the
, where the duty cycle is given by
Figure 35. Inverting buck-boost regulator
36/42
The GND pin of the device is connected to the output voltage so, given the output voltage, input voltage range is limited by the maximum voltage the device can withstand across VCC and GND (28 V). Thus if the output is -5 V the input voltage can range from 4.5 V to 23 V.
As in the positive buck-boost, the maximum output current according to application conditions is shown in
. The dashed line considers a more accurate estimation of the duty cycles given by
, where power losses across diodes and internal Power
MOSFET are taken into account.
Equation 43
D
=
– V
IN
–
V
V
OUT
SW
+
–
V
V
OUT
– V
D
DocID15181 Rev 6
L7980 Application ideas
Figure 36. Maximum output current according to max DC switch current (2.0 A):
V
O
= -5 V
DocID15181 Rev 6 37/42
42
Package information L7980
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 37. VFQFPN8 (3 x 3 x 1.08 mm) package outline
38/42 DocID15181 Rev 6
L7980
b
D
D2
A1
A2
A3
E
E2 e
L ddd
Package information
Symbol
A
Table 10. VFQFPN8 (3 x 3 x 1.08 mm) package mechanical data
Dimensions
Min.
0.80
mm
Typ.
0.90
Max.
1.00
Min.
0.0315
inch
Typ.
0.0354
Max.
0.0394
0.05
0.0020
0.18
2.95
2.23
2.95
1.65
0.35
0.02
0.70
0.20
0.23
3.00
2.38
3.00
1.70
0.50
0.40
0.30
3.05
2.48
3.05
1.75
0.45
0.08
0.0071
0.1161
0.0878
0.1161
0.0649
0.0137
0.0008
0.0276
0.0079
0.0091
0.1181
0.0937
0.1181
0.0669
0.0197
0.0157
0.0118
0.1200
0.0976
0.1200
0.0689
0.0177
0.0031
DocID15181 Rev 6 39/42
42
Package information
Figure 38. HSOP8 package outline
L7980
40/42
Symbol
c
D
E
E1 e h
L k ccc
A
A1
A2 b
Min.
0.00
1.25
0.31
0.17
4.80
5.80
3.80
0.25
0.40
0
Table 11. HSOP8 mechanical data
Dimensions mm
Typ.
4.90
6.00
3.90
1.27
inch
Max.
Min.
Typ.
Max.
0.25
5.00
6.20
4.00
1.70 0.0669
0.15
0.00
0.0059
0.51
0.0492
0.0122
0.0201
0.0067
0.1890
0.2283
0.1496
0.1929
0.0098
0.1969
0.2441
0.1575
0.50
1.27
8
0.10
0.0098
0.0157
0.0197
0.0500
0.3150
0.0039
DocID15181 Rev 6
L7980 Order codes
Order codes
L7980A
L7980TR
L7980ATR
Table 12. Order codes
Package
HSOP8
VFQFPN8
HSOP8
Packaging
Tube
Tape and reel
Tape and reel
Date
19-Nov-2008
12-Mar-2009
01-Jul-2010
13-Dec-2010
21-Mar-2014
05-May-2014
Revision
Table 13. Document revision history
Changes
1
2
3
4
5
6
Initial release.
Content reworked to improve readability, no technical changes
Added application information
Updated
(added header).
(replaced ”K” value: “9” by “13”).
Numbered
and
to
(added “V
IN
”and “V
OUT
” with values).
Section 8: Package information on page 38
(reversed order of
,
modifications).
Updated cross-references throughout document.
Minor modifications throughout document.
Updated
related to the VFQFPN8 in tube).
Minor modifications throughout document.
DocID15181 Rev 6 41/42
42
L7980
Please Read Carefully:
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DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
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42/42 DocID15181 Rev 6
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