STL65N3LLH5
N-channel 30 V, 0.0048
Ω
, 19 A, PowerFLAT™ 5x6
STripFET™ V Power MOSFET
Features
Order code
STL65N3LLH5
V
DSS
30 V
R
DS(on) max
I
D
<0.0058 Ω 19 A
(1)
1.
The value is rated according R thj-pcb
■
■
■
■
■
R
DS(on)
* Q g
industry benchmark
Extremely low on-resistance R
DS(on)
Very low switching gate charge
High avalanche ruggedness
Low gate drive power losses
Applications
■ Switching applications
Description
This device is an N-channel Power MOSFET developed using STMicroelectronics’
STripFET™V technology. The device has been optimized to achieve very low on-state resistance, contributing to an FOM that is among the best in its class.
1
2
3
4
PowerFLAT™ 5x6
Figure 1.
Internal schematic diagram
$ $ $ $
' 3 3 3
"OTTOM6IEW 4OP6IEW
!-6
Device summary
Order code
STL65N3LLH5
Marking
65N3LLH5
Package
PowerFLAT™ 5x6
Packaging
Tape and reel
December 2011 Doc ID 14299 Rev 5 1/16 www.st.com
16
3
4
5
1
2
Contents
Contents
STL65N3LLH5
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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2/16 Doc ID 14299 Rev 5
STL65N3LLH5 Electrical ratings
Table 2.
Absolute maximum ratings
Symbol Parameter
V
DS
V
GS
I
D
(1)
I
D
(1)
I
D
(2)
I
D
(2)
I
DM
(3)
P
TOT
(1)
P
TOT
(2)
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (continuous) at T pcb
= 25 °C
Drain current (continuous) at T pcb
=100°C
Drain current (pulsed)
Total dissipation at T
C
= 25°C
Total dissipation at T pcb
= 25°C
Derating factor
T
J
T stg
Operating junction temperature
Storage temperature
1.
The value is rated according to R thj-c
2.
The value is rated according to R thj-pcb
3.
Pulse width limited by safe operating area
Value
11.8
76
60
4
0.03
30
± 22
65
41
19
-55 to 150
Unit
A
A
W
W
W/°C
A
A
A
V
V
°C
Table 3.
Thermal resistance
Symbol Parameter
R thj-case
R thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
1.
When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
Value
2.08
31.3
Unit
°C/W
°C/W
Table 4.
Avalanche data
Symbol
I
AV
Parameter
Not-repetitive avalanche current,
(pulse width limited by Tj Max)
Value
Obsolete Product(s) - Obsolete Product(s)
8.5
Unit
A
E
AS
Single pulse avalanche energy
(starting T
J
= 25 °C, I
D
= I
AV
, V
DD
= 24 V)
180 mJ
Doc ID 14299 Rev 5 3/16
Electrical characteristics STL65N3LLH5
(T
CASE
=25°C unless otherwise specified)
Table 5.
On/off states
Symbol Parameter
V
(BR)DSS
Drain-source breakdown voltage
V
I
I
DSS
GSS
GS(th)
Zero gate voltage drain current (V
GS
= 0)
Gate body leakage current
(V
DS
= 0)
Gate threshold voltage
R
DS(on)
Static drain-source on resistance
Test conditions
I
D
= 250 µA, V
GS
= 0
V
DS
= 30 V,
V
DS
= 30 V at T
C
= 125 °C
V
GS
= ±22 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 9.5 A
V
GS
= 4.5 V, I
D
= 9.5 A
Min.
Typ.
Max.
Unit
30
1
1
10
± 100 nA
1.65
2.5
0.0048
0.006
0.0058
0.0075
V
µA
µA
V
Ω
Ω
Table 6.
Dynamic
Symbol Parameter
C iss
C oss
C rss
Input capacitance
Output capacitance
Reverse transfer capacitance
Q g
Q gs
Q gd
Total gate charge
Gate-source charge
Gate-drain charge
Test conditions
V
DS
=25 V, f=1 MHz,
V
GS
=0
V
DD
=15 V, I
D
= 19 A
V
GS
=4.5 V
(see Figure 14)
Min.
Typ.
Max.
Unit
-
1500
295
39
pF pF pF
-
12
4
4.7
nC nC nC
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4/16 Doc ID 14299 Rev 5
STL65N3LLH5
Table 7.
Switching times
Symbol Parameter t d(on) t r t d(off) t f
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Electrical characteristics
Test conditions
V
DD
=15 V, I
D
= 9.5 A,
R
G
=4.7 Ω, V
GS
=10 V
(see Figure 13)
Min.
Typ.
Max.
Unit
-
9.3
14.5
22.7
4.5
ns ns ns ns
Table 8.
Source drain diode
Symbol Parameter Test conditions
I
SD
I
SDM
(1)
V
SD
(2) t rr
Q rr
I
RRM
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1.
Pulse width limited by safe operating area
2.
Pulsed: pulse duration=300µs, duty cycle 1.5%
I
SD
= 19 A, V
GS
=0
I
SD
= 19 A, di/dt = 100 A/µs,
V
DD
=25 V, Tj=150 °C
Min.
Typ.
Max.
Unit
19 A
76 A
1.1
V
-
25
17.5
1.4
ns nC
A
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Electrical characteristics STL65N3LLH5
2.1 Electrical characteristics (curves)
Figure 2.
Safe operating area Figure 3.
Thermal impedance
I D (A)
HV42910
T
J
=150°C
T
C
=25°C
S ingle p u l s e
100 s a re a
Oper a tion in thi b y m a x R
D
S
(on) limited
10
1
10 m s
100 m s
1 s
0.1
0.01
0.1
1 10
Figure 4.
Output characteristics
V
S D
(V)
Figure 5.
Transfer characteristics
Figure 6.
Normalized B
VDSS
vs temperature Figure 7.
Static drain-source on resistance
BV
D SS
(norm)
HV42950
HV42990
R
D S (on)
( Ω )
1.1
1.0
8
I D =17.5A
V
G S
=10V 5
1.06
1.02
I
D
=1 mA
Obsolete Product(s) - Obsolete Product(s)
1
0.9
8
0.96
0.94
0.92
-55 3 0 -5 20 45 70 95 120 145 T
J
(°C)
4
3 .5
3
2 7 12 17 22 27 I
D
(A)
6/16 Doc ID 14299 Rev 5
STL65N3LLH5 Electrical characteristics
Figure 8.
Gate charge vs gate-source voltage Figure 9.
Capacitance variations
V
G S
(V)
12
10
8
6
4
2
0
0
I D =14 A
V
G S
=5 V
V DD =15 V
HV42940
C(pF)
2000
1500
1000
500
Cr ss f=1MHz
V
G S
=0
HV429 3 0
Ci ss
Co ss
5 10 15 20 Qg(nC)
0
0 10 20 C(pF)
Figure 10. Normalized gate threshold voltage vs temperature
HV42960
V
G S (th)
(norm)
1.2
I
D
=250 µ A
1
0.
8
0.6
0.4
0.2
0
-55 3 0 -5 20 45 70 95 120 145 T
J
(°C)
Figure 11. Normalized on resistance vs temperature
HV42970
R
D S (on)
(norm)
1.
8
1.6
1.4
I
D
= 8 .5 A
V
G S
=10 V
1.2
1
0.
8
0.6
0.4
0.2
0
-55 3 0 -5 20 45 70 95 120 145 T
J
(°C)
Figure 12. Source-drain diode forward characteristics
HV429 8 0
V
S D
(V)
0.9
T
J
=-55 °C
0.
8
0.7
Obsolete Product(s) - Obsolete Product(s)
0.6
T
J
=25 °C
T
J
=150 °C
0.5
0.4
0 5 10 15 I
S D
(A)
Doc ID 14299 Rev 5 7/16
STL65N3LLH5 Test circuits
3 Test circuits
Figure 13. Switching times test circuit for resistive load
Figure 14. Gate charge test circuit
V
DD
12V
47k
Ω
100nF
1k Ω
V
G S
V
D
R
G
R
L
D.U.T.
2200
μ
F
3 .
3
μ
F
V
DD
V i
=20V=V
GMAX
2200
μ F
I
G
=CON S T
2.7k
Ω
100 Ω
D.U.T.
V
G
P
W
47k
Ω
P
W
1k
Ω
AM0146 8 v1 AM01469v1
Figure 15. Test circuit for inductive load switching and diode recovery times
Figure 16. Unclamped inductive load test circuit
25 Ω
G
A
D
D.U.T.
S
B
R
G
A
FA S T
DIODE
A
B
B
G
D
S
L=100 μ H
3 .
3
μ F
1000
μ F
V
DD
V i
V
D
I
D
L
D.U.T.
2200
μ F
3 .
3
μ F
V
DD
P w
AM01470v1
Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform
AM01471v1 t on t off V
(BR)D SS t r
V
D
Obsolete Product(s) - Obsolete Product(s)
90 %
90 %
I
DM td on td off t f
10 %
10 % V
D S
I
D 0
V
DD
V
DD
90 %
V
G S
0
10 %
AM01472v1 AM0147 3 v1
8/16 Doc ID 14299 Rev 5
STL65N3LLH5
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 14299 Rev 5 9/16
Package mechanical data
D
D1
D2
E
E1
E2
E4 e
L
A
A1
A3 b
Table 9.
Dim.
PowerFLAT™ 5x6 type C-B mechanical data mm
Min.
0.80
0
0.35
4.15
3.43
2.58
0.70
Typ.
5.00
4.75
4.20
6.00
5.75
3.48
0.83
0.02
0.20
0.40
2.63
1.27
0.80
STL65N3LLH5
4.25
3.53
2.68
0.90
Max.
0.93
0.05
0.47
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10/16 Doc ID 14299 Rev 5
STL65N3LLH5
Figure 19.
PowerFLAT™ 5x6 type C-B drawing
Bottom View e/2
1 e
PIN 1 IDENTIFICATION
EXPO S ED PAD
E4
E2
Package mechanical data b 8 x
D2/2
D2
Top View
D/2
E/2
E1 E
PIN 1 IDENTIFICATION 1
D1
D
0.1
C
A 3
S EATING PLANE
A A1
C
0.0
8 C Obsolete Product(s) - Obsolete Product(s)
72 8 646 3 _Rev_H
Doc ID 14299 Rev 5 11/16
Package mechanical data
Table 10.
PowerFLAT™ 5x6 type S-C mechanical data mm
Dim.
Min.
Typ.
A
A1
A2 b
D
E
D2
E2 e e1
L
K
0.80
0.02
0.30
4.11
3.50
0.715
1.05
0.25
5.20
6.15
1.27
0.65
STL65N3LLH5
4.31
3.70
1.015
1.35
Max.
1.00
0.05
0.50
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12/16 Doc ID 14299 Rev 5
STL65N3LLH5
Figure 20.
PowerFLAT™ 5x6 type S-C mechanical data
"OTTOMVIEW
Package mechanical data
4OPVIEW
3IDEVIEW
?$?TYPE#
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Doc ID 14299 Rev 5 13/16
Package mechanical data STL65N3LLH5
Figure 21.
PowerFLAT™ 5x6 recommended footprint (dimensions in mm)
5.
3 5
4.41
1.27
0.62
Footprint
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STL65N3LLH5 Revision history
Table 11.
Document revision history
Date Revision
04-Jan-2007
01-Apr-2008
07-May-2008
23-Sep-2008
02-Dec-2011
1
2
3
4
5
Changes
First release
Document status promoted from preliminary data to datasheet.
Updated Figure 9: Capacitance variations .
V
GS
value has been changed on
Table 2 and
Table 5 .
Figure 7: Static drain-source on resistance has been modified.
Section 4: Package mechanical data has been updated.
Minor text changes.
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Doc ID 14299 Rev 5 15/16
STL65N3LLH5
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