STMicroelectronics STL120N4F6AG Datasheet
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STL120N4F6AG
Automotive-grade Nchannel 40 V, 2.9 mΩ typ., 55 A
STripFET™ F6 Power MOSFET in a PowerFLAT™ 5x6 package
Datasheet - production data
Features
Order code V
DS
R
DS(on)
max.
STL120N4F6AG 40 V 3.6 mΩ
AEC-Q101 qualified
Very low on-resistance
Very low gate charge
High avalanche ruggedness
Low gate drive power loss
Wettable flank package
I
D
55 A
Figure 1: Internal schematic diagram
Applications
Switching applications
Description
This device is an N-channel Power MOSFET developed usi ng the STripFET™ F6 technology with a new trench gate structure. The resulting
Power MOSFET exhibits very low R
DS(on)
in all packages.
Order code
STL120N4F6AG
Table 1: Device summary
Marking
120N4F6
Package
PowerFLAT™ 5x6
Packaging
Tape and reel
March 2017 DocID027498 Rev 4
This is information on a product in full production.
1/15 www.st.com
Contents
Contents
STL120N4F6AG
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
Electrical characteristics (curves) ...................................................... 6
4 Package information ....................................................................... 9
PowerFLAT™ 5x6 WF type R package information .......................... 9
P owerFLAT™ 5x6 WF packing information .................................... 12
5 Revision history ............................................................................ 14
2/15 DocID027498 Rev 4
STL120N4F6AG
1 Electrical ratings
Symbol
V
GS
V
DS
I
I
I
P
TOT
T stg
T j
Table 2: Absolute maximum ratings
Parameter
Gate-source voltage
Drain-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Storage temperature range
Operating junction temperature range
Electrical ratings
Notes:
(1)
Drain current is limited by package, the current capability of the silicon is 120 A at 25 °C.
(2)
Pulse width is limited by safe operating area.
Symbol
Table 3: Thermal data
Parameter Value
R thj-case
Thermal resistance junction-case
R
Thermal resistance junction-pcb
1.3
31.3
Notes:
(1)
When mounted on 1 inch² 2 Oz. Cu board, t ≤ 10 s
Symbol
Table 4: Avalanche characteristics
Parameter
I
AV
E
AS
Avalanche current, repetitive or not repetitive
(pulse width limited by maximum junction temperature)
Single pulse avalanche energy
(T j
= 25 °C, I
C
= I
AV
, V
DD
= 25 V)
Value
20
200
Value
±20
40
55
55
220
115
-55 to 175
Unit
V
V
A
A
A
W
°C
°C
Unit
°C/W
Unit
A mJ
DocID027498 Rev 4 3/15
Electrical characteristics
2 Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: On/off states
Test conditions
V
(BR)DSS
I
DSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 250 µA
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 40 V
V
GS
= 0 V, V
DS
= 40 V,
Gate-body leakage current V
DS
= 0 V, V
GS
= ±20 V I
GSS
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source on-resistance
V
V
DS
GS
= V
GS
, I
D
= 10 V, I
= 250 µA
D
= 13 A
STL120N4F6AG
Min. Typ. Max. Unit
40
2
V
1 µA
10 µA
±100 nA
4 V
2.9 3.6 mΩ
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
Q g
Q gs
Q gd
R
G
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Intrinsic gate resistance
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0 V
V
DD
= 20 V, I
D
= 26 A,
V
GS
= 0 to 10 V
(see Figure 14: "Test circuit for gate charge behavior" )
f = 1 MHz, I
D
= 0 A
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off-delay time t f
Fall time
Table 7: Switching times
Test conditions
V
DD
= 20 V, I
D
= 13 A,
R
G
= 4.7 Ω, V
GS
= 10 V
Min. Typ. Max. Unit
-
-
3700
625
-
- pF pF
-
-
-
-
-
295
63
19
15
1.5
-
-
-
-
- pF
Min. Typ. Max. Unit
-
-
-
20
70
40
-
-
- ns ns ns
- 20 - nC nC nC
Ω ns
4/15 DocID027498 Rev 4
STL120N4F6AG
Symbol
I
SD
Source-drain current
I
Source-drain current
(pulsed)
V
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
RRM
Parameter
Table 8: Source drain diode
Test conditions
Reverse recovery current
V
GS
= 0 V, I
SD
= 13 A
I
SD
= 26 A, di/dt = 100 A/µs,
V
DD
= 25 V
(see Figure 15: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
- 55 A
- 220 A
1.1 -
-
-
40
5.6
V ns nC
- 2.8 A
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
Pulse test: pulse duration = 300 µs, duty cycle 1.5%
DocID027498 Rev 4 5/15
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STL120N4F6AG
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/15 DocID027498 Rev 4
STL120N4F6AG
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized V
(BR)DSS
vs temperature
Figure 10: Normalized gate threshold voltage vs temperature
Figure 11: Normalized on-resistance vs. temperature
Figure 12: Source-drain diode forward characteristics
DocID027498 Rev 4 7/15
Test circuits
3 Test circuits
Figure 13: Test circuit for resistive load switching times
STL120N4F6AG
Figure 14: Test circuit for gate charge behavior
Figure 15: Test circuit for inductive load switching and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform
8/15 DocID027498 Rev 4
STL120N4F6AG
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
PowerFLAT™ 5x6 WF type R package information
Figure 19
: PowerFLAT™ 5x6 WF type R package outline
DocID027498 Rev 4
A0Y5_8231817_R_WF_Rev_14
9/15
Package information
Dim.
D4
D5
D6 e
E
E2
E3
C
D
D2
D3
A
A1
A2 b
E4
E5
E6
E7
E9
E10
K
L
L1
ϴ
Table 9: PowerFLAT™ 5x6 WF type R mechanical data mm
Min. Typ.
0.80
0.02
0.25
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
6.00
5.20
4.20
5.00
0.4
0.3
1.27
6.40 6.20
3.50
2.35
0.40
0.08
0.20
0.85
4.00
3.55
1.275
0.725
0.175
0°
0.325
1.00
4.20
3.70
0.825
0.275
STL120N4F6AG
Max.
1.00
0.05
6.60
3.70
2.55
0.60
0.28
0.45
1.15
4.40
3.85
1.575
0.925
0.375
12°
0.50
6.10
5.40
4.45
4.35
5.10
0.55
0.45
10/15 DocID027498 Rev 4
STL120N4F6AG Package information
Figure 20
: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)
8231817_FOOTPRINT_rev14
DocID027498 Rev 4 11/15
Package information
4.2 PowerFLAT™ 5x6 WF packing information
STL120N4F6AG
Figure 21
: PowerFLAT™ 5x6 WF tape (dimensions are in mm)
Figure 22
: PowerFLAT™ 5x6 package orientation in carrier tape
12/15 DocID027498 Rev 4
STL120N4F6AG Package information
Figure 23
: PowerFLAT™ 5x6 reel (dimensions are in mm)
DocID027498 Rev 4 13/15
Revision history
5
STL120N4F6AG
Revision history
Date Revision
Table 10: Document revision history
Changes
19-Feb-2015
11-Apr-2016
10-Jan-2017
09-Mar-2017
1
2
3
4
First release.
Updated Table 2: "Absolute maximum ratings"
Minor text changes.
Updated Table 2: "Absolute maximum ratings" and Table 8: "Source drain diode" .
Updated Figure 6: "Gate charge vs gate-source voltage" and Figure 8:
"Capacitance variations" .
Minor text changes
Updated Table 2: "Absolute maximum ratings" and Table 3: "Thermal data" .
Updated Figure 2: "Safe operating area" , Figure 3: "Thermal impedance"
and Figure 8: "Capacitance variations" .
Added Figure 9: "Normalized V(BR)DSS vs temperature" and Figure
10: "Normalized gate threshold voltage vs temperature" .
Minor text changes
14/15 DocID027498 Rev 4
STL120N4F6AG
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– All rights reserved
DocID027498 Rev 4 15/15
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