STMicroelectronics VNQ830PEP-E Datasheet

VNQ830PEP-E

Quad channel high side driver

Features

Type

VNQ830PEP-E

1. Per each channel.

R

DS(on)

60m  (1)

I

OUT

14A

(1)

V

CC

36V

• CMOS compatible inputs

• Open drain status outputs

• On-state open load detection

• Off-state open load detection

• Shorted load protection

• Undervoltage and overvoltage shutdown

• Loss of ground protection

• Very low standby current

• Reverse battery protection (a)

• In compliance with the 2002/95/EC european directive a. See

Application schematic on page 16

Table 1.

Device summary

Package

PowerSSO-24

PowerSSO-24

Description

The VNQ830PEP-E is a monolithic device made using | STMicroelectronics VIPower™ M0-3

Technology. The VNQ830PEP-E is intended for driving any type of multiple load with one side connected to ground.

The Active V

CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table).

Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects the open load condition in both the on and off-state.

In the off-state the device detects if the output is shorted to V

CC

. The device automatically turns off in the case where the ground pin becomes disconnected.

Order codes

Tube

VNQ830PEP-E

Tape and reel

VNQ830PEPTR-E

September 2013 Doc ID 10871 Rev 8 1/27 www.st.com

1

2/27

1

2

Contents

Contents

3

4

5

6

VNQ830PEP-E

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1

GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16

3.1.1

Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 16

3.1.2

Solution 2: a diode (D

GND

) in the ground line . . . . . . . . . . . . . . . . . . . . 17

3.2

Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3

MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4

Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.5

Maximum demagnetization energy (V

CC

= 13.5V) . . . . . . . . . . . . . . . . . . 19

Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1

PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1

ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2

PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Doc ID 10871 Rev 8

VNQ830PEP-E

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 5.

Table 6.

Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 7.

Table 8.

Table 9.

V

CC

- output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Switching (V

CC

= 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 10.

Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 11.

Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 12.

Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 13.

Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 14.

Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 15.

Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 16.

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 17.

PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 18.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Doc ID 10871 Rev 8 3/27

4/27

List of figures

List of figures

VNQ830PEP-E

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4.

Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5.

Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6.

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 7.

Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8.

High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 9.

Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10.

Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 11.

Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 12.

Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 13.

ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 14.

On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 15.

Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 16.

Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 17.

On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 18.

Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 19.

Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 20.

Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 21.

Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 22.

Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 23.

Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 24.

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 25.

Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 26.

Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 27.

PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 28.

Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 20

Figure 29.

PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 21

Figure 30.

Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 21

Figure 31.

PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 32.

PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 33.

PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Doc ID 10871 Rev 8

VNQ830PEP-E

1

Block diagram and pin description

Block diagram and pin description

Figure 1.

Block diagram

V

CC

CLAMP

GND

INPUT1

STATUS1

INPUT2

STATUS2

INPUT3

STATUS3

INPUT4

STATUS4

OVERTEMP. 1

LOGIC

OVERVOLTAGE

UNDERVOLTAGE

CLAMP 1

DRIVER 1

CURRENT LIMITER 1

OPENLOAD ON 1

OPENLOAD OFF 1

V

CC

OUTPUT1

INPUT2

STATUS2

CONTROL & PROTECTION

EQUIVALENT TO

CHANNEL1

V

CC

OUTPUT2

INPUT3

STATUS3

CONTROL & PROTECTION

EQUIVALENT TO

CHANNEL1

V

CC

INPUT4

STATUS4

CONTROL & PROTECTION

EQUIVALENT TO

CHANNEL1

V

CC

OUTPUT3

OUTPUT4

Figure 2.

Configuration diagram (top view)

V

CC

GND

INPUT1

STATUS1

INPUT2

STATUS2

INPUT3

STATUS3

INPUT4

STATUS4

N.C.

V

CC

OUTPUT1

OUTPUT1

OUTPUT1

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT3

OUTPUT3

OUTPUT3

OUTPUT4

OUTPUT4

OUTPUT4

TAB = V

CC

Table 2.

Suggested connections for unused and not connected pins

Connection / pin Status N.C.

Output Input

Floating

To ground

X X

X

X X

Through 10K  resistor

Doc ID 10871 Rev 8 5/27

Electrical specifications VNQ830PEP-E

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality document.

Table 3.

Symbol

V

CC

- V

CC

- I

GND

I

OUT

- I

OUT

I

IN

I

STAT

V

ESD

P tot

T j

T c

T stg

Absolute maximum ratings

Parameter

DC supply voltage

Reverse DC supply voltage

DC reverse ground pin current

DC output current

Reverse DC output current

DC input current

DC Status current

Electrostatic discharge (human body model: R=1.5K



C = 100pF)

– Input

– Status

– Output

– V

CC

Power dissipation (per island) at T lead

= 25°C

Junction operating temperature

Case operating temperature

Storage temperature

Value

41

- 0.3

- 200

Internally limited

- 12

+/- 10

+/- 10

4000

4000

5000

5000

83

Internally limited

- 40 to 150

- 55 to 150

W

°C

V

V

V

V

°C

°C

Unit

V

V mA

A

A mA mA

6/27

Table 4.

Symbol

Thermal data (per island)

Parameter Value Unit

R thj-case

Thermal resistance junction-case 1.5

°C/W

R thj-amb

Thermal resistance junction-ambient

(one chip ON)

56

(1)

41.7

(2)

°C/W

1. When mounted on a standard single-sided FR-4 board with 0.5cm

2 mounting and no artificial air flow.

of Cu (at least 35 µm thick). Horizontal

2. When mounted on a standard single-sided FR-4 board with 8cm 2 mounting and no artificial air flow.

of Cu (at least 35  µm thick). Horizontal

Doc ID 10871 Rev 8

VNQ830PEP-E Electrical specifications

Note:

Values specified in this section are for 8V < V

CC otherwise stated.

< 36V; -40°C < T j

< 150°C, unless

Figure 3.

Current and voltage conventions

I

S

V

CC

V

F1

(*)

V

CC

I

INn

INPUTn

V

INn

I

STATn

STATUSn

OUTPUTn

I

OUTn

V

OUTn

V

STATn

GND

I

GND

V

Fn

= V

CCn

- V

OUTn

during reverse battery condition.

Table 5.

Symbol

V

CC

V

USD

V

OV

Power output

Parameter

Operating supply voltage

Undervoltage shutdown

Overvoltage shutdown

R

ON

On-state resistance

Test conditions

I

OUT

= 2A; T j

= 25°C

I

OUT

= 2A; V

CC

> 8V

Off-state; V

CC

= 13V;

V

IN

= V

OUT

= 0V

I

S

I

L(off1)

I

L(off2)

Supply current

Off-state; V

CC

= 13V;

V

IN

= V

OUT

= 0V;

T j

= 25°C

On-state; V

CC

= 13V; V

IN

= 5V;

I

OUT

= 0A

Off-state output current V

IN

= V

OUT

= 0V

Off-state output current V

IN

= 0V; V

OUT

= 3.5V

Min. Typ. Max. Unit

5.5

13

3

36

4

36

5.5

65

120

V

V

V m  m 

20 60 µA

20 40 µA

0

-75

8.5

13.5

mA

50 µA

0 µA

Doc ID 10871 Rev 8 7/27

Electrical specifications

Table 5.

Symbol

I

L(off3)

I

L(off4)

Power output (continued)

Parameter Test conditions

Off-state output current

Off-state output current

V

IN

= V

OUT

= 0V; V

CC

= 13V;

T j

= 125°C

V

IN

= V

OUT

= 0V; V

CC

= 13V;

T j

= 25°C

Table 6.

Symbol

T

TSD

T

R

T hyst t

SDL

Protections

Parameter

Shutdown temperature

Reset temperature

Thermal hysteresis

Status delay in overload conditions

I lim

Current limitation

V demag

Turn-off output clamp voltage

Test conditions

T j

> T

TSD

V

CC

= 13V

5.5V < V

CC

< 36V

I

OUT

= 2A; L = 6mH

Note:

VNQ830PEP-E

Min. Typ. Max. Unit

5 µA

3 µA

Min.

Typ.

Max.

Unit

150 175 200 °C

135 °C

7 15 °C

14 18

V

CC

41

V

CC

48

-

20

23

23

V

CC

55

-

µs

A

A

V

To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.

Table 7.

Symbol

V

F

V

CC

- output diode

Parameter

Forward on voltage

Test conditions

- I

OUT

= 1.3A; T j

= 150°C

Min.

Typ. Max.

Unit

0.6

V

Table 8.

Symbol t d(on) t d(off)

Switching (V

CC

= 13V; T j

= 25°C)

Parameter Test conditions

Turn-on delay time

Turn-off delay time dV

OUT

/dt

(on)

Turn-on voltage slope dV

OUT

/dt

(off)

Turn-off voltage slope

R

L

= 6.5

to V

 from V

IN

rising edge

OUT

= 1.3V (see Figure 5 )

R

L

= 6.5

 from V

IN to V

OUT

falling edge

= 11.7V (see

Figure 5

)

R

L

V

= 6.5

 from V

OUT

OUT

= 1.3V to

= 10.4V (see Figure 5

)

R

L

= 6.5

 from V

OUT to V

OUT

= 11.7V

= 1.3V (see Figure 5 )

Min.

-

-

-

-

Typ.

30

30

See

Figure 10

See

Figure 12

Max. Unit

-

-

-

µs

µs

V/µs

V/µs

8/27 Doc ID 10871 Rev 8

VNQ830PEP-E Electrical specifications

Table 9.

Symbol

V

IL

I

IL

V

IH

I

IH

V

I(hyst)

Logic inputs

Parameter

Input low level

Low level input current

Input high level

High level input current

Input hysteresis voltage

V

ICL

Input clamp voltage

Test conditions

V

IN

= 1.25V

V

IN

= 3.25V

Min.

Typ.

Max.

Unit

1

3.25

0.5

6 6.8

- 0.7

1.25

10

8

V

µA

V

µA

V

V

V

I

IN

= 1mA

I

IN

= -1mA

Table 10.

Status pin

Symbol

V

STAT

I

LSTAT

C

STAT

V

SCL

Parameter

Status low output voltage

Status leakage current

Status pin input capacitance

Status clamp voltage

Test conditions

I

STAT

= 1.6mA

Normal operation; V

STAT

5V

=

Normal operation; V

STAT

5V

=

I

STAT

= 1mA

I

STAT

= - 1mA

Min.

Typ. Max.

Unit

0.5

V

10 µA

6 6.8

- 0.7

100 pF

8 V

V

Table 11.

Open-load detection

Symbol

I

OL t

DOL(on)

V

OL t

DOL(off)

Parameter

Open-load on-state detection threshold V

IN

= 5V

Open-load on-state detection delay I

OUT

= 0A

Open-load off-state voltage detection threshold

Open-load detection delay at turn-off

V

Test conditions Min. Typ. Max. Unit

IN

= 0V

35

1.5

70

2.5

140 mA

200 µs

3.5

1000

V

µs

Figure 4.

Status timings

OPEN LOAD STATUS TIMING (with external pull-up)

V

OUT

> V

OL

I

OUT

< I

OL

V

INn

V

INn

OVER TEMP STATUS TIMING

T j

> T

TSD

V

STATn

V

STATn t

SDL t

SDL t

DOL(off) t

DOL(on)

Doc ID 10871 Rev 8 9/27

Electrical specifications

Figure 5.

Switching characteristics

V

OUTn

80% dV

OUT

/dt

(on)

10%

V

INn t d(on) t d(off)

90% dV

OUT

/dt

(off)

VNQ830PEP-E t t

Table 12.

Truth table

Conditions

Normal operation

Current limitation

Overtemperature

Undervoltage

Overvoltage

Output voltage > V

OL

Output current < I

OL

Input

L

H

L

H

L

H

L

H

L

H

L

H

H

L

H

Output

H

H

L

L

L

H

L

L

L

L

L

X

X

L

H

Status

H

H

H

(T j

< T

TSD

) H

(T j

> T

TSD

) L

H

L

H

H

X

X

H

L

L

H

10/27 Doc ID 10871 Rev 8

VNQ830PEP-E Electrical specifications

Table 13.

Electrical transient requirements (part 1/3)

ISO T/R

7637/1

Test pulse

I II III

Test level

IV

3a

3b

1

2

4

5

- 25V

+ 25V

- 25V

+ 25V

- 4V

+ 26.5V

- 50V

+ 50V

- 50V

+ 50V

- 5V

+ 46.5V

- 75V

+ 75V

- 100V

+ 75V

- 6V

+ 66.5V

- 100V

+ 100V

- 150V

+ 100V

- 7V

+ 86.5V

Delays and impedance

2ms, 10 

0.2ms, 10 

0.1µs, 50 

0.1µs, 50 

100ms, 0.01



400ms, 2 

Table 14.

Electrical transient requirements (part 2/3)

ISO T/R

7637/1

Test pulse

I II

Test level

3a

3b

1

2

4

5

C

C

C

C

C

C

C

C

C

C

C

E

III

C

C

C

C

C

E

IV

C

C

C

C

C

E

Table 15.

Electrical transient requirements (part 3/3)

Class Contents

C

E

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.

Doc ID 10871 Rev 8 11/27

Electrical specifications

Figure 6.

Waveforms

NORMAL OPERATION

INPUT n

OUTPUT VOLTAGE n

STATUS n

V

CC

INPUT n

OUTPUT VOLTAGE n

STATUS n

V

UNDERVOLTAGE

USD

V

USDhyst undefined

V

CC

INPUT n

OUTPUT VOLTAGE n

STATUS n

V

CC

<V

OV

OVERVOLTAGE

V

CC

>V

OV

OPEN LOAD with external pull-up

INPUT n

OUTPUT VOLTAGE n

STATUS n

V

OL

V

OUT

>V

OL

INPUT n

OUTPUT VOLTAGE n

STATUS n

OPEN LOAD without external pull-up

T j

INPUT n

OUTPUT CURRENT n

STATUS n

T

T

TSD

R

OVERTEMPERATURE

12/27 Doc ID 10871 Rev 8

VNQ830PEP-E

VNQ830PEP-E Electrical specifications

Figure 7.

Off-state output current

IL (off1) (µA)

2.8

2.45

2.1

1.75

1.4

1.05

0.7

0.35

0

-50 -25

Vcc=36

0 25 50

Tc (°C)

75 100 125 150 175

Figure 9.

Input clamp voltage

Vicl (V)

8

7.8

7.6

7.4

7.2

7

6.8

6.6

6.4

6.2

6

-50 -25

Iin=1mA

0 25 50 75

Tc (°C)

100 125 150 175

Figure 11. Overvoltage shutdown

Vov (V)

50

47.5

45

42.5

40

37.5

35

32.5

30

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 8.

High level input current

Iih (µA)

8

7

6

5

4

3

2

1

0

-50 -25

Vcc=13V

Vin=3.25V

0 25 50 75

Tc (°C)

100 125 150 175

Figure 10. Turn-on voltage slope

0.6

0.5

0.4

0.3

0.2

dVout/dt (on) (V/ms)

0.9

0.8

0.7

Vcc=13V

Rl=6.5Ohm

0.1

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 12. Turn-off voltage slope

0.2

0.15

0.1

0.05

0

-50 dVout/dt (off) (V/ms)

0.5

0.45

0.4

Vcc=13V

Rl=6.5Ohm

0.35

0.3

0.25

-25 0 25 50 75

Tc (°C)

100 125 150 175

Doc ID 10871 Rev 8 13/27

Electrical specifications

Figure 13. I

LIM

vs T case

Ilim (A)

26

24

22

20

18

16

14

12

10

-50 -25

Vcc=13V

0 25 50 75

Tc (°C)

100 125 150 175

Figure 15. Input high level

Vih(V)

4

3.8

3.6

3.4

3.2

3

2.8

2.6

2.4

2.2

2

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 17. On-state resistance vs Tcase

Ron (mOhm)

160

140

120

100

Iout=2A

Vcc=8v; 13V; 36V

80

60

40

20

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

VNQ830PEP-E

Figure 14. On-state resistance vs V

CC

Ron (mOhm)

180

160

140

120

100

80

60

40

20

0

0 5

Iout=2A

10 15 20

Vcc (V)

25

Tc=150°C

Tc=25°C

Tc=-40°C

30 35 40

Figure 16. Input hysteresis voltage

Vhyst (V)

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 18. Input low level

Vil (V)

4

3.6

3.2

2.8

2.4

2

1.6

1.2

0.8

0.4

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

14/27 Doc ID 10871 Rev 8

VNQ830PEP-E

Figure 19. Status leakage current

Istat (nA)

300

270

240

210

180

150

120

90

60

30

0

-50 -25

Vstat=5V

0 25 50 75

Tc (°C)

100 125 150 175

Figure 21. Status clamp voltage

Vscl (V)

8

7.8

7.6

7.4

7.2

7

6.8

6.6

6.4

6.2

6

-50 -25

Iin=1mA

0 25 50 75

Tc (°C)

100 125 150 175

Figure 23. Open-load off-state voltage detection threshold

Vol (V)

3.8

3.6

3.4

3.2

3

2.8

2.6

2.4

2.2

2

1.8

-50 -25

Vin=0V

0 25 50 75

Tc (°C)

100 125 150 175

Electrical specifications

Figure 20. Status low output voltage

Vstat (V)

0.8

0.7

Istat=1.6mA

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 22. Open-load on-state detection threshold

Iol (mA)

0.13

0.12

0.11

0.1

0.09

0.08

0.07

0.06

0.05

0.04

-50 -25

Vcc=13V

0 25 50 75

Tc (°C)

100 125 150 175

Doc ID 10871 Rev 8 15/27

Application information

Figure 24. Application schematic

+5V

+5V

R prot STATUSn

 C R prot

INPUTn

V

CC

GND

V

GND

R

GND

D

GND

OUTPUTn

VNQ830PEP-E

D ld

3.1

3.1.1

GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against reverse battery.

Solution 1: a resistor in the ground line (R

GND

only)

This can be used with any type of load.

The following show how to dimension the R

GND resistor:

1.

R

GND

 600mV / 2 (I

S(on)max

)

2. R

GND

  V

CC

) / (- I

GND

) where - I

GND

is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.

Power dissipation in R

GND

(when V

CC

< 0 during reverse battery situations) is:

P

D

= (- V

CC

) 2 / R

GND

This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I

S(on)max maximum on-state currents of the different devices.

becomes the sum of the

16/27 Doc ID 10871 Rev 8

VNQ830PEP-E

3.1.2

Application information

Please note that, if the microprocessor ground is not shared by the device ground, then the

R

GND will produce a shift (I

S(on)max

* R

GND

) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R

GND

.

If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below.

Solution 2: a diode (D

GND

) in the ground line

A resistor (R

GND

= 1k  ) should be inserted in parallel to D

GND

if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD.

Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum

Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.

3.3

D ld

is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the

V

CC

maximum DC rating. The same applies if the device is subject to transients on the V line that are greater than those shown in the ISO T/R 7637/1 table.

CC

MCU I/O protection

If a ground protection network is used and negative transients are present on the V

CC the control pins will be pulled negative. ST suggests to insert a resistor (R prot prevent the µC I/O pins from latching up.

line,

) in line to

The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC

I/Os:

- V

CCpeak

/ I latchup

 R prot

 (V

OH  C

- V

IH

- V

GND

) / I

IHmax

Example

For the following conditions:

V

CCpeak

= - 100V

I latchup

 20mA

V

OH  C

 4.5V

5k   R prot

 65k  .

Recommended values are:

R prot

= 10k 

Doc ID 10871 Rev 8 17/27

Application information VNQ830PEP-E

Off-state open load detection requires an external pull-up resistor (R

PU

OUTPUT pin and a positive supply voltage (V

PU microprocessor.

) connected between

) like the +5V line used to supply the

The external resistor has to be selected according to the following requirements:

1) no false open load indication when load is connected: in this case we have to avoid V

OUT to be higher than V

Olmin

; this results in the following condition

V

OUT

= (V

PU

/ (R

L

+ R

PU

))R

L

< V

Olmin.

2) no misdetection when load is disconnected: in this case the V

OUT

has to be higher than

V

OLmax

; this results in the following condition R

PU

< (V

PU

- V

OLmax

) / I

L(off2)

.

Because I s(OFF) up resistor R standby.

PU

may significantly increase if V out

is pulled high (up to several mA), the pull-

should be connected to a supply that is switched OFF when the module is in

Figure 25. Open-load detection in off-state

V batt.

V

PU

V

CC

R

PU

INPUT

DRIVER

+

LOGIC

I L(off2)

OUT

STATUS

+

-

V

OL

R

R

L

GROUND

18/27 Doc ID 10871 Rev 8

VNQ830PEP-E

3.5

Application information

Maximum demagnetization energy (V

CC

= 13.5V)

Figure 26. Maximum turn-off current versus load inductance

I LMAX (A)

100

10

C

B

A

1

0.01

0.1

1

L(mH)

A = single pulse at T

Jstart

= 150ºC

B= repetitive pulse at T

Jstart

= 100ºC

C= repetitive pulse at T

Jstart

= 125ºC

V

IN

, I

L

Demagnetization Demagnetization

10 100

Demagnetization

Note: t

Values are generated with R

L

= 0 

In case of repetitive pulses, T jstart

(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C.

Doc ID 10871 Rev 8 19/27

Package and PC board thermal data

4 Package and PC board thermal data

4.1 PowerSSO-24 thermal data

Figure 27. PowerSSO-24 PC board

VNQ830PEP-E

Note: Layout condition of R th

and Z th

measurements (PCB FR4 area= 78 mm x 78 mm, PCB thickness=2 mm, Cu thickness=70 mm (front and back side), Copper areas: from minimum pad lay-out to 8 cm 2 ).

Figure 28. R thj-amb

vs PCB copper area in open box free air condition (one channel ON)

RTHj_amb(°C/W)

60

55

50

45

40

35

30

0 2 4 6

PCB Cu heatsink area (cm^2)

8 10

20/27 Doc ID 10871 Rev 8

VNQ830PEP-E Package and PC board thermal data

Figure 29. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON)

100

ZTH (°C/W)

Footprint

8 cm 2

10

1

0.1

0.0001

0.001

0.01

0.1

Time (s)

1 10 100 1000

Figure 30. Thermal fitting model of a double channel HSD in PowerSSO-24 (b) b. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

Doc ID 10871 Rev 8 21/27

Package and PC board thermal data

Equation 1 : pulse calculation formula :

ZTH



= RTH where  = t

P

/T

  + –  

Table 16.

Thermal parameters

Area/island (cm 2 )

R1 = R7 = R9 = R11 (°C/W)

R2 = R8 = R10 = R12 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1 = C7 = C9 = C11 (W.s/°C)

C2 = C8 = C10 = C12 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

VNQ830PEP-E

Footprint

13.5

37

0.0006

0.0025

0.1

0.9

1

4

0.025

0.08

0.7

3

8

22

5

22/27 Doc ID 10871 Rev 8

VNQ830PEP-E

5

Package and packing information

Package and packing information

5.1 ECOPACK

®

packages

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

Figure 31. PowerSSO-24 package dimensions

Doc ID 10871 Rev 8 23/27

Package and packing information

Table 17.

PowerSSO-24 mechanical data (1) (2)

Millimeters

Symbol

Min.

Typ.

G1

H h e e3

F

G

A

A2 a1 b c

D

(3)

E (3)

2.15

0

0.33

0.23

10.10

7.40

10.1

0.8

8.8

2.3

k

L

O

0°

0.55

Q

S

T

1.2

0.8

2.9

U

N

X

3.65

1

4.1

Y

6.5

4.9

(4)

1. No intrusion allowed inwards the leads.

2. Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side

3. “D and E” do not include mold flash or protusions.

Mold flash or protusions shall not exceed 0.15 mm.

4. Variations for small window lead frame option.

VNQ830PEP-E

10º

4.7

7.1

5.5

(4)

Max.

2.45

2.35

0.10

0.51

0.32

10.50

7.60

0.1

0.06

10.5

0.4

8°

0.85

24/27 Doc ID 10871 Rev 8

VNQ830PEP-E Package and packing information

Figure 32. PowerSSO-24 tube shipment (no suffix)

C

B

Base Q.ty

Bulk Q.ty

49

1225

Tube length (± 0.5) 532

A 3.5

B

C (± 0.1)

13.8

0.6

All dimensions are in mm.

A

Figure 33. PowerSSO-24 tape and reel shipment (suffix “TR”)

Reel dimensions

Base Q.ty

Bulk Q.ty

A (max)

B (min)

C (± 0.2)

F

G (+ 2 / -0)

N (min)

T (max)

1000

1000

330

1.5

13

20.2

24.4

100

30.4

Tape dimensions

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

W

P0 (± 0.1)

D1 (min)

F (± 0.1)

K (max)

P1 (± 0.1)

24

4

P 12

D (± 0.05) 1.55

1.5

11.5

2.85

2

All dimensions are in mm.

End

Top cover tape

Start

No components Components No components

500mm min 500mm min

Empty components pockets saled with cover tape.

User direction of feed

Doc ID 10871 Rev 8 25/27

Revision history VNQ830PEP-E

Table 18.

Document revision history

Date

10-Nov-2004

22-Nov-2006

07-Dec-2004

04-May-2005

03-May-2006

26-Nov-2008

01-Jul-2009

20-Sep-2013

Revision

1

2

3

4

5

6

7

8

Changes

Initial release.

Pdf changed.

Mechanical data updating.

PowerSSO-24 thermal characterization insertion

PCB copper area correction.

Changed document status from preliminary to definitive.

Configuration diagram modification

Shipment data insertion

Document reformatted and restructured.

Added list of contents, tables and figures.

Added ECOPACK® packages information.

Update

PowerSSO-24 mechanical data .

Table 17: PowerSSO-24 mechanical data

:

– Deleted A (min) value

– Changed A (max) value from 2.50 to 2.45

– Changed A2 (max) value from 2.40 to 2.35

– Updated k values

– Changed L (min) value from 0.6 to 0.55

– Changed L (max) value from 1 to 0.85

Updated Disclaimer.

26/27 Doc ID 10871 Rev 8

VNQ830PEP-E

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

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DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE

DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.

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Information in this document supersedes and replaces all information previously supplied.

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Doc ID 10871 Rev 8 27/27