STMicroelectronics VNQ5050K-E Datasheet
STMicroelectronics VNQ5050K-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology, intended for driving resistive or inductive loads with one side connected to ground. It features inrush current active management by power limitation, very low standby current, 3.0 V CMOS compatible input, optimized electromagnetic emission, very low electromagnetic susceptibility, and compliance with the 2002/95/EC European directive. It offers general features like 41 V max supply voltage, 4.
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VNQ5050K-E
Quad channel high side driver for automotive applications
Features
Max supply voltage
Operating voltage range
V
CC
V
CC
Max on-state resistance (per ch.) R
ON
Current limitation (typ) I
LIMH
Off-state supply current I
S
41 V
4.5 to 36 V
50 m Ω
19 A
2 µA
(1)
1.
Typical value with all loads connected
■ General features
– Inrush current active management by power limitation
– Very low standby current
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
European directive
■
■
Diagnostic functions
– Open drain status output
– On-state open load detection
– Off-state open load detection
– Thermal shutdown indication
Protection
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss of V
CC
– Thermal shutdown
– Reverse battery protection (see
Application schematic on page 19 )
– Electrostatic discharge protection
PowerSSO-24
Applications
■ All types of resistive, inductive and capacitive loads
Description
The VNQ5050K-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V
CC
pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table).
The device detects open load condition both in on and off-state, when STAT_DIS is left open or driven low. Output shorted to Vcc is detected in the off-state.
When STAT_DIS is driven high, the STATUS pin is in a high impedance condition.
Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to a safe level up to thermal shutdown intervention.
Thermal shutdown with automatic restart allows the device to recover normal operation as soon as the fault condition disappears.
Table 1.
Package
Device summary
Order code
Tube Tape and reel
PowerSSO-24 VNQ5050K-E VNQ5050KTR-E
September 2013 Doc ID 10864 Rev 7 1/31 www.st.com
1
Contents
Contents
VNQ5050K-E
Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 19
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 19
Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 20
Microprocessor I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
®
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/31 Doc ID 10864 Rev 7
VNQ5050K-E
List of tables
List of tables
CC
=13V; Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Doc ID 10864 Rev 7 3/31
4/31
List of figures
List of figures
VNQ5050K-E
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
vs T case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . 24
PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 25
Doc ID 10864 Rev 7
VNQ5050K-E
1
Block diagram and pin configuration
Block diagram and pin configuration
Figure 1.
Block diagram
V
CC
OUTPUT1
GND
INPUT1
STATUS1
STAT_DIS
INPUT2
STATUS2
INPUT3
STATUS3
INPUT4
STATUS4
V
CC
CLAMP
UNDERVOLTAGE
OVERTEMP. 1
LOGIC
CLAMP 1
DRIVER 1
CURRENT LIMITER 1
OPENLOAD ON 1
OPENLOAD OFF 1
PWR
LIM
1
INPUT2
STATUS2
CONTROL & PROTECTION
EQUIVALENT TO
CHANNEL1
V
CC
OUTPUT2
INPUT3
STATUS3
CONTROL & PROTECTION
EQUIVALENT TO
CHANNEL1
V
CC
OUTPUT3
INPUT4
STATUS4
CONTROL & PROTECTION
EQUIVALENT TO
CHANNEL1
V
CC
OUTPUT4
Table 2.
Name
Pin functions
V
CC
OUTPUTn
GND
INPUTn
STATUSn
STAT_DIS
Function
Battery connection
Power output
Ground connection. Must be reverse battery protected by an external diode/resistor network
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state
Open drain digital diagnostic pin
Active high CMOS compatible pin, to disable the STATUS pin
Doc ID 10864 Rev 7 5/31
Block diagram and pin configuration
Figure 2.
Configuration diagram (top view)
V
CC
GND
INPUT1
STATUS1
INPUT2
STATUS2
INPUT3
STATUS3
INPUT4
STATUS4
STAT_DIS
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT3
OUTPUT3
OUTPUT3
OUTPUT4
OUTPUT4
OUTPUT4
VNQ5050K-E
TAB = V
CC
Table 3.
Suggested connections for unused and not connected pins
Connection/pin Status N.C.
Output Input STAT_DIS
Floating
To ground
X
N.R.
(1)
X
X
X
N.R.
X
Through 10 K Ω resistor
X
Through 10 K Ω resistor
1.
Not recommended
6/31 Doc ID 10864 Rev 7
VNQ5050K-E Electrical specifications
Note:
Figure 3.
Current and voltage conventions
V
CC
I
SD
STAT_DIS OUTPUTn
V
SD
I
INn
INPUTn STATUSn
V
INn
GND
I
GND
V
Fn
= V
OUTn
- V
CC
during reverse battery condition
I
OUTn
I
STATn
V
STATn
V
OUTn
I
S
V
CC
Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in this section for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 4.
Symbol
Absolute maximum ratings
Parameter
V
CC
- V
CC
- I
GND
I
OUT
- I
OUT
I
IN
DC supply voltage
Reverse DC supply voltage
DC reverse ground pin current
DC output current
Reverse DC output current
DC input current
I
STAT
I
STAT_DIS
DC status current
DC status disable current
E
MAX
Maximum switching energy (single pulse)
(L=3 mH; R
L
=0 Ω ; V bat
=13.5V; T jstart
=150ºC;
I
OUT
= I limL
(typ.))
Value
41
0.3
200
Internally limited
15
+10/-1
+10/-1
+10 / -1
104 mJ
Unit
V
V mA
A
A mA mA mA
Doc ID 10864 Rev 7 7/31
Electrical specifications
Table 4.
Symbol
V
ESD
V
ESD
T j
T stg
Absolute maximum ratings (continued)
Parameter
Electrostatic discharge
(human body model: R=1.5K
Ω; C=100pF)
– Input
– Status
– STAT_DIS
– Output
– V
CC
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
VNQ5050K-E
Value Unit
4000
4000
4000
5000
5000
750
-40 to 150
- 55 to 150
V
V
V
V
V
V
°C
°C
Table 5.
Symbol
R thj-case
R thj-amb
Thermal data
Parameter
Thermal resistance junction-case (With one channel ON)
Thermal resistance junction-ambient
Max value
2.8
Unit
°C/W
°C/W
8/31 Doc ID 10864 Rev 7
VNQ5050K-E Electrical specifications
Values specified in this section are for 8 V<V
CC
<36 V, -40 °C< T j
<150 °C, unless otherwise stated.
Table 6.
Symbol
Power section
Parameter Test conditions
V
CC
V
USD
Operating supply voltage
Undervoltage shutdown
V
USDhyst
Undervoltage shutdown hysteresis
V
I
I
R clamp
I
L(off1)
L(off2)
V
ON
S
F
On-state resistance
(1)
I
OUT
=2A; T j
=25°C
I
OUT
=2A; T j
=150°C
I
OUT
=2A; V
CC
=5V; T j
=25°C
Clamp Voltage
Supply current
I
S
=20 mA
Off-state; V
CC
=13V;
V
IN
=V
OUT
=0V; T j
=25°C
On-state; V
IN
=5V; V
CC
=13V;
I
OUT
=0A
Off-state output current
(1)
V
IN
=V
OUT
=0V; V
CC
=13V; T j
=25°C
V
IN
=V
OUT
=0V; V
CC
=13V;
T j
=125°C
Off-state output current
(1)
V
IN
=0V; V
OUT
= 4V
Output - V
CC voltage
(1)
diode
-I
OUT
=2A; T j
=150°C
1.
For each channel.
2.
PowerMOS leakage included
Min.
Typ.
Max.
Unit
4.5
41
0
0
-75
13
3.5
0.5
46
2
(2)
8
0.01
36
4.5
50
100
65
52
5
(2)
14
3
5
0
0.7
μ A
μ A
μ A m Ω m
Ω m Ω
V
μ
V
V
V
A mA
V
Table 7.
Symbol t d(on) t d(off) dV
OUT
/dt
(off)
Turn-off voltage slope
W
ON
W
OFF
Switching (V
CC
=13V; T j
=25°C)
Parameter Test conditions
Turn-on delay time
Turn-off delay time dV
OUT
/dt
(on)
Turn-on voltage slope
Switching energy losses during t won
Switching energy losses during t woff
R
L
=6.5
Ω
R
L
=6.5
Ω
R
L
=6.5
Ω
(See
R
L
=6.5
Ω
(See
R
L
=6.5
Ω
R
L
=6.5
Ω
Min.
Typ.
Max.
Unit
15 μ s
-
-
40
-
-
μ s
V/ μ s
V/ μ s
0.19
mJ
0.27
mJ
Doc ID 10864 Rev 7 9/31
Electrical specifications
Note:
VNQ5050K-E
Table 8.
Symbol
V
STAT
I
LSTAT
C
STAT
V
SCL
Status pin (V
SD
=0)
Parameter Test conditions
Status low output voltage
I
STAT
= 1.6 mA, V
SD
=0V
Status leakage current
Normal operation or V
SD
=5V,
V
STAT
= 5V
Status pin input capacitance
Normal operation or V
SD
=5V,
V
STAT
= 5V
Status clamp voltage
I
STAT
= 1mA
I
STAT
= - 1mA
Table 9.
Symbol
Protections
Parameter Test conditions
T
I
T t
I limH limL
TSD
T
T
R
RS
HYST
SDL
DC short circuit current
Short circuit current during thermal cycling
V
CC
=13V
5V<V
CC
<36V
V
CC
=13V
T
R
<T j
<T
TSD
Shutdown temperature
Reset temperature
Thermal reset of
STATUS
Thermal hysteresis
(T
TSD
-T
R
)
Status delay in overload conditions
T j
>T
TSD
V
DEMAG
Turn-off output voltage clamp
I
OUT
=2A; V
IN
=0; L=6mH
V
ON
Output voltage drop limitation
I
OUT
=0.1A (see
)
T j
= -40°C...+150°C
Min.
Typ.
Max.
Unit
0.5
V
5.5
-0.7
10
100
7
μ A pF
V
V
Min.
Typ.
Max.
Unit
13.5
19 26.5
26.5
A
A
7 A
150 175
T
RS
+ 1 T
RS
+ 5
135
200 °C
°C
°C
7
20
°C
μ s
V
CC
-41 V
CC
-46 V
CC
-52 V
25 mV
To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles
Table 10.
Open-load detection
Symbol Parameter
I
OL
Open-load on-state detection threshold t
DOL(on)
Open-load on-state detection delay
Test conditions
V
IN
= 5V, 8V<Vcc<18V
(See
)
I
OUT
= 0A, V
CC
=13V
(See
Min.
Typ.
Max.
Unit
10 70
200 mA
μ s
10/31 Doc ID 10864 Rev 7
VNQ5050K-E
Table 10.
Open-load detection (continued)
Symbol Parameter Test conditions t
POL
Delay between input falling edge and status rising edge in openload condition
I
OUT
= 0A (See
V
OL
Open-load off-state voltage detection threshold t
DSTKON
Output short circuit to
V cc
detection delay at turn-off
V
IN
= 0V, 8V<V
CC
<16V
(See
)
(See
Table 11.
Logic input
Symbol Parameter Test conditions
V
I
V
I
I
V
IL
IL
IH
IH
I(hyst)
V
V
V
ICL
SDL
SDL
SDH
Input low level
Low level input current V
IN
= 0.9V
Input high level
High level input current V
IN
= 2.1V
Input hysteresis voltage
Input clamp voltage
I
IN
= 1mA
I
IN
= -1mA
STAT_DIS low level voltage
Low level STAT_DIS current
STAT_DIS high level voltage
V
SD
=0.9V
I
SDH
High level STAT_DIS current
V
SD(hyst)
STAT_DIS hysteresis voltage
V
SD
=2.1V
V
SDCL
STAT_DIS clamp voltage
I
SD
=1mA
I
SD
=-1mA
Electrical specifications
Min.
Typ.
Max.
Unit
200 500 1000 μ s
2
180
4 V t
POL
μ s
Min.
Typ.
Max.
Unit
0.9
1
2.1
10
V
μ A
V
μ A
0.25
V
5.5
7
-0.7
0.9
V
V
V
1
2.1
μ A
V
0.25
5.5
-0.7
10
7
μ A
V
V
V
Doc ID 10864 Rev 7 11/31
Electrical specifications VNQ5050K-E
Figure 4.
Status timings
OPEN LOAD STATUS TIMING (without external pull-up)
V
IN
I
OUT
< I
OL
V
OUT
< V
OL
OPEN LOAD STATUS TIMING (with external pull-up)
V
IN
I
OUT
< I
OL
V
OUT
> V
OL
V
STAT t
DOL(on) t
POL
V
STAT t
DOL(on)
V
IN
OUTPUT STUCK TO Vcc
I
OUT
> I
OL
V
OUT
> V
OL
V
STAT t
DOL(on) t
DSTKON
V
IN
OVER TEMP STATUS TIMING
T j
> T
TSD
V
STAT t
SDL t
SDL
Figure 5.
Output voltage drop limitation
V cc
-V out
T j
=150 o
C
T j
=25 o
C
T j
=-40 o
C
12/31
V on
V on
/R on(T)
Table 12.
Truth table
Conditions
Normal operation
Current limitation
Input
L
H
L
H
Output
L
X
L
H
I out
Status (V
SD
=0V)
(1)
H
H
H
H
Doc ID 10864 Rev 7
VNQ5050K-E Electrical specifications
Table 12.
Truth table (continued)
Conditions Input Output
Over temperature
Undervoltage
Output voltage > V
Output current < I
OL
OL
L
H
L
H
L
H
L
H
L
L
L
L
H
H
L
H
1.
If the V
SD
is high, the STATUS pin is in a high impedance.
2.
The STATUS pin is low with a delay equal to t
DSTKON
after INPUT falling edge.
3.
The STATUS pin becomes high with a delay equal to t
POL
after INPUT falling edge.
Status (V
SD
=0V)
(1)
H
L
X
X
L
(2)
H
H
(3)
L
Figure 6.
Switching characteristics
V
OUT t
Won t
Woff
90%
80% dV
OUT
/dt
(on) dV
OUT
/dt
(off) t r
10% t f t
INPUT t d(on) t d(off) t
Table 13.
Electrical transient requirements (part 1/3)
Test levels
(1)
ISO 7637-2:
2004(E) test Pulse
III IV
Number of pulses or test times
Burst cycle/pulse repetition time
1
2a
3a
3b
-75 V
+37 V
-100 V
+75 V
-100 V
+50 V
-150 V
+100 V
5000 pulses
5000 pulses
1h
1h
0.5 s
0.2 s
90 ms
90 ms
5 s
5 s
100 ms
100 ms
Delays and impedance
2 ms, 10
Ω
50 μ s, 2 Ω
0.1 μ s, 50 Ω
0.1 μ s, 50 Ω
Doc ID 10864 Rev 7 13/31
14/31
Electrical specifications VNQ5050K-E
Table 13.
Electrical transient requirements (part 1/3) (continued)
ISO 7637-2:
2004(E) test Pulse
III
Test levels
(1)
IV
Number of pulses or test times
Burst cycle/pulse repetition time
4
5b
(2)
-6 V
+65 V
-7 V
+87 V
1 pulse
1 pulse
Delays and impedance
100 ms, 0.01
Ω
400 ms, 2 Ω
Table 14.
Electrical transient requirements (part 2/3)
ISO 7637-2:
2004(E) test pulse
III
Test level results
(1)
IV
1
2a
3a
3b
4
5b
(2)
C
C
C
C
C
C
1.
The above test levels must be considered referred to V
CC
= 13.5V except for pulse 5b
2.
Valid in case of external load dump clamp: 40V maximum referred to ground.
C
C
C
C
C
C
Table 15.
Electrical transient requirements (part 3/3)
Class Contents
C
E
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 10864 Rev 7
VNQ5050K-E Electrical specifications
Figure 7.
Off-state output current
Iloff1 (uA)
0.5
0.4
0.3
0.2
0.1
Off state
Vcc=13V
Vin=Vout=0V
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 9.
Input clamp voltage
Vicl (V)
8
7.75
7.5
7.25
7
Iin=1mA
6.75
6.5
6.25
6
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 11. Input high level
Vih (V)
4
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 8.
High level input current
Iih (uA)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25
Vin=2.1V
0 25 50 75
Tc (°C)
100 125 150 175
Figure 10. Input low level
Vil (V)
4
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 12. Input hysteresis voltage
Vihyst (V)
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Doc ID 10864 Rev 7 15/31
Electrical specifications VNQ5050K-E
Figure 13. On-state resistance vs T case
Ron (mOhm)
100
90
80
70
60
50
40
30
20
10
0
-50 -25
Iout=2A
Vcc=13V
0 25 50 75
Tc (°C)
100 125 150 175
Figure 15. Undervoltage shutdown
Vusd (V)
14
12
10
8
6
4
2
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 17. I
LIMH
vs T case
Ilimh (A)
25
22.5
20
17.5
Vcc=13V
15
12.5
10
7.5
5
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 14. On-state resistance vs V
CC
Ron (mOhm)
100
90
80
70
60
50
40
30
20
10
0
0 5 10 15 20
Vcc (V)
25
Tc=150°C
Tc=125°C
Tc=25°C
Tc=-40°C
30 35 40
Figure 16. Turn-on voltage slope
700
600
500
400
300 dVout/dt(on)(V/ms)
1000
900
800
Vcc=13V
RI=6.5Ohm
200
100
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 18. Turn-off voltage slope dVout/dt(off)(V/ms)
1000
900
800
700
600
500
400
300
200
100
0
-50 -25
Vcc=13V
RI=6.5Ohm
0 25 50 75
Tc (°C)
100 125 150 175
16/31 Doc ID 10864 Rev 7
VNQ5050K-E Electrical specifications
Figure 19.
Status low output voltage
Vstat (V)
0.9
0.8
0.7
0.6
0.5
Istat=1.6mA
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 21.
Status clamp voltage
Vscl (V)
9
6
5.5
5
4.5
4
-50
8.5
8
7.5
7
6.5
-25
Istat=1mA
0 25 50 75
Tc (°C)
100 125 150 175
Figure 23.
Open-load off-state voltage detection threshold
Vol (V)
5
4.5
4
3.5
Vin=0V
3
2.5
2
1.5
1
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 20.
Vsdcl (V)
14
12
10
8
6
4
2
Status leakage current
Ilstat (uA)
0.18
0.17
0.16
0.15
0.14
0.13
0.12
0.11
0.1
0.09
0.08
-50 -25
Vstat=5V
0 25
Isd=1mA
0
-50 -25 0
50 75
Tc (°C)
100 125 150 175
Figure 22.
Open-load on-state detection threshold
Iol (mA)
100
90
80
70
60
50
40
30
20
10
0
-50 -25
Vin=5V
0 25 50 75
Tc (°C)
100 125 150 175
Figure 24.
STAT_DIS clamp voltage
25 50 75
Tc (°C)
100 125 150 175
Doc ID 10864 Rev 7 17/31
Electrical specifications VNQ5050K-E
Figure 25.
High level STAT_DIS voltage Figure 26.
Low level STAT_DIS voltage
Vsdh (V)
8
Vsdl (V)
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
18/31 Doc ID 10864 Rev 7
VNQ5050K-E Application information
Figure 27.
Application schematic
+5V +5V
R prot STAT_DIS
μ C
R prot
R prot
INPUTn
STATUSn
V
CC
GND
V
GND
R
GND
D
GND
OUTPUTn
D ld
Note:
3.1
3.1.1
Channels 2, 3 and 4 have the same internal circuit as channel 1.
GND protection network against reverse battery
Solution 1: resistor in the ground line (R
GND
only)
This can be used with any type of load.
The following is an indication on how to dimension the R
GND resistor.
1.
R
GND
≤ 600mV / (I
S(on)max
).
2. R
GND
≥ (−
V
CC
) / (-I
GND
) where -I
GND
is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.
Power Dissipation in R
GND
(when V
CC
<0: during reverse battery situations) is:
P
D
= (-V
CC
)
2
/R
GND
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I
S(on)max
becomes the sum of the maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND will produce a shift (I
S(on)max
* R
GND
) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R
GND
.
Doc ID 10864 Rev 7 19/31
Application information
3.1.2
VNQ5050K-E
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
Solution 2: a diode (D
GND
) in the ground line
A resistor (R
GND
=1k
Ω) should be inserted in parallel to D
GND
if the device drives an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (
≈
600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.2 Load dump protection
D ld
is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V
CC
max DC rating. The same applies if the device is subject to transients on the V
CC
line that are greater than the ones shown in the ISO T/R 7637/1 table.
3.3
3.4
Microprocessor I/Os protection
If a ground protection network is used and negative transients are present on the V
CC
line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot prevent the
μ
C I/Os pins to latch-up.
) in line to
The value of these resistors is a compromise between the leakage current of
μ
C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
μ
C
I/Os.
-V
CCpeak
/I latchup
≤
R prot
≤
(V
OH
μ
C
-V
IH
-V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= - 100V and I latchup
≥
20mA; V
OH
μ
C
≥
4.5V
5k
Ω ≤
R prot
≤
65k
Ω
.
Recommended value: R prot
=10k
Ω.
Open-load detection in off-state
Off-state open-load detection requires an external pull-up resistor (R
PU
OUTPUT pin and a positive supply voltage (V
PU
) connected between
) like the +5V line used to supply the microprocessor.
The external resistor has to be selected according to the following requirements:
1.
no false open-load indication when load is connected: in this case we have to avoid
V
OUT
to be higher than V
Olmin
; this results in the following condition
V
OUT
=(V
PU
/(R
L
+R
PU
))R
L
<V
Olmin.
2. no misdetection when load is disconnected: in this case the V
OUT
has to be higher than
V
OLmax
; this results in the following condition R
PU
<(V
PU–
V
OLmax
)/I
L(off2)
.
20/31 Doc ID 10864 Rev 7
VNQ5050K-E Application information
Because I s(OFF)
may significantly increase if V out
is pulled high (up to several mA), the pullup resistor R
PU
should be connected to a supply that is switched OFF when the module is in standby.
The values of V
OLmin
, V section.
OLmax
and I
L(off2)
are available in the Electrical Characteristics
Figure 28.
Open-load detection in off-state
V batt.
V
PU
V
CC
R
PU
INPUT
DRIVER
+
LOGIC
I L(off2)
OUT
STATUS
+
-
V
OL
R
R
L
GROUND
Doc ID 10864 Rev 7 21/31
Application information
Figure 29.
Waveforms
VNQ5050K-E
NORMAL OPERATION
INPUT
STAT_DIS
LOAD CURRENT
STATUS
UNDERVOLTAGE
V
USDhyst
V
CC
INPUT
STAT_DIS
LOAD CURRENT
STATUS
V
USD undefined
OPEN LOAD with external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
STATUS
V
OUT
>V
OL
V
OL
OPEN LOAD without external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
LOAD CURRENT
STATUS
I
OUT
<I
OL t
POL
RESISTIVE SHORT TO Vcc, NORMAL LOAD
INPUT
STAT_DIS
LOAD VOLTAGE
STATUS
I
OUT
>I
OL V
OUT
>V
OL t
DSTKON
OVERLOAD OPERATION
T j
T
R
T
TSD
T
RS
INPUT
STAT_DIS
LOAD CURRENT
STATUS current limitation power limitation thermal cycling
SHORTED LOAD
V
OL
I
LIMH
I
LIML
NORMAL LOAD
22/31 Doc ID 10864 Rev 7
VNQ5050K-E
3.5
Application information
Maximum demagnetization energy (V
CC
= 13.5V)
Figure 30.
Maximum turn-off current versus inductance (for each channel)
100
10
1
0.1
1 10
L (mH)
A: T jstart
= 150°C single pulse
B: T jstart
= 100°C repetitive pulse
C: T jstart
= 125°C repetitive pulse
V
IN
, I
L
Demagnetization Demagnetization
100
Demagnetization t
Note: Values are generated with R
L
= 0 Ω
In case of repetitive pulses, T jstart
(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
Doc ID 10864 Rev 7 23/31
Package and PC board thermal data
4 Package and PC board thermal data
4.1 PowerSSO-24 thermal data
Figure 31.
PowerSSO-24 PC board
VNQ5050K-E
Note: Layout condition of R th
and Z th
measurements (PCB: Double layer, Thermal Vias, FR4 area= 77 mm x 86 mm,PCB thickness=1.6mm, Cu thickness=70 µm (front and back side),
Copper areas: from minimum pad lay-out to 8 cm
2
).
Figure 32.
R thj-amb
vs PCB copper area in open box free air condition (one channel on)
RTHj_amb(°C/W)
55
50
45
40
35
30
0 2 4 6
PCB Cu heatsink area (cm^2)
8 10
24/31 Doc ID 10864 Rev 7
VNQ5050K-E Package and PC board thermal data
Figure 33.
PowerSSO-24 thermal impedance junction ambient single pulse (one channel on)
ZTH (°C/W)
1000
100 Footprint
2 cm
2
8 cm
2
10
1
0.1
0.0001
0.001
0.01
0.1
Time (s)
1 10 100 1000
Figure 34.
Thermal fitting model of a double channel HSD in PowerSSO-24
(a) a.
The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered
Doc ID 10864 Rev 7 25/31
Package and PC board thermal data
Equation 1 : pulse calculation formula
Z
TH δ where
= R
T H
⋅ δ
+ Z
THtp
(
1 –
δ )
δ = t p
⁄ T
Table 16.
Thermal parameters
Area/island (cm
2
)
R1=R7=R9=R11 (°C/W)
R2=R8=R10=R12 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1=C7=C9=C11 (W.s/°C)
C2=C8=C10=C12 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
VNQ5050K-E
Footprint
0.4
2
6
7.7
9
28
0.001
0.0022
0.025
0.75
1
2.2
2
9
17
4
5
8
8
10
9
17
26/31 Doc ID 10864 Rev 7
VNQ5050K-E
5
Package and packing information
Package and packing information
5.1 ECOPACK
®
packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
5.2 PowerSSO-24™ mechanical data
Figure 35.
PowerSSO-24™ package dimensions
Doc ID 10864 Rev 7 27/31
Package and packing information
Table 17.
PowerSSO-24™ mechanical data
Symbol
Min h k
G
H e e3
F
A
A2
D
E a1 b c
L
O
Q
S
T
U
N
X
Y
2.15
0
0.33
0.23
10.10
7.4
10.1
0 deg
0.55
4.1
6.5
Millimeters
Typ
0.8
8.8
2.3
1.2
0.8
2.9
3.65
1.0
10 deg
4.7
7.1
0.1
10.5
0.4
8 deg
0.85
VNQ5050K-E
Max
2.45
2.35
0.1
0.51
0.32
10.50
7.6
28/31 Doc ID 10864 Rev 7
VNQ5050K-E Package and packing information
Figure 36.
PowerSSO-24 tube shipment (no suffix)
C
B
Base Q.ty
Bulk Q.ty
49
1225
Tube length (± 0.5) 532
A 3.5
B
C (± 0.1)
13.8
0.6
All dimensions are in mm.
A
Figure 37.
PowerSSO-24 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05) 1.55
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
24
4
12
1.5
11.5
2.85
2
All dimensions are in mm.
End
Top cover tape
Start
No components Components No components
500mm min 500mm min
Empty components pockets saled with cover tape.
User direction of feed
Doc ID 10864 Rev 7 29/31
30/31
Revision history VNQ5050K-E
Table 18.
Document revision history
Date Revision
01-Oct-2004
01-Mar-2005
04-Jun-2007
24-Jul-2007
17-Jun-2009
22-Jun-2009
25-Sep-2013
1
2
3
4
5
6
7
Changes
Initial release.
Minor changes.
Reformatted and restructured.
Contents and lists of tables and figures added.
Section 3.5: Maximum demagnetization energy (VCC = 13.5V)
added.
New disclaimer added.
Table 4: Absolute maximum ratings : E
MAX entries updated.
Table 13: Electrical transient requirements (part 1/3)
:Test level values III and IV for test pulse 5b and notes updated
Figure 34: Thermal fitting model of a double channel HSD in
Table 17: PowerSSO-24™ mechanical data updated
Table 17: PowerSSO-24™ mechanical data :
– Deleted A (min) value
– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added F row
– Updated k row
Updated Figure 35: PowerSSO-24™ package dimensions
Updated Table 17: PowerSSO-24™ mechanical data :
– Deleted G1 row
– Added O, Q, S, T, and U rows
Updated disclaimer.
Doc ID 10864 Rev 7
VNQ5050K-E
Please Read Carefully:
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Doc ID 10864 Rev 7 31/31
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