STMicroelectronics VND5160J-E Datasheet
Reklama
Reklama
VND5160J-E
Double channel high side driver for automotive applications
Features
Max supply voltage
Operating voltage range
Max on-state resistance
Current limitation (typ)
Off state supply current (typ)
V
CC
V
CC
R
ON
I
LIMH
I
S
1.
Typical value with all loads connected.
41V
4.5 to 36V
160 m
5A
2 µA
(1)
■
■
General
– Inrush current active management by power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
European directive
Diagnostic functions
– Open drain status output
– On state open load detection
– Off state open load detection
– Thermal shutdown indication
■ Protection
– Undervoltage shut-down
– Overvoltage clamp
– Output stuck to Vcc detection
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss of V
CC
– Thermal shut down
– Reverse battery protection (see Figure 28 )
Table 1.
Device summary
Package
PowerSSO-12
– Electrostatic discharge protection
Application
■ All types of resistive, inductive and capacitive loads
Description
The VND5160J-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V
CC
pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table).
The device detects open load condition in both
ON and OFF states, when STAT_DIS is left open or driven low. Output shorted to V
CC
is detected in the OFF state.
When STAT_DIS is driven high, the STATUS pin is in a high impedance condition.
Output current limitation protects the device in overload condition. In case of long duration overload, the device limits the dissipated power to safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears.
Part number (Tube)
Order codes
Part number (Tape & Reel)
PowerSSO-12 VND5160J-E VND5160JTR-E
September 2013 Rev 6 1/31 www.st.com
31
Contents
Contents
VND5160J-E
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 20
Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 21
Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
®
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/31
VND5160J-E
List of tables
List of tables
=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3/31
List of figures
List of figures
VND5160J-E
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
LIM
vs T case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 24
PowerSSO-12™ Thermal impedance junction ambient single pulse (one channel ON) . . 25
Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25
4/31
VND5160J-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
V
CC
OUTPUT1
GND
INPUT1
STATUS1
STAT_DIS
INPUT2
STATUS2
V
CC
CLAMP
UNDERVOLTAGE
CLAMP 1
LOGIC
DRIVER 1
PWR
LIM
1
I
LIM
1
V
DSLIM
1
OPENLOAD ON 1
OVERTEMP. 1
OVERTEMP. 2
OPENLOAD OFF 1
PWR
LIM
2
CLAMP 2
DRIVER 2
I
LIM
2
V
DSLIM
2
OPENLOAD ON 2
OPENLOAD OFF 2
OUTPUT2
Table 2.
Name
Pin functions
V
CC
OUTPUTn
GND
INPUTn
STATUSn
STAT_DIS
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external diode/ resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.
Open Drain digital diagnostic pin.
Active high CMOS compatible pin, to disable the STATUS pin.
5/31
Block diagram and pin description
Figure 2.
Configuration diagram (top view)
GND
STAT_DIS
INPUT 1
STATUS 1
STATUS 2
INPUT 2
1
2
3
4
5
6
12
11
10
9
8
7
TAB = V cc
V cc
OUTPUT 1
OUTPUT 1
OUTPUT 2
OUTPUT 2
V cc
VND5160J-E
Table 3.
Suggested connections for unused and N.C. pins
Connection / Pin STATUS N.C.
OUTPUT INPUT
Floating
To ground
X
N.R.
(1)
X
X
X
N.R.
X
Through 10k
resistor
1.
Not recommended.
STAT_DIS
X
Through 10k
resistor
6/31
VND5160J-E Electrical specifications
Figure 3.
Current and voltage conventions
V
SD
V
INn
I
SD
I
INn
V
CC
STAT_DIS OUTPUTn
INPUTn
STATUSn
I
S
V
Fn
V
CC
I
OUTn
V
OUTn
I
STATn
V
STATn
GND
I
GND
Note:
2.1
V
Fn
= V
OUTn
- V
CCn
during reverse battery condition.
Absolute maximum ratings
Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in this section for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 4.
Symbol
Absolute maximum ratings
Parameter
V
CC
-V
CC
-I
GND
I
OUT
-I
OUT
I
IN
I
STAT
I
STAT_DIS
DC supply voltage
Reverse DC supply voltage
DC reverse ground pin current
DC output current
Reverse DC output current
DC input current
DC status current
DC status disable current
E
MAX
Maximum switching energy
(L=12mH; R
L
=0
; V bat
=13.5V; T jstart
=150°C;
I
OUT
= I limL
(Typ.) )
Value
41
0.3
200
Internally limited
6
+10 / -1
+10 / -1
+10 / -1
33 mJ
Unit
A mA mA mA
V
V mA
A
7/31
Electrical specifications
Table 4.
Symbol
V
ESD
V
ESD
T j
T stg
Absolute maximum ratings (continued)
Parameter
Electrostatic discharge (Human Body Model: R=1.5K
C=100pF)
– INPUT
– STATUS
– STAT_DIS
– OUTPUT
– V
CC
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
VND5160J-E
Value
4000
4000
4000
5000
5000
750
-40 to 150
-55 to 150
Unit
V
V
V
V
V
V
°C
°C
Table 5.
Symbol
Thermal data
Parameter Max value Unit
R thj-case
R thj-amb
Thermal resistance junction-case (max.) (with one channel ON)
Thermal resistance junction-ambient
8 °C/W
°C/W
8/31
VND5160J-E Electrical specifications
Values specified in this section are for 8V<V
CC stated.
<36V; -40°C<T j
<150°C, unless otherwise
.
Table 6.
Symbol
Power section
Parameter Test conditions Min. Typ. Max. Unit
V
CC
V
USD
Operating supply voltage
Undervoltage shutdown
V
USDhyst
Undervoltage Shut-down hysteresis
V
I
I
R clamp
I
L(off1)
L(off2)
V
ON
S
F
On state resistance
Clamp voltage
(2)
I
OUT
= 1A; T j
= 25°C
I
OUT
= 1A; T j
= 150°C
I
OUT
= 1A; V
CC
= 5V; T j
= 25°C
I
S
= 20mA
Supply current
Off State; V
CC
=13V; V
IN
=V
OUT
=0
T j
= 25°C;
On State; V
CC
=13V; V
IN
=5V;
I
OUT
= 0A
Off state output current
(2)
V
IN
=V
OUT
=0V; V
CC
=13V; T j
=25°C
V
IN
=V
OUT
=0V; V
CC
=13V; T j
=125°C
V
IN
=0V; V
OUT
=4V
Output - V
CC voltage
(2)
diode
-I
OUT
=0.6A; T j
=150°C
4.5
13 36 V
3.5
4.5
V
0
0
-75
0.5
41 46
2
(1)
3
160
320
210
52
5
(1)
6
0.01
3
5
0
V m
m
m
V
µA mA
µA
0.7
V
1.
PowerMOS leakage included.
2.
For each channel.
Table 7.
Switching (V
CC
= 13V; T j
= 25°C)
Parameter Symbol Test conditions dV
OUT
/dt
(on) dV t t d(on) d(off)
OUT
W
W
/dt
ON
OFF
(off)
Turn-On delay time
Turn-Off delay time
Turn-On voltage slope
Turn-Off voltage slope
Switching energy losses during t won
Switching energy losses during t woff
R
L
=13
(see
)
R
L
=13
(see
)
R
L
=13
R
L
=13
R
L
=13
(see
)
R
L
=13
(see
)
Min. Typ. Max. Unit
10
15 µs
See
V
µs
See
V
µs
0.07
0.04
µs mJ mJ
9/31
Electrical specifications VND5160J-E
Table 8.
Symbol
V
STAT
I
LSTAT
C
STAT
V
SCL
Status pin (V
SD
=0)
Parameter Test conditions
Status low output voltage
Status leakage current
Status pin input capacitance
Status clamp voltage
I
STAT
= 1.6 mA, V
SD
=0V
Normal operation or V
SD
=5V,
V
STAT
= 5V
Normal operation or V
SD
=5V,
V
STAT
= 5V
I
STAT
= 1mA
I
STAT
= - 1mA
Min. Typ. Max. Unit
0.5
V
10 µA
5.5
-0.7
100 pF
7 V
V
Table 9.
Symbol
Protection
(1)
Parameter Test conditions Min.
Typ.
Max.
Unit
T
I
T t
I limH limL
T
TSD
T
R
RS
HYST
SDL
DC short circuit current
V
CC
= 13V
5V<V
CC
<36V
Short circuit current during thermal cycling
Shutdown temperature
Reset temperature
Thermal reset of STATUS
V
CC
= 13V T
Thermal hysteresis (T
TSD
-T
R
)
Status delay in overload conditions
T j
>T
TSD
R
<T j
<T
TSD
3.5
150
5
2
175
T
RS
+ 1 T
RS
+ 5
135
7
7.5
7.5
200
20
A
A
A
µs
V
DEMAG
Turn-Off output voltage clamp
I
OUT
=1A; V
IN
=0; L=20mH V
CC
-41 V
CC
-46 V
CC
-52 V
V
ON
Output voltage drop limitation
I
OUT
= 0.03A;
T j
= -40°C...+150°C
25
1.
To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
mV
°C
°C
°C
°C
10/31
VND5160J-E Electrical specifications
Table 10.
Openload detection
Symbol Parameter Test conditions Min.
I
OL t
DOL(on)
Openload On state detection threshold
Openload On state detection delay t
POL
I
V
IN
= 5V, 8V<V
OUT
= 0A, V
CC
=13V
(see
)
CC
<18V 10
Delay between INPUT falling edge and STATUS rising edge in Openload condition
I
OUT
= 0A (see
) 200
V
OL
Openload Off state voltage detection threshold
V
IN
= 0V, 8V<V
CC
<16V 2 t
DSTKON
Output short circuit to V cc detection delay at turn Off
180
Typ.
See
500
See
Max.
Unit
40
200 t
POL mA
µs
1000 µs
4 V
µs
Table 11.
Logic input
Symbol Parameter
V
IL
I
IL
V
IH
I
IH
V
I(hyst)
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
V
ICL
Input clamp voltage
V
SDL
I
SDL
V
SDH
I
SDH
V
SD(hyst)
STAT_DIS low level voltage
Low level STAT_DIS current
STAT_DIS high level voltage
High level STAT_DIS current
STAT_DIS hysteresis voltage
V
SDCL
STAT_DIS clamp voltage
Test conditions
V
IN
= 0.9V
V
IN
= 2.1V
I
IN
= 1mA
I
IN
= -1mA
V
CSD
= 0.9V
V
CSD
= 2.1V
I
SD
= 1mA
I
SD
= -1mA
Min.
Typ.
Max.
Unit
0.9
1
2.1
0.25
5.5
1
2.1
0.25
5.5
-0.7
-0.7
10
7
0.9
10
7
V
V
V
V
µA
V
V
µA
V
µA
µA
V
V
V
11/31
Electrical specifications
Figure 4.
Status timings
VND5160J-E
V
OPEN LOAD STATUS TIMING (without external pull-up)
IN
I
OUT
< I
OL
V
OUT
< V
OL
V
IN
OPEN LOAD STATUS TIMING (with external pull-up)
I
OUT
< I
OL
V
OUT
> V
OL
V
STAT
V
STAT t
DOL(on) t
POL t
DOL(on)
V
IN
V
STAT t
DOL(on)
OUTPUT STUCK TO Vcc
I
OUT
> I
OL
V
OUT
> V
OL t
DSTKON
V
IN
OVER TEMP STATUS TIMING
T j
> T
TSD
V
STAT t
SDL t
SDL
Figure 5.
Output voltage drop limitation
V cc
-V out
T j
=150 o
C
T j
=25 o
C
T j
=-40 o
C
V on
V on
/R on(T)
I out
12/31
VND5160J-E Electrical specifications
Table 12.
Truth table
Conditions
Normal operation
Current limitation
Overtemperature
Undervoltage
Output Voltage > V
Output Current < I
OL
OL
INPUT
L
H
L
H
L
H
L
H
L
H
L
H n
OUTPUT
L
H
L
X
L
L
L
L
H
H
L
H n
1.
If the V
SD
is high, the STATUS pin is in a high impedance.
2.
The STATUS pin is low with a delay equal to t
DSTKON
after INPUT falling edge.
3.
The STATUS pin becomes high with a delay equal to t
POL
after INPUT falling edge.
STATUS n
(V
SD
=0V)
(1)
H
H
H
H
H
L
X
X
L
(2)
H
H
(3)
L
Figure 6.
Switching characteristics
V
OUT t
Won
80% dV
OUT
/dt
(on) t r
10%
INPUT t d(on) t d(off) t
Woff
90% t f dV
OUT
/dt
(off) t t
13/31
Electrical specifications VND5160J-E
Table 13.
Electrical transient requirements
Test levels
(1)
ISO 7637-2:
2004(E) test pulse
III IV
Number of pulses or test times
1
2a
3a
3b
4
5b
(2)
-75V
+37V
-100V
+75V
-6V
+65V
-100V
+50V
-150V
+100V
-7V
+87V
5000 pulses
5000 pulses
1h
1h
1 pulse
1 pulse
Burst cycle/pulse repetition time
0.5 s
0.2 s
90 ms
90 ms
5 s
5 s
100 ms
100 ms
Delays and impedance
2 ms, 10
50 µs, 2
0.1 µs, 50
0.1 µs, 50
100 ms, 0.01
400 ms, 2
ISO 7637-2:
2004(E) test pulse
E
III
Test level results
(1)
IV
1
2a
3a
3b
C
C
C
C
4
5b
(2)
C
C
1.
The above test levels must be considered referred to V
CC
= 13.5V except for pulse 5b.
2.
Valid in case of external load dump clamp: 40V maximum referred to ground.
Class Contents
C
C
C
C
C
C
C All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
14/31
VND5160J-E
Figure 7.
Waveforms
NORMAL OPERATION
INPUT
STAT_DIS
LOAD CURRENT
STATUS
UNDERVOLTAGE
V
USDhyst
V
CC
INPUT
STAT_DIS
LOAD CURRENT
STATUS
V
USD undefined
OPEN LOAD with external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
STATUS
V
OL
V
OUT
>V
OL
OPEN LOAD without external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
LOAD CURRENT
STATUS t
I
OUT
POL
<I
OL
RESISTIVE SHORT TO Vcc, NORMAL LOAD
INPUT
STAT_DIS
LOAD VOLTAGE
STATUS
T j
T
R
T
TSD
T
RS
INPUT
STAT_DIS
LOAD CURRENT
STATUS
I
OUT
>I
OL V
OUT
>V
OL t
DSTKON
OVERLOAD OPERATION
V
OL
Electrical specifications
I
I
LIMH
LIML current limitation power limitation thermal cycling
SHORTED LOAD NORMAL LOAD
15/31
Electrical specifications VND5160J-E
Figure 8.
Off state output current
Iloff1 (uA)
0.25
0.2
Off state
Vcc=13V
Vin=Vout=0V
0.15
0.1
0.05
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 10.
High level input current
3
2.5
2
1.5
1
0.5
Iih (uA)
5
4.5
4
3.5
Vin=2.1V
0
-50 -25 0 25 50 75
Tc (°C)
Figure 12.
Input low level
Vil (V)
4
100 125 150 175
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 9.
Input clamp voltage
Vicl (V)
8
7.75
Iin=1mA
7.5
7.25
7
6.75
6.5
6.25
6
-50 -25 0 25 50 75
Tc (°C)
Figure 11.
Input high level
Vih (V)
4
100 125 150 175
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75
Tc (°C)
100 125
Figure 13.
Input hysteresis voltage
150
Vihyst (V)
2
175
1.75
1.5
1.25
0.75
1
0.5
0.25
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
16/31
VND5160J-E
Figure 14.
Status low output voltage
Vstat (V)
0.9
0.8
0.7
0.6
Istat=1.6mA
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75
Tc (°C)
100 125
Figure 16.
Status clamp voltage
8
7.5
7
6.5
Vscl (V)
9
8.5
Istat=1mA
6
5.5
5
4.5
4
-50 -25 0 25 50 75
Tc (°C)
100 125
150 175
150 175
Figure 18.
On state resistance vs V
CC
Ron (mOhm)
300
275
250
225
200
175
150
125
100
75
50
0 5
Tc=150°C
Tc=125°C
Tc=25°C
Tc=-40°C
10 15 20
Vcc (V)
25 30 35 40
Electrical specifications
Figure 15.
Status leakage current
Ilstat (uA)
0.08
0.072
0.064
0.056
0.048
0.04
0.032
Vstat=5V
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 17.
On state resistance vs T case
Ron (mOhm)
300
180
150
120
90
270
240
210
60
30
0
-50 -25
Iout=1A
Vcc=13V
0 25 50 75
Tc (°C)
100 125 150 175
Figure 19.
Openload On state detection threshold
Iol (mA)
100
90
80
70
60
50
40
30
20
10
0
-50 -25
Vin=5V
0 25 50 75
Tc (°C)
100 125 150 175
17/31
Electrical specifications
Figure 20.
Openload Off state voltage detection threshold
4
3.5
3
2.5
Vol (V)
5
4.5
Vin=0V
2
1.5
1
0.5
0
-50 -25 0 25 50 75
Tc (°C)
100 125
Figure 22.
Turn - Off voltage slope
600
500
400
300 dVout/dt(off) (V/ms)
1000
900
800
700
Vcc=13V
Ri=13Ohm
150 175
200
100
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 24.
Undervoltage shutdown
Vusd (V)
14
8
6
4
2
12
10
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
18/31
VND5160J-E
Figure 21.
Turn - On voltage slope
9
8
7
4
3
6
5
2
1
0
-50 dVout/dt(on) (V/ms)
1000
900
800
Vcc=13V
Ri=6.5Ohm
700
600
500
400
300
200
100
0
-50 -25 0 25 50 75
Tc (°C)
Figure 23.
I
LIM
vs T case
Ilimh (A)
10
-25
Vcc=13V
0 25 50 75
Tc (°C)
100 125
100 125
150 175
150 175
Figure 25.
STAT_DIS clamp voltage
Vsdcl (V)
14
12
10
8
6
4
Isd=1mA
2
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
VND5160J-E
Figure 26.
High level STAT_DIS voltage
Vsdh (V)
8
7
6
5
4
3
2
1
0
-50 -25 0 25 50
Tc (°C)
75 100 125 150 175
Electrical specifications
Figure 27.
Low level STAT_DIS voltage
Vsdl (V)
8
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
19/31
Application information VND5160J-E
Figure 28.
Application schematic
+5V +5V
R prot
STAT_DIS
µC
R prot
R prot
INPUT
STATUS
V
CC
GND
V
GND
R
GND
D
GND
OUTPUT
D ld
Note:
3.1
3.1.1
Channels 2, has the same internal circuit as channel 1.
GND protection network against reverse battery
Solution 1 : resistor in the ground line (R
GND
only)
This can be used with any type of load.
The following is an indication on how to dimension the R
GND resistor.
1.
R
GND
600mV / (I
S(on)max
).
2. R
GND
V
CC
) / (-I
GND
) where -I
GND
is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.
Power Dissipation in R
GND
(when V
CC
<0: during reverse battery situations) is:
P
D
= (-V
CC
)
2
/R
GND
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I
S(on)max
becomes the sum of the maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND will produce a shift (I
S(on)max
* R
GND
) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R
GND
.
20/31
VND5160J-E
3.1.2
Application information
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
Solution 2: a diode (D
GND
) in the ground line
A resistor (R
GND
=1k
inductive load.
should be inserted in parallel to D
GND
if the device drives an
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (
600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.3
3.4
D ld
is necessary (Voltage transient suppressor) if the load dump peak voltage exceeds the
V
CC
max DC rating. The same applies if the device is subject to transients on the V
CC
line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
MCU I/Os protection
If a ground protection network is used and negative transient are present on the V
CC
line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot
) in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of
C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
C
I/Os.
-V
CCpeak
/I latchup
R prot
(V
OH
C
-V
IH
-V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= - 100V and I latchup
20mA; V
OH
C
4.5V
5k
R prot
180k
.
Recommended R prot values is 10k
Open load detection in Off state
Off state open load detection requires an external pull-up resistor (R
PU
) connected between
OUTPUT pin and a positive supply voltage (V
PU
) like the +5V line used to supply the microprocessor.
The external resistor has to be selected according to the following requirements:
1.
no false open load indication when load is connected: in this case we have to avoid
V
OUT
V
OUT
to be higher than V
Olmin
; this results in the following condition
=(V
PU
/(R
L
+R
PU
))R
L
<V
Olmin
.
2. no misdetection when load is disconnected: in this case the V out
has to be higher than
V
OLmax
; this results in the following condition R
PU
<(V
PU
–V
OLmax
)/I
L(off2)
.
21/31
Application information VND5160J-E
Because I s(OFF)
may significantly increase if V out
is pulled high (up to several mA), the pullup resistor R
PU
should be connected to a supply that is switched OFF when the module is in standby.
The values of V
OLmin section.
, V
OLmax
and I
L(off2)
are available in the Electrical characteristics
Figure 29.
Open load detection in Off state
V batt.
V
PU
V
CC
R
PU
INPUT
DRIVER
+
LOGIC
I
L(off2)
OUT
STATUS
+
-
V
OL
R
R
L
GROUND
22/31
VND5160J-E
3.5
Application information
Maximum demagnetization energy (V
CC
= 13.5V)
Figure 30.
Maximum turn Off current versus inductance (for each channel)
10
C
A
B
1
0,1
0,1 1
A: T jstart
= 150°C single pulse
B: T jstart
= 100°C repetitive pulse
C: T jstart
= 125°C repetitive pulse
V
IN
, I
L
Demagnetization
L (mH) 10
Demagnetization
100
Demagnetization
Note: t
Values are generated with R
L
= 0
In case of repetitive pulses, T jstart
(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
23/31
Package and PCB thermal data
4 Package and PCB thermal data
4.1 PowerSSO-12
™
thermal data
Figure 31.
PowerSSO-12 ™ PC board
VND5160J-E
Note: Layout condition of R th
and Z th
measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm
2
).
Figure 32.
R thj-amb
vs. PCB copper area in open box free air condition (one channel
ON)
RTHj_amb(°C/ W)
65
60
55
50
45
40
35
30
0 2 4 6
PCB Cu heatsink area (cm^ 2)
8 10
24/31
VND5160J-E Package and PCB thermal data
Figure 33. PowerSSO-12™ Thermal impedance junction ambient single pulse (one channel ON)
ZTH (°C/ W)
100
Footprint
2 cm
2
8 cm
2
10
1
0,1
0,0001 0,001 0,01 0,1
Time ( s)
1 10 100 1000
Pulse calculation formula
Z
TH
= R
TH where
= t
P
/T
+ Z
THtp
1 –
Figure 34. Thermal fitting model of a double channel HSD in PowerSSO-12™ (a) a.
The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
25/31
Package and PCB thermal data
Table 14.
Thermal parameters
Area/island (cm
2
)
R1=R7 (°C/W)
R2=R8 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1=C7 (W.s/°C)
C2=C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Footprint
1.2
6
7
10
22
26
0.0008
0.0016
0.05
0.2
0.27
3
2
VND5160J-E
8
10
15
20
9
10
15
0.1
0.8
6
0.1
1
9
26/31
VND5160J-E
5
Package and packing information
Package and packing information
5.1 ECOPACK
®
packages
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
PowerSSO-12™
package information
Figure 35.
PowerSSO-12™ package dimensions
27/31
Package and packing information
Table 15.
PowerSSO-12™ mechanical data
Symbol k
X
Y ddd e
H h
L
B
C
D
E
A
A1
A2
5.800
0.250
0.400
0°
1.900
3.600
Min.
1.250
0.000
1.100
0.230
0.190
4.800
3.800
Millimeters
Typ.
0.800
VND5160J-E
6.200
0.500
1.270
8°
2.500
4.200
0.100
Max.
1.620
0.100
1.650
0.410
0.250
5.000
4.000
28/31
VND5160J-E Package and packing information
Figure 36.
PowerSSO-12 ™ tube shipment (no suffix)
B
A
C
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
All dimensions are in mm.
100
2000
532
1.85
6.75
0.6
Figure 37.
PowerSSO-12 ™ tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
1.5
5.5
4.5
2
12
4
8
1.5
All dimensions are in mm.
End
Top cover tape
No components Components No components
Start
500mm min
Empty components pockets
500mm min saled with cover tape.
User direction of feed
29/31
Revision history VND5160J-E
Table 16.
Document revision history
Date
7-Jan-2004
3-Feb-2006
20-Mar-2007
01-Jun-2007
17-Dic-2007
24-Sep-2013
Revision
1
2
3
4
5
6
Changes
Initial release.
Major series of updates incorporated.
Reformatted.
Added list of tables and list of figures.
Added Section 3.5: Maximum demagnetization energy
Added new disclaimer.
Updated Table 4: Absolute maximum ratings
: E MAX entries.
Updated Table 13: Electrical transient requirements :Test level
values III and IV for test pulse 5b and notes.
Figure 34: Thermal fitting model of a double channel HSD in
added note.
Updated Section 4.1: PowerSSO-12™ thermal data :
– Changed
Figure 32: Rthj-amb vs. PCB copper area in open box free air condition (one channel ON)
.
– Changed
Figure 33: PowerSSO-12™ Thermal impedance junction ambient single pulse (one channel ON) .
– Updated Table 14: Thermal parameters :
R1 and R7 values changed from 1.2 to 0.1 °C/W.
R2 = R8 values changed from 6 to 0.2 °C/W.
R3 value changed from 7 to 4 °C/W.
R4 values changed from 10/10/9 to 8/8/7 °C/W.
C1=C7 values changed from 0.0008 to 0.0001 °C/W.
C2=C8 values changed from 0.0016 to 0.002 °C/W.
Updated disclaimer.
30/31
VND5160J-E
Please Read Carefully:
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