STMicroelectronics STIPN2M50T-HL Datasheet
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STIPN2M50T-HL
Datasheet
SLLIMM-nano IPM, 3-phase inverter, 2 A, 1.7 Ω max., 500 V MOSFET
26
17
1
NDIP-26L in line
16
Product status link
STIPN2M50T-HL
Product summary
Order code STIPN2M50T-HL
Marking
Package
Packing
IPN2M50T-HL
NDIP-26L
Tube
Features
• IPM 2 A, 500 V, R
DS(on)
= 1.7 Ω, 3-phase MOSFET inverter bridge including control ICs for gate driving
• Optimized for low electromagnetic interference
• 3.3 V, 5 V, 15 V CMOS/TTL input comparators with hysteresis and pull-down/ pull-up resistors
• Undervoltage lockout
• Internal bootstrap diode
• Interlocking function
• Shutdown function
• Comparator for fault protection against overtemperature and overcurrent
• Op-amp for advanced current sensing
• Optimized pinout for easy board layout
• NTC for temperature control (UL 1434 CA 2 and 4)
• Up to ±2 kV ESD protection (HBM C = 100 pF, R = 1.5 kΩ)
Applications
• 3-phase inverters for motor drives
• Dish washers
• Refrigerator compressors
• Air-conditioning fans
• Draining and recirculation pumps
Description
This SLLIMM (small low-loss intelligent molded module) nano provides a compact, high-performance AC motor drive in a simple, rugged design. It is composed of six
MOSFETs and three half-bridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed.
The package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. This
IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM is a trademark of STMicroelectronics.
DS11753 - Rev 5 - March 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
STIPN2M50T-HL
Internal schematic diagram and pin configuration
1
Internal schematic diagram and pin configuration
Figure 1. Internal schematic diagram
GND(1 )
T/SD/OD (2)
VccW(3 )
HinW(4 )
LinW(5 )
OP+(6 )
OPOUT(7 )
OP-(8 )
VccV(9 )
HinV(10)
LinV(11 )
Cin(12)
VccU(13 )
HinU(14)
T/SD/OD(15)
LinU(16 )
NTC
GND
HVG
OUT
VCC
HIN LVG
SD/OD
LIN Vboot
GND
OPOUT
OP-
OP+
HVG
OUT
VCC
HIN LVG
SD/OD
LIN Vboot
GND
CIN
HVG
OUT
VCC
HIN LVG
SD/OD
LIN Vboot
(26)N W
(25)W,OUT W
(24)Vboot W
(23)N V
(22)V,OUT V
(21)Vboot V
(20)N U
(19)U,OUT U
(18) P
(17)Vboot U
GIPD120120170806SA
DS11753 - Rev 5 page 2/23
DS11753 - Rev 5
STIPN2M50T-HL
Internal schematic diagram and pin configuration
Table 1. Pin description
3
4
5
Pin Symbol
1
2
GND Ground
Description
T/SD/OD NTC thermistor terminal / shutdown logic input (active low) / open-drain (comparator output)
6
V
CC
W
HIN W
LIN W
OP+
Low voltage power supply W phase
High-side logic input for W phase
Low-side logic input for W phase
Op-amp non inverting input
7
8
9
10
11
12
OP
OUT
OP-
V
CC
V
HIN V
LIN V
CIN
Op-amp output
Op-amp inverting input
Low voltage power supply V phase
High-side logic input for V phase
Low-side logic input for V phase
Comparator input
13 V
CC
U
14 HIN U
Low voltage power supply for U phase
High-side logic input for U phase
15 T/SD/OD NTC thermistor terminal / shutdown logic input (active low) / open-drain (comparator output)
16 LIN U
17 V
BOOT
18 P
U
19 U, OUT
U
Low-side logic input for U phase
Bootstrap voltage for U phase
Positive DC input
U phase output
20 N
U
21 V
BOOT
V
22 V, OUT
V
23 N
V
V phase output
Negative DC input for V phase
24 V
BOOT
W Bootstrap voltage for W phase
25 W, OUT
W
26 N
W
Negative DC input for U phase
Bootstrap voltage for V phase
W phase output
Negative DC input for W phase page 3/23
STIPN2M50T-HL
Internal schematic diagram and pin configuration
Figure 2. Pin layout (top view)
(*) (*)
PIN #1 ID
(*) Dummy pin internally connected to P (positive DC input).
GADG130720161515FSR
DS11753 - Rev 5 page 4/23
2
2.1
STIPN2M50T-HL
Electrical ratings
Electrical ratings
Absolute maximum ratings
Table 2. Inverter part
Symbol Parameter
V
DSS
± I
D
± I
DP
P
TOT
MOSFET blocking voltage (or drain-source voltage) for each MOSFET (V
Continuous drain current each MOSFET (T
C
= 25 °C)
Peak drain current each MOSFET (less than 1 ms)
Total power dissipation for each MOSFET (T
C
= 25 °C) T
C
= 25 °C
1. Applied between HINi, LINi and GND for i = U, V, W.
2. Pulse width limited by max. junction temperature.
IN
= 0 V)
Symbol
V
OUT
V
CC
V
CIN
V op+
V op-
V boot
V
IN
V
T/SD/OD dV
OUT
/dt
Table 3. Control part
Parameter
Output voltage applied between OUT
U
GND
, OUT
V
, OUT
W
-
Low voltage power supply
Comparator input voltage
Op-amp non-inverting input
Op-amp inverting input
Bootstrap voltage
Logic input voltage applied between HIN, LIN and GND
Open-drain voltage
Allowed output slew rate
Value Unit
500 V
2
4
A
A
10.4
W
Min.
Max.
V boot
- 21 V boot
+ 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
21
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
620
15
15
50
Unit
V
V
V
V
V
V
V
V
V/ns
Symbol
V
ISO
T
J
T
C
Table 4. Total system
Parameter
Isolation withstand voltage applied between each pin and heat sink plate
(AC voltage, t = 60 s)
Power chip operating junction temperature range
Module case operation temperature range
Value
1000
-40 to 150
-40 to 125
Unit
Vrms
°C
°C
DS11753 - Rev 5 page 5/23
2.2
Thermal data
Symbol
R th(j-c)
R th(j-c)
Table 5. Thermal data
Parameter
Thermal resistance junction-case single MOSFET
Thermal resistance junction-ambient (per module)
STIPN2M50T-HL
Thermal data
Value
10.6
22
Unit
°C/W
°C/W
DS11753 - Rev 5 page 6/23
3
3.1
STIPN2M50T-HL
Electrical characteristics
Electrical characteristics
T
J
= 25 °C unless otherwise specified.
Inverter part
Table 6. Static
Symbol
V
I
DSS
(BR)DSS
R
DS(on)
Drain-source breakdown voltage
Static drain-source turn-on resistance
Parameter
Zero-gate voltage drain current
Test conditions
V
DS
= 500 V, V
CC
= 15 V, V
Boot
=
15 V
V
CC
= V boot
= 15 V, V
IN
I
D
= 1 mA
V
CC
= V boot
= 15 V, V
IN
V, I
D
= 1.2 A
V
SD
Drain-source diode forward voltage
V
IN
D
1. Applied between HINx, LINx and GND for x = U, V, W.
= 2 A
Min.
500
Typ.
1.5
0.9
Max.
1
1.7
1.6
Table 7. Inductive load switching time and energy
Symbol Parameter t on
Turn-on time t c(on)
Crossover time (on) t off
t c(off)
Turn-off time
Crossover time (off) t rr
E on
E off
Reverse recovery time
Turn-on switching energy
Turn-off switching energy
V
DD
V
CC
V
I
C
Test conditions
= 300 V,
= V boot
IN
= 1.2 A
(see
Figure 4. Switching time definition
)
= 15 V,
Min.
-
-
-
-
-
-
-
Typ.
267
153
265
46
192
61
4
Max.
-
-
-
-
-
-
-
Unit ns
µJ
1. t
ON
and t
OFF
include the propagation delay time of the internal drive. t itself under the internally given gate driving conditions.
C(ON)
and t
C(OFF)
are the switching time of MOSFET
2. Applied between HINx, LINx and GND for x = U, V, W.
Unit mA
V
Ω
V
DS11753 - Rev 5 page 7/23
Figure 3. Switching time test circuit
STIPN2M50T-HL
Inverter part
GIPD161120151702RV
V
Figure 4. Switching time definition
100% I
D
100% I
D t rr
DS
I
D
I
D
V
DS
DS11753 - Rev 5
V
IN
V
IN(ON) t
ON t
C(ON)
10% I
D
90% I
D
10% V
DS
V
IN t
OFF
V
IN(OFF)
(a) turn-on
Figure 4. Switching time definition refers to HIN, LIN inputs (active high).
10% V
DS t
C(OFF)
10% I
D
(b) turn-off
AM09223V2 page 8/23
3.2
STIPN2M50T-HL
Control part
Control part
V
CC
= 15 V unless otherwise specified
Symbol
V
CC_hys
V
CC_thON
V
CC_thOFF
I qccu
I qcc
V ref
Quiescent current
Table 8. Low voltage power supply
Parameter
V
CC
UV hysteresis
V
CC
UV turn-ON threshold
V
CC
UV turn-OFF threshold
Undervoltage quiescent supply current
Test conditions
V
CC
= 15 V, T/SD/OD = 5 V; LIN = 0 V;
HIN = 0 V, CIN = 0 V
V cc
= 15 V, T/SD/OD = 5 V; LIN = 0 V;
HIN = 0 V, CIN = 0 V
Internal comparator (CIN) reference voltage
Min.
Typ.
Max.
Unit
1.2
1.5
1.8
V
11.5
10
12
10.5
12.5
11
V
V
150 µA
1
0.5
0.54
0.58
mA
V
Symbol
V
BS_hys
V
BS_thON
V
BS_thOFF
I
QBSU
I
QBS
R
DS(on)
Table 9. Bootstrapped voltage
Parameter
V
BS
UV hysteresis
V
BS
UV turn-ON threshold
V
BS
UV turn-OFF threshold
Undervoltage V
BS current
V
BS
quiescent
quiescent current
Test conditions
V
BS
< 9 V T/SD/OD = 5 V; LIN = 0 V and
HIN = 5 V; CIN = 0 V
V
BS
= 15 V T/SD/OD = 5 V; LIN = 0 V and HIN = 5 V; CIN = 0 V
Bootstrap driver on-resistance LVG ON
Min.
Typ.
Max.
Unit
1.2
11.1
9.8
1.5
11.5
10
1.8
12.1
10.6
V
V
V
70
200
120
110
300
µA
µA
Ω
Symbol
V il
V ih
I
HINh
I
HINI
I
LINI
I
LINh
I
SDh
I
SDI
Dt
Table 10. Logic inputs
Parameter
Low logic level voltage
High logic level voltage
HIN logic “1” input bias current HIN = 15 V
HIN logic “0” input bias current HIN = 0 V
LIN logic “1” input bias current LIN = 15 V
Test conditions
LIN logic “0” input bias current LIN = 0 V
SD logic “0” input bias current SD = 15 V
SD logic “1” input bias current
Dead time
SD = 0 V
See Figure 9. Dead time and interlocking waveform definitions
Min.
Typ.
Max.
Unit
0.8
V
2.25
20 40 100
1
V
µA
µA
20 40
200 350
100
1
500
3
µA
µA
µA
µA
180 ns
DS11753 - Rev 5 page 9/23
DS11753 - Rev 5
STIPN2M50T-HL
Control part
Table 11. Op-amp characteristics
Symbol
V io
I io
I ib
V
OL
V
OH
I o
SR
GBWP
Input offset voltage
Input offset current
Low level output voltage
High level output voltage
Output short-circuit current
Slew rate
Parameter
Gain bandwidth product
A vd
SVR
CMRR
Large signal voltage gain
Supply voltage rejection ratio
Common mode rejection ratio
1. The direction of the input current is out of the IC.
V ic
V ic
= 0 V, V o
= 0 V, V o
Test conditions
= 7.5 V
= 7.5 V
R
L
= 10 kΩ to V
CC
R
L
= 10 kΩ to GND
Source, V id
= +1 V; V o
= 0 V
Sink, V id
= -1 V; V o
= V
CC
V i
= 1 - 4 V; C
L
= 100 pF; unity gain
V o
= 7.5 V
R
L
= 2 kΩ vs. V
CC
2.5
8
70
60
55
14
16
50
Min.
Typ.
Max.
Unit
6 mV
4
100
75
40
200
150 nA nA mV
14.7
30
80
V mA mA
3.8
12
85
75
70
V/µs
MHz dB dB dB
Table 12. Sense comparator characteristics
Symbol
R
V
I ib od
ON_OD
Parameter
Input bias current
Open-drain low level output voltage
Open-drain low level output resistance
SD pull-down resistor
I
I
V
CIN od od
= 1 V
= 3 mA
= 3 mA
Test conditions Min.
R
PD_SD t d_comp
Comparator delay
T/SD/OD pulled to 5 V through 100 kΩ resistor
C
L
= 180 pF; R pu
= 5 kΩ t t
SR sd isd
Slew rate
Shutdown to high / low-side driver propagation delay
Comparator triggering to high / low-side driver turn-off propagation delay
V
OUT
= 0 V, V boot
= V
CC
, V
IN
Measured applying a voltage step from 0 V to 3.3 V to pin CIN
1. Equivalent values are as a result of the resistances of three drivers in parallel.
= 0 to 3.3 V 50
50
Typ.
166
125
90
60
125
200
Max.
1
0.5
130
200
250
Unit
µA
V
Ω kΩ ns
V/µs ns page 10/23
STIPN2M50T-HL
Control part
3.2.1
Conditions
Shutdown enable half-bridge tri-state
Interlocking half-bridge tri-state
0 “logic state” half-bridge tri-state
1 “logic state” low-side direct driving
1 “logic state” high-side direct driving
1. X: do not care.
NTC thermistor
Table 13. Truth table
T/SD/OD
L
H
H
Logic input (V
I
)
LIN
H
L
H
H
H
L
Figure 5. Internal structure of SD and NTC
Vbias
HIN
H
L
L
H
LVG
L
H
L
L
L
Output
HVG
L
L
H
L
L
V
T/SD/OD
R SD
C SD NTC
LIN
SD/OD
HIN
VCC
Vboot
HVG
RPD_SD
OUT
LVG
GND CIN
R
PD_SD
: equivalent value as result of resistances of three drivers in parallel.
DS11753 - Rev 5 page 11/23
DS11753 - Rev 5
STIPN2M50T-HL
Control part
14
12
10
8
6
4
2
0
70
Figure 6. Equivalent resistance (NTC//R
PD_SD
)
140
120
100
80
60
40
20
0
-40 -20 0 20 40
Temperature (°C)
60 80 100 120
Figure 7. Equivalent resistance (NTC//R
PD_SD
) zoom
80 90 100
Temperature (°C)
110 120 page 12/23
DS11753 - Rev 5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
25
Figure 8. Voltage of T/SD/OD pin according to NTC temperature
V
R
Bias
SD
R
V
Bias
SD
= 2.2 kΩ
= 3.3 V
= 1.0 kΩ
50
= 5 V
SD/OD: high
75
Temperature (°C)
100
STIPN2M50T-HL
Control part
125 page 13/23
3.3
Waveform definitions
Figure 9. Dead time and interlocking waveform definitions
G
STIPN2M50T-HL
Waveform definitions
DS11753 - Rev 5 page 14/23
4
STIPN2M50T-HL
Shutdown function
Shutdown function
The device is equipped with three half-bridge IC gate drivers and integrates a comparator for fault detection.
The comparator has an internal voltage reference V
REF
connected to the inverting input, while the non-inverting input pin (CIN) can be connected to an external shunt resistor for current monitoring.
Since the comparator is embedded in the U IC gate driver, in case of fault it disables directly the U outputs, whereas the shutdown of V and W IC gate drivers depends on the RC value of the external SD circuitry, which fixes the disabling time.
For an effective design of the shutdown circuit, please refer to Application note AN4966.
Figure 10. Shutdown timing waveforms
GADG250120171515FSR
V
REF
CI N
HIN or LIN
HVG or LVG
SD/OD or
T/SD/OD
U V, W
PROTECT ION open -drain gate
(interna l)
A
B
A B
∗
∗
∗
∗
≅
_
R
SD
and C
SD
external circuitry must be designed to ensure
Please refer to AN4966 for further details.
∗
∗
* R
NTC
to be considered only when the NTC is internally connected to the T/SD/OD pin.
DS11753 - Rev 5 page 15/23
5
Application circuit example
Figure 11. Application circuit example
STIPN2M50T-HL
Application circuit example
DS11753 - Rev 5
MICROCONTROLLE R
GADG100620160912FSR
Application designers are free to use a different scheme according to the specifications of the device.
page 16/23
5.1
STIPN2M50T-HL
Guidelines
Guidelines
•
•
•
•
•
•
•
•
•
•
•
Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-in for each input. To avoid input signal oscillation, the wiring of each input should be as short as possible, and the use of RC filters (R
1
, C
1
) on each input signal is suggested. The filters should be with a time constant of about 100 ns and placed as close as possible to the IPM input pins.
The use of a bypass capacitor C
VCC
(aluminum or tantalum) can reduce the transient circuit demand on the power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, a decoupling capacitor C
2
(100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to the V cc
pin and in parallel with the bypass capacitor.
The use of an RC filter (R
SF
, C
SF
) is recommended to prevent protection circuit malfunction. The time constant (R
SF
x C
SF
) should be set to 1 μs and the filter must be placed as close as possible to the C
IN
pin.
The SD is an input/output pin (open-drain type if it is used as output). A built-in thermistor NTC is internally connected between the SD pin and GND. The voltage V
SD
-GND decreases as the temperature increases, due to the pull-up resistor R
SD
. In order to keep the voltage always higher than the high-level logic threshold, the pull-up resistor should be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply, respectively. The capacitor C
SD
of the filter on SD should be fixed no higher than 3.3 nF in order to assure the SD activation time τ
A
≤ 500 ns. Besides, the filter should be placed as close as possible to the SD pin.
The decoupling capacitor C
3
C boot
(from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each
, filters high-frequency disturbance. Both C possible to the U, V, W and V boot boot
and C
3
(if present) should be placed as close as
pins. Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires.
To avoid overvoltage on the V cc
pin, a Zener diode (Dz1) can be used. Similarly on the V boot
pin, a Zener diode (Dz2) can be placed in parallel with each C boot
.
The use of the decoupling capacitor C
4
(100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor C vdc
is useful to prevent surge destruction. Both capacitors C placed as close as possible to the IPM (C
4
has priority over C vdc
).
4
and C vdc
should be
By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-couplers is possible.
Low-inductance shunt resistors have to be used for phase leg current sensing.
In order to avoid malfunctions, the wiring on N pins, the shunt resistor and P
WR_GND
should be as short as possible.
The connection of SGN_GND to PWR_GND on one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation.
These guidelines ensure the device specifications for application designs. For further details, please refer to the relevant application note.
Symbol
V
PN
V
CC
V
BS t dead f
PWM
T
C
Parameter
Supply voltage
Control supply voltage
High-side bias voltage
Table 14. Recommended operating conditions
Test conditions
Applied between P-Nu, Nv, Nw
Applied between V
CC
-GND
Applied between V
BOOTx
-OUT for x = U, V, W
Blanking time to prevent arm-short
For each input signal
PWM input signal
-40 °C < T
C
< 100 °C
-40 °C < T
J
< 125 °C
Case operation temperature
Min.
13.5
13
1
Typ.
300
15
Max.
400
18
Unit
V
V
18
25
100
V
μs kHz
°C
DS11753 - Rev 5 page 17/23
6
6.1
STIPN2M50T-HL
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
NDIP-26L in line package information
Figure 12. NDIP-26L in line package outline
DS11753 - Rev 5
8278949_7 page 18/23
DS11753 - Rev 5
Dim.
b1 b2 b3 c c1
D
D1
A
A1
A2
A3
A4 b e e1 eB1
L
D2
D3
E
Table 15. NDIP-26L in line mechanical data
Min.
mm
Typ.
0.82
0.46
0.45
29.05
0.55
0.35
0.80
3.00
1.70
5.70
0.53
0.52
0.83
12.35
1.70
2.40
14.25
0.90
0.90
0.50
29.15
0.77
0.53
12.45
1.80
2.50
14.55
1.05
1.00
3.10
1.80
5.90
0.60
STIPN2M50T-HL
NDIP-26L in line package information
0.70
29.55
12.55
1.90
2.60
14.85
1.20
0.98
0.59
0.55
29.25
1.00
1.90
6.10
0.72
0.68
1.02
Max.
4.40
1.20
3.20
page 19/23
6.2
NDIP-26L packing information
Figure 13. NDIP-26L tube (dimensions are in mm)
STIPN2M50T-HL
NDIP-26L packing information
Base quantity
Bulk quantity
Notes:
1- Material: extrused/transparent PVC 0.80
±0.1
mm thickness 10E6~10E11/SQ PVC
2- General tolerance unless otherwise specified: ±0.25 mm
Parameter
Table 16. Shipping details
17 pieces
476 pieces
Value
8313150_3
DS11753 - Rev 5 page 20/23
STIPN2M50T-HL
Contents
Contents
DS11753 - Rev 5 page 21/23
STIPN2M50T-HL
Revision history
Table 17. Document revision history
Date
13-Jul-2016
11-Oct-2016
12-Jan-2017
01-Feb-2017
02-Mar-2020
Revision
1 Initial release.
2
3
Changes
Document status promoted from preliminary to production data.
Updated Table 8: "Inductive load switching time and energy".
Minor text changes.
4
5
Modified description on cover page
Updated
Section Features , Section Applications ,
Table 2. Inverter part , Table 3. Control part
,
, Table 6. Static , Table 7. Inductive load switching time and energy ,
,
DS11753 - Rev 5 page 22/23
STIPN2M50T-HL
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DS11753 - Rev 5 page 23/23
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