STMicroelectronics STIPN1M50-H Datasheet
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STIPN1M50-H
Datasheet
SLLIMM-nano IPM, 3-phase inverter, 1 A, 3.6 Ω max., 500 V MOSFET
NDIP-26L
Product status link
STIPN1M50-H
Product summary
Order code
Marking
Package
Packing
STIPN1M50-H
IPN1M50-H
NDIP-26L
Tube
Features
• IPM 1 A, 500 V, R
DS(on)
= 3.6 Ω, 3-phase MOSFET inverter bridge including control ICs for gate driving
• Optimized for low electromagnetic interference
• 3.3 V, 5 V, 15 V CMOS/TTL input comparators with hysteresis and pull-down/ pull-up resistors
• Undervoltage lockout
• Internal bootstrap diode
• Interlocking function
• Shutdown function
• Comparator for fault protection against overtemperature and overcurrent
• Op-amp for advanced current sensing
• Optimized pinout for easy board layout
• Up to ±2 kV ESD protection (HBM C = 100 pF, R = 1.5 kΩ)
Applications
• 3-phase inverters for motor drives
• Dish washers
• Roller shutters
• Air-conditioning fans
• Draining and recirculation pumps
Description
This SLLIMM (small low-loss intelligent molded module) nano provides a compact, high-performance AC motor drive in a simple, rugged design. It is composed of six
MOSFETs and three half-bridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed.
The package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. This
IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM is a trademark of STMicroelectronics.
DS11939 - Rev 4 - January 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
STIPN1M50-H
Internal schematic diagram and pin configuration
1
Internal schematic diagram and pin configuration
Figure 1. Internal schematic diagram
GND(1 )
SD/OD(2 )
VccW(3 )
HinW(4 )
LinW(5 )
OP+(6 )
OPOUT(7 )
OP-(8 )
VccV(9 )
HinV(10 )
LinV(11 )
Cin(12 )
VccU(13 )
HinU(14 )
SD/OD(15 )
LinU(16 )
GND
HVG
OUT
VCC
HIN LVG
SD/OD
LIN Vboot
GND
OPOUT
OP+
OPHVG
OUT
VCC
HIN LVG
SD/OD
LIN Vboot
GND
CIN
HVG
OUT
VCC
HIN
SD/OD
LIN
LVG
Vboot
(26)N W
(25)W,OUT W
(24)Vboot W
(23)N V
(22)V,OUT V
(21)Vboot V
(20)N U
(19)U,OUT U
(18) P
(17)Vboot U
ADG171120161035SA
DS11939 - Rev 4 page 2/21
DS11939 - Rev 4
STIPN1M50-H
Internal schematic diagram and pin configuration
20
21
22
10
11
12
13
7
8
9
4
5
6
Pin
1
2
3
14
15
16
17
18
19
23
24
25
26
Table 1. Pin description
Symbol
GND
SD/OD
V
CC
W
HIN W
LIN W
OP+
Ground
Shutdown logic input (active low) / open-drain (comparator output)
Low voltage power supply W phase
High-side logic input for W phase
Low-side logic input for W phase
Op-amp non inverting input
Description
OP
OUT
OP-
V
CC
V
HIN V
LIN V
CIN
V
CC
U
HIN U
SD/OD
Op-amp output
Op-amp inverting input
Low voltage power supply V phase
High-side logic input for V phase
Low-side logic input for V phase
Comparator input
Low voltage power supply for U phase
LIN U
V
BOOT
U
P
U, OUT
U
High-side logic input for U phase
Shutdown logic input (active low) / open-drain (comparator output)
Low-side logic input for U phase
Bootstrap voltage for U phase
Positive DC input
U phase output
N
U
V
BOOT
V
V, OUT
V
N
V
V phase output
Negative DC input for V phase
V
BOOT
W Bootstrap voltage for W phase
W, OUT
W
N
W
Negative DC input for U phase
Bootstrap voltage for V phase
W phase output
Negative DC input for W phase page 3/21
PIN26
STIPN1M50-H
Internal schematic diagram and pin configuration
Figure 2. Pin layout (top view)
(*) (*)
PIN17
PIN #1 ID
PIN1
(*) Dummy pin internally connected to P (positive DC input).
PIN16
AM09368V1
DS11939 - Rev 4 page 4/21
2
2.1
STIPN1M50-H
Electrical ratings
Electrical ratings
Absolute maximum ratings
Table 2. Inverter part
Symbol
V
DSS
± I
D
± I
DP
P
TOT
Parameter
MOSFET blocking voltage (or drain-source voltage) for each MOSFET (V
IN
Continuous drain current each MOSFET (T
C
= 25 °C)
Peak drain current each MOSFET (less than 1 ms)
Total power dissipation for each MOSFET (T
C
= 25 °C)
1. Applied between HINi, LINi and GND for i = U, V, W.
2. Pulse width limited by max. junction temperature.
Value
500
1
2
10.8
Symbol
V
OUT
V
CC
V
CIN
V op+
V op-
V boot
V
IN
V
T/SD/OD dV out
/dt
Table 3. Control part
Parameter
Output voltage applied between OUT
U
, OUT
V
, OUT
W
- GND
Low voltage power supply
Comparator input voltage
Op-amp non-inverting input
Op-amp inverting input
Bootstrap voltage
Logic input voltage applied between HIN, LIN and GND
Open-drain voltage
Allowed output slew rate
Min.
V boot
- 21
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
Max.
V boot
+ 0.3
21
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
620
15
15
50
V
V
V
V
Unit
V
V
V
V
V/ns
Unit
V
A
A
W
Symbol
V
ISO
T
J
T
C
Table 4. Total system
Parameter
Isolation withstand voltage applied between each pin and heat sink plate
(AC voltage, t = 60 s)
Power chip operating junction temperature range
Module case operation temperature range
Value
1000
-40 to 150
-40 to 125
Unit
Vrms
°C
°C
DS11939 - Rev 4 page 5/21
STIPN1M50-H
Thermal data
2.2
Thermal data
Symbol
R th(j-c)
R th(j-a)
Table 5. Thermal data
Parameter
Thermal resistance junction-case single MOSFET
Thermal resistance junction-ambient (per module)
Value
11.5
22
Unit
°C/W
°C/W
DS11939 - Rev 4 page 6/21
3
3.1
STIPN1M50-H
Electrical characteristics
Electrical characteristics
T
J
= 25 °C unless otherwise specified.
Inverter part
Table 6. Static
Symbol
I
DSS
Parameter
Zero-gate voltage drain current
V
DS
Test conditions
= 500 V, V
CC
= 15 V; V
V
(BR)DSS
R
DS(on)
V
SD
Drain-source breakdown voltage
Static drain source turnon resistance
Drain-source diode forward voltage
V
CC
= V boot
= 15 V,
V
IN
= 0 V , I
D
= 1 mA
V
CC
= V boot
= 15 V,
V
IN
= 0 to 5 V, I
D
= 0.5 A
I
V
IN
D
= 0 “logic state”,
= 1 A
1. Applied between HINx, LINx and GND for x=U,V,W.
Boot
= 15 V
Min.
500
Typ.
3.2
0.9
Max.
1
3.6
1.6
Unit mA
V
Ω
V
Table 7. Inductive load switching time and energy
Symbol t on
t c(on)
t off
t c(off)
E
E t rr on off
Parameter
Turn-on time
Crossover time (on)
Turn-off time
Crossover time (off)
Reverse recovery time
Turn-on switching energy
Turn-off switching energy
I
C
= 0.5 A
(see
Test conditions
V
DD
= 300 V,
V
CC
= V boot
= 15 V,
V
IN
= 0 to 5 V ,
Figure 4. Switching time definition
)
Min.
-
-
-
-
-
-
-
Typ.
226
130
248
56
155
25
3.8
Max.
-
-
-
-
-
-
-
Unit ns
µJ
1. t
ON
and t
OFF
include the propagation delay time of the internal drive. t itself under the internally given gate driving conditions.
C(ON)
and t
C(OFF)
are the switching time of MOSFET
2. Applied between HINx, LINx and GND for x=U,V,W.
DS11939 - Rev 4 page 7/21
Figure 3. Switching time test circuit
STIPN1M50-H
Inverter part
DS11939 - Rev 4
V
Figure 4. Switching time definition
100% I D 100% I D t rr
DS
I
D
I
D
GIPD161120151702RV
V
DS
V
IN
V
IN(ON) t
ON t
C(ON)
10% I
D
90% I
D
10% V
DS
V
IN t
OFF
V
IN(OFF)
(a) turn-on
Figure 4. Switching time definition refers to HIN, LIN inputs (active high).
10% V
DS t
C(OFF)
10% I
D
(b) turn-off
AM09223V2 page 8/21
3.2
STIPN1M50-H
Control part
Control part
Symbol
V
CC_hys
V
CC_thON
V
CC_thOFF
I qccu
I qcc
V ref
Table 8. Low voltage power supply (V
CC
= 15 V unless otherwise specified)
Test conditions Parameter
V
CC
UV hysteresis
V
CC
UV turn ON threshold
V
CC
UV turn OFF threshold
Min.
1.2
11.5
10
Typ.
1.5
12
10.5
Max.
1.8
12.5
11
Undervoltage quiescent supply current
Quiescent current
V
CC
= 15 V, SD/OD = 5 V;
LIN = 0 V; HIN = 0 V,
CIN = 0 V
V
CC
= 15 V, SD/OD = 5 V;
LIN = 0 V; HIN = 0 V,
CIN = 0 V
150
1
Internal comparator (CIN) reference voltage
0.5
0.54
0.58
Unit
V
V
V
µA mA
V
Symbol
V
BS_hys
V
BS_thON
V
BS_thOFF
I
QBSU
I
QBS
R
DS(on)
Table 9. Bootstrapped voltage (V
CC
= 15 V unless otherwise specified)
Test conditions Parameter
V
BS
UV hysteresis
V
BS
UV turn-ON threshold
V
BS
UV turn-OFF threshold
Min.
1.2
11.1
9.8
Typ.
1.5
11.5
10
Max.
1.8
12.1
10.6
Undervoltage V
BS current
quiescent
V
BS
quiescent current
Bootstrap driver on- resistance
V
BS
< 9 V, SD/OD = 5 V;
LIN = 0 V and HIN = 5 V;
CIN = 0 V
V
BS
= 15 V, SD/OD = 5 V;
LIN = 0 V and HIN = 5 V;
CIN = 0 V
LVG ON
70
200
120
110
300
Unit
V
V
V
µA
µA
Ω
DS11939 - Rev 4 page 9/21
DS11939 - Rev 4
STIPN1M50-H
Control part
Symbol
I
LINh
I
LINI
I
SDh
I
SDI
V il
V ih
I
HINh
I
HINI
Dt
Table 10. Logic inputs (V
CC
= 15 V unless otherwise specified)
Min.
Typ.
Parameter
Low logic level voltage
High logic level voltage
Test conditions
HIN logic “1” input bias current HIN = 15 V
HIN logic “0” input bias current HIN = 0 V
LIN logic “1” input bias current LIN = 15 V
LIN logic “0” input bias current LIN = 0 V
SD logic “0” input bias current SD = 15 V
SD logic “1” input bias current SD = 0 V
Dead time
(see
Figure 5. Dead time and interlocking waveform definitions
)
2.25
20
20
30
40
40
120
180
Max.
0.8
100
1
100
1
300
3
µA
µA
µA
µA
Unit
V
V
µA
µA ns
Table 11. Op-amp characteristics (V
CC
= 15 V unless otherwise specified)
Min.
Typ.
Symbol
V io
I io
I
I ib
V
OL
V
OH o
SR
GBWP
A vd
SVR
CMRR
Parameter
Input offset voltage
Test conditions
V ic
= 0 V, V o
= 7.5 V
Input offset current
V ic
= 0 V, V o
= 7.5 V
Input bias current
Low level output voltage R
L
= 10 kΩ to V
CC
High level output voltage R
L
= 10 kΩ to GND
Output short-circuit current
Source, V id
= +1 V; V o
= 0 V
Supply voltage rejection ratio
Sink, V id
= -1 V; V o
= V
CC
Slew rate V i
= 1 - 4 V; C
L
= 100 pF; unity gain
Gain bandwidth product V o
= 7.5 V
Large signal voltage gain R
L
= 2 kΩ vs. V
CC
Common mode rejection ratio
1. The direction of input current is out of the IC.
14
16
50
2.5
8
70
60
55
4
100
75
14.7
30
80
3.8
12
85
75
70
Max.
6
40
200
150
Unit mV nA nA mV
V mA mA
V/µs
MHz dB dB dB page 10/21
DS11939 - Rev 4
STIPN1M50-H
Control part
Table 12. Sense comparator characteristics (V
CC
= 15 V unless otherwise specified)
Symbol
R
V
I ib od
ON_OD
Parameter
Input bias current
Open-drain low level output voltage
Open-drain low level output resistance
SD pull-down resistor
I
I
V
CIN od od
Test conditions
= 1 V
= 3 mA
= 3 mA
R
PD_SD t d_comp t
SR t sd isd
Comparator delay
Slew rate
Shutdown to high / lowside driver propagation delay
Comparator triggering to high / low-side driver turnoff propagation delay
SD/OD pulled to 5 V through
100 kΩ resistor
C
L
= 180 pF; R pu
= 5 kΩ
V
V
OUT
IN
= 0, V boot
= 0 to 3.3 V
= V
CC
,
Measured applying a voltage step from 0 V to 3.3 V to pin CIN
1. Equivalent values as a result of the resistances of three drivers in parallel.
Min.
50
50
Typ.
166
125
90
60
125
200
Max.
1
0.5
130
200
250
Unit
µA
V
Ω kΩ ns
V/µs ns
Condition
Shutdown enable half-bridge tri-state
Interlocking half-bridge tri-state
0 “logic state” half-bridge tri-state
1 “logic state” low-side direct driving
1 “logic state” high-side direct driving
1. X: don’t care.
Table 13. Truth table
SD/OD
H
H
L
H
H
Logic input (V
I
)
LIN
H
L
H
L
HIN
H
L
L
H
LVG
L
H
L
L
L
Output
HVG
L
L
L
L
H page 11/21
3.3
Waveform definitions
Figure 5. Dead time and interlocking waveform definitions
G
STIPN1M50-H
Waveform definitions
DS11939 - Rev 4 page 12/21
4
STIPN1M50-H
Shutdown function
Shutdown function
The device is equipped with three half-bridge IC gate drivers and integrates a comparator for fault detection.
The comparator has an internal voltage reference V
REF
connected to the inverting input, while the non-inverting input pin (CIN) can be connected to an external shunt resistor for current monitoring.
Since the comparator is embedded in the U IC gate driver, in case of fault it disables directly the U outputs, whereas the shutdown of V and W IC gate drivers depends on the RC value of the external SD circuitry, which fixes the disabling time.
For an effective design of the shutdown circuit, please refer to Application note AN4966.
Figure 6. Shutdown timing waveforms
GADG250120171515FSR
V
REF
CI N
HIN or LIN
HVG or LVG
SD/OD or
T/SD/OD
U V, W
PROTECT ION open -drain gate
(interna l)
A
B
A B
∗
∗
∗
∗
≅
_
R
SD
and C
SD
external circuitry must be designed to ensure
Please refer to AN4966 for further details.
∗
∗
* R
NTC
to be considered only when the NTC is internally connected to the T/SD/OD pin.
DS11939 - Rev 4 page 13/21
5
Application circuit example
Figure 7. Application circuit example
STIPN1M50-H
Application circuit example
DS11939 - Rev 4
MICROCONTROLLE R
GADG181120160820SA
Application designers are free to use a different scheme according to the specifications of the device.
page 14/21
5.1
STIPN1M50-H
Guidelines
Guidelines
•
•
•
•
•
•
•
•
•
•
•
Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-in for each input. To avoid input signal oscillation, the wiring of each input should be as short as possible, and the use of RC filters (R
1
, C
1
) on each input signal is suggested. The filters should be with a time constant of about 100 ns and placed as close as possible to the IPM input pins.
The use of a bypass capacitor C
VCC
(aluminum or tantalum) can reduce the transient circuit demand on the power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, a decoupling capacitor C
2
(100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to the V cc
pin and in parallel with the bypass capacitor.
The use of an RC filter (R
SF
, C
SF
) is recommended to prevent protection circuit malfunction. The time constant (R
SF
x C
SF
) should be set to 1 μs and the filter must be placed as close as possible to the CIN pin.
The SD is an input/output pin (open-drain type if it is used as output). The capacitor C
SD
of the filter on SD should be fixed no higher than 3.3 nF in order to assure the SD activation time τ
A
≤ 500 ns. Besides, the filter should be placed as close as possible to the SD pin.
The decoupling capacitor C
3
(from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each
C boot
, filters high-frequency disturbance. Both C boot
and C
3
(if present) should be placed as close as possible to the U, V, W and V boot
pins. Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires.
To avoid overvoltage on the V cc
pin, a Zener diode (Dz1) can be used. Similarly on the V diode (Dz2) can be placed in parallel with each C boot
.
boot
pin, a Zener
The use of the decoupling capacitor C
4
(100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor C vdc
is useful to prevent surge destruction. Both capacitors C placed as close as possible to the IPM (C
4
has priority over C vdc
).
4
and C vdc
should be
By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-couplers is possible.
Low-inductance shunt resistors have to be used for phase leg current sensing.
In order to avoid malfunctions, the wiring on N pins, the shunt resistor and P
WR_GND
should be as short as possible.
The connection of SGN_GND to PWR_GND on one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation.
These guidelines ensure the specifications of the device for application designs. For further details, please refer to the relevant application note.
Symbol
V
PN
V
CC
V
BS t dead f
PWM
T
C
Parameter
Supply voltage
Control supply voltage
PWM input signal
Table 14. Recommended operating conditions
High-side bias voltage
Blanking time to prevent arm-short
Test conditions
Applied between P-Nu, Nv, Nw
Applied between V
CC
-GND
Applied between V
BOOTi
-OUT i for i = U, V, W
For each input signal
-40 °C < T
C
< 100 °C
-40 °C < T
J
< 125 °C
Case operation temperature
Min.
Typ.
Max.
Unit
300 400 V
13.5
15 18 V
13 18 V
1
25
µs kHz
100 °C
DS11939 - Rev 4 page 15/21
6
6.1
STIPN1M50-H
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
NDIP-26L type C package information
Figure 8. NDIP-26L type C package outline
DS11939 - Rev 4
8278949_7 page 16/21
DS11939 - Rev 4
Dim.
eB1 eB2
L
D2
D3
E e e1 b1 b2 b3 c c1
D
D1
A
A1
A2
A3
A4 b
STIPN1M50-H
NDIP-26L type C package information
Table 15. NDIP-26L type C mechanical data
Min.
mm
Typ.
0.82
0.46
0.45
29.05
0.50
0.35
0.80
3.00
1.70
5.70
0.53
0.52
0.83
12.35
1.70
2.40
16.10
21.18
1.24
0.90
0.50
29.15
0.77
0.53
12.45
1.80
2.50
16.40
21.48
1.39
1.00
3.10
1.80
5.90
0.60
0.70
29.55
12.55
1.90
2.60
0.98
0.59
0.55
29.25
1.00
16.70
21.78
1.54
1.90
6.10
0.72
0.68
1.02
Max.
4.40
1.20
3.20
page 17/21
6.2
NDIP-26L packing information
Figure 9. NDIP-26L tube (dimensions are in mm)
STIPN1M50-H
NDIP-26L packing information
Notes:
1- Material: extrused/transparent PVC 0.80
±0.1
mm thickness 10E6~10E11/SQ PVC
2- General tolerance unless otherwise specified: ±0.25 mm
Table 16. Shipping details
Parameter
Base quantity
Bulk quantity
Value
17 pieces
476 pieces
8313150_3
DS11939 - Rev 4 page 18/21
STIPN1M50-H
Revision history
Table 17. Document revision history
Date
18-Nov-2016
Revision
1 Initial release.
01-Feb-2017
07-Jun-2017
28-Jan-2020
2
3
4
Changes
Modified features and description on cover page.
Modified Table 15: "Recommended operating conditions"
Modified Table 3: "Inverter part", Table 6: "Thermal data" and
Table 11: "Logic inputs (V
CC
= 15 V unless otherwise specified)" .
Minor text changes.
Modified title, features and applications in cover page.
Updated Section 2 Electrical ratings
, Section 3 Electrical characteristics ,
Section 4 Shutdown function and
.
Minor text changes.
DS11939 - Rev 4 page 19/21
STIPN1M50-H
Contents
Contents
DS11939 - Rev 4 page 20/21
STIPN1M50-H
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS11939 - Rev 4 page 21/21
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