STMicroelectronics STEF512SRX Datasheet
Annonce
Annonce
STEF512SRX
Datasheet
Dual electronic fuse for 5 V and 12 V rails with reverse current blocking
Maturity status link
STEF512SRX
Features
• 5 V and 12 V channels into one chip
• 25 V absolute maximum input voltage
• Precise output overvoltage clamp
• Fixed overcurrent protection for both channels
• Reverse current protection on 5 V channel
• Thermal protection
• Available in auto-retry version
• Input undervoltage lockout
• Adjustable output voltage slew rate
• Integrated 45 mΩ power MOSFETs
• SAS disable pin
• Current monitor pin selection
• Current monitor output in a single pin for both rails
• DFN10 (2 x 3 mm) package
Applications
• HD and SSD
• Hard disk arrays and NAS
• Hot plug protections
Description
The STEF512SRX is an integrated dual electronic fuse, designed to protect circuitry on the output from overcurrent and overvoltage events, in those applications requiring hot swap operation and inrush current control.
The device embeds two electronic fuses, one for the 5 V rail and one for the 12 V rail.
Thanks to the very low on-resistance of the integrated power MOSFETs, the voltage drop from the main supply to the load is very low during normal operation.
The 5 V channel provides a reverse blocking feature, preventing current flow to the input in case of brown-out or shutdown.
The start-up time is internally controlled by a dedicated slew rate circuit. In this way the inrush current at startup can be kept under control.
The maximum load current is precisely limited, by utilizing a sense FET topology, to factory-defined values.
The device also provides precise overvoltage clamp for each channel, preventing the load being damaged from power supply failures, and undervoltage lockout (UVLO), assuring that the input voltage is above the minimum operating threshold, before the power is turned on.
When an overload condition occurs, the STEF512SRX limits the output current to the predefined safe value. If the anomalous overload condition persists, the device goes into thermal shutdown, the internal switch is opened and the load is disconnected from the power supply.
Load current on each channel can be accurately monitored by reading the signal on the I
MON_5/12
pin.
DS13826 - Rev 1 - January 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
1
Diagram
Figure 1. Block diagram
STEF512SRX
Diagram
DS13826 - Rev 1 page 2/27
2
STEF512SRX
Pin configuration
Pin configuration
Figure 2. Pin connection (top view)
Symbol
V
IN_12
SS
12
SS
5
GND
V
IN_5
V
OUT_5
I
MON_5/12
I
MON_SEL
EN
V
OUT_12
V
IN_12
SS
12
SS
5
GND
V
IN_5
1
2
3
4
5
9
8
7
6
10
V
OUT_12
EN
I
MON_SEL
I
MON_5/12
V
OUT_5
DFN 10 (2 x 3 mm)
Marking view
3
6
7
4
5
8
9
10
Pin
1
2
Table 1. Pin description
Description
12 V rail supply voltage.
If not connected, default start-up time of 12 V channel is 13 ms. If bypassed to
GND with Css, the start-up time can be increased to more than 13 ms. Leave the pin floating if not used.
If not connected, default start-up time of 5 V channel is 13 ms. If bypassed to GND with Css, the start-up time can be increased to more than 13 ms. Leave the pin floating if not used.
Ground.
5 V rail supply voltage.
5 V rail output voltage.
Current monitoring for 5 V or 12 V rail.
Current monitoring selection pin. If connected to GND, pin 7 shows the I
MON_5 value. If connected to high level voltage or left floating it shows the I
MON_12
value.
This pin is pulled up to 3.3 V via 750 kΩ resistor.
SAS disable input: set this pin logic-low to turn on the device, high to turn off the device. This pin is internally pulled down to GND via 3.3 MΩ resistor.
12 V rail output voltage.
DS13826 - Rev 1 page 3/27
3
Typical application
Figure 3. Typical application circuit
STEF512SRX
Typical application
Note: C
SS_5
and C
SS_12
are optional.
DS13826 - Rev 1 page 4/27
4
STEF512SRX
Maximum ratings
Maximum ratings
Table 2. Absolute maximum ratings
Symbol
V
V
IN_5
IN_12
Parameter
5 V supply voltage
Negative transient tolerance (< 1 ms)
12 V supply voltage
Negative transient tolerance (< 1 ms)
Value
-0.3 to 25
-3
-0.3 to 25
-3
Unit
V
V
V
V
V
EN
I
I
V
V
OUT_5
OUT_12
SSx
I
OUT_5
OUT_12
, I
MON_SEL
MON_5,12
ESD
5 V output voltage
12 V output voltage
Soft-start pin voltage
Continuous output current
Continuous output current
Enable pin, I
MON
selection
Monitor pins voltage
Charge device model
Human body model
-0.3 to 7
-0.3 to V
IN
+ 0.3
(18 V max.)
-0.3 to 7
3.6
3.6
-0.3 to 7
-0.3 to 7
± 500
± 2000
V
V
V
A
A
V
V
V
T
J-OP
T
STG
Operating junction temperature
Storage temperature
-40 to 125
-55 to 150
°C
°C
1. This value can be applied for guaranteed lifetime. Higher value can be applied for a time lower than 200 ms. The maximum allowable power dissipation is a function of the maximum operative junction temperature of 125 °C, the junction-to-ambient thermal resistance R thJA
, and the ambient temperature T
A
. It can be estimated by: P
D(MAX)
= (125 - T the maximum allowable power dissipation produces overheating that may cause thermal shutdown.
A
) / R thJA
. Exceeding
2. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures greater than the maximum ratings for extended periods of time.
Table 3. Thermal data
Symbol
R thJA
R thJC
Parameter
Thermal resistance junction-ambient
Thermal resistance junction-case
1. Based on JESD51-7, 4-layer PCB.
Value
82
12
Unit
°C/W
°C/W
DS13826 - Rev 1 page 5/27
5
STEF512SRX
Electrical characteristics
Electrical characteristics
T
J
= 25 °C, V
IN_5
= 5 V, V
IN_12
= 12 V, V
EN
= 0 V, C
IN
= 1 µF, C
OUT
= 10 µF, unless otherwise specified.
Table 4. Electrical characteristics for STEF512SRX
Symbol
5 V eFuse
V
IN_5
V
Clamp_5
Parameter
Operating input voltage
Output clamping voltage
Test conditions Min.
V
UVLO_5
R
DSon_5
I
L_5
I
PLP_5
T
PLP
Undervoltage lockout
On-resistance
Off-state leakage current
PLP reverse leakage current
PLP intervention time
V
IN_5
= 8 V
Turn-on, voltage rising
Hysteresis
T
J
= 25 °C, I
OUT_05
= 0.5 A
T
J
V
EN
= 5 V, V
OUT_5
= GND
V
EN
= 0 V, V
OUT_5
= 5 V,
V
IN_5
< V
UVLO_5
V
EN
= 0V, V
OUT_5
= 5 V,
V
IN_5
< V
UVLO_5
, I
PLP_5
< 1 µA,
(see
)
4.5
5.5
3.9
Typ.
600
5.7
4.0
0.3
45
I
TRIP_5
I
HOLD_5
I
SHORT_5
Overload current limit
dV/dt
_5
Output voltage ramp time
V
OUT_5
> 2.5 V
V
OUT_5
< 2.5 V
From 10% to 90% of V
OUT
,
C
SS_5
floating
2.9
10.5
3.6
3.1
1.75
13
A
I_5
Current monitor output current gain
I
MON_5
/ I
OUT_5
12 V eFuse
V
IN_12
V
Clamp_12
V
UVLO_12
V
Hyst_12
Operating input voltage
Output clamping voltage
Undervoltage lockout
UVLO hysteresis
R
DSon_12
On-resistance
I
L_12
I
TRIP_12
I
HOLD_12
I
SHORT_12
A
I_12
Off-state leakage current
Overload current limit
Current monitor output current gain
I
MON_12
/ I
OUT_12
I
OUT_5
> = 100 mA
V
IN_12
= 17 V
Turn-on, voltage rising
Turn-off, voltage falling
T
J
= 25 °C, I
OUT_12
= 0.5 A
T
J
V
EN
= 5 V, V
OUT_12
= GND
V
OUT_12
> 7.5 V
V
OUT_12
< 7.5 V
I
OUT_12
> = 100 mA
26
10.5
14.5
7.7
2.9
27.5
28.5
15
8.5
0.8
40
3.6
3.1
1.75
30
Max.
V
Clamp_5
5.9
4.1
70
1
1
3.3
15.5
31
V
Clamp_12
15.5
9.3
70
1
3.3
32.5
Unit ns
µA/A
µA/A
A
A
A ms mΩ
µA
A
A
A
V
V
V
V
V
V
V
V mΩ
µA
µA
DS13826 - Rev 1 page 6/27
DS13826 - Rev 1
STEF512SRX
Electrical characteristics
Symbol dV/dt
_12
Parameter
Output voltage ramp time
Test conditions
From 10% to 90% of V
OUT
,
C
SS_12
floating
Min.
10.5
Typ.
13
Max.
15.5
Common features
V
V
IL
IH
Low level input voltage, EN pin
High level input voltage, EN pin
R
Pull-down
I
EN
Pull-down resistor on EN
EN consumption
T
V
V
IH_IMSL
R
IL_IMSL
V pull1
Pull-up
DELAY
I
MON_SEL
low level input voltage
I
MON_SEL
high level input voltage
Pull-up (I mon_sel
)
Pull-up resistor on I mon_sel
Startup output delay time
I
I
Output enabled
Output disabled
Connected to GND
V
EN
= 5 V
MON_5/12
pin outputs I
MON_5/12
pin outputs I
EN set to low state
MON_5
MON_12
1.7
1.6
3.3
1.5
3.3
750
500
0.7
0.7
I q
Quiescent current (GND)
Device operating, no load
Off-state, V
EN
= 5 V
400
8
600
Thermal protection
Shutdown temperature
TSD
Hysteresis
165
30
1. Values across temperature range are guaranteed by design/correlation and tested in production only at ambient temperature.
2. Guaranteed by design, but not tested in production.
Symbol
C
IN
C
OUT
C
IMON_x
R
IMONx
Table 5. Recommended operating condition
Parameter
Input capacitance
Output capacitance
Monitor pin filter capacitor
Monitor pin resistor
Min.
1
10
1
Typ.
10
47
10
10
Max
Unit ms
°C
Unit
µF nF kΩ
V
V
MΩ
µA
V
V
V kΩ
µs
µA
µA page 7/27
6
6.1
6.2
6.3
STEF512SRX
Device functional description
Device functional description
The STEF512SRX embeds a 5 V and a 12 V electronic fuse (eFuses). Each eFuse can limit the voltage or the current during fault events, such as input overvoltage or output overload, respectively. For this purpose, it contains
2 hysteretic control loops, one limiting the output voltage and one limiting the input current.
The current limiting loop is also used during the start-up phase of the eFuse to limit the inrush current into the output capacitor.
During normal operation, the eFuse behaves as a low-resistance power FET, therefore the output voltage follows the input one. In case of overvoltage or overcurrent event, the eFuse limits the V
GS
of the internal FET, to clamp the output voltage or current respectively. During such events the die temperature increases due to the power dissipation and so, if the fault persists and the overtemperature threshold is overcome, the device goes into thermal shutdown, the internal FET is turned off and the load disconnected from the power supply.
Each eFuse provides factory-trimmed undervoltage lockout feature.
Undervoltage lockout
Undervoltage lockout circuit prevents each eFuse from turning on if the supply voltage is below the UVLO rising threshold. During operation, if the input voltage of one channel falls below (V
UVLO_x
- V
Hyst_x
), the outputs of both channels are turned off simultaneously.
Start-up sequence and voltage clamp
•
•
The typical start-up sequence of the eFuse is described below and shown in
, as follows:
• The power supply is connected to the V undervoltage lockout threshold.
IN_x
pins and both 5 V and 12 V input voltages are higher than the
The disable pin (EN) is connected to GND or left floating by the user to enable the device.
Typically 500 µs after the eFuse starts ramping up the output voltage. Each channel ramps up with the default or user-defined value.
• If the input voltage continues rising, above the overvoltage threshold (V
Clamp_x
), as a consequence of a failure in the power supply, the eFuse limits the output voltage to V
Clamp_x
. The eFuse keeps operating in this state until overtemperature threshold is reached and then it shuts down. The power MOSFET remains in an off-state until the die temperature drops below the hysteresis value. Once this happens, the internal auto-retry circuit attempts to reset the device.
Soft-start function
In order to reduce the inrush current the device starts with a controlled slew rate.
•
•
•
If SS
12
and SS
5
pins are floating the device starts with an internal controlled slew rate of 13 ms on both channels.
The soft-start time can be increased from 13 ms to higher values, by connecting the external C
SS_X capacitors.
At each new startup the internal circuitry choses the longer slew rate between the default internal one
(13 ms) and the one set by C
SS_X
During the start-up phase the foldback current limit is disabled, the current limit is set to I
HOLD_x
value.
Given the desired time interval Δt, the capacitance to be added on the C
SS_X
pin with nominal input voltage
V
IN_12
= 12 V, V
IN_5
= 5 V can be calculated using the following theoretical formula, valid for C
SS_X
> 100 nF.
Δt ms = CSS_X nF × 0.13
(1)
DS13826 - Rev 1 page 8/27
Figure 4. Typical start-up sequence (Enable after V
IN
rise)
STEF512SRX
Enable pin
Figure 5. Typical start-up sequence (Enable during V
IN
rise)
6.4
6.5
Enable pin
The device provides an SAS-compliant chip disable pin (EN). The pin is internally pulled down to GND via 3.3
MΩ.
If this function is not needed in the application, it can be left floating. As soon as the input voltage of both channels is higher than the UVLO thresholds, the device ON/OFF status depends on the enable pin as described in the above images.
Current limit function after startup
Each eFuse provides 2 kinds of current limit protection mechanisms (see
•
•
Operative current limit (I
HOLD_x
) for both channels, active once the output voltage reaches the input voltage.
Short-circuit current limit (I
SHORT_x
) is applied when the output voltage falls below the short-circuit detection thresholds (2.5 V for the 5 V eFuse and 7.5 V for the 12 V eFuse).
DS13826 - Rev 1 page 9/27
Figure 6. Current limit function graph (5 V and 12 V channels)
STEF512SRX eFuse current monitor
6.6
eFuse current monitor
Each channel is equipped with a current monitoring feature that allows the host processor to read the current flowing through the fuse. To use only one ADC converter, the I
MON_5/12
pin is able to manage both outputs current information, thanks to a current monitoring selection pin (I
MON_SEL
).
If I
MON_SEL the I
MON_12
is connected to GND, the pin 7 outputs the I
MON_5
signal.
signal. If I
MON_SEL
is set to high level, pin 7 outputs
The I
MON_x
signal is a current proportional to the relevant channel load current, by factor A
I_x
= I
MON_x
/ I
OUT_x
.
This current is imposed on an external R
MON_x
, converting the sensing current into voltage for further processing
by the host system (see Figure 7 ).
Figure 7. Current monitor simplified circuit
6.7
Current monitoring circuit is also equipped with an internal clamp that limits the voltage on the pin at a static value of 1.8 V. Bypassing the pin to GND with a minimum C
MON
of 1 nF is recommended as it avoids voltage spikes during fast output current transition.
Thermal shutdown
If the device temperature exceeds the thermal threshold, typically 165 °C, the thermal shutdown circuitry turns the power MOSFET off, thus disconnecting the load. The power MOSFET remains in an off-state until the die temperature drops below the hysteresis value. Once this happens, the internal auto-retry circuit attempts to reset the device.
The device is also equipped with a differential thermal protection that avoids damage in case of fast thermal gradients inside the chip. When the differential thermal protection is activated, both the channels are switched off.
This protection works in auto-retry mode without soft-start phase.
DS13826 - Rev 1 page 10/27
6.8
STEF512SRX
Reverse current blocking feature on the 5 V channel
Reverse current blocking feature on the 5 V channel
The 5 V eFuse contains a second power transistor (ISOFET) connected in a back-to-back configuration with the main one, to prevent significant current flowing back from the 5 V output into the 5 V input, in case of input short to ground, brown-out or deep input voltage glitch. The simplified structure is shown in
. The ISOFET is controlled by the UVLO circuit and by a reverse comparator, which continuously monitors the voltage difference between the V
IN_5
and V
OUT_5
.
Figure 8. 5 V eFuse diagram
6.9
As soon as the reverse comparator detects significant negative voltage across the 5 V eFuse (typically 50 mV), the M2 transistor is turned off immediately. M2 can be turned back on only if the voltage drop across the eFuse has become zero (no negative current). However, in case of slow V
IN_5
decay, the V
OUT_5
V
IN_5
because of the output capacitor being discharged through the eFuse into the V
IN_5
voltage follows the
, hence no significant negative voltage is generated across the eFuse. In that case the UVLO circuit serves as a “stop loss” feature, i.e.
the information from the reverse comparator is overridden by the V
IN_5
undervoltage lockout and M2 is forced to turn off.
As soon as the UVLO threshold has been reached again, the eFuse restarts with normal soft-start cycle.
•
•
•
•
External capacitors and application suggestions
Input and output capacitors are mandatory to reduce the transient effects of stray inductances which may be present on the input and output power paths. In fact, when the STEF512SRX interrupts the current flow, input inductance generates a positive voltage spike on the input, and output inductance generates a negative voltage spike on the output. To reduce the effects of such transients, a C
IN
capacitor of at least 1 µF (including derating effects) must be connected between the input pin and GND and placed as close as possible to the device.
For the same reason, a C
OUT
capacitor of at least 10 µF must be connected at the output port.
When the device is connected to the power supplies by means of long wires, whose inductance is higher than 1
µH, the input capacitor should be increased.
It is suggested to provide for additional protections and methods for addressing these transients, such as:
Minimizing inductance of the input and output tracks
TVS diodes on the input to absorb inductive spikes placed as close as possible to input pins
Schottky diode on the output to absorb negative spikes
Combination of ceramic and electrolytic capacitors on the input and output.
DS13826 - Rev 1 page 11/27
STEF512SRX
Typical characteristics
7
Typical characteristics
The following plots refer to the typical application circuit with V
CC_12
= 12 V, V
CC_5
= 5 V, I
SS_5 and SS_12 floating, EN set to low state and unless otherwise noted, at T
A
= 25 °C.
OUT_12
= I
OUT_5
= 0 A,
Figure 9. Quiescent current vs. temperature (ON Mode) Figure 10. Quiescent current vs. temperature (OFF Mode)
600
550
500
450
400
350
300
250
200
-50 -25 0
12
10
8
6
16
14
4
2
0
-50 -25 0 25 50
Temperature [ºC]
75 100 125 150 25 50
Temperature [ ºC]
75 100 125 150
Figure 11. R
DS_ON
12 V eFuse vs. temperature
I
OUT_12
= 500 mA, pulsed
80
70
60
50
40
30
20
10
-50 -25 0 25 50
Temperature [ºC]
75 100 125 150
Figure 12. R
DS_ON
5 V eFuse vs. temperature
I
OUT_5
= 500 mA, pulsed
80
70
60
50
40
30
20
10
-50 -25 0 25 50
Temperature [ºC]
75 100 125 150
DS13826 - Rev 1 page 12/27
Figure 13. 12 V eFuse voltage clamp vs. temperature
15.50
15.40
15.30
15.20
15.10
15.00
14.90
14.80
14.70
14.60
14.50
-50
V
IN_12
= 18 V, I
OUT_12
= 10 mA
-25 0 25 50
Temperature [ºC]
75 100 125 150
3.90
3.80
3.70
3.60
3.50
-50
4.20
Figure 15. UVLO 5 V eFuse vs. temperature
4.10
Rising threshold
Falling threshold
4.00
-25 0 25 50
Temperature [ºC]
75 100 125 150
Figure 17. 5 V eFuse overload current limit vs.
temperature
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
2.20
-50 -25 0 25 50
Temperature [ ºC]
75 100 125 150
STEF512SRX
Typical characteristics
Figure 14. 5 V eFuse voltage clamp vs. temperature
6.1
6.0
5.9
5.8
5.7
5.6
5.5
5.4
5.3
5.2
-50
V
IN_5
= 18 V, I
OUT_5
= 10 mA
-25 0 25 50
Temperature [ºC]
75 100 125 150
Figure 16. UVLO 12 V eFuse vs. temperature
8.00
7.75
7.50
7.25
7.00
-50
9.00
8.75
8.50
8.25
-25 0 25 50
Temperature [ºC]
75 100
Rising threshold
Falling threshold
125 150
Figure 18. 12 V eFuse overload current limit vs.
temperature
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
2.20
-50 -25 0 25 50
Temperature [ºC]
75 100 125 150
DS13826 - Rev 1 page 13/27
18.0
Figure 19. Soft-start time vs. temperature
C
SS_5
= C
SS_12
= 100nF
17.0
16.0
15.0
14.0
13.0
12.0
11.0
10.0
9.0
-50 -25 0 25 50
Temperature [ºC]
75 100
5 V channel
12 V channel
125 150
Figure 21. I
MON_SEL
pin threshold vs. temperature
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
-50 -25 0 25 50
Temperature [ºC]
75 100
VIL
VIH
125 150
Figure 23. 5 V and 12 V current monitor gain vs. load current
33
32
12 V channel
5 V channel
31
30
29
28
27
26
0.00
0.50
2.50
3.00
1.00
1.50
I
OUT current (A)
2.00
STEF512SRX
Typical characteristics
Figure 20. SAS disable pin threshold vs. temperature
1.8
1.6
1.4
VIL
VIH
1.2
1.0
0.8
0.6
0.4
0.2
-50 -25 0 25 50
Temperature [ºC]
75 100 125 150
Figure 22. Current monitor gain vs. temperature
I
OUT_12
= I
OUT _ 5
= 500 mA
34.0
33.0
32.0
31.0
30.0
29.0
28.0
27.0
26.0
25.0
24.0
-50 -25 0 25 50
Temperature [ºC]
75 100
Ai_12
Ai_5
125 150
Figure 24. Startup via input voltage
DS13826 - Rev 1 page 14/27
Figure 25. Startup via input voltage (Hot-plug) 5 V
STEF512SRX
Typical characteristics
Figure 26. Startup via input voltage (Hot-plug) 12 V
Figure 27. Startup via input voltage (Hot-plug) 5 V & 12 V Figure 28. Startup via EN_N signal
Figure 29. Shutdown via EN_N signal Figure 30. Startup into voltage clamp (5 V eFuse)
DS13826 - Rev 1 page 15/27
Figure 31. Startup into voltage clamp (12 V eFuse)
STEF512SRX
Typical characteristics
Figure 32. Voltage clamp during operation (5 V eFuse)
Figure 33. Voltage clamp during operation (12 V eFuse)
Figure 34. Startup into output short-circuit by EN_N
(5 V eFuse)
Figure 35. Startup into output short-circuit by EN_N
(12 V eFuse)
Figure 36. Startup into overload (5 V eFuse)
DS13826 - Rev 1 page 16/27
Figure 37. Startup into overload (12 V eFuse)
STEF512SRX
Typical characteristics
Figure 38. Overcurrent protection during operation
(5 V eFuse)
Figure 39. Overcurrent protection during operation
(12 V eFuse)
Figure 40. PLP protection through UVLO_5
Figure 41. Current monitor response time to load step Figure 42. Current monitor response time to channel switch via I
MON-SEL
DS13826 - Rev 1 page 17/27
8
8.1
STEF512SRX
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DFN10 (2 x 3 mm) package information
Figure 43. DFN10 (2 x 3 mm) package outline
BOTTOM VIEW
SIDE VIEW
TOP VIEW
DS13826 - Rev 1 page 18/27
DS13826 - Rev 1
Dim.
E
L1
D e
L2
L3
A
A1
A3 b
K
N aaa bbb ccc ddd eee
STEF512SRX
DFN10 (2 x 3 mm) package information
Table 6. DFN10 (2 x 3 mm) mechanical data
Min.
0.70
0.00
0.180
0.60
0.40
0.45
0.20
mm
Typ.
0.75
0.02
0.203 ref.
0.230
3.00 BSC
0.50 BSC
2.00 BCS
0.70
0.50
0.55
10
0.05
0.10
0.10
0.05
0.08
Figure 44. DFN10 (2 x 3 mm) recommended footprint
Max.
0.80
0.05
0.280
0.80
0.60
0.65
page 19/27
8.2
DFN10 (2 x 3) carrier tape information
Figure 45. Carrier tape information
STEF512SRX
DFN10 (2 x 3) carrier tape information
Figure 46. Marking information
DS13826 - Rev 1 page 20/27
Figure 47. Reel drawing
STEF512SRX
DFN10 (2 x 3) carrier tape information
DS13826 - Rev 1 page 21/27
9
Ordering information
Order code
STEF512SRXCPUR
Table 7. Order codes
Package
DFN10 (2 x 3 mm)
STEF512SRX
Ordering information
Marking
EXC
DS13826 - Rev 1 page 22/27
Revision history
Date
31-Jan-2022
Revision
1
Table 8. Document revision history
Changes
Initial release.
STEF512SRX
DS13826 - Rev 1 page 23/27
STEF512SRX
Contents
Contents
DS13826 - Rev 1 page 24/27
STEF512SRX
List of tables
List of tables
DS13826 - Rev 1 page 25/27
STEF512SRX
List of figures
List of figures
Figure 4. Typical start-up sequence (Enable after V
rise). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Typical start-up sequence (Enable during V
rise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 42. Current monitor response time to channel switch via I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DS13826 - Rev 1 page 26/27
STEF512SRX
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
DS13826 - Rev 1 page 27/27
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