STMicroelectronics STEF05L Datasheet
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STEF05L
STEF05L
Electronic fuse for 5 V line
Features
• Continuous current typ.: 3.6 A (DFN), 2.5 A (Flip Chip)
• N-channel on resistance (typ): 40 mΩ (DFN), 25 mΩ (Flip Chip)
• Enable/Fault functions
• Output clamp voltage (typ.): 6.1 V
• Undervoltage lockout
• Short-circuit limit
• Overload current limit
• Controlled output voltage ramp
• Thermal latch (typ): 160 °C
• Uses tiny capacitors
• Latching and auto-retry versions
• Operative junction temp. - 40 °C to 125 °C
• Available in DFN10 (3 x 3 mm) and Flip Chip 9 bumps
Applications
• Hard disk drives
• Solid state drives (SSD)
• Hard disk and SSD arrays
• Computer
• DVD and Blu-Ray disc drivers
Description
The STEF05L is an integrated electronic fuse optimized for monitoring output current and the input voltage. Connected in series to the 5 V rail, it is able to protect the electronic circuitry on its output from overcurrent and overvoltage. The STEF05L has controlled delay and turn-on time. When an overload condition occurs, the device limits the output current to a predefined safe value. If the anomalous overload condition persists, it goes into an open state, disconnecting the load from the power supply. If a continuous short-circuit is present on the board, when the power is re-applied the eFuse initially limits the output current to a safe value and then goes again into the open state. The voltage clamping circuit prevents the output voltage from exceeding a fixed value, if the input voltage goes beyond this threshold. The device is equipped with a thermal protection circuit. Intervention of thermal protection is signaled to the board-monitoring circuits through an appropriate signal on the
Fault pin. Unlike mechanical fuses, which must be physically replaced after a single event, the eFuse does not degrade in its performances following short-circuit/thermal protection intervention and is reset either by re-cycling the supply voltage or using the appropriate Enable pin. The STEF05L is also available in an autoretry version; in case of thermal fault it automatically attempts to re-apply power to the load when the die temperature returns to a safe value.
DS11527 - Rev 2 - December 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
1
Device block diagram
Figure 1. Block diagram
STEF05L
Device block diagram
DS11527 - Rev 2 page 2/25
STEF05L
Pin configuration
2
Pin configuration
Figure 2. Pin configuration
A B C
1
2
3
4
5 exp pad
10
9
8
7
6
3
2
1
Pin n°
DFN10 (3 x 3 mm)
1, 2, 3, 4, 5
6
7
Pin n°
Flip Chip 9
C1, C2, C3
N.C.
A1
8
9
10
Exposed pad
A2
N.C.
A3
B1, B2, B3
DFN10 (3 x 3mm)
(top view)
Flip Chip 9
(marking view)
GIPD040220161119MT
Table 1. Pin description
Symbol Note
V
OUT
/source
I-lim -
I-lim +
En/Fault dv/dt
GND
V
CC
Connected to the source of the internal power MOSFET and to the output terminal of the eFuse.
A resistor between these two pins sets the overload and short-circuit current limit levels. On the Flip Chip the resistor must be connected between the I-Lim+ and
Source pins.
The Enable/Fault pin is a tri-state, bi-directional interface. During normal operation the pin must be left floating, or it can be used to disable the output of the device by pulling it to ground using an open drain or open collector device. If a thermal fault occurs, the voltage on this pin goes into an intermediate state to signal a monitor circuit that the device is in thermal shutdown. It can be connected to another device of this family to cause a simultaneous shutdown during thermal events.
The internal dv/dt circuit controls the slew rate of the output voltage at turn-on. The internal capacitor allows a ramp-up time of around 1.4 ms. An external capacitor can be added to this pin to increase the ramp time. If an additional capacitor is not required, this pin should be left open. This feature is not available on the Flip Chip version.
Ground pin.
Exposed pad.
Positive input voltage must be connected to V
CC
.
DS11527 - Rev 2 page 3/25
STEF05L
Maximum ratings
3
Maximum ratings
Table 2. Absolute maximum ratings
Symbol
V
CC
V
OUT
/Source
I-Lim+/I-Lim-
En/Fault dv/dt
T
OP
T
STG
T
LEAD
Positive power supply voltage
V
OUT
pin voltage
V
OUT
pin voltage (100 ms)
Current limit pin voltage
Current limit pin voltage (100 ms)
Enable/Fault pin voltage dv/dt pin voltage
Parameter
Operating junction temperature range
Storage temperature range
Lead temperature (soldering) 10 sec
Value
-0.3 to 10
-0.3 to 7
- 0.3 to V
CC
+ 0.3
-0.3 to 7
- 0.3 to V
CC
+ 0.3
-0.3 to 4.6
-0.3 to 4.6
- 40 to 125
- 65 to 150
260
1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures greater than the maximum ratings for extended periods of time.
Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
Unit
V
V
V
°C
°C
V
V
°C
Symbol
V
CC
R
Limit
C dv/dt
V
EN
Table 3. Recommended operating condition
Parameter
Positive power supply voltage
Current sense resistor range, STEF05L, STEF05LA
Current limitation resistor range, STEF05LJ, STEF05LAJ
Soft-start capacitor range
Enable/Fault pin voltage
Value
4.5 to 8
10 to 120
15 to 120
0 to 1
0 to 3.6
Unit
V
Ω nF
V
Symbol
R thJA
R thJC
Table 4. Thermal data
Parameter
Thermal resistance junction-ambient, DFN10 (3 x 3 mm)
Thermal resistance junction-ambient, Flip Chip 9
Thermal resistance junction-case, DFN10 (3 x 3 mm)
Value
70
90
34
Unit
°C/W
Symbol
ESD
Parameter
ESD protection
Table 5. ESD performance
Test conditions
HBM
MM
CDM DFN10 (3 x 3 mm)
CDM (Flip Chip 9)
Value
4
400
500
250
Unit kV
V
V
V
DS11527 - Rev 2 page 4/25
STEF05L
Electrical characteristics
4
Electrical characteristics
V
CC
= 5 V, C
I
= 10 μF, C
O
=10 μF, T
J
= 25 °C (unless otherwise specified).
Symbol Parameter
Under/over voltage protection
V
Clamp
V
UVLO
Output clamping voltage
Under voltage lockout
V
Hyst
UVLO hysteresis
Power MOSFET
R
V t
I dly
DSon
OFF
D
Table 6. Electrical characteristics
V
CC
= 8 V
Test conditions
Turn-on, voltage increasing
Delay time
ON resistance (DFN package)
Off state output voltage
Continuous current
ON resistance (Flip Chip package)
Enabling of chip to V
OUT nominal value
= 10 % of
I
OUT
= 500 mA, T
J
= 25 °C
I
OUT
= 500 mA, -40 °C < T
J
< 125 °C
I
OUT
= 500 mA, T
J
= 25 °C
I
OUT
= 500 mA, -40 °C < T
J
< 125 °C
V
EN
= GND, R
L
= infinite
DFN package
Flip Chip package
Current limit
I
Short
Short-circuit current limit
I
Lim dv/dt circuit
Overload current limit
R
Limit
= 24 Ω, DFN package
R
Limit
= 24 Ω, Flip Chip package
R
Limit
= 24 Ω
dv/dt Output voltage ramp time
V
OUT
= 10 % to 90 % of nominal voltage, No C dv/dt
Enable/Fault
V
IL
V
I(INT)
V
IH
V
I(MAX)
I
IL
Low level input voltage
Intermediate level input voltage
High level input voltage
High state maximum voltage
Low level input current (sink)
Maximum fan-out for fault signal
Output disabled
Thermal fault, output disabled
Output enabled
V
Enable
= GND
Total number of chips that can be connected to this pin for simultaneous
Total device
I
Bias
Bias current
Device operational
Thermal shutdown (only on latching
Device disabled (V
EN
= GND)
Min.
5.5
3.1
0.8
1.1
0.8
0.8
2.5
1.4
0.7
0.5
0.35
1.4
3.25
-28
3.6
2.5
1.2
1.5
2.5
500
40
30
Typ.
6.1
3.4
0.1
Max.
6.8
4.0
Unit
V
V
V
60
70
50
70
100
1.6
1.9
2.5
0.5
2
-50
3
2
A
A ms mA
V
µA
V
V
V
Units
µs mΩ mΩ mV
A
DS11527 - Rev 2 page 5/25
Symbol
Thermal latch
Parameter Test conditions
TSD
Shutdown temperature
Hysteresis
Only on auto-retry versions
1. Pulse test.
2. Guaranteed by design, but not tested in production.
STEF05L
Electrical characteristics
Min.
Typ.
160
25
Max.
Unit
°C
DS11527 - Rev 2 page 6/25
5
STEF05L
Typical application
Typical application
Figure 3. Application circuit, STEF05L and STEF05LA (DFN10 (3 x3 mm) package)
GIPD040220161423MT
Figure 4. Application circuit with Kelvin current sensing, STEF05LJ and STEF05LAJ (Flip-Chip 9 bump package)
5.1
5.1.1
5.1.2
GIPD040220161425MT
Operating modes
Turn-on
When the input voltage is applied, the Enable/Fault pin goes up to the high state, enabling the internal control circuitry.
After an initial delay time of typically 500 ms, the output voltage is supplied with a slope defined by the internal dv/dt circuitry. If no additional capacitor is connected to dv/dt pin, the total time from the Enable signal going high and the output voltage reaching the nominal value is around 1.6 ms (refer to
Normal operating condition
The STEF05L eFuse behaves like a mechanical fuse, buffering the circuitry on its output with the same voltage shown at its input, with a small voltage fall due to the N-Channel MOSFET R
DSOn
.
DS11527 - Rev 2 page 7/25
5.1.3
5.1.4
5.1.5
5.2
5.3
STEF05L
RLimit calculation
Output voltage clamp
This internal protection circuit clamps the output voltage to a maximum safe value, typically 6.1 V, if the input voltage exceeds this threshold.
Current limiting
When an overload event occurs, the current limiting circuit reduces the conductivity of the power MOSFET, in order to clamp the output current at the value selected externally by means of the limiting resistor R
Limit
( Figure 3. Application circuit, STEF05L and STEF05LA (DFN10 (3 x3 mm) package) ).
Thermal shutdown and auto-retry function
If the device temperature exceeds the thermal latch threshold, typically 160 °C, the thermal shutdown circuitry turns the power MOSFET off, thus disconnecting the load. The EN/Fault pin of the device is automatically set to an intermediate voltage, in order to signal the overtemperature event.
The STEF05L latch version can be reset from this condition either by cycling the supply voltage or by pulling down the EN pin below the V il
threshold and then releasing it.
On the STEF05LA auto-retry version, the power MOSFET will remain in an OFF state until the die temperature drops below the hysteresis value. Once this happens, the internal autoretry circuit attempts to reset the device, pulling up the EN/Fault pin to the operative value.
R
Limit
calculation
monitor the output current and limit it at the level set by the user.
The R
Limit
value for achieving the requested current limitation can be estimated by using the “current limit vs
R
Limit
”, graph in
The device has two levels of current limitation, depending on the load condition.
The short-circuit current limit (I
Short
) is the current level that is imposed when the output voltage decreases sharply, as in the case of a short-circuit on the output.
The overload current limit (I
Lim
), also described as “current limit trip-point”, represents the current level that is recognized by the device as an overload condition. Following this, the current limit trip point is reached the device enters into current limitation, and the current to the load is limited to the I
Short
value, which is generally lower than the trip-point value.
The overload current limit (I
Lim
) is dependent on the device reaction time, so it is influenced by the load current slew-rate. The faster the current increase, the higher the current limit trip point.
C
dv/dt
calculation
The device includes a rise-time control circuit, allowing the soft-start during turn-on and Hotplug of the equipment.
The pre-programmed rise time, defined as the time interval during which the output voltage goes from 10 % to
90 % of the nominal voltage, is typically 1.4 ms.
The STEF05L and STEF05LA in DFN10 package feature a user-programmable output voltage ramp-up time; by connecting a capacitor between the C dv/dt
pin and GND, modification of the output voltage ramp-up time is possible. The capacitance to be added on the C dv/dt
pin can be selected using the following table.
Table 7. Typical rise time values vs dv/dt capacitor
C dv/dt
Rise time [ms]
None
1.4
1. V
CC
= 5 V, C
IN
= 10 μF, C
OUT
= 10 μF, R
LIMIT
= 24 Ω, I
OUT
= 1 A.
100 pF
2.8
470 pF
8
1 nF
16
DS11527 - Rev 2 page 8/25
Figure 5. Delay time and V
OUT
rise time
STEF05L
Enable-Fault pin
5.4
GIPD080220161046MT
Enable-Fault pin
The Enable/Fault pin has the dual function of controlling the output of the device and, at the same time, of providing information about the device status to the application.
It can be connected to an external open-drain or open-collector device. In this case, when it is pulled at low logic level, it will turn the output of the eFuse off.
If this pin is left floating, since it has internal pull-up circuitry, the output of the eFuse is kept ON in normal operating conditions.
This pin should never be biased to a voltage higher than 3.6 V.
In case of thermal fault, the pin is pulled to an intermediate state (
Figure 6. Enable/Fault pin status
). This signal can be provided to a monitor circuit, signaling that a thermal shutdown has occurred, or it can be directly connected to the Enable/Fault pins of other STEFxx devices on the same application, in order to achieve a simultaneous enable/disable feature.
When a thermal fault occurs, the device can be reset either by cycling the supply voltage or by pulling down the
Enable pin below the V il
threshold and then releasing it.
DS11527 - Rev 2 page 9/25
DS11527 - Rev 2
Figure 6. Enable/Fault pin status
STEF05L
Enable-Fault pin
GIPD080220161207MT page 10/25
6
STEF05L
Typical performance characteristics
Typical performance characteristics
The following plots are referred to the typical application circuit and, unless otherwise noted, at T
A
= 25 °C.
Figure 7.
8
7
6
5
4
3
2
1
0
-40
Clamping voltage vs temperature
-25 0 25 55 85
V
CC
= 8 V
125
GIPD190220160931MT
1
0.5
0
2
1.5
2.5
3
Figure 8. Short-circuit current vs temperature
Vcc = 5 V, R - limit = 24 Ω, flip-chip package
-40 -25 0 25 55 85 125
GIPD190220160932MT
Figure 9. Bias current vs temperature (device operational)
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Vcc = 5 V, V
-40 -25
EN
= floating
0 25 55 85 125
GIPD190220160933MT
Figure 10. Bias current vs temperature (device disabled)
1.4
1.2
1
0.8
0.6
2
1.8
1.6
0.4
0.2
0
Vcc = 5 V, V
-40 -25
EN
= GND
0 25 55 85 125
GIPD190220160934MT
DS11527 - Rev 2 page 11/25
DS11527 - Rev 2
STEF05L
Typical performance characteristics
Figure 11. ON resistance vs temperature
70
60
50
40
30
20
10
0
-40
Vcc = 5 V, DFN10 package
-20 0 20 40 60 80 100
Iout 500 mA
Iout 1 A
Iout 2 A
Iout 4 A
120 140
GIPD190220160935MT
3
2
1
0
0
6
Figure 12. Current limit vs R
Limit
(I
OUT
ramp)
5
Ishort
Ilimit
4
20 40 60 80
External sensing resistor (Ω)
100 120 140
GIPD190220160936MT
Figure 13. V
OUT
ramp-up vs enable (NO C dvdt
) Figure 14. V
OUT
ramp-up vs enable (C dvdt
= 470 pF)
Figure 15. V
OUT
turn-on vs enable Figure 16. V
OUT
turn-off vs enable page 12/25
Figure 17. Startup (slow rising)
STEF05L
Typical performance characteristics
Figure 18. Startup and voltage clamp
Figure 19. Startup into output short-circuit Figure 20. Voltage clamp
DS11527 - Rev 2 page 13/25
7
STEF05L
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DS11527 - Rev 2 page 14/25
7.1
STEF05L
DFN10 (3x3 mm) package information
DFN10 (3x3 mm) package information
Figure 21. DFN10 (3x3 mm) package outline
DS11527 - Rev 2
7426335_L page 15/25
DS11527 - Rev 2
Dim.
D
D2
E
E2
E3
E4 e
L ddd
A
A1
A2
A3 b
Table 8. DFN10 (3x3 mm) mechanical data
Min.
0.80
0.18
2.85
2.23
2.85
1.49
0.230
0.365
mm
Typ.
0.90
0.02
0.70
0.20
0.23
3.00
2.38
3.00
1.64
0.30
0.50
0.40
STEF05L
DFN10 (3x3 mm) package information
Max.
1.00
00.5
0.30
3.15
2.50
3.15
1.75
0.50
0.08
Figure 22. DFN10 (3x3 mm) recommended footprint
7426335_L page 16/25
7.2
STEF05L
QFNxx/DFNxx (3 x 3 mm) package information
QFNxx/DFNxx (3 x 3 mm) package information
Figure 23. DFN10 (3x3 mm) tape and reel outline
DS11527 - Rev 2
Dim.
T
Ao
Bo
Ko
Po
P
A
C
D
N
Table 9. DFN10 (3x3 mm) tape and reel mechanical data
Min.
mm
Typ.
12.8
20.2
60
3.3
3.3
1.1
4
8
Max.
330
13.2
18.4
page 17/25
7.3
Flip Chip 9 package information
Figure 24. Flip Chip 9 package outline
STEF05L
Flip Chip 9 package information
DS11527 - Rev 2
Dim.
A
A1
A2 b
D
Table 10. Flip Chip 9 mechanical data
Min.
0.50
0.17
0.33
0.23
1.16
mm
Typ.
0.55
0.20
0.35
0.25
1.19
7504895_M
Max.
0.60
0.23
0.37
0.29
1.22
page 18/25
DS11527 - Rev 2
Dim.
D1
E
E1 e f ccc
Min.
1.16
mm
Typ.
0.8
1.19
0.8
0.40
0.195
0.075
Figure 25. Flip Chip 9 recommended footprint
0.8
0.4
0.4
Grid placemente area
C
B
A
3 2 1 Ø
0.8
0.22
STEF05L
Flip Chip 9 package information
Max.
1.22
page 19/25
STEF05L
Ordering information
8
Ordering information
Tape and reel
STEF05LPUR
STEF05LJR
STEF05LAPUR
STEF05LAJR
Table 11. Order code
Package
DFN10 (3 x 3 mm)
Flip Chip 9
DFN10 (3 x 3 mm)
Flip Chip 9
Version
Latch
Latch
Auto-retry
Auto-retry
Marking
EF05L
5L
EF05LA
5A
DS11527 - Rev 2 page 20/25
Revision history
Date
04-Nov-2016
15-Dec-2020
Revision
1
2
Table 12. Document revision history
Changes
Initial release
Updated
STEF05L
DS11527 - Rev 2 page 21/25
STEF05L
Contents
Contents
DS11527 - Rev 2 page 22/25
STEF05L
List of tables
List of tables
DS11527 - Rev 2 page 23/25
STEF05L
List of figures
List of figures
DS11527 - Rev 2 page 24/25
STEF05L
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS11527 - Rev 2 page 25/25
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