STMicroelectronics STEF033 Datasheet
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STEF033
Electronic fuse for 3.3 V line
DFN10 (3 x 3 mm) Flip Chip 9
Features
•
Continuous current typ.: 3.6 A (DFN), 2.5 A
(Flip Chip)
•
N-channel on resistance (typ): 40 m Ω (DFN),
25 m Ω (Flip Chip)
•
Enable/Fault functions
•
Output clamp voltage (typ): 4.5 V
•
Undervoltage lockout
•
Short-circuit limit
•
Overload current limit
•
Controlled output voltage ramp
•
Thermal latch (typ): 160 °C
•
Uses tiny capacitors
•
Latching and auto-retry versions
•
Operative junction temp. - 40 °C to 125 °C
•
Available in DFN10 3x3 and Flip Chip 9 bumps
Applications
•
Hard disk drives
•
Solid state drives (SSD)
•
Hard disk and SSD arrays
•
Computer
•
DVD and Blu-Ray disc drivers
Datasheet production data
Description
The STEF033 is an integrated electronic fuse optimized for monitoring output current and the input voltage. Connected in series to the 3.3 V rail, it is able to protect the electronic circuitry on its output from overcurrent and overvoltage. The
STEF033 has controlled delay and turn-on time.
When an overload condition occurs, the device limits the output current to a predefined safe value. If the anomalous overload condition persists, it goes into an open state, disconnecting the load from the power supply. If a continuous short-circuit is present on the board, when the power is re-applied the eFuse initially limits the output current to a safe value and then goes again into the open state. The voltage clamping circuit prevents the output voltage from exceeding a fixed value, if the input voltage goes beyond this threshold. The device is equipped with a thermal protection circuit. Intervention of thermal protection is signaled to the board-monitoring circuits through an appropriate signal on the Fault pin. Unlike mechanical fuses, which must be physically replaced after a single event, the eFuse does not degrade in its performances following short-circuit/thermal protection intervention and is reset either by re-cycling the supply voltage or using the appropriate Enable pin. The STEF033 is also available in an auto-retry version; in case of thermal fault it automatically attempts to reapply power to the load when the die temperature returns to a safe value.
November 2020
This is information on a product in full production.
DocID025099 Rev 4 1/25 www.st.com
Contents
Contents
STEF033
Normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal shutdown and Auto-retry function . . . . . . . . . . . . . . . . . . . . . . 10
calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DFN10 (3x3 mm) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 17
QFNxx/DFNxx (3x3 mm) packing information . . . . . . . . . . . . . . . . . . . . . 20
Flip Chip 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/25 DocID025099 Rev 4
STEF033
1 Device block diagram
Figure 1. STEF033 block diagram
Device block diagram
DocID025099 Rev 4 3/25
25
Pin configuration
2 Pin configuration
Figure 2. Pin configuration (top view)
STEF033
Table 1. Pin description
Pin n°
(DFN)
Pin n°
(Flip Chip)
Symbol Note
1,2,3,4,5 C1,C2,C3 V
OUT
/Source
Connected to the source of the internal power MOSFET and to the output terminal of the eFuse
6 N.C.
I-lim -
7
8
A1
A2
I-lim +
En/Fault
A resistor between these two pins sets the overload and short-circuit current limit levels. On the Flip Chip the resistor must be connected between the I-Lim+ and Source pins
The Enable/Fault pin is a tri-state, bi-directional interface. During normal operation the pin must be left floating, or it can be used to disable the output of the device by pulling it to ground using an open drain or open collector device. If a thermal fault occurs, the voltage on this pin goes into an intermediate state to signal a monitor circuit that the device is in thermal shutdown. It can be connected to another device of this family to cause a simultaneous shutdown during thermal events.
9 N.C.
A3 dv/dt
GND
The internal dv/dt circuit controls the slew rate of the output voltage at turn-on. The internal capacitor allows a ramp-up time of around 1.4 ms.
An external capacitor can be added to this pin to increase the ramp time.
If an additional capacitor is not required, this pin should be left open.
This feature is not available on the Flip Chip version.
Ground pin 10
Exposed pad
B1,B2,B3 V
CC
Exposed pad. Positive input voltage must be connected to V
CC
.
4/25 DocID025099 Rev 4
STEF033
3 Maximum ratings
Note:
Maximum ratings
Symbol
Table 2. Absolute maximum ratings
Parameter Value Unit
V
CC
Positive power supply voltage
V
OUT
/source
V
OUT
pin voltage
V
OUT
pin voltage (100 ms)
I-Lim+/I-Lim-
Current limit pin voltage
Current limit pin voltage (100 ms)
En/Fault Enable/Fault pin voltage
- 0.3 to 10
- 0.3 to 7
- 0.3 to Vcc+0.3
-0.3 to 7
V
V
V
- 0.3 to V
CC
+0.3
- 0.3 to 4.6
V dv/dt
T
OP
T
STG
T
LEAD dv/dt pin voltage
Operating junction temperature range
Storage temperature range
Lead temperature (soldering) 10 sec
(1)
- 0.3 to 4.6
- 40 to 125
- 65 to 150
260
V
°C
°C
°C
1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures greater than the maximum ratings for extended periods of time.
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Symbol
V
CC
R-limit
C
V dv/dt
EN
Table 3. Recommended operating conditions
Parameter
Positive power supply voltage
Current limitation resistor range, STEF033, STEF033A
Current limitation resistor range, STEF033J, STEF033JA
Soft-start capacitor range
Enable/Fault pin voltage
Value
3.1 to 8
10 to 120
15 to 120
0 to 1
0 to 3.6
Unit
V
Ω nF
V
Symbol
R thJA
R thJC
Table 4. Thermal data
Parameter
Thermal resistance junction-ambient, DFN10
Thermal resistance junction-ambient, Flip Chip
Thermal resistance junction-case, DFN10
Value
70
90
34
Unit
°C/W
DocID025099 Rev 4 5/25
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Maximum ratings
Symbol Parameter
Table 5. ESD performance
Test conditions
ESD ESD protection
HBM
MM
CDM (DFN10)
CDM (Flip Chip)
STEF033
Value
4
400
500
250
Unit kV
V
V
V
6/25 DocID025099 Rev 4
STEF033
4 Electrical characteristics
Electrical characteristics
V
CC
= 3.3 V, C
I
= 10 µF, C
O
=10 µF, T
J
= 25°C (unless otherwise specified)
Parameter
Table 6. Electrical characteristics
Test conditions Min.
Typ.
Symbol
Under/Over Voltage Protection
V
Clamp
V
UVLO
V
Hyst
Output clamping voltage
Under voltage Lockout
UVLO hysteresis
Power MOSFET
R
V t dly
DSon
I
OFF
D
V
CC
= 8 V
Turn-on, voltage increasing
Delay time
ON-resistance (DFN package)
(1)
ON resistance
(Flip Chip package)
(1)
Off-state output voltage
Continuous current
Enabling of chip to V
OUT
=10% of nominal value
I
OUT
= 500 mA, T
J
= 25 °C
I
OUT
= 500 mA,
-40 °C<T
J
<125 °C
I
OUT
= 500 mA, T
J
= 25 °C
I
OUT
= 500 mA,
-40 °C<T
J
<125 °C
V
EN
=GND, R
L
=infinite
DFN package
Flip Chip package
Current limit
I
Short
I
Lim dv/dt circuit
Short-circuit current limit
Overload current limit
R
R
Limit
Limit
= 24 Ω
= 24
Ω (2) dv/dt Output voltage ramp time
V
OUT
= 10% to 90% of nominal voltage, no C dv/dt
Enable/Fault
V
V
I(INT)
V
IL
IH
V
I(MAX)
I
IL
Low level input voltage Output disabled
(2)
Intermediate level input voltage Thermal fault, output disabled
(2)
High level input voltage
High state maximum voltage
Low level input current (sink)
Maximum fan-out for fault signal
Output enabled
V
Enable
= GND
Total number of chips that can be connected to this pin for simultaneous shutdown
(2)
4
2.15
1
0.8
0.8
2.5
4.5
2.35
0.1
500
40
30
3.6
2.5
1.35
2.5
1.4
1.4
3.25
-28
Max.
Unit
5
2.5
µs
60
70
50
70
100 m
Ω m Ω mV
A
1.75
2.5
0.5
2
-50
3
V
V
V
A
A ms
V
V
V
V
µA
Units
DocID025099 Rev 4 7/25
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Electrical characteristics STEF033
Symbol
Table 6. Electrical characteristics (continued)
Parameter Test conditions
Total device
I
Bias
Bias current
Device operational
Thermal shutdown (only on latching versions)
(2)
Device disabled (V
EN
= GND)
Thermal latch
TSD
Shutdown temperature
Hysteresis
(2)
Only on auto-retry versions
(2)
1. Pulse test
2. Guaranteed by design, but not tested in production
Min.
Typ.
Max.
Unit
0.6
0.5
0.35
160
25
2 mA
°C
8/25 DocID025099 Rev 4
STEF033
5 Typical application
Typical application
Figure 3. Application circuit, STEF033 and STEF033A (DFN10 package)
Figure 4. Application circuit with Kelvin current sensing, STEF033J and STEF033JA
(Flip Chip 9 bump package)
5.1
5.1.1
Operating modes
Turn-on
When the input voltage is applied, the Enable/Fault pin goes up to the high state, enabling the internal control circuitry.
After an initial delay time of typically 500 µ s, the output voltage is supplied with a slope defined by the internal dv/dt circuitry. If no additional capacitor is connected to dv/dt pin, the total time from the Enable signal going high and the output voltage reaching the nominal
value is around 1.6 ms (refer to Figure 5
, and
).
DocID025099 Rev 4 9/25
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Typical application
5.1.2
5.1.3
5.1.4
5.1.5
STEF033
Normal operating condition
The STEF033 eFuse behaves like a mechanical eFuse, buffering the circuitry on its output with the same voltage shown at its input, with a small voltage fall due to the N-channel
MOSFET R
DS(on)
.
Output voltage clamp
This internal protection circuit clamps the output voltage to a maximum safe value, typically
4.5 V, if the input voltage exceeds this threshold.
Current limiting
When an overload event occurs, the current limiting circuit reduces the conductivity of the power MOSFET, in order to clamp the output current at the value selected externally by means of the limiting resistor R
Limit
(
Thermal shutdown and Auto-retry function
If the device temperature exceeds the thermal latch threshold, typically 160 °C, the thermal shutdown circuitry turns the power MOSFET off, thus disconnecting the load. The EN/Fault pin of the device is automatically set to an intermediate voltage, in order to signal the overtemperature event.
The STEF033 latch version can be reset from this condition either by cycling the supply voltage or by pulling down the EN pin below the V il
threshold and then releasing it.
On the STEF033A auto-retry version, the power MOSFET will remain in an OFF state until the die temperature drops below the hysteresis value. Once this happens, the internal autoretry circuit attempts to reset the device, pulling up the EN/Fault pin to the operative value.
5.2 R
Limit calculation
As shown in
Figure 1 the device uses an internal N-channel Sense FET with a fixed ratio, to
monitor the output current and limit it at the level set by the user.
The R
Limit
value for achieving the requested current limitation can be estimated by using the
“Current limit vs R
Limit
The device has two levels of current limitation, depending on the load condition.
The short-circuit current limit (I
Short
) is the current level that is imposed when the output voltage decreases sharply, as in the case of a short-circuit on the output.
The overload current limit (I
Lim
), also described as “Current limit trip-point”, represents the current level that is recognized by the device as an overload condition. Following this, the current limit trip point is reached the device enters into current limitation, and the current to the load is limited to the I
Short
value, which is generally lower than the trip-point value.
The overload current limit (I
Lim
) is dependent on the device reaction time, so it is influenced by the load current slew-rate. The faster the current increase, the higher the current limit trip point.
10/25 DocID025099 Rev 4
STEF033
5.3
Typical application
C dv/dt
calculation
The device includes a rise-time control circuit, allowing the soft-start during turn-on and Hotplug of the equipment. The pre-programmed rise time, defined as the time interval during which the output voltage goes from 10% to 90% of the nominal voltage, is typically 1.4 ms.
The STEF033 and STEF033A in DFN10 package feature a user-programmable output voltage ramp-up time; by connecting a capacitor between the C dv/dt
pin and GND, modification of the output voltage ramp-up time is possible. The capacitance to be added on the C dv/dt
pin can be selected using the following table.
Table 7. Typical rise time values vs. dv/dt capacitor
Rise time
(1)
C dv/dt
[ms] none
1.4
100 pF
2.8
1. V
CC
= 3.3 V, C
IN
= 10 µF, C
OUT
= 10 µF, R
LIMIT
= 24
Ω,
I
OUT
= 1 A
470 pF
8
1 nF
16
Figure 5. Delay time and V
OUT
rise time
V
OUT
Enable
90%
10%
delay time
rise time
5.4 Enable-Fault pin
The Enable/Fault pin has the dual function of controlling the output of the device and, at the same time, of providing information about the device status to the application.
It can be connected to an external open-drain or open-collector device. In this case, when it is pulled at low logic level, it will turn the output of the eFuse off.
If this pin is left floating, since it has internal pull-up circuitry, the output of the eFuse is kept
ON in normal operating conditions.
This pin should never be biased to a voltage higher than 3.6 V.
In case of thermal fault, the pin is pulled to an intermediate state ( Figure 6
). This signal can be provided to a monitor circuit, signaling that a thermal shutdown has occurred, or it can be
DocID025099 Rev 4 11/25
25
Typical application STEF033 directly connected to the Enable/Fault pins of other STEFxx devices on the same application, in order to achieve a simultaneous enable/disable feature.
When a thermal fault occurs, the device can be reset either by cycling the supply voltage or by pulling down the Enable pin below the V il
threshold and then releasing it.
Figure 6. Enable/Fault pin status
5
4
Normal operating condition
3
2
Thermal fault condition
1
0
Off/Reset
time
AM17209v1
12/25 DocID025099 Rev 4
STEF033
6
Typical performance characteristics
Typical performance characteristics
The following plots are referred to the typical application circuit and, unless otherwise noted, at T
A
= 25 °C.
Figure 7. Clamping voltage vs. temperature
AM17210v1
8
V
C C
= 6 V
7
4
3
2
1
0
6
5
-40 -25 0 25 55
Temperature [ºC]
85 125
Figure 8. Short-circuit current vs. temperature
AM17211v1
3
2.5
2
1.5
1
0.5
0
V
CC
= 3.3 V, R- limit = 24 Ω
-40 -25 0 25
Temperature [ °C]
55 85 125
Figure 9. Bias current vs. temperature (device operational)
Figure 10. Bias current vs. temperature (device disabled)
9FF 99
( 1
IORDWLQJ 9FF 99
( 1
*1'
7HPSHUDWXUH>&@
40
30
20
10
0
-40
Figure 11. ON-resistance vs. temperature
AM17214v1
70
V cc = 3.3 V, R - limit = 5 Ω
60
50
-20 0 20 40 60
Temperature (°C)
80
Iout 500 mA
Iout 1 A
Iout 2 A
Iout 4 A
100 120 140
5
4
3
2
1
0
0
7HPSHUDWXUH>&@
Figure 12. Current limit vs. R
Limit
( I
OUT
ramp )
6
AM17215v1
20 40 60 80 100
External Sensing Resistor ( Ω )
ILIMIT
ISHORT
120 140
DocID025099 Rev 4 13/25
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Typical performance characteristics
Figure 13. V
OUT
ramp-up vs. enable
STEF033
Figure 14. V
OUT
ramp-up vs. enable
V
CC
= 3,3 V, I
OUT
= 1 A, C
NO C dv/dt
IN
= C
OUT
= 10 µF, R
Limit
= 24 Ω ,
Figure 15. V
OUT
turn-on vs. enable
V
CC
= 3.3 V, I
OUT
C dv/dt
= 1 A, C
= 470 pF
IN
= C
OUT
= 10 µF, R
Limit
= 24 Ω ,
Figure 16. V
OUT
turn-off vs. enable
V
CC
= 3.3 V, C
I
OUT
IN
= C
OUT
= 10 µF, R
Limit
= 24 Ω , NO C
= 1 A, Enable from GND to Floating dv/dt
,
Figure 17. Startup (slow rising)
V
CC
I
= 3.3 V, C
IN
= C
OUT
= 10 µF, R
Limit
= 24 Ω , NO C
OUT
= 1 A, Enable from Floating to GND dv/dt
,
Figure 18. Startup and voltage clam
V
CC
= from 0 to 3.3 V, C
C dv/dt
, I
OUT
= 1 A
IN
= C
OUT
= 10 µF, R
Limit
= 24 Ω , NO V
CC
= from 0 to 6 V, C
IN
C dv/dt
, I
OUT
= 1 A
= C
OUT
= 10 µF, R
Limit
= 24 Ω , NO
14/25 DocID025099 Rev 4
STEF033 Typical performance characteristics
Figure 19. Thermal latch from 2 A load to shortcircuit
Figure 20. Startup into output short-circuit
V
CC
= from 0 to 3.3 V, C
C dv/dt
, I
OUT
= 1 A
IN
= C
OUT
= 10 µF, R
Limit
= 24 Ω , NO
Figure 21. Voltage clamp
V
CC
= from 0 to 3.3 V, C
IN
V
OUT short to GND
= C
OUT
= 10 µF, R
Limit
= 24 Ω ,
Figure 22. Trip and short current (I
OUT
ramp)
V
CC
= from 3.3 to 6 V, C
I
OUT
= 1 A
IN
= C
OUT
=10 µF, R
Limit
= 24 Ω , V
CC
= from 0 to 3.3 V, C
IN
= C
OUT
= 10 µF, R
Limit
= 24 Ω
DocID025099 Rev 4 15/25
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Package information
7 Package information
STEF033
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
16/25 DocID025099 Rev 4
STEF033
7.1 DFN10 (3x3 mm) package information
Figure 23. DFN10 (3x3 mm) outline
Package information
DocID025099 Rev 4
@-
17/25
25
Package information
Dim.
E
E2
E3
E4 e
L ddd
A3 b
D
D2
A
A1
A2
Table 8. DFN10 (3x3 mm) mechanical data mm
Typ.
0.90
0.02
0.70
0.20
0.23
3.00
2.38
3.00
1.64
Min.
0.80
0.18
2.85
2.23
2.85
1.49
0.230
0.365
0.50
0.40
0.30
STEF033
Max.
1.00
00.5
0.30
3.15
2.50
3.15
1.75
0.50
0.08
18/25 DocID025099 Rev 4
STEF033 Package information
Figure 24. DFN10 (3x3 mm) recommended footprint
@-
DocID025099 Rev 4 19/25
25
Package information
7.2 QFNxx/DFNxx (3x3 mm) packing information
Figure 25. QFNxx/DFNxx (3x3 mm) tape and reel outline
STEF033
20/25
N
T
Ao
Bo
A
C
D
Ko
Po
P
Table 9. QFNxx/DFNxx (3x3 mm) tape and reel mechanical data mm
Dim.
Min.
Typ.
Max.
330
13.2
12.8
20.2
60
3.3
3.3
1.1
4
8
18.4
DocID025099 Rev 4
STEF033
7.3 Flip Chip 9 package information
Figure 26. Flip Chip 9 package outline
Package information
7504895_K
DocID025099 Rev 4 21/25
25
Package information
Dim.
b
D
D1
E
A
A1
A2
E1 e f ccc
Table 10. Flip Chip 9 mechanical data mm
Min.
0.50
0.17
0.33
0.23
1.16
1.16
Typ.
0.55
0.20
0.35
0.25
1.19
0.8
1.19
0.8
0.40
0.195
0.075
Figure 27. Flip Chip 9 recommended footprint (dimensions in mm)
Max.
0.60
0.23
0.37
0.29
1.22
1.22
STEF033
22/25
&
%
$
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DocID025099 Rev 4
B.
STEF033
8 Order codes
Tape and reel
STEF033PUR
STEF033JR
(1)
STEF033APUR
STEF033AJR
(1)
1. Available on request.
Table 11. Order codes
Package Version
DFN
Flip Chip 9
DFN
Flip Chip 9
Latch
Latch
Auto-retry
Auto-retry
Order codes
Marking
EF03
33
EF03A
3A
DocID025099 Rev 4 23/25
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Revision history
9 Revision history
STEF033
Date
06-Aug-2013
28-Jan-2015
28-Jun-2020
24-Nov-2020
Revision
Table 12. Document revision history
Changes
1
2
3
4
Initial release.
Updated features in cover page, Figure 2: Pin configuration (top view) , Table 1: Pin description , Table 4: Thermal data , Table 5: ESD performance , Table 6: Electrical characteristics for STEF033 and
Section 7: Package information .
Minor text changes.
Text minor changes.
Updated Figure 9 and Figure 10 .
24/25 DocID025099 Rev 4
STEF033
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
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