STMicroelectronics STUSB1702 Datasheet
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STUSB1702
Datasheet
USB Type-C™ source controller with TX/RX line driver and BMC
Maturity status link
STUSB1702
Device summary
Order code
AEC-Q100
Package
Temp. range
Marking
STUSB1702YQTR
Yes
QFN24 EP 4x4 mm wettable flanks
- 40 °C up to 105 °C
1702Y
Features
• Type-C™ attach and cable orientation detection
• Power role support: source
• Integrated power switch for V
CONN
supply:
– programmable current limit up to 600 mA
– overcurrent, overvoltage, and thermal protection
– undervoltage lockout
• I²C interface and interrupt
• Integrated V
BUS
voltage monitoring
• Integrated V
BUS
and V
CONN
discharge path
• Integrated BMC transceiver
• V
BUS
switch gate driver
• Short-to-V
BUS
protection on CC pins (22 V) and V
BUS
pins (28 V)
• Accessory mode support
• Dual power supply (V
SYS
and/or V
DD
):
– V
SYS
= [3.0 V; 5.5 V]
– V
DD
= [4.1 V; 22 V]
• Temperature range: -40 °C up to 105 °C
• ESD: 4 kV HBM - 1.5 kV CDM
• AEC-Q100 qualified
• Compliant with:
– USB Type-C™ rev 1.2
– USB PD rev 2.0
• Compatible with:
– USB PD rev 3.0
Applications
• Car charger, car infotainment
• Smart plugs, wall adapters, and chargers
• Power hubs and docking stations
• Any Type-C source device
Description
The STUSB1702 is a generic IC, in a 20 V technology it addresses a USB Type-C™ port management on the host side. It is designed for a broad range of applications and can handle the following USB Type-C functions: attach detection, plug orientation detection, host to device connection, V
CONN
support, and V
BUS configuration.
It also provides a USB PD TX/RX line driver and BMC (bi-phase mark coding) transceiver which allow USB PD negotiation and an alternate mode through an external MCU.
DS12664 - Rev 1 - July 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STUSB1702
Functional description
Functional description
The STUSB1702 is a USB Type-C controller IC. It is designed to interface with the Type-C receptacle on host side. It is used to establish and manage the source-to-sink connection between two USB Type-C host and device ports.
The STUSB1702 major role is to:
1.
Detect the connection between two USB Type-C ports (attach detection)
2.
Establish a valid source-to-sink connection
3.
Determine the attached device mode
4.
Resolve cable orientation and twist connections to establish USB data routing (MUX control)
5.
Configure and monitor V
BUS
power path
6.
Manage V
BUS
power capability: USB default, Type-C medium or Type-C high current mode
7.
Configure V
CONN
when required
8.
Support USB PD negotiation
•
•
The STUSB1702 also provides:
• Low power standby mode
•
I²C interface and interrupt
Start-up configuration customization: static through NVM and/or dynamic through I²C
High voltage protection
• Accessory mode detection
Figure 1. Functional block diagram
VREG_1V2 VDD VSYS GND VREG_2V7 RESET
CC1GND
CC1
VCONN
CC2
CC2GND
VDD1V2
VREG_1V2
Power Supply
Generation
VPU
VREG_2V7
I2C_REGx
VPU
Power On
Reset
Controller
Oscillator NVM
I2C Interface
&
Registers
RESET
I2C_REGx
VDD2V7 RESET CLK I2C_REGx
VCONN Monitoring
& Power Switches
VBUS Monitoring
& Control
CC Lines
Interface
BMC
Transceiver
BMC
Clock Recovery
Tx Enc. / Rx Dec.
CC Control
Logic
MISO TX_EN SCLK NSS MOSI
High voltage pins
SCL
SDA
ALERT#
VBUS_SENSE
VBUS_EN_SRC
A_B_SIDE
DS12664 - Rev 1 page 2/38
STUSB1702
Inputs / outputs
2
Inputs / outputs
2.1
Pinout
Figure 2. STUSB1702 pin connections
CC1GND
CC1
VCONN
CC2
CC2GND
RESET
4
5
2
3
1
24 23 22 21 20 19
18
17
16
EP
15
6
7 8 9 10
14
11 12
13
VBUS_SENSE
A_B_SIDE
SCLK
TX_EN
MISO
ADDR0
2.2
Pin list
8
9
10
11
6
7
Pin
1
2
3
4
5
12
Name
CC1GND
CC1
VCONN
CC2
CC2GND
RESET
SCL
SDA
ALERT#
GND
MOSI
NSS
Table 1. Pin functions list
DI
DI
DI/OD
OD
GND
DO
Type
GND
Description
Ground reference channel 1
HV AIO Type-C configuration channel 1
PWR Power input for active plug
HV AIO Type-C configuration channel 2
GND Ground reference channel 2
OD
Reset input (active high)
I²C clock input
I²C data input/output, active low open drain
I²C interrupt, active low open drain
Ground
Master out slave in: serial data from
STUSB1702 to MCU, BMC decoded from connected CC line
Chip select, open drain active low to control
MCU SPI/MSP interface
Ground
Typical connection
Type-C receptacle A5
5 V power source
Type-C receptacle B5
Ground
To I²C master, ext. pull-up
To I²C master, ext. pull-up
To I²C master, ext. pull-up
Ground
To MCU, ext. pull-up referenced to
MCU Vio
To MCU, ext. pull-up referenced to
MCU Vio
DS12664 - Rev 1 page 3/38
STUSB1702
Pin description
2.3
2.3.1
15
16
21
22
23
24
-
Pin
13
14
17
18
19
20
Name
ADDR0
MISO
TX_EN
SCLK
A_B_SIDE
VBUS_SENSE
NC
VBUS_EN_SRC
VREG_1V2
VSYS
VREG_2V7
VDD
EP
Type
DI
DI
DI
DO
Description
I²C device address setting (see Section 5 I²C interface )
Master in slave out: serial data from MCU to
STUSB1702 encoded in BMC to drive the CC line
TX enable, open drain active high to drive CC line from the embedded BMC interface
Static
Typical connection
From MCU, ext. pull-up referenced to MCU Vio
From MCU, needs to be maintained low by MCU or pulled down when receiving standby
Serial clock to clock data transfer between
MCU and the STUSB1702. Open drain output pin, needs external pull-up referenced to MCU
Vio
To MCU, ext. pull-up referenced to
MCU Vio
OD Cable orientation, active low open drain
HV AI V
BUS
voltage monitoring and discharge path From V
BUS
HV AIO Not connected Open
HV AIO V
BUS
source power path enable, active low open drain
USB super speed MUX select, ext.
pull-up
To switch or power system, ext.
pull-up
PWR
PWR
1.2 V internal regulator output
Power supply from system
PWR
HV PWR
GND
2.7 V internal regulator output
Main power supply from USB power line
Exposed pad is connected to ground
1 µF typ. decoupling capacitor
From power system, connect to ground if not used
1 µF typ. decoupling capacitor
From V
BUS
To ground
Type
O
I
D
A
IO
OD
PD
PU
HV
PWR
GND
Table 2. Pin function descriptions
Description
Digital
Analog
Output pad
Input pad
Bidirectional pad
Open drain output
Pull-down
Pull-up
High voltage
Power
Ground
Pin description
CC1 / CC2
CC1 and CC2 are the configuration channel pins used for connection and attachment detection, plug orientation determination and system configuration management across USB Type-C cable.
DS12664 - Rev 1 page 4/38
STUSB1702
Pin description
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10
Note:
CC1GND / CC2GND
CC1GND and CC2GND are used as a reference to ground and must be connected to ground.
VCONN
This power input is connected to a power source that can be a 5 V power supply. It is used to provide power to the local plug. It is internally connected to power switches that are protected against short-circuit and overvoltage.
This does not require any protection on the input side. When a valid source-to-sink connection is determined and the V
CONN
power switches are enabled, V
CONN
is provided by the source to the unused CC pin (see
RESET
Active high reset.
I²C interface pins
Name
SCL
SDA
ALERT#
ADDR0
Table 3. I²C interface pins list
Description
I²C clock – need external pull-up
I²C data – need external pull-up
I²C interrupt – need external pull-up
I²C device address bit (see Section 5 I²C interface
)
GND
Ground.
MOSI
Master out slave in: data from the connected CC line are decoded using the BMC and then transmitted via the
STUSB1702 to the MCU. Data are valid on the falling edge of the SCLK line and must be sampled by the MCU on this edge.
NSS
The chip select signal is driven by the STUSB1702 and is connected to the MCU. It activates the SPI/MSP interface transfer. The NSS signal drives the MCU so that:
•
•
When TX_EN is asserted (TX mode), the STUSB1702 transmits data from the MCU over the CC line. Note, the MCU must provide data to be encoded on the MISO line which must be in synchrony with the SCLK
When TX_EN is not asserted (RX mode, default), the CC line is activity detected, data are received, and the
BMC is decoded by the STUSB1702. Decoded data are sent on the MOSI line in synchrony with the SCLK
MISO
Master in slave out: data from the MCU are encoded using the BMC and then transmitted via the STUSB1702 to the connected CC line driver. Data are sampled by the STUSB1702 on the rising edge of the SCLK line and must be stable on this edge.
TX_EN
TX_EN is a control signal from the MCU to the STUSB1702. It enables the BMC control logic that transfers data from the MCU serial interface, encodes it in BMC format, and drives the connected CC line.
TX mode overrides RX mode.
DS12664 - Rev 1 page 5/38
STUSB1702
Pin description
2.3.11
2.3.12
2.3.13
2.3.14
2.3.15
2.3.16
2.3.17
2.3.18
SCLK
The serial clock signal from the STUSB1702 drives the SPI/MSP interface of the MCU and the clock data on the
MISO and MOSI pins.
A_B_SIDE
This output pin provides cable orientation. It is used to establish USB SuperSpeed signal routing. The cable orientation is also provided by an internal I²C register. This signal is not required in the case of USB 2.0 support.
Value
HiZ
0
Table 4. USB data MUX select
CC pin position
CC1 pin is attached to CC line
CC2 pin is attached to CC line
VBUS_SENSE
This input pin is used to sense V
BUS
presence, monitor V
BUS
voltage and discharge V
BUS
on USB Type-C receptacle side.
VBUS_EN_SRC
In source power role, this pin allows the outgoing V
BUS
power to be enabled when the connection to a sink is established and V
BUS
is in a valid operating range. The open drain output allows a PMOS transistor to be directly driven. The logic value of the pin is also advertised in a dedicated I²C register bit.
VREG_1V2
This pin is used only for external decoupling of 1.2 V internal regulator. The recommended decoupling capacitor is: 1 µF typ. (0.5 µF min.; 10 µF max.).
VSYS
This is the low power supply of the system, if there is any. It can be connected directly to a system power supply delivering 3.3 V or 5 V. It is recommended to connect this pin to ground when it is not used.
VREG_2V7
This pin is used for external decoupling of the 2.7 V internal regulator. The recommended decoupling capacitor is:
1 µF typ. (0.5 µF min., 10 µF max.).
VDD
This is the power supply from the USB power line for applications powered by V
BUS
.
In source power role, this pin can be used to sense the voltage level of the main power supply providing the V
BUS
It allows UVLO and OVLO thresholds to be considered independently on the VDD pin as additional conditions to
.
enable the V
BUS
power path through the VBUS_EN_SRC pin (see
When the UVLO threshold detection is enabled, the VDD pin must be connected to the main power supply to establish the connection and to assert the V
BUS
power path.
DS12664 - Rev 1 page 6/38
STUSB1702
General description
3
General description
3.1
3.2
CC interface
The STUSB1702 controls the connection to the configuration channel (CC) pins, CC1 and CC2, through two main blocks: the CC line interface block and the CC control logic block.
The CC line interface block is used to:
• Configure termination mode on the CC pins relative to the power mode supported i.e. pull-up for source power role
• Monitor the CC pin voltage values relative to the attachment detection thresholds
•
•
Configure V
CONN
on the unconnected CC pin when required
Protect the CC pins against overvoltage
•
•
•
•
•
•
The CC control logic block is used to:
• Execute the Type-C FSM relative to the Type-C power mode supported
Determine the electrical state for each CC pin relative to the detected thresholds
Evaluate the conditions relative to the CC pin states and the V
BUS to another in the Type-C FSM
voltage value to transition from one state
•
Detect and establish a valid source-to-sink connection
Determine the attached device mode
Determine cable orientation to allow external routing of the USB data
Manage V
BUS
power capability: USB default, Type-C medium or Type-C high current mode
Handle hardware faults
The CC control logic block implements the Type-C FSMs corresponding to the following Type-C power modes:
• Source power role with accessory support
The default Type-C power mode is selected through NVM programming (see
Section 6 Start-up configuration )
and can be changed by software during operation through the I²C interface.
BMC interface
Figure 3. BMC interface
3.2.1
BMC interface behavior
When a connection is established on the STUSB1702 (any attached state), the CC line used for connection is also internally connected to BMC block which allows the communication on this line.
The CC line is primary managed by CC control logic. BMC communication on the CC line must not interact with this control logic, as driving times of the line are short and are related to denounce times of the CC logic.
DS12664 - Rev 1 page 7/38
STUSB1702
VBUS power path control
3.2.2
3.2.3
3.3
3.3.1
BMC block handles BMC encoding and decoding. It also handles CC line activity detection, discharging the external MCU of such operations.
The default state of the BMC block is to listen to the line (RX mode). TX mode is enabled only by assertion of the
TX_EN signal via the external MCU.
TX mode
•
•
When the TX_EN signal is asserted via MCU, BMC block goes to the TX state:
•
•
•
NSS signal is driven low, indicating to the SPI/MSP slave interface of the MCU that data are being transmitted on the CC line. MCU provides the data
The STUSB1702 drives the NSS signal low, informing SPI/MSP slave interface of the MCU that data are requested on the MISO line
The STUSB1702 clocks the SCLK signal
MCU presents data to be transmitted on the MISO line and data are sampled on the rising edge of SCLK
(data must be stable on this edge)
Sampled data (from MISO line) are encoded by the BMC, and the resulting values drive the CC line according to USB PD standard
When all data are transmitted, MCU drives the TX_EN pin low, and lists the end of transmission. The STUSB1702 ends transmission with a corresponding trailing edge termination. It then goes back into to default state and releases the CC line from the BMC driver to the pull-up/pull-down CC line interfaces.
RX mode
•
•
RX mode is the default state of the BMC interface.
In this mode, the receiver listens to the connected CC line. It does not interface with the CC line interfaces or the
CC control logic.
When all data are detected and received on the CC line, according to the activity described in the USB Power
Delivery Standard, the BMC interface:
Drives NSS signal low
Outputs the clock on the SCLK signal which is recovered from the BMC signal
• Outputs recovered data (from the BMC signal) on the MOSI line to the connected MCU. Data are valid on the SCLK falling edge and are sampled on this edge by the SPI/MSP interface of MCU
When no more data are detected on the CC line, the NSS goes back to “high” which is its default state. This informs the MCU that no more activity is present on the bus.
VBUS power path control
VBUS monitoring
•
•
The V
BUS
monitoring block supervises from the VBUS_SENSE pin the V
BUS receptacle side.
voltage on the USB Type-C
It is used to check that the V
BUS
is within a valid voltage range:
To establish a valid source-to-sink connection according to USB Type-C standard specifications
To safely enable the VBUS power path through the VBUS_EN_SRC pin
It allows detection of unexpected V
BUS valid V
BUS
voltage conditions such as undervoltage or overvoltage relative to the
voltage range. When such conditions occur, the STUSB1702 reacts as follows:
• At attachment, it prevents the source-to-sink connection and the V
BUS
power path assertion
• After attachment, it deactivates the source-to-sink connection and disables the V
BUS
power path. In source power role, the device goes into error recovery state.
The V
BUS
voltage value is adjusted automatically at attachment (vSafe5V) and via MCU at each PDO transition.
Monitoring is then disabled during T_PDO_transition (i.e. the default value of 300 ms is changed through NVM programming). Additionally, if a transition occurs to a lower voltage, the discharge path is activated during this time.
DS12664 - Rev 1 page 8/38
STUSB1702
VBUS power path control
3.3.2
3.3.3
The valid V
BUS
voltage range is defined from the V
BUS
nominal voltage by a high threshold voltage and a low threshold voltage whose nominal values are respectively V
BUS
+5% and V
BUS
-5%. The nominal threshold limits can be shifted by a fraction of V
BUS
from +1% to +15% for the high threshold voltage and from -1% to -15% for the low threshold voltage. This means the threshold limits can vary from V
BUS
+5% to V
BUS
+20% for the high limit and from V
BUS
-5% to V
BUS
-20% for the low limit.
threshold limits can be changed independently through NVM programming (see
Section 6 Start-up configuration )
and also by software during attachment through the I²C interface.
VBUS discharge
The monitoring block also handles the internal V
BUS
discharge path connected to the VBUS_SENSE pin. The discharge path is activated at detachment, or when the device goes into the error recovery state whatever the power role (see
Section 3.6 Hardware fault management
).
The V
BUS
discharge path is enabled by default in NVM and can be disabled through NVM programming only (see
8.3 Electrical and timing characteristics
). The discharge time duration can be changed through NVM programming
(see
Section 6 Start-up configuration ) and also by software through the I²C interface.
VBUS power path assertion
The STUSB1702 can control the assertion of the V
BUS
power path on the USB Type-C port, directly or indirectly, through the VBUS_EN_SRC pin.
The tables below summarize the configurations of the STUSB1702 and the operation conditions that determine the electrical value of the VBUS_EN_SRC pin during system operations.
Pin
VBUS_EN_SRC
Table 5. Conditions for V
BUS
power path assertion in source power role
Electrical value
0
HiZ
Type-C attached state
Attached.SRC or
UnorientedDebug
Accessory.SRC or
OrientedDebug
Accessory.SRC
Any other state
Operation conditions
VDD pin monitoring
VBUS_SENSE pin monitoring
VDD > UVLO if
VDD_UVLO enabled and/or
VDD < OVLO if
VDD_OVLO enabled
VDD < UVLO if
VDD_UVLO enabled and/or
VDD > OVLO if
VDD_OVLO enabled
V
BUS
is within valid voltage range if
VBUS_VALID_RANGE enabled or
V
BUS
> UVLO if V
BUS
_VALID_RANGE disabled
V
BUS
is out ofvalid voltage range if
VBUS_VALID_RANGE enabled or
VBUS < UVLO if V
BUS
_VALID_RANGE disabled
Comment
The signal is asserted only if all the valid operation conditions are met
The signal is deasserted when at least one non valid operation condition is met
As specified in the USB Type-C standard specification, the attached state “Attached.SRC” is reached only if the voltage on the V
BUS
receptacle side is at vSafe0V condition when a connection is detected.
“Type-C attached state” refers to the Type-C FSM states as defined in the USB Type-C standard specification and as described in the I²C register CC_OPERATION_STATUS.
“VDD pin monitoring” is valid only in source power role. Activation of the UVLO and OVLO threshold detections
I²C interface. When UVLO and/or OVLO threshold detection is activated, VBUS_EN_SRC pin is asserted only if the device is attached and the valid threshold conditions on VDD are met. Once the VBUS_EN_SRC pin is asserted, the V
BUS
monitoring is done on VBUS_SENSE pin instead of the VDD pin.
DS12664 - Rev 1 page 9/38
STUSB1702
VCONN supply
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
“VBUS_SENSE pin monitoring” relies, by default, on a valid V
BUS
voltage range. The voltage range condition can be disabled to consider UVLO threshold detection instead. The monitoring condition of the V
BUS
voltage can be changed through NVM programming (see
Section 6 Start-up configuration
) and also by software through the I²C interface. VBUS_EN_SRC pin is maintained asserted as long as the device is attached and a valid voltage condition on the V
BUS
is met.
V
CONN
supply
V
CONN
input voltage
V
CONN
is a regulated supply used to power circuits in the plug of USB3.1 full-featured cables and other accessories. V
CONN
nominal operating voltage is 5.0 V +/- 5%.
V
CONN
application conditions
•
•
V
CONN
pin of the STUSB1702 is connected to each CC pin (CC1 and CC2) across independent power switches.
The STUSB1702 applies V
CONN
only to the CC pin not connected to the CC wire when all below conditions are met:
The device is configured in source power role
•
V
CONN
power switches are enabled
A valid connection to a sink is achieved
•
•
R a
presence is detected on the unwired CC pin
A valid power source is applied to the V
CONN
pin with respect to a predefined UVLO threshold
V
CONN
monitoring
The V
CONN
monitoring block detects if V
CONN
power supply is available on the V
CONN
pin. It is used to check that
V
CONN
voltage is above a pre-defined undervoltage lockout (UVLO) threshold to allow the enabling of the V
CONN power switches.
The default value of the UVLO threshold is 4.65 V typical for powered cables operating at 5 V. This value can be changed by software to 2.65 V typical to support V
CONN
-powered accessories that operate down to 2.7 V.
V
CONN
discharge
The behavior of Type-C FSMs is extended to an internal V
CONN
discharge path capability on the CC pins in source power mode only. The discharge path is activated during 250 ms from sink detachment detection. This
) and also by software through the I²C interface.
V
CONN
control and status
The supplying conditions of V
CONN
across the STUSB1702 are managed through the I²C interface. Different I²C registers and bits are used specifically for this purpose.
V
CONN
power switches
Features
•
•
•
•
The STUSB1702 integrates two current limited high-side power switches with protection that tolerates high voltage up to 22 V on the CC pins.
Each V
CONN
power switch is presents the following features:
Soft-start to limit inrush current
Constant current mode overcurrent protection
Adjustable current limit
Thermal protection
DS12664 - Rev 1 page 10/38
•
•
Undervoltage and overvoltage protections
Reverse current and reverse voltage protections
Figure 4. V
CONN to CC1 and CC2 power switch protections
STUSB1702
VCONN supply
DS12664 - Rev 1
Current limit programming
The current limit can be set within the range 100 mA to 600 mA by a step of 50 mA. The default current limit is programmed through NVM programming (see
Section 6 Start-up configuration ) and can be changed by software
through the I²C interface. At power-on or after a reset, the current limit takes the default value preset in the NVM.
Fault management
The table below summarizes the different fault conditions that could occur during switch operation and the associated responses. An I²C alert is generated when a fault condition happens.
Fault types
Short-circuit
Overcurrent
Overheating
Undervoltage
Overvoltage
Table 6. Fault management conditions
Fault conditions
CC output pin shorted to ground via very low resistive path causing rapid current surge
V
CONN
input voltage drops below
UVLO threshold minus hysteresis
CC output pin voltage exceeds maximum operating limit of 6.0 V
Expected actions
Power switch limits the current and reduces the output voltage. I²C alert is asserted immediately thanks to VCONN_SW_OCP_FAULT bits
CC output pin connected to a load that sinks current above programmed limit
Power switch limits the current and reduces the output voltage. I²C alert is asserted immediately thanks to VCONN_SW_OCP_FAULT bits
Junction temperature exceeding 145
°C due to any reason
Power switch is disabled immediately until the temperature falls below 145 °C minus hysteresis of 15 °C. I²C alert is asserted immediately thanks to THERMAL_FAULT bit. The STUSB1702 goes into transient error recovery state
Power switch is disabled immediately until the input voltage rises above the UVLO threshold. I²C alert is asserted immediately thanks to VCONN_PRESENCE bit
Power switch is opened immediately until the voltage falls below the voltage limit. I²C alert is asserted immediately thanks to
VCONN_SW_OVP_FAULT bits page 11/38
STUSB1702
High voltage protection
3.5
3.6
3.7
3.7.1
3.7.2
Fault types Fault conditions Expected actions
Reverse current
CC output pin voltage exceeds
V
CONN input voltage when the power switch is turned off
Reverse voltage
CC output pin voltage exceeds
V
CONN
input voltage of more than
0.35 V for 5 V when the power switch is turned on
The reverse biased body diode of the back- to-back MOS switches is naturally disabled preventing current from flowing from CC output pin to the input
Power switch is opened immediately until the voltage difference falls below the voltage limit. I²C alert is asserted immediately thanks to
VCONN_SW_RVP_FAULT bits
High voltage protection
The STUSB1702 can be safely used in systems or connected to systems that handle high voltage on the V
BUS power path. The device integrates an internal circuitry on the CC pins that tolerates high voltages and ensures protection up to 22 V in case of unexpected short-circuits with the V
BUS
or in the case of a connection to a device supplying high voltage on the V
BUS
.
Hardware fault management
•
•
The STUSB1702 handles hardware fault conditions related to the device itself and to the V
BUS
power path during system operation.
When such conditions occur, the circuit goes into a transient error recovery state named ErrorRecovery in the
Type-C FSM. In this state, the device de-asserts the V
BUS
power path by disabling the VBUS_EN_SRC pin and it removes the terminations from the CC pins during several tens of milliseconds. Then, it goes to the unattached source state.
•
•
The STUSB1702 goes into error recovery state when at least one condition listed below is met:
• If an overtemperature is detected, the “THERMAL_FAULT” flag is asserted
If an internal pull-up voltage on the CC pins is below the UVLO threshold, the “VPU_VALID” flag is asserted
If an overvoltage is detected on the CC pins, the “VPU_OVP_FAULT” flag is asserted
•
If the VBUS voltage is out of the valid voltage range during attachment, the “VBUS_VALID” flag is asserted
If an undervoltage is detected on the VDD pin during attachment when UVLO detection is enabled, the
“VDD_UVLO_DISABLE” flag is asserted
If an overvoltage is detected on the VDD pin during attachment when OVLO detection is enabled, the
“VDD_OVLO_DISABLE” flag is asserted
The I²C register bits mentioned above give either the state of the hardware fault when it occurs or the setting condition to detect the hardware fault.
Accessory mode detection
The STUSB1702 supports the detection of audio accessory mode and debug accessory mode as defined in the
USB Type-C standard specification with the following Type-C power modes (see
Section 6 Start-up configuration ):
• Source power role with accessory support
Audio accessory mode detection
The STUSB1702 detects an audio accessory device when both CC1 and CC2 pins are pulled down to ground by an R a
resistor from the connected device. The audio accessory detection is advertised through the
CC_ATTACHED_MODE bits of the I²C register CC_CONNECTION_STATUS.
Debug accessory mode detection
The STUSB1702 detects a connection to a debug and test system (DTS). The debug accessory detection is advertised through the CC_ATTACHED_MODE bits of the I²C register CC_CONNECTION_STATUS.
• In source power role, a debug accessory device is detected when both the CC1 and CC2 pins are pulled down to ground by an R d
resistor from the connected device. The orientation detection is performed in two
DS12664 - Rev 1 page 12/38
STUSB1702
Accessory mode detection steps as described in the table below. The DEBUG2 pin is asserted to advertise the DTS detection and the
A_B_SIDE pin indicates the orientation of the connection. The orientation detection is advertised through the
TYPEC_FSM_STATE bits of the I²C register CC_OPERATION_STATUS.
#
CC1 pin
(CC2 pin)
1
2
R d
R d
CC2 pin
(CC1 pin)
R d
≤ R a
Table 7. Orientation detection
Detection process
1 st step: debug accessory mode detected
2 nd step: orientation detected (DTS presents a resistance to GND with a value
≤ R a
on its CC2 pin)
A_B_SIDE pin
CC1/CC2
(CC2/CC1)
Orientation detection state
TYPEC_FSM_STATE bits value
HiZ (HiZ) UnorientedDebugAccessory.SRC
HiZ (0) OrientedDebugAccessory.SRC
DS12664 - Rev 1 page 13/38
4
STUSB1702
Managing USB PD transactions
Managing USB PD transactions
•
•
•
Due to specific HW/SW partitioning, the STUSB1702 requires a specific alignment between the lower protocol stack (managed by the STUSB1702) and the higher protocol stack (managed by the external MCU). Therefore, dedicated read and write I²C accesses are needed to perform the following actions:
•
Acknowledge a HW reset request
Request a HW reset
Perform a V
CONN
SWAP
Perform a data role SWAP
DS12664 - Rev 1 page 14/38
STUSB1702
I²C interface
5
I²C interface
5.1
Read and write operations
•
•
The I²C interface is used to configure, control and read the operation status of the device. It is compatible with the
Philips I²C BUS® (version 2.1). The I²C is a slave serial interface based on two signals:
SCL - serial clock line: input clock used to shift data
SDA - serial data line: input/output bidirectional data transfers
A filter rejects the potential spikes on the bus data line to preserve data integrity.
The bidirectional data line supports transfers up to 400 Kbit/s (fast mode). The data are shifted to and from the chip on the SDA line, MSB first.
The first bit must be high (START) followed by the 7-bit device address and the read/write control bit.
Two 7-bit device addresses are available for the STUSB1702 thanks to external programming of DevADDR0 through ADDR0 pin setting, i.e. 0x28 or 0x29. This allows two STUSB1702 devices to be connected on the same
I²C bus.
Bit7
DevADDR6
0
Bit6
DevADDR5
1
Table 8. Device address format
Bit5
DevADDR4
0
Bit4
DevADDR3
1
Bit3
DevADDR2
0
Bit2
DevADDR1
0
Bit1
DevADDR0
ADDR0
Bit0
R/W
0/1
Table 9. Register address format
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RegADDR7 RegADDR6 RegADDR5 RegADDR4 RegADDR3 RegADDR2 RegADDR1 RegADDR0
Bit7
DATA7
Bit6
DATA6
Bit5
DATA5
Table 10. Register data format
Bit4
DATA4
Bit3
DATA3
Bit2
DATA2
Bit1
DATA1
Bit0
DATA0
Figure 5. Read operation
Master Slave
Start Device addr
7 bits
W A Reg address
8 bits
A Restart Device addr
7 bits
R A Reg data
8 bits
A Reg data
8 bits
Address n+1
A Reg data
8 bits
Address n+2 Start bit = SDA falling when SCL= 1
Stop bit = SDA rising when SCL= 1
Restart bit = start after a start
Acknowledge = SDA forced low during a SCL clock
A
Stop
DS12664 - Rev 1 page 15/38
STUSB1702
Timing specifications
Figure 6. Write operation
Start Device addr
7 bits
W A Reg address
8 bits
Start bit = SDA falling when SCL = 1
Stop bit = SDA rising when SCL = 1
Restart bit = start after a start
A Reg data
8 bits
A Reg data
8 bits
Address n+1
A Reg data
8 bits
Address n+2
A Stop
5.2
Timing specifications
The device uses a standard slave I²C channel at speed up to 400 kHz.
Symbol
F scl t hd,sta t low t high t su,dat t hd,dat t su,dat t r t f t su,sto t buf
C b
Table 11. I²C timing parameters - V
DD
= 5 V
Parameter
SCL clock frequency
Hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for repeated START condition
Data hold time
Data setup time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Min.
0
0.6
1.3
0.6
0.6
0.04
100
20 + 0.1 C b
20 + 0.1 C b
0.6
1.3
-
Figure 7. I²C timing diagram t f
V ih
SDA
V il t hd,st a t r t su,dat t high
SCL t low t hd,dat t su,sta
-
300
300
-
-
400
Max.
400
-
-
0.9
-
-
-
-
-
-
-
-
-
-
-
-
Typ.
-
-
Unit kHz
μs ns
μs pF
DS12664 - Rev 1 page 16/38
5.3
STUSB1702
I²C register map
I²C register map
Access code
RO
R/W
RC
Table 12. Register access legend
Expanded name
Read only
Read /write
Read and clear
Description
Register can be read only
Register can be read or written
Register can be read and is cleared after it is read
0Eh
0Fh
10h
CC_DETECTION_STATUS
TYPE_C_HANDSHAKE and
MONITORING_STATUS_TRANS
MONITORING_STATUS
11h
12h
CC_CONNECTION_STATUS
HW_FAULT_STATUS_TRANS
13h HW_FAULT_STATUS
14h to 17h Reserved
18h CC_CAPABILITY_STATUS_CTRL
19h to 1Dh Reserved
23h
25h
26h
RESET_CTRL
VBUS_DISCHARGE_TIME_CTRL
VBUS_DISCHARGE_CTRL
27h VBUS_ENABLE_STATUS
29h to 2Dh Reserved
2Fh Reserved
Table 13. STUSB1702 register map overview
Address
00h to 0Ah Reserved
0Bh
Register name
ALERT_STATUS
0Ch
0Dh
1Eh
1Fh
20h
21h
22h
2Eh
ALERT_STATUS_MASK_CTRL
CC_DETECTION_STATUS_TRANS
CC_VCONN_SWITCH_CTRL
TYPE_C_CTRL
VCONN_MONITORING_CTRL
VBUS_SELECT
VBUS_RANGE_MONITORING_CTRL
VBUS_MONITORING_CTRL
Access
RO Do not use
Description
RC Alerts register linked to transition registers
R/W
Allows the interrupt mask on the ALERT_STATUS register to be changed
RC
Alerts about transition in CC_DETECTION_STATUS register
RO CC detection status
RC
Allows Type-C FSM to be synchronized with software.
Alerts about transition in MONITORING_STATUS register
RO Gives status on V
BUS
and V
CONN
voltage monitoring
RO CC connection status
RC Alerts about transition in HW_FAULT_STATUS register
RO Gives status on hardware faults
RO Do not use
R/W Allows the CC capabilities to be changed
RO Do not use
R/W
Allows the current limit of V
CONN
power switches to be changed
R/W Allows software to be synchronized with Type- C FSM
R/W
Allows the monitoring conditions of V
CONN changed
voltage to be
R/W
R/W
Allows the DAC value related to the targeted V
BUS to be changed
voltage
Allows the voltage range for V
BUS changed
monitoring to be
R/W Controls the device reset by software
R/W Allows the V
BUS
discharge time to be changed
R/W Controls the V
BUS
discharge path
R/W Gives status on V
BUS
power path activation
RO Do not use
R/W
Allows the monitoring conditions of V
BUS changed
voltage to be
RO Do not use
DS12664 - Rev 1 page 17/38
STUSB1702
Start-up configuration
6
Start-up configuration
6.1
6.2
User-defined parameters
The STUSB1702 has a set of user-defined parameters that can be customized by NVM reprogramming and/or by software through the I²C interface. This feature allows the customer to change the preset configuration of the USB
Type-C interface and to define a new configuration to meet specific customer requirements addressing various applications, use cases, or specific implementations.
The NVM re-programming overrides the initial default setting to define a new default setting that is used at powerup or after a reset. The default value is copied at power-up, or after a reset, from the embedded NVM into dedicated I²C register bits. The NVM re-programming is possible only once with a customer password.
When a default value is changed during functioning by software, the new setting remains in effect as long as the
STUSB1702 runs or when it is changed again. But after power- off and power-up, or after a reset, the
STUSB1702 takes back the default values defined in the NVM.
Default start-up configuration
•
•
The table below lists the user-defined parameters and indicates the default start-up configuration of the
STUSB1702.
Three types of user-defined parameters are specified in the table with respect to the “Customization type” column:
• SW: indicates parameters that can be customized only by software through the I²C interface during system operation
NVM: indicates parameters that can be customized only by NVM re-programming
NVM/SW: indicates parameters that can be customized by NVM re-programming and/or by software through the I²C interface during system operation
Table 14. STUSB1702 user-defined parameters and default setting
Customization type
NVM/SW
NVM/SW
NVM/SW
NVM
NVM/SW
NVM/SW
NVM/SW
NVM/SW
SW
SW
NVM/SW
NVM/SW
SW
Parameter Default value and description
CC_CONNECTION_STATUS_AL_MASK 1b: interrupt masked
MONITORING_STATUS_AL_MASK
HW_FAULT_STATUS_AL_MASK
1b: interrupt masked
1b: interrupt masked
STANDBY_POWER_MODE_DISABLE
CC_CURRENT_ADVERTISED
CC_VCONN_DISCHARGE_EN
CC_VCONN_SUPPLY_EN
1b: disables standby power mode
01b: 1.5 A
0b: V
CONN
discharge disabled on CC pin
1b: V
CONN
CC pin
supply capability enabled on
CC_VCONN_SWITCH_ILIM
VCONN_MONITORING_EN
VCONN_UVLO_THRESHOLD
SHIFT_HIGH_VBUS_LIMIT_SOURCE
SHIFT_LOW_VBUS_LIMIT_SOURCE
SW_RESET_EN
0000b: 350 mA
1b: enables UVLO threshold detection on
VCONN pin
0b: high UVLO threshold of 4.65 V
0101b: in source power role, shifts nominal high voltage limit by 5% of V
BUS
0101b: in source power role, shifts nominal low voltage limit by -5% of V
BUS
0b: device reset is performed from hardware RESET pin
I²Cregister address
0Ch
0Ch
0Ch n.a.
18h
18h
18h
1Eh
20h
20h
22h
22h
23h
DS12664 - Rev 1 page 18/38
STUSB1702
Default start-up configuration
Customization type
NVM/SW
NVM/SW
NVM
NVM/SW
NVM/SW
NVM/SW
NVM/SW
Parameter Default value and description
VBUS_DISCHARGE_TIME_TO_0V 1010b: 840 ms discharge time
VBUS_DISCHARGE_TIME_TRANSITION 1010b: 200 ms discharge time
VBUS_DISCHARGE_DISABLE
VDD_OVLO_DISABLE
VBUS_VALID_RANGE_DISABLE
0b: enables V
BUS
discharge path
0b: enables OVLO threshold detection on
VDD pin
0b: enables valid V
BUS
voltagerange detection
VBUS_VSAFE0V_THRESHOLD
VDD_UVLO_DISABLE
00b: V
BUS
vSafe0Vthreshold = 0.6 V
1b: disables UVLO threshold detection on
VDD pin
I²Cregister address
25h
25h n. a.
2Eh
2Eh
2Eh
2Eh
DS12664 - Rev 1 page 19/38
STUSB1702
Application
7
7.1
7.1.1
7.1.2
Application
The sections below are not part of the ST product specifications. They are intended to give a generic application overview to be used by the customer as a starting point for further implementation and customization. ST does not warrant compliancy with customer specifications. Full system implementation and validation are under the customer’s responsibility.
General description
Power supplies
•
•
The STUSB1702 can be supplied in three different ways depending on the targeted application:
• Through the VDD pin only for applications powered by V
BUS
that operate either in source power role
Through the VSYS pin only for AC powered applications with a system power supply delivering 3.3 V or 5 V
Through the VDD and VSYS pins for applications powered by V
BUS
with a system power supply delivering
3.3 V or 5 V. When both VDD and VSYS power supplies are present, the low power supply VSYS is selected when VSYS voltage is above 3.1 V. Otherwise VDD is selected
Connection to MCU or application processor
The I²C interface is used to provide extensive functionality during system operation. For instance:
1.
Define the port configuration during system boot (in case NVM parameters are not customized during manufacturing)
2.
Change the default configuration at any time during operation
3.
Adjust the port power capability in source power role according to contextual power availability and/or the power partitioning with other ports
4.
Save system power by shutting down the DC-DC converter according to the attachment detection state
5.
Provide a diagnostic of the Type-C connection and the V
BUS
power path in real time
DS12664 - Rev 1 page 20/38
STUSB1702
USB Type-C typical applications
7.2
7.2.1
USB Type-C typical applications
Source type application schematic
Figure 8. Typical STUSB1702 implementation in source type application
Power
Management
Unit
VBUS
3V3
VI O
C2
1µF
STL9P3LLH6
R1
10K
STL9P3LLH6
C1
10µF
R2
1K
GND
VI O
Application
Processor
SPC5 Power Architecture
32-bit MCUs
To Super Speed M UX
To GND/VIO
MI SO
MOSI
NSS
SCLK
TX_EN
SCL
SDA
ALERT#
RESET
R10
10K
R4
10K
R5
10K
R6
10K
R7
10K
R8
10K
R9
10K
R3
10K
A_B_Side
ADDR0
R11
10K
GND
R12
100K
GND
24
U1
15
7
8
9
6
14
11
12
16
MISO
MOSI
NSS
SCLK
TX_EN
SCL
SDA
AL ERT#
RESET
I²C
SSI
STUSB1702
VBUS_SENSE 18
CC1GND
CC1
1
CC2
CC2GND 5
2
4
VReg_1V2 21
GND
GND
VReg_2V7 23
5V
C3
1µF
C4
1µF
GND
17
13
A_B_SIDE
ADDR0
VCONN
3
GND
10
EP
0
C5 10µF
GND GND
VBUS
CC1
CC2
D1
D2
GND
GND
Type C connector
Table 15. Default setting for a source type application
I²C register address
0Eh
18h
18h
18h
1Eh
20h
20h
22h
22h
25h
25h
26h
2Eh
I²C register field name I²C register reset value/description
START_UP_POWER_MODE
CC_CURRENT_ADVERTISED
CC_VCONN_DISCHARGE_EN
CC_VCONN_SUPPLY_EN
0b: device starts in normal mode
01b: 1.5 A
0b: V
CONN
discharge disabled on CC pin
1b: V
CONN pin
supply capability enabled on CC
CC_VCONN_SWITCH_ILIM
VCONN_MONITORING_EN
0000b: 350 mA
1b: enables UVLO threshold detection on
V
CONN
pin
0b: high UVLO threshold of 4.65 V VCONN_UVLO_THRESHOLD
SHIFT_HIGH_VBUS_LIMIT_SOURCE
SHIFT_LOW_VBUS_LIMIT_SOURCE
VBUS_DISCHARGE_TIME_TO_0V
0101b: in source power role, shifts nominal high voltage limit by +5% of V
BUS
0101b: in source power role, shifts nominal low voltage limit by -5% of V
BUS
1010b: 840 ms discharge time
VBUS_DISCHARGE_TIME_TRANSITION 1010b: 200 ms discharge time
VBUS_DISCHARGE_EN
VDD_OVLO_DISABLE
1b: enables the V
BUS
discharge path
0b: enables OVLO threshold detection on
VDD pin
Customization type
NVM/SW
NVM/SW
NVM/SW
NVM/SW
NVM/SW
SW
SW
NVM/SW
NVM/SW
NVM/SW
NVM/SW
NVM/SW
SW
DS12664 - Rev 1 page 21/38
DS12664 - Rev 1
STUSB1702
USB Type-C typical applications
I²C register address
2Eh
2Eh
I²C register field name
VBUS_RANGE_DISABLE
VBUS_VSAFE0V_THRESHOLD
2Eh VDD_UVLO_DISABLE
I²C register reset value/description
0b: enables V
BUS
voltage range detection
00b: V
BUS
vSafe0V threshold = 0.6 V
1b: disables UVLO threshold detection on
VDD pin
Customization type
SW
SW
SW
Pin
VBUS_EN_SRC
Table 16. Conditions for V
BUS
power path assertion in source power role
Electrical value
0
Type-C attached state
Attached.SRC or
UnorientedDebug
Accessory.SRC
or OrientedDebug
Accessory.SRC
Operation conditions
VDD pin monitoring
VBUS_SENSEpin monitoring
VDD < OVLO if
VDD pin is supplied
V
BUS
within valid voltage range
Comment
The signal is asserted only if all the valid operation conditions are met
HiZ Anyother state
VDD > OVLO if
VDD pin is supplied
V
BUS
is out ofvalid voltage range
The signal is deasserted when at least one non valid operation condition is met.
Table 17. Source power role with accessory support
Connection state
CC1 pin
CC2 pin
Type-C device state
CC_OPERATION_STATUS register @11h
A_B_SIDE pin
VCONN supply
VBUS_EN_SRC pin
CC_CONNECTION_STATUS register @0Eh
Nothing attached
Open Open
Sink attached
Powered cable withoutsink attached
Powered cable with sink attached or
VCONNpowered accessory attached
Debug accessory mode attached source role
Debug accessory mode attached sink role
Rd Open
Open Rd
Open Ra
Ra
Rd
Ra
Rp
Rd
Open
Ra
Rd
Rp
Rd
Unattached.SRC
Attached.SRC
Unattached.SRC
Attached.SRC
Unattached.SRC
UnorientedDebug
Accessory.SRC
HiZ
HiZ
0
HiZ
HiZ
HiZ
0
HiZ
HiZ
OFF
OFF
OFF
OFF
OFF
CC2
CC1
OFF
OFF
HiZ
0
0
HiZ
HiZ
0
0
HiZ
0
00h
2Dh
2Dh
00h
00h
2Fh
2Fh
00h
6Dh page 22/38
STUSB1702
USB Type-C typical applications
Connection state
Debug accessory mode attached sink role
Audio adapter accessory mode attached
CC1 pin
Rd
≤ Ra
Ra
CC2 pin
≤Ra
Rd
Ra
Type-C device state
CC_OPERATION_STATUS register @11h
A_B_SIDE pin
VCONN supply
VBUS_EN_SRC pin
CC_CONNECTION_STATUS register @0Eh
HiZ OFF 0 6Dh
OrientedDebug
Accessory.SRC
0 OFF 0 6Dh
AudioAccessory HiZ OFF HiZ 81h
The value of the CC1 and CC2 pins is defined from a termination perspective and corresponds to the termination presented by the connected device. The CC_CONNECTION_STATUS register can report other values than the one presented in table above. In this table, it reflects the state transitions in Type-C FSM that can be ignored from the application stand point.
DS12664 - Rev 1 page 23/38
STUSB1702
Electrical characteristics
8
Electrical characteristics
8.1
8.2
Note:
Absolute maximum ratings
All voltages are referenced to GND.
Symbol
V
DD
V
SYS
V
CC1
, V
CC2
, V
CC1GND
, V
CC2GND
V
VBUS_EN_SRC
, V
VBUS_SENSE
V
SCL
, V
SDA
, V
ALERT#
, V
RESET
, V
A_B_SIDE
V
MOSI
, V
MISO
, V
NSS
, V
TX_EN
, V
SCLK
V
CONN
T
STG
T
J
ESD
Table 18. Absolute maximum ratings
Parameter
Supply voltage
Supply voltage on VSYS pin
High voltage on CC pins
High voltage on V
BUS
pins
Operating voltage on I/O pins
V
CONN
voltage
Storagetemperature
Maximum junction temperature
HBM
CDM
Operating conditions
Symbol
V
DD
V
SYS
V
CC1
, V
CC2
, V
CC1GND
, V
CC2GND
V
VBUS_EN_SRC
, V
VBUS_SENSE
V
SCL
, V
SDA
, V
ALERT#
, V
RESET
, V
A_B_SIDE
V
MOSI
, V
MISO
, V
NSS
, V
TX_EN
, V
SCLK
V
CONN
I
CONN
T
A
Table 19. Operating conditions
Parameter
Supply voltage
Supply voltage on V
SYS
pin
CC pins
High voltage pins
Operating voltage on I/O pins
V
CONN
voltage
V
CONN
rated current (default = 0.35 A)
Operating temperature
The transient voltage on the CC1 and CC2 pins drops to -0.3 during BMC communication.
Value
28
6
22
28
-0.3 to 6
6
-55 to 150
145
4
1.5
Unit
V
°C kV
Value
4.1 to 22
3.0 to 5.5
-0.3 to 5.5
0 to 22
Unit
V
0 to 4.5
2.7 to 5.5
0.1 to 0.6
-40 to 105
A
°C
DS12664 - Rev 1 page 24/38
STUSB1702
Electrical and timing characteristics
8.3
Electrical and timing characteristics
Unless otherwise specified: V
DD
= 5 V, T
A
= +25 °C, all voltages are referenced to GND.
Symbol
I
DD (SRC)
Parameter
Current consumption
Table 20. Electrical characteristics
Conditions
Device idle as a SOURCE (not connected, no communication)
Device in standby (not connected, low power)
V
SYS
@ 3.3 V
V
DD
@ 5.0 V
V
SYS
@ 3.3 V
V
DD
@ 5.0 V
I
STDBY
Standby current consumption
CC1 and CC2 pins
I
P-USB
I
P-1.5
I
P-3.0
CC current sources
V
CCO
CC open pin voltage
R
R d
INCC
CC pull-down resistors
CC input impedance
V
TH0.2
Detection threshold 1
V
V
V
TH0.4
TH0.8
TH1.6
Detection threshold 2
Detection threshold 4
Detection threshold 6
V
TH2.6
Detection threshold 7
V
CONN
protection
R
VCONN
V
CONN
power path resistance
CC pin voltage, V
CC
= -0.3 to 2.6 V,
40 °C < T
A
< 105 °C
CC unconnected, V
DD
= 3.0 to 5.5 V
40 °C < T
A
< 105 °C
Pull-up and pull-down resistors off
Max. R a
detection by DFP at I detection by UFP on R d
UFP
P
= I
P-USB
, min. I
P_USB
, min CC voltage for connected
Max. R a
detection by DFP at I
P
= I
P-1.5
Max. R a
detection by DFP at I
P
= I
P-3.0
Max. R d
detection by DFP at I
P
= I
P-USB
and I
P
= I
P-1.5
Max. R d
detection by DFP at I connected UFP
P-3.0
, max. CC voltage for
I
VCONN
= 0.2 A-
Min.
-20%
-8%
-8%
2.75
-10%
200
0.15
0.35
0.75
1.50
2.45
I
OCP
Overcurrent protection
Programmable current limit threshold
(from 100 mA to 600 mA by step of 50 mA)
0.25
85
300
550
V
OVP
Output overvoltage protection
V
UVP
Input undervoltage protection
V
BUS
monitoring and driving
V
THUSB
V
BUS
presence threshold
Low UVLO threshold
High UVLO threshold (default)
V
SYS
= 3.0 to 5.5 V
5.9
2.6
4.6
3.8
Typ.
158
188
33
53
Max.
Unit
µA
µA
80
180
330
+20%
+8%
+8%
µA
V
5.1
10% kΩ kΩ
0.20
0.25
V
0.40
0.80
0.45
V
0.85
V
1.60
2.60
1.65
V
2.75
V
0.50
100
350
600
0.975
Ω
125
400
650 mA
6.0
V 6.1
2.7
4.8
V
3.9
4.0
V
DS12664 - Rev 1 page 25/38
8.4
STUSB1702
Thermal Information
Symbol
V
TH0V
V
Parameter
BUS
safe 0 V threshold
(vSafe0V)
Conditions
V
SYS
= 3.0 to 5.5 V
Programmable threshold
Programmable threshold from 0.6 V to 1.8 V
Default V
THOV
= 0.6 V
T
V
V
R
DISUSB
DISUSB
MONUSBH
MONUSBL
V
BUS
discharge resistor
V
BUS
discharge time to 0V
V
BUS
discharge time to PDO
V
BUS
monitoring high voltage threshold
V
BUS
monitoring low voltage threshold
Default T
DISPARAM
= 840 ms, the coefficient T
DISPARAM is programmable by NVM
Default T
DISPARAM
= 200 ms, the coefficient T
DISPARAM is programmable by NVM
V
BUS
= nominal target value, default V
MONUSBH
= V
BUS
+10 %, the threshold limit is programmable by NVM from +5 % to +20 %
V
BUS
= nominal target value, default V
MONUSBL
= V
BUS
-10 %, the threshold limit is programmable by NVM from
-20 % to -5 %
Digital input/output (SCL, SDA, ALERT#, A_B_SIDE, MOSI, MISO, NSS, TX_EN, SCLK)
V
IH
High level input voltage
V
V
IL
OL
Low level input voltage
Low level output voltage
Ioh = 3 mA
20 V open drain outputs (VBUS_EN_SRC)
V
OL
Low level output voltage
Ioh = 3 mA
1. T
DISPARAM
Min.
0.5
0.8
1.1
1.7
600
70
20
1.2
V
BUS
+
10%
V
84
24
BUS
10%
-
Typ.
0.6
0.9
1.2
1.8
700
Max.
Unit
0.7
V
1
1.3
1.9
V
V
V
800 Ω
100
28
0.35
0.4
0.4
ms
V
V
V
V
V
V
Thermal Information
Symbol
R
θJA
R
θJC
Table 21. Thermal information
Parameter
Junction to ambient thermal resistance
Junction to case thermal resistance
Value
37
5
Unit
°C/W
°C/W
DS12664 - Rev 1 page 26/38
STUSB1702
Ordering information
9
Ordering information
Order code
STUSB1702YQTR
AEC-Q100
Yes
Table 22. Order code
Package
QFN24 EP 4x4 mm wettable flanks
Temperature range
- 40 °C up to105 °C
Marking
1702Y
DS12664 - Rev 1 page 27/38
10
STUSB1702
Terms and abbreviations
Terms and abbreviations
Term
Accessory modes
DFP
DRP
Sink
Source
UFP
Table 23. List of terms and abbreviations
Description
Audio adapter accessory mode. It is defined by the presence of R a
/R a
on the CC1/CC2 pins.
Debug accessory mode. It is defined by the presence of R d
/R d
on CC1/CC2 pins in source power role or R p
/R p
on CC1/CC2 pins in sink power role.
Downstream facing port, specifically associated with the flow of data in a USB connection.
Typically, the ports on a HOST or the ports on a hub to which devices are connected. In its initial state, DFP sources V
BUS
and V
CONN
, and supports data.
Dual-role port. A port that can operate as either a source or a sink. The port role may be changed dynamically.
Port asserting R d
on the CC pins and consuming power from the V
BUS
; most commonly a device.
Port asserting R p
on the CC pins and providing power over the V
BUS
; most commonly a host or hub DFP.
Upstream facing port, specifically associated with the flow of data in a USB connection. The port on a device or a hub that connects to a host or the DFP of a hub. In its initial state, the
UFP sinks the V
BUS
and supports data.
DS12664 - Rev 1 page 28/38
11
STUSB1702
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS12664 - Rev 1 page 29/38
STUSB1702
QFN24 EP 4x4 mm wetable flank package information
11.1
QFN24 EP 4x4 mm wettable flank package information
Figure 9. QFN24 EP 4x4 mm wetable flank package outline
D
TOP VIEW
Detail A
19
SIDE VIEW
D
24
L2
18 1
C0.35
D2
13 6
12
BOTTOM VIEW
7
Terminal length
L1 L3
FRONT VIEW
L
DETAIL A
L3
L1
Terminal thickness
L2
SECTION VIEW
DS12664 - Rev 1 page 30/38
DS12664 - Rev 1
STUSB1702
QFN24 EP 4x4 mm wetable flank package information
Ref.
D2
E
E2 e
J
A
A1
A2
A3 b
D
L
L1
L2
L3
Table 24. QFN24 EP 4x4 mm wetable flank mechanical data
Min.
0.90
0.00
0.20
3.85
2.40
3.85
2.40
0.30
Dimensions (mm)
Typ.
0.95
0.10
0.02
0.20
0.25
4.00
2.50
4.00
2.50
0.50
0.35
0.40
0.20
0.05
0.10
0.30
4.15
2.60
4.15
2.60
Max.
1.00
0.05
0.50
Figure 10. QFN24 EP 4x4 mm wetable flank recommended footprint page 31/38
Revision history
Date
06-Jul-2018
Revision
1
Table 25. Document revision history
Changes
Initial release.
STUSB1702
DS12664 - Rev 1 page 32/38
STUSB1702
Contents
Contents
DS12664 - Rev 1 page 33/38
STUSB1702
Contents
DS12664 - Rev 1 page 34/38
STUSB1702
Contents
DS12664 - Rev 1 page 35/38
STUSB1702
List of tables
List of tables
Table 11. I²C timing parameters - V
DS12664 - Rev 1 page 36/38
STUSB1702
List of figures
List of figures
DS12664 - Rev 1 page 37/38
STUSB1702
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS12664 - Rev 1 page 38/38
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