STMicroelectronics STUSB4500L Datasheet
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STUSB4500L
Datasheet
Standalone USB Type-C™ sink port controller
Product status link
STUSB4500L
Product summary
Order code
Description
Package
Marking
STUSB4500LQTR
STUSB4500LBJR
Standalone USB
Type-C controller
(auto-run mode)
QFN-24 EP (4x4)
WLCSP-25
(2.6x2.6x0.5)
4500L
Features
• Auto-run Type-C™ sink controller (5 V)
• Dead battery mode support
• Integrated V
BUS
switch gate drivers (PMOS)
• Integrated V
BUS
voltage monitoring
• Short-to-VBUS protections on CC pins
• High voltage capability on V
BUS
pins
• Source power budget reporting: (default / 1.5 A / 3 A) current at 5 V
• V
BUS
powered:
– Zero consumption on local battery or application
– V
DD
= [4.1 V; 22 V]
• Temperature range: -40 °C up to 105 °C
• ESD: 3 kV HBM - 1.5 kV CDM
• Certified:
– USB Type-C™ rev 1.4
– Power sinking device (TID #1455)
Applications
• Printers, camcorders, cameras
• IoT, drones, accessories and battery powered devices
• Computer accessories (keyboards, mouse)
• Toys, gaming, POS, scanner, LED lighting
• Healthcare, e-cigarettes, handheld devices
• 5 V DC barrel, USB STD-B and micro-B replacement
• Any 5 V Type-C sink device
Description
The STUSB4500L is a USB Type-C controller that addresses 5 V-only sink devices up to 3 A (15 W max.).
This device supports dead battery mode and is suited for sink devices powered from dead battery state. It is able to operate without any external software support for quick application power-on and immediate charging process start. At type-C connection, the STUSB4500L seeks CC pin for SOURCE termination and monitors
V
BUS
voltage in order to protect the application from an incorrect SOURCE operation.
When V
BUS
is within the appropriate range, the STUSB4500L powers the application by closing the input switch. The available current advertised by the SOURCE is reported to the application in order to align the sinking current. Port status can be optionally monitored by the software through I²C interface.
Thanks to its 20 V technology, it implements high voltage features to protect the CC pins against short-circuits to V
BUS
.
DS13102 - Rev 5 - June 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
1.1
STUSB4500L
Functional description
Functional description
The STUSB4500L is a USB Type-C™ IC controller addressing 5 V sink applications. It supports dead battery mode to allow a system to be powered from a V
BUS
power source directly.
The STUSB4500L major role is to:
1.
Detect the connection between two USB Type-C ports (attach detection)
2.
Establish a valid source-to-sink connection
3.
Identify the attached device: source or debug accessory
4.
Resolve cable orientation and twist connections to establish USB 3 data routing (MUX control) if any
5.
Configure the incoming V
BUS
power path
6.
Monitor the V
BUS
power path
7.
Report the available power advertised by the source
•
•
•
•
8.
Handle the high voltage protections
The STUSB4500L also provides:
Dead battery mode
Internal and/or external V
BUS
discharge paths
Debug accessory mode detection
Customization of the device configuration through NVM to support specific applications
Block overview
Figure 1. Functional block diagram
VDD
VSYS
VREG_2V7
VREG_1V2
VBUS_EN_SNK
DISCH
A_B_SIDE
ADDR[1..0]
SCL
SDA
ALERT
ATTACH
RP_3A; RP_1A5
GPIO
RESET
GND
Internal supply
I²C slave
Control
POR voltage monitoring
V
BUS status
Discharge path
VBUS_VS_DISCH
Port C controller
CC line access
CC1DB
CC1
CC2
CC2DB
DS13102 - Rev 5 page 2/32
2
Inputs/outputs
2.1
Pinout
Figure 2. QFN-24 pin connections (top view)
STUSB4500L
Inputs/outputs
CC1DB
CC1
NU
CC2
CC2DB
RESET
1
24 23 22 21 20 19
18
2
17
3
16
4
EP
15
5 14
6
13
7 8 9 10 11 12
VBUS_VS_DISCH
A_B_SIDE
VBUS_EN_SNK
GPIO
RP_1A5
ADDR1
A
Figure 3. WLCSP-25 pin connections (top view)
1 2 4 5
VBUS_VS
_DISCH
RP_3A
3
VREG
_1V2
VREG
_2V7
VDD
B
VSYS ALERT CC1DB CC1
C VBUS_
EN_SNK
A_B_
SIDE
CC2DB CC2
D
GPIO ADDR1 ADDR0 RESET SCL
E
RP_1A5 ATTACH GND DISCH SDA
DS13102 - Rev 5 page 3/32
STUSB4500L
Pinout
13
16
17
14
15
18
19
20
21
22
23
24
EP
9
10
11
QFN
1
2
3
4
5
6
7
8
12
E1
D1
C1
C2
A1
B2
A2
A3
B1
A4
A5
-
E4
E3
E2
CSP
B4
B5
B3, C3
C5
C4
D4
D5
E5
D3
D2
Name
CC1DB
CC1
NU
CC2
CC2DB
RESET
SCL
SDA
DISCH
GND
ATTACH
ADDR0
ADDR1
RP_1A5
GPIO
VBUS_EN_SNK
A_B_SIDE
VBUS_VS_DISCH
ALERT
RP_3A
VREG_1V2
VSYS
VREG_2V7
VDD
EP
Table 1. Pin function list
Type
HV AIO
DI
I 2 C clock input
Description
HV AIO Dead battery enable on CC1 pin
HV AIO Type-C configuration channel 1
-
Type-C configuration channel 2
HV AIO Dead battery enable on CC2 pin
DI Reset input, active high
Typical connection
To CC1 pin if used or ground
To Type-C receptacle A5
To ground
To Type-C receptacle B5
To CC2 pin if used or ground
From system
To I²C master, ext. pull-up or floating (if not used
DI/OD
HV AI/OD
GND
OD
DI
DI
OD
OD
HV OD
OD
HV AI
OD
HV OD
PWR
PWR
PWR
HV PWR
GND
I 2 C data input/output, active low open drain To I²C master, ext. pull-up or floating (if not used
Internal discharge path or external discharge path enable, active low open drain
From power system (internal path) or to the discharge path switch (external path), ext. pullup
Ground
Attachment detection, active low open drain
I²C device address setting
Ground
To MCU if any, ext. pull-up
I²C device address setting
Static, to ground or ext. pull-up for address selection, to ground if no connection to
MCU
Static, to ground or ext. pull-up for address selection, to ground if no connection to
MCU
1.5 A source flag, active low open drain
General purpose output, active low open drain
V
BUS
sink power path enable, active low open drain
Cable orientation, active low open drain
To power system, ext. pull-up
To system, ext. pull-up
To power switch or to power system, ext. pull-up
USB super speed MUX select, ext. pull-up
From V
BUS, receptacle side V
BUS
voltage monitoring and discharge path
I 2 C interrupt, active low open drain
3 A source flag, active low open drain
To I²C master, ext. pull-up
1.2 V internal regulator output
Power supply from system
2.7 V internal regulator output
Power supply from USB power line
Exposed pad is connected to ground
To power switch or to power system, ext. pull-up
1 µF typ. decoupling capacitor
From power system, connect to ground if not used
1 µF typ. decoupling capacitor
From V
BUS
, receptacle side
To ground
DS13102 - Rev 5 page 4/32
2.2
2.2.1
2.2.2
2.2.3
2.2.4
STUSB4500L
Pin description
I
IO
OD
PD
PU
Type
D
A
O
HV
PWR
GND
Table 2. Pin function descriptions
Description
Digital
Analog
Output pad
Input pad
Bidirectional pad
Open drain output
Pull-down
Pull-up
High voltage
Power
Ground
Pin description
CC1 / CC2
CC1 and CC2 are the configuration channel pins used for connection and attachment detection, plug orientation determination. CC1 and CC2 are HiZ during reset.
CC1DB / CC2DB
CC1DB and CC2DB are enabled by dead battery mode by connecting CC1DB and CC2DB respectively to CC1 and CC2. Thanks to this connection, the pull-down terminations on the CC pins are present by default even if the device is not supplied (see
).
Warning: CC1DB and CC2DB must be connected to ground when dead battery mode is not supported, then V sys must be used.
RESET
Active high reset.
I²C interface pins
Table 3. I 2 C interface pin list
Name
SCL
SDA
I²C clock, need external pull-up
I²C data, need external pull-up
Description
ALERT I²C interrupt, need external pull-up
ADDR0, ADDR1
I²C device address bits (see Section 4 I²C Interface
)
Warning: ADDR0 and ADDR1 pins must be connected to ground when there is no connection to an MCU.
DS13102 - Rev 5 page 5/32
2.2.5
2.2.6
2.2.7
2.2.8
Note:
STUSB4500L
Pin description
DISCH
This input/output pin can be used to implement a discharge path for highly capacitive V
BUS side.
line on power system
When used as input, the discharge is internal and a serial resistor must connected to the pin to limit the discharge current through the pin. Maximum discharge current is 500 mA.
The pin can be also used as an open drain output to control an external V
BUS
discharge path when higher discharge current is required by the application, for instance.
The pin is activated at the same time as the internal discharge path on VBUS_VS_DISCH pin. The discharge is activated automatically during cable disconnection and error recovery state. The discharge time is programmable by NVM (see
Section 5 Start-up configuration
).
GND
Ground.
ATTACH
This pin is asserted when a valid source-to-sink connection is established. It is also asserted when a connection to a debug accessory device is detected.
RP_3A/RP_1A5
These pins report by default the status of the USB source current capabilities.
Pin name
VBUS_EN_SNK
RP_3A
RP_1A5
Table 4. Source current capability
Value
Hi-Z No source attached
Description
0 Source attached
Hi-Z No source attached or source supplies default USB Type-C current at 5 V
0 Source supplies 3.0 A USB Type-C current at 5 V
Hi-Z No source attached or source supplies default USB Type-C current at 5 V.
0 Source supplies 1.5 A USB Type-C current at 5 V.
RP_3A and RP_1A5 signals are valid when a SOURCE is attached.
DS13102 - Rev 5 page 6/32
STUSB4500L
Pin description
2.2.9
2.2.10
2.2.11
2.2.12
2.2.13
GPIO
This pin is an active low open drain output that can be configured by NVM as per table below (see
Section 5 Start-up configuration
).
Table 5. GPIO pin configuration
NVM parameter
GPIO_CFG[1:0]
00b
01b
10b
11b
(default)
Pin name
SINK_POWER
Indicates USB Type-C current capability advertised by the source
Pin function
SW_CTRL_GPIO
ERROR_RECOVERY
DEBUG
Software controlled GPIO.
The output state is defined by the value of I 2 C register bit #0 at address 2Dh
Hardware fault detection
(see Section 3.4 Hardware fault management )
Debug accessory detection
(see Section 3.6 Debug accessory mode detection
)
Value Description
Hi-Z When bit #0 value is 0b (at start-up)
0
Hi-Z
0
When bit #0 value is 1b
No hardware fault detected
Hardware fault detected
Hi-Z No debug accessory detected
0 Debug accessory detected
Hi-Z
0
Source supplies default or 1.5 A USB
Type-C current at 5 V
Source supplies 3.0 A USB Type-C current at 5 V
VBUS_EN_SNK
This pin allows the incoming V
BUS
power from the USB Type-C receptacle to be enabled when a source is connected according to different operating conditions stated in the table below. VBUS_EN_SNK pin is a high voltage open drain output that allows a PMOS transistor to be directly driven to enable the VBUS power path.
A_B_SIDE
This output pin provides the cable orientation. It is used to establish USB SuperSpeed signal routing. This signal is not required in case of USB 2.0 support.
Value
HiZ
0
Table 6. USB data MUX select
Description
CC1 pin is attached to CC line
CC2 pin is attached to CC line
VBUS_VS_DISCH
This input pin is used to sense V
BUS
presence, monitor V
BUS
voltage, and discharge V receptacle side.
BUS
from the USB Type-C
A serial resistor connected to the pin must be used to limit the discharge current through the pin. Maximum discharge current is 50 mA.
The discharge is activated automatically during cable disconnection, and error recovery state. The discharge time is programmable by NVM (see
Section 5 Start-up configuration
).
VREG_1V2
This pin is used only for external decoupling of the 1.2 V internal regulator. The recommended decoupling capacitor is: 1 µF typ. (0.5 µF min., 10 µF max.)
DS13102 - Rev 5 page 7/32
STUSB4500L
Pin description
2.2.14
2.2.15
2.2.16
VSYS
This is the low power supply from the system, if there is any. It can be connected directly to a single cell Lithium battery or to the system power supply delivering 3.3 V up to 5 V. It is recommended to connect the pin to ground when it is not used.
VREG_2V7
This pin is used only for external decoupling of the 2.7 V internal regulator. The recommended decoupling capacitor is: 1 µF typ. (0.5 µF min., 10 µF max.)
VDD
This is the main STUSB4500L power supply. Whatever the application is VBUS powered or not, VDD mandatory connection is to USB power line (VBUS). The STUSB4500L can indeed work in dead battery mode, even for self-powered application, in order to reduce power consumption to ZERO when the port is not attached, therefore having no impact on application power leakage.
DS13102 - Rev 5 page 8/32
STUSB4500L
Description of the features
3
Description of the features
3.1
3.2
3.2.1
3.2.2
CC interface
The STUSB4500L controls the connection to the configuration channel (CC) pins, CC1 and CC2, through two main blocks: the CC line interface block and the CC control logic block.
•
•
The CC line interface block is used to:
• Set pull-down termination mode on the CC pins
Monitor the CC pin voltage values related to the attachment detection thresholds
Protect the CC pins against overvoltage
•
•
•
•
•
The CC control logic block is used to:
• Execute the Type-C FSM related to the sink power role with debug accessory support
Determine the electrical state for each CC pin related to the detected thresholds
Evaluate the conditions related to the CC pin states and the V
BUS
voltage value to transition from one state to another in the Type-C FSM
Advertise a valid source-to-sink connection
Determine the identity of the attached device: source or debug accessory
Determine cable orientation to allow external routing of the USB data
•
•
Manage USB Type-C power capability on V
BUS
: USB default, medium or high current mode
Handle hardware faults
VBUS power path control
VBUS monitoring
The V
BUS
monitoring block supervises from the VBUS_VS_DISCH input pin the V
BUS voltage on the USB Type-C receptacle side.
It is used to check that V
BUS
is within a valid voltage range to establish a valid source-to-sink connection and to enable safely the V
BUS
power path through the VBUS_EN_SNK pin.
It allows detection of unexpected V
BUS
V
BUS
voltage conditions such as undervoltage or overvoltage related to the valid
voltage range. When such conditions occur, the STUSB4500L reacts as follows:
• At attachment, it prevents the source-to-sink connection to be established and the V asserted
BUS
power path to be
• After attachment, it goes into unattached state and it disables the V
BUS
power path
The valid V
BUS
voltage range is defined by a low limit V
THUSB
and a high limit V
MONUSBH
(overvoltage condition):
• V
THUSB
low limit is fixed by hardware at 3.3 V in order to detect a V edge (disconnection)
BUS
rising edge (connection) or falling
• The minimum value of V
MONUSBH
is V
BUS
+5% and can be shifted by fraction of 1% from V
BUS
+5% to
V
BUS
+20%. The value is preset by default in the NVM (see
Section 7.3 Electrical and timing characteristics )
and can be changed independently through NVM programming (see Section 5 Start-up configuration )
VBUS discharge
The monitoring block also handles the V
BUS
discharge paths connected to the VBUS_VS_DISCH pin for the
USB Type-C receptacle side and to the DISCH pin for the power system side. The discharge paths are activated at the same time when disconnection is detected or when the device goes into the error recovery state (see
for T
DISUSB0V
time.
DS13102 - Rev 5 page 9/32
3.2.3
3.3
3.4
STUSB4500L
Dead battery mode
The discharge time durations are also preset by default in the NVM (see
Section 7.3 Electrical and timing characteristics
The V
BUS discharge feature is enabled by default in the NVM and can be disabled through NVM programming
(see
Section 5 Start-up configuration
).
VBUS power path assertion
The STUSB4500L can control the assertion of the V
BUS
power path from the USB Type-C receptacle, directly or indirectly, through the VBUS_EN_SNK pin.
The table below summarizes the operating conditions that determine the electrical value of the VBUS_EN_SNK pin during system operation.
Value
0
Hi-Z
Table 7. VBUS_EN_SNK pin behavior depending on the operating conditions
Connection stage
At attachment or during operation
At detachment or during ErrorRecovery
Operating conditions
V
BUS
monitoring conditions on VBUS_VS_DISCH pin
V
BUS
< V
MONUSBH and
V
BUS
> V
THUSB
V
BUS
> V
MONUSBH or
V
BUS
< V
THUSB
Type-C state column refers to the Type-C FSM states as defined in the USB Type-C standard specification.
Dead battery mode
Dead battery mode allows systems powered by a battery to be supplied by the V
BUS
when the battery is discharged and therefore to start the battery charging process without any external support. This mode is also used in systems that are powered through the V
BUS only.
Dead battery mode operates only if the CC1DB and CC2DB pins are connected respectively to the CC1 and
CC2 pins. Thanks to these connections, the STUSB4500L presents a pull-down termination on its CC pins and advertises itself as a sink even if the device is not supplied.
When a source system connects to a USB Type-C port, it detects the pull-down termination, establish the source-to-sink connection, and provide the V
BUS.
The STUSB4500L is then supplied thanks to the VDD pin connected to V
BUS
on the USB Type-C receptacle side. The STUSB4500L can finalize the connection and enable the power path on V
BUS
thanks to the VBUS_EN_SNK pin to allow the system to be powered.
Hardware fault management
During system operation, the STUSB4500L handles some pre-identified hardware fault conditions. When such conditions happen, the circuit goes into an ErrorRecovery state as defined in the USB Type-C standard specifications.
The error recovery state is equivalent to force a detach event. When entering this state, the device de-asserts the
V
BUS
power path by disabling the VBUS_EN_SNK, RP_3A and RP_1A5 pins, and it removes the terminations from the CC pins. Then, it transitions to the unattached state.
The STUSB4500L goes into error recovery state when at least one condition listed below is met:
•
•
If an overtemperature is detected (junction temperature above maximum T
J
)
If an overvoltage is detected on the CC pins (voltage on CC pins above V
OVP
)
The detection of a hardware fault is advertised through the GPIO pin when configured in ERROR_RECOVERY mode.
DS13102 - Rev 5 page 10/32
3.5
STUSB4500L
High voltage protections
See
Section 7 Electrical characteristics for threshold values.
High voltage protections
The STUSB4500L can be used in systems or connected to systems that handle high voltage on the V
BUS
power path. The device integrates an internal circuitry on the CC pins that tolerates high voltage and ensures protection up to 22 V in case of unexpected short-circuits with the V
BUS
as per figure below.
Figure 4. Short-to-V
BUS
3.6
#
1
2
3
4
Debug accessory mode detection
The STUSB4500L detects a connection to a debug and test system (DTS) as defined in the USB Type-C standard specification. The debug accessory detection is advertised through the GPIO pin when configured in
DEBUG mode.
A debug accessory device is detected when both the CC1 and CC2 pins are pulled up by an R p
resistor from the connected device. The voltage levels on the CC1 and CC2 pins give the orientation and current capability as described in the table below. The GPIO pin configured in DEBUG mode is asserted to advertise the DTS detection and the A_B_SIDE pin indicates the orientation of the connection.
Table 8. Orientation and current capability detection in sink power role
CC1 pin
(CC2 pin)
R p
3 A
R p
1.5 A
R p
3 A
R p def/1.5 A/3 A
CC2 pin
(CC1 pin)
R p
1.5 A
R p
default
R p
default
R p def/1.5 A/3 A
Charging current configuration
Default
1.5 A
3.0 A
Default
A_B_SIDE pin
CC1/CC2
(CC2/CC1)
Hi-Z (0)
Hi-Z (0)
Hi-Z (0)
Hi-Z (Hi-Z)
DS13102 - Rev 5 page 11/32
STUSB4500L
I²C Interface
4
I²C Interface
4.1
•
•
Read and write operations
The I²C interface is used to configure, control and read the operation status of the device. It is compatible with the
Philips I²C Bus® (version 2.1). The I²C is a slave serial interface based on two signals:
SCL - serial clock line: input clock used to shift data
SDA - serial data line: input/output bidirectional data transfers
A filter rejects the potential spikes on the bus data line to preserve data integrity.
The bidirectional data line supports transfers up to 400 Kbit/s (fast mode). The data are shifted to and from the chip on the SDA line, MSB first.
The first bit must be high (START) followed by the 7-bit device address and the read/write control bit.
Four 7-bit device address are available for the STUSB4500 thanks to the external programming of DevADDR0 and DevADDR1 bits through ADDR0 and ADDR1 pins setting i.e. 0x28 or 0x29 or 0x2A or 0x2B. It allows four
STUSB4500 devices to be connected on the same I 2 C bus.
Bit7
DevADDR6
0
Bit6
DevADDR5
1
Bit5
DevADDR4
0
Table 9. Device address format
Bit4
DevADDR3
1
Bit3
DevADDR2
0
Bit2
DevADDR1
ADDR1
Bit1
DevADDR0
ADDR0
Bit0
R/W
0/1
Table 10. Register address format
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RegADDR7 RegADDR6 RegADDR5 RegADDR4 RegADDR3 RegADDR2 RegADDR1 RegADDR0
Bit7
DATA7
Bit6
DATA6
Bit5
DATA5
Table 11. Register data format
Bit4
DATA4
Bit3
DATA3
Bit2
DATA2
Figure 5. Read operation
Bit1
DATA1
Master Slave
Start Device addr
7 bits
W A Reg address
8 bits
A Restart Device addr
7 bits
R A
8 bits
tart bit = SDA falling when SCL = 1
Stop bit = SDA rising when SCL = 1
Restart bit = start after a start
Acknowledge = SDA forced low during a SCL clock
Figure 6. Write operation
Start Device addr
7 bits
W A Reg address
8 bits
A Reg data
8 bits
A Reg data
8 bits
Address n+1 Start bit = SDA falling when SCL = 1
Stop bit = SDA rising when SCL = 1
Restart bit = start after a start
A Reg data
8 bits
Address n+1
A Reg data
8 bits
Address n+2
A Reg data
8 bits
Address n+2
A Stop
Ᾱ Stop
Bit0
DATA0
DS13102 - Rev 5 page 12/32
4.2
Timing specifications
The device uses a standard slave I²C channel at speed up to 400 kHz.
Symbol
F scl t hd,sta t low t high t su,dat t hd,dat t su,dat t r t f t su,sto t buf
C b
Table 12. I²C timing parameters - VDD = 5 V
Parameter
SCL clock frequency
Hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for repeated START condition
Data hold time
Data setup time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Min.
0
0.6
1.3
0.6
0.6
0.04
100
20 + 0.1 C b
20 + 0.1 C b
0.6
1.3
-
Typ.
-
Figure 7. I²C timing diagram t f
V ih
SDA
V il t hd,sta t r t su,dat t high
SCL t low t hd,dat t su,sto
Max.
400
-
-
-
-
0.9
-
300
300
-
-
400
STUSB4500L
Timing specifications
Unit kHz
μs ns
μs pF
DS13102 - Rev 5 page 13/32
STUSB4500L
Start-up configuration
5
Start-up configuration
5.1
5.2
User-defined parameters
The STUSB4500L has a set of user-defined parameters that can be customized by NVM re-programming through the I
2
C interface. This feature allows the customer to change the preset configuration of the USB Type-C interface and to define a new configuration to meet specific application requirements addressing various use cases, or specific implementations.
The NVM re-programming overrides the initial default setting to define a new default setting that is used at power-up or after a reset. The default setting is copied at power-up, or after a reset, from the embedded NVM into
I 2 C registers. The values copied in the I 2 C registers are used by the STUSB4500L during the system operation.
The NVM re-programming is possible with a customer password. The I 2 C registers must be re-initialized after each NVM re-programming to make effective the new parameters setting either through power-off and power-up sequence, or through reset.
Default start-up configuration
The table below lists the user-defined parameters and indicates the default start-up configuration of the
STUSB4500L.
Table 13. STUSB4500L user-defined parameters and default settings
Parameter name Parameter description
Reset value
(default)
Value Description
SHIFT_VBUS_HIGH_LIMIT
Coefficient to shift up nominal
V
BUS
high voltage limit applicable to 5 V
VBUS_DISCH_TIME_TO_0V
Coefficient used to compute
V
BUS
discharge time to 0 V
VBUS_DISCH_DISABLE
GPIO_CFG[1:0]
VBUSdischarge deactivation on
VBUS_VS_DISCH and DISCH pins
Selects GPIO pin configuration
)
1010b
(10%)
1001b
(9)
0b
11b
0000b to
1111b
0% ≤ V
SHUSBH
≤ 15% of VBUS by increment of 1%
Default V
SHUSBH
= 10%
0001b to
1111b
1 ≤ T
DISPAR0V of 1
≤ 15 by increment
Unit discharge time: 84 ms (typ.)
Default coefficient T
DISPAR0V
= 9, discharge time T
DISUSB0V
= 756 ms
0b
1b
V
BUS
discharge enabled
V
BUS
discharge disabled
SW_CTRL_GPIO 00b
01b
10b
11b
ERROR_RECOVERY
DEBUG
SINK_POWER (default)
DS13102 - Rev 5 page 14/32
6
6.1
6.1.1
6.1.2
STUSB4500L
Application
Application
The sections below are not part of the ST product specifications. They are intended to give a generic application overview to be used by the customer as a starting point for further implementation and customization. ST does not warrant compliance with customer specifications. Full system implementation and validation are under the customer’s responsibility.
General information
•
•
•
Power supplies
The STUSB4500L can be supplied in three different ways depending on the targeted application:
Through the VDD pin only for applications powered by V
BUS
that operate with dead battery mode support
Through the VSYS pin only for AC powered applications with a system power supply delivering from 3.3 V up to 5 V
Through the VDD and VSYS pins either for applications powered by a battery with dead battery mode support or for applications powered by V
BUS
with a system power supply delivering 3.3 V or 5 V. When both
VDD and VSYS power supplies are present, the low power supply VSYS is selected when VSYS voltage is above 3.1 V. Otherwise VDD is selected
When possible, please prefer VDD supply only, and connect it to VBUS in order to minimize application power consumption. In this case, VSYS is not used and must be connected to GND.
Connection to MCU or application processor
The STUSB4500L connection to an MCU or an application processor is optional. However, an I²C interface with an interrupt allows a simple connection to most of MCU and SOC of the market.
When a connection through the I²C interface is implemented, it provides an extensive functionality during the system operation. For instance, it may be used to:
1.
Define the port configuration during system boot (in case the NVM parameters are not customized during manufacturing)
2.
Provide a diagnostic of the Type-C connection in real time
At power-up or after a reset, the first software access to the I 2 C registers of the STUSB4500L can be done only after T
LOAD as shown in the figure below. T
LOAD
corresponds to the time required to initialize the I 2 C registers with the default values from the embedded NVM. At power-up, the loading phase starts when the voltage level on the
VREG_1V2 output pin of the 1.2 V internal regulator reaches 1.08 V to release the internal POR signal. After a reset, the loading phase starts when the signal on the RESET pin is released.
Figure 8. I 2 C register initialization sequence at power-up or after a reset
At power-up
Power On Reset I 2 C registers loading from NVM I 2 C access Reset
After a reset
I 2 C registers loading from NVM I 2 C access
VSYS or VDD VSYS or VDD
1.08 V
VREG_1V2 VREG_1V2
POR
I 2 C (SCL,SDA)
RESET
I 2 C (SCL,SDA)
T
LOAD
T
LOAD
DS13102 - Rev 5 page 15/32
STUSB4500L
Typical application
6.2
Typical application
Figure 9. Implementation example
VBUS
STL9P3LLH6
R2
1K
R1
100K
VBUS
VBUS
USB_DM
USB_DP
CC2
D1
GND GND
B12
GND
B11
Rx+1
B10
Rx-1
B9
Vbus
B8
Sbu2
B7
D-2
B6
D+2
B5
CC2
B4
Vbus
B3
Tx-2
B2
Tx+2
B1
GND
USB3
TYPE C
GND
Vbus
A1
Tx+1
Tx-1
Sbu1
A2
A3
Vbus
A4
CC1
A5
D+1
A6
D-1
A7
A8
A9
Rx-2
A10
Rx+2
A11
GND
A12
J1
USB3-C
CC1
USB_DP
USB_DM
GND
VBUS
C2
1µF
GND
C3
1µF
D2
ESDA25L
2V7
1V2
GND
U_stusb4500L
23
VREG_2V7
21
VREG_1V2
22
VSYS
3
Not_Used
10
GND
1
CC1DB
2
CC1
4
CC2
VDD 24
VBUS_VS_DISCH 18
RP_3A 20
VBUS_EN_SNK 16
A_B_SIDE 17
DISCH 9
GPIO 15
RP_1A5 14
5
CC2DB
6
RESET
SDA 7
SCL
SCL 8
SDA
ADDR1 13
ADDR0 12
ATTACH 11
ALERT 19
GND
ILIM_3A0
ILIM _1A5
Alert
C1
1µF
GPIO can be configured to flag hardware fault, if system needs to be informed
R3
20K
GND
STUSB4500L
GND
GND GND
R7
10K
GND
V3V3
R8
10K
V3V3
R9
10K
SDA
SCL
Alert
MCU
OPTIONAL
R4
1K
(Optional)
VBUS_SYS
USB_DP
USB_DM
C4
BatteryCharger
Cap
100pF
L1
Inductor
10mH
INM _ILIM
GND
ILIM_3A0
R5
130
VSYS
VSYS
ILIM _1A5
R6
130
R10
520
GND
Note: The STUSB4500L can be connected to an application processor using I²C interface. This connection is optional.
DS13102 - Rev 5 page 16/32
STUSB4500L
Electrical characteristics
7
Electrical characteristics
7.1
7.2
Absolute maximum ratings
All voltages are referenced to GND.
Symbol
V
DD
V
SYS
V
CC1,
V
CC2
V
CC1DB,
V
CC2DB
V
VBUS_EN_SNK
V
VBUS_VS_DISCH
V
DISCH
V
RP_3A
V
SCL,
V
SDA
V
ALERT
V
RESET
V
ATTACH
V
A_B_SIDE
V
RP_1A5
V
GPIO
V
ADDR0,
V
ADDR1
T
STG
T
J
ESD
Table 14. Absolute maximum ratings
Parameter
Supply voltage on VDD pin
Supply voltage on VSYS pin
Value
28
6
High voltage on CC pins 22
High voltage on V
BUS
pins
Operating voltage on I/O pins
Storage temperature
Maximum junction temperature
HBM
CDM
28
-0.3 to 6
-55 to 150
145
3
1.5
Operating conditions
V
DD
V
SYS
V
CC1,
V
CC2
V
CC1DB,
V
CC2DB
V
VBUS_EN_SNK
V
VBUS_VS_DISCH
Symbol
Table 15. Operating conditions
Parameter
Supply voltage on VDD pin
Supply voltage on VSYS pin
CC pins
High voltage pins
Value
3.3 to 6
3.0 to 5.5
0 to 5.5
0 to 22
Unit
V
°C kV
Unit
V
DS13102 - Rev 5 page 17/32
Value
STUSB4500L
Operating conditions
Unit
V
DISCH
V
RP_3A
V
SCL,
V
SDA
V
ALERT
V
RESET
V
ATTACH
V
A_B_SIDE
V
RP_1A5
V
GPIO
V
ADDR0,
V
ADDR1
T
A
Symbol Parameter
Operating voltage on I/O pins
Operating temperature
V
0 to 4.5
-40 to 105 °C
DS13102 - Rev 5 page 18/32
7.3
STUSB4500L
Electrical and timing characteristics
Electrical and timing characteristics
Unless otherwise specified: V
DD
= 5 V, T
A
= 25 °C, all voltages are referenced to GND.
Table 16. Electrical characteristics
Symbol Parameter Conditions Min.
Typ.
Max.
I
DD (SNK)
Current consumption
Device connected to VBUS
V
DD
@ VBUS level
110 160 210
T
LOAD
I 2 C registers loading time from NVM
At power-up or after a reset 30
R d
R
INCC
CC pull-down resistors
CC input impedance
-40 °C < T
A
CC1 and CC2 pins
< +105 °C
Terminations off
-10%
200
5.1
+10%
V
TH0.2
V
TH0.66
V
TH1.23
V
TH2.6
Detection threshold 1
Detection threshold 2
Detection threshold 3
Detection threshold 4
Min. I
P-USB
detection by sink on R
CC voltage for connected sink d
, min
Min. I
Min. I
P_1.5
detection by sink on R d
P_3.0
detection by sink on Rd
Max. CC voltage for connected sink
0.15
0.61
1.16
2.45
0.20
0.66
1.23
2.60
0.25
0.71
1.31
2.75
V
OVP
Overvoltage protection on
CC pins
5.82
6 6.18
VBUS_VS_DISCH pin monitoring and driving
V
THUSB
V
BUS
disconnection threshold
V
DD
@ 5 V 3.2
3.3
3.4
I
T
DISUSB
V
DISUSB0V
MONUSBH
V
V
BUS
BUS
discharge current
discharge time to 0 V
V
BUS
monitoring high voltage limit
Through external resistor connected to
VBUS_VS_DISCH pin
At detachment, during error recovery state.
Coefficient T
DISPAR0V
programmable by
NVM,
Default T
DISPAR0V
= 9, T
DISUSB0V ms
= 756
V
BUS
+5% is nominal high voltage limit,
Shift coefficient V
SHUSBH
is programmable by NVM from 0% to 15% of V
BUS
by step of 1%
Default
V
SHUSBH
V
BUS
= 10%, V
+15%
MONUSBH
=
DISCH pin driving
*T
70
DISPAR0V
*T
V
+V
84
DISPAR0V
BUS
+5%
SHUSBH
*T
50
100
DISPAR0V
I
DISPWR
Power system discharge current
Through external resistor connected to
DISCH pin
500
Digital input/output (SCL, SDA, ALERT, RESET, ATTACH, A_B_SIDE, RP_1A5, GPIO, ADDR0, ADDR1)
V
IH
V
IL
V
OL
High level input voltage
Low level input voltage
Low level output voltage Ioh = 3 mA
1.2
0.35
0.4
20 V open drain outputs (VBUS_EN_SNK, DISCH, RP_3A)
Unit
µA ms kΩ kΩ
V
V
V
V
V
V mA ms
V mA
V
V
V
DS13102 - Rev 5 page 19/32
Symbol
V
OL
Parameter
Low level output voltage Ioh = 3 mA
Conditions
STUSB4500L
Electrical and timing characteristics
Min.
Typ.
Max.
0.4
Unit
V
DS13102 - Rev 5 page 20/32
8
8.1
STUSB4500L
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
QFN-24 EP (4x4) package information
Figure 10. QFN-24 EP (4x4) package information
D
0.08 C
TOP VIEW
SIDE VIEW e b
SEATING
PLANE
C
Pin#1 ID
D2
BOTTOM VIEW
L
DS13102 - Rev 5 page 21/32
Ref.
K
L
E
E2 e
A
A1 b
D
D2
STUSB4500L
QFN-24 EP (4x4) package information
Min.
3.95
2.55
0.45
0.15
0.30
0.80
0.00
0.18
3.95
2.55
Table 17. QFN-24 EP (4x4) package mechanical data mm
Typ
4.00
2.70
0.50
-
0.40
0.90
0.02
0.25
4.00
2.70
Max.
4.05
2.80
0.55
-
0.50
1.00
0.05
0.30
4.05
2.80
Min.
0.156
0.100
0.018
0.006
0.012
0.031
0.000
0.007
0.156
0.100
Inches
Typ.
0.035
0.001
0.0010
0.157
0.106
0.157
0.106
0.020
-
0.016
Figure 11. QFN-24 EP (4x4) recommended footprint
Max.
0.159
0.110
0.022
-
0.020
0.039
0.002
0.012
0.159
0.110
DS13102 - Rev 5 page 22/32
8.2
STUSB4500L
WLCSP (2.6x2.6x0.5) 25 bumps package information
WLCSP (2.6x2.6x0.5) 25 bumps package information
Figure 12. WLCSP (2.6x2.6x0.5) package outline
DS13102 - Rev 5 page 23/32
Note:
STUSB4500L
WLCSP (2.6x2.6x0.5) 25 bumps package information
Symbol e b n
D
E1
D1
A
A1
A2
A3
E aaa bbb ccc ddd
Table 18. WLCSP (2.6x2.6x0.5) package mechanical data
Min.
mm
Typ.
0.456
0.179
0.255
0.022
2.563
2.563
0.245
25
Tolerance of form and position
0.03
0.06
0.05
0.015
0.50
195
0.28
0.025
2.593
2.593
1.6 BSC
1.6 BSC
0.4 BSC
Max.
0.544
0.211
0.305
0.028
2.623
2.623
0.295
WLCSP stands for wafer level chip scale package. The typical ball diameter before mounting is 0.25 mm. The terminal A1 corner must be identified on the top surface by using a laser marking dot.
Figure 13. WLCSP (2.6x2.6x0.5) recommended footprint
DS13102 - Rev 5 page 24/32
8.3
Thermal information
Symbol
R
θJA
R
θJC
Table 19. Thermal information
Parameter
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
Value
37
5
STUSB4500L
Thermal information
Unit
°C/W
DS13102 - Rev 5 page 25/32
9
STUSB4500L
Terms and abbreviations
Terms and abbreviations
Term
Accessory mode
DFP
DRP
Sink
Source
UFP
Table 20. List of terms and abbreviations
Description
Debug accessory mode. It is defined by the presence of pull-up resistors R p
CC1/CC2 pins in sink power role.
/R p on
Downstream facing port, specifically associated with the flow of data in a USB connection. Typically the ports on a HOST or the ports on a hub to which devices are connected. In its initial state, the DFP sources V
BUS
and optionally V
CONN
, and supports data.
Dual-role port. A port that can operate as either a source or a sink. The port role may be changed dynamically.
Port asserting R d
on the CC pins and consuming power from the V
BUS
.
Port asserting R p
on the CC pins and providing power over the V
BUS
.
Upstream facing port, specifically associated with the flow of data in a USB connection. The port on a device or a hub that connects to a host or the DFP of a hub. In its initial state, the UFP sinks V
BUS
and supports data.
DS13102 - Rev 5 page 26/32
STUSB4500L
Revision history
Date
10-Oct-2019
22-Oct-2019
29-Apr-2020
08-Jun-2020
15-Jun-2021
Table 21. Document revision history
Revision
1
2
3
4
5
Changes
Initial release.
Added Figure 13. WLCSP (2.6x2.6x0.5) recommended footprint
.
Added Section 3.5 High voltage protections .
Updated
(2.6x2.6x0.5) recommended footprint
Updated
DS13102 - Rev 5 page 27/32
STUSB4500L
Contents
Contents
DS13102 - Rev 5 page 28/32
STUSB4500L
Contents
DS13102 - Rev 5 page 29/32
STUSB4500L
List of tables
List of tables
DS13102 - Rev 5 page 30/32
STUSB4500L
List of figures
List of figures
DS13102 - Rev 5 page 31/32
STUSB4500L
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
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ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13102 - Rev 5 page 32/32
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