STMicroelectronics STUSB1602 Datasheet
বিজ্ঞাপন
বিজ্ঞাপন
STUSB1602
Datasheet
USB Type-C™ controller with TX/RX line driver and BMC
Device summary
Order code STUSB1602AQTR
Power role
Package
SOURCE, SINK, DRP
QFN24 EP 4x4 mm
Temp. range
Marking
- 40 °C up to 105 °C
1602A
Related products
STM32F072RB and STSW-STUSB010
STM32F446ZE and STSW-STUSB012
STM32G474RE and STSW-STUSB014
STM32L4R5ZI and STSW-STUSB015
Features
• Type-C™ attach and cable orientation detection
• Power role support: source/sink/DRP
• Integrated power switch for V
CONN
supply:
– programmable current limit up to 600 mA
– overcurrent, overvoltage, and thermal protection
– undervoltage lockout
• Integrated V
BUS
voltage monitoring
• Integrated V
BUS
and V
CONN
discharge path
• Integrated BMC transceiver
• V
BUS
switch gate driver
• Short-to-V
BUS
protection on CC
• Dual power supply (V
SYS
and/or V
DD
):
– V
SYS
= [3.0 V; 5.5 V]
– V
DD
= [4.1 V; 22 V]
• Compliant with:
– USB Type-C™ rev 2.0
– USB PD rev 3.0
• Certified:
– Source: TID 1070031
– Sink PPS: TID 5477
Applications
• Power hubs and docking stations
• Smartphones, tablets and gimbal stabilizers
• Gaming, PNDs and drones
• Cameras, camcorders, and MP3 players
• Smart plugs, wall adapters, and chargers
• Power sourcing devices (PoE)
• Power sinking hosts
• PPS applications
• Any source or sink or dual role device
Description
The STUSB1602 is a generic IC, in a 20 V technology it addresses a USB Type-C™ port management both for source, sink and dual role devices, with or without USB data. It is designed for a broad range of applications and can handle the following
USB Type-C functions: attach detection, plug orientation detection, host to device connection, V
CONN
support, and V
BUS
configuration.
It also provides a USB PD TX/RX line driver and a BMC (bi-phase mark coding) transceiver which enable USB PD communication through an external MCU.
DS11254 - Rev 5 - July 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STUSB1602
Functional description
Functional description
•
•
•
The STUSB1602 is a high voltage standalone USB Type-C controller also acting as a USB PD TX/RX physical layer for an external MCU. It is designed to interface with the Type-C receptacle on host side. It is used to establish and manage the source-to-sink connection between two USB Type-C host and device ports.
The STUSB1602 major role is to:
1.
Detect the connection between two USB Type-C ports (attach detection)
2.
Establish a valid source-to-sink connection
3.
Determine the attached device mode: source, sink or accessory
4.
Resolve cable orientation and twist connections to establish USB data routing (MUX control)
5.
Configure and monitor V
BUS
power path
6.
Manage V
BUS
power capability: USB default, Type-C medium or Type-C high current mode
7.
Configure V
CONN
when required
•
•
8.
Support USB PD negotiation
The STUSB1602 also provides:
Dead battery mode
I²C interface and interrupt
Start-up configuration customization: static through NVM and/or dynamic through I²C
High voltage protection
Accessory mode detection
Figure 1. Functional block diagram
DS11254 - Rev 5 page 2/39
STUSB1602
Inputs / outputs
2
Inputs / outputs
2.1
Pinout
Figure 2. STUSB1602 pin connections
CC1DB
CC1
VCONN
CC2
CC2DB
RESET
4
5
2
3
1
24 23 22 21 20 19
18
17
16
EP
15
14
6
7 8 9 10 11 12
13
VBUS_SENSE
A_B_SIDE
SCLK
TX_EN
MISO
ADDR0
2.2
Pin list
8
9
10
6
7
Pin
1
2
3
4
5
11
12
Name
CC1DB
CC1
VCONN
CC2
CC2DB
RESET
SCL
SDA
ALERT#
GND
MOSI
NSS
Type
HV AIO
HV AIO
PWR
HV AIO
HV AIO
DI
DI
DI/OD
OD
GND
DO
OD
Table 1. Pin functions list
Description
Dead battery enable on CC1 pin
Type-C configuration channel 1
Power input for active plug
Type-C configuration channel 2
Dead battery enable on CC2 pin
Reset input (active high)
I²C clock input
I²C data input/output, active low open drain
I²C interrupt, active low open drain
Ground
Master out slave in: serial data from
STUSB1602 to MCU, BMC decoded from connected CC line
Chip select, open drain active low to control
MCU SPI/MSP interface
Typical connection
CC1 pin if used or ground
Type-C receptacle A5
5 V power source
Type-C receptacle B5
CC2 pin if used or ground
To I²C master, ext. pull-up
To I²C master, ext. pull-up
To I²C master, ext. pull-up
Ground
To MCU, ext. pull-up referenced to
MCU Vio
To MCU, ext. pull-up referenced to
MCU Vio
DS11254 - Rev 5 page 3/39
DS11254 - Rev 5
STUSB1602
Pin list
Pin
13
14
15
16
17
18
19
20
21
22
23
24
-
Name
ADDR0
MISO
TX_EN
SCLK
A_B_SIDE
VBUS_SENSE
VBUS_EN_SNK
VBUS_EN_SRC
VREG_1V2
VSYS
VREG_2V7
VDD
EP
Type
DI
DI
DI
DO
OD
HV AI
HV AIO
HV AIO
PWR
PWR
PWR
HV PWR
GND
Description Typical connection
I²C device address setting (see Section 5 I²C interface )
Master in slave out: serial data from MCU to
STUSB1602 encoded in BMC to drive the CC line
Static
From MCU, ext. pull-up referenced to MCU Vio
TX enable, open drain active high to drive CC line from the embedded BMC interface
From MCU, needs to be maintained low by MCU or pulled down when receiving standby
Serial clock to clock data transfer between
MCU and the STUSB1602. Open drain output pin, needs external pull-up referenced to MCU
Vio
To MCU, ext. pull-up referenced to
MCU Vio
Cable orientation, active low open drain
USB super speed MUX select, ext.
pull-up
From V
BUS
V
BUS
voltage monitoring and discharge path
VBUS sink power path enable, active low open drain
V
BUS
source power path enable, active low open drain
1.2 V internal regulator output
To switch or power system, ext.
pull-up
To switch or power system, ext.
pull-up
Power supply from system
2.7 V internal regulator output
Main power supply from USB power line
Exposed pad is connected to ground
1 µF typ. decoupling capacitor
From power system, connect to ground if not used
1 µF typ. decoupling capacitor
From V
BUS
To ground
PD
PU
HV
PWR
GND
Type
D
A
O
I
IO
OD
Table 2. Pin function descriptions
Description
Digital
Analog
Output pad
Input pad
Bidirectional pad
Open drain output
Pull-down
Pull-up
High voltage
Power
Ground page 4/39
2.3
2.3.1
2.3.2
Note:
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
STUSB1602
Pin description
Pin description
CC1 / CC2
CC1 and CC2 are the configuration channel pins used for connection and attachment detection, plug orientation determination and system configuration management across USB Type-C cable.
CC1DB/CC2DB
CC1DB and CC2DB are used for dead battery mode when the STUSB1602 is configured in sink power role or dual power role. This mode is enabled by connecting CC1DB and CC2DB respectively to CC1 and CC2. Thanks to this connection, the pull down terminations on the CC pins are present by default even if the device is not supplied (see
CC1DB and CC2DB must be connected to ground when the STUSB1602 is configured in source power role or when dead battery mode is not supported.
VCONN
This power input is connected to a power source that can be a 5 V power supply. It is used to provide power to the local plug. It is internally connected to power switches that are protected against short-circuit and overvoltage.
This does not require any protection on the input side. When a valid source-to-sink connection is determined and the V
CONN
power switches are enabled, V
CONN
is provided by the source to the unused CC pin (see
). If not used, VCONN can be left floating.
RESET
Active high reset.
I²C interface pins
Name
SCL
SDA
ALERT#
ADDR0
Table 3. I²C interface pins list
Description
I²C clock – need external pull-up
I²C data – need external pull-up
I²C interrupt – need external pull-up
I²C device address bit (see
)
GND
Ground.
MOSI
Master out slave in: data from the connected CC line are decoded using the BMC and then transmitted via the
STUSB1602 to the MCU. Data are valid on the falling edge of the SCLK line and must be sampled by the MCU on this edge.
•
•
NSS
The chip select signal is driven by the STUSB1602 and is connected to the MCU. It activates the SPI/MSP interface transfer. The NSS signal drives the MCU so that:
When TX_EN is asserted (TX mode), the STUSB1602 transmits data from the MCU over the CC line. Note, the MCU must provide data to be encoded on the MISO line which must be in synchrony with the SCLK
When TX_EN is not asserted (RX mode, default), the CC line is activity detected, data are received, and the
BMC is decoded by the STUSB1602. Decoded data are sent on the MOSI line in synchrony with the SCLK
DS11254 - Rev 5 page 5/39
STUSB1602
Pin description
2.3.9
2.3.10
Note:
2.3.11
2.3.12
2.3.13
2.3.14
2.3.15
2.3.16
2.3.17
2.3.18
MISO
Master in slave out: data from the MCU are encoded using the BMC and then transmitted via the STUSB1602 to the connected CC line driver. Data are sampled by the STUSB1602 on the rising edge of the SCLK line and must be stable on this edge.
TX_EN
TX_EN is a control signal from the MCU to the STUSB1602. It enables the BMC control logic that transfers data from the MCU serial interface, encodes it in BMC format, and drives the connected CC line.
TX mode overrides RX mode.
SCLK
The serial clock signal from the STUSB1602 drives the SPI/MSP interface of the MCU and the clock data on the
MISO and MOSI pins.
A_B_SIDE
This output pin provides cable orientation. It is used to establish USB SuperSpeed signal routing. The cable orientation is also provided by an internal I²C register. This signal is not required if no data support or USB 2.0
supports only.
Value
HiZ
0
Table 4. USB data MUX select
CC pin position
CC1 pin is attached to CC line
CC2 pin is attached to CC line
VBUS_SENSE
This input pin is used to sense V
BUS
presence, monitor V
BUS
voltage and discharge V
BUS
on USB Type-C receptacle side.
VBUS_EN_SNK
In sink power role, this pin allows the incoming VBUS power to be enabled when the connection to a source is established and VBUS is in a valid operating range. The open drain output allows a PMOS transistor to be directly driven. The logic value of the pin is also advertised in a dedicated I²C register bit.
VBUS_EN_SRC
In source power role, this pin allows the outgoing V
BUS
power to be enabled when the connection to a sink is established and V
BUS
is in a valid operating range. The open drain output allows a PMOS transistor to be directly driven. The logic value of the pin is also advertised in a dedicated I²C register bit.
VREG_1V2
This pin is used only for external decoupling of 1.2 V internal regulator. The recommended decoupling capacitor is: 1 µF typ. (0.5 µF min.; 10 µF max.).
VSYS
This is the low power supply of the system, if there is any. It can be connected directly to a system power supply delivering 3.3 V or 5 V. It is recommended to connect this pin to ground when it is not used.
VREG_2V7
This pin is used for external decoupling of the 2.7 V internal regulator. The recommended decoupling capacitor is:
1 µF typ. (0.5 µF min., 10 µF max.).
DS11254 - Rev 5 page 6/39
STUSB1602
Pin description
2.3.19
VDD
This is the power supply from the USB power line for applications powered by V
BUS
.
In source power role, this pin can be used to sense the voltage level of the main power supply providing the V
BUS
It allows UVLO and OVLO thresholds to be considered independently on the VDD pin as additional conditions to
.
enable the V
BUS
power path through the VBUS_EN_SRC pin (see
Section 3.3.3 VBUS power path assertion ).
When the UVLO threshold detection is enabled, the VDD pin must be connected to the main power supply to establish the connection and to assert the V
BUS
power path.
DS11254 - Rev 5 page 7/39
STUSB1602
General description
3
General description
3.1
3.2
CC interface
The STUSB1602 controls the connection to the configuration channel (CC) pins, CC1 and CC2, through two main blocks: the CC line interface block and the CC control logic block.
•
•
The CC line interface block is used to:
• Configure termination mode on the CC pins relative to the power mode supported i.e. pull-up for source power role
•
Monitor the CC pin voltage values relative to the attachment detection thresholds
Configure V
CONN
on the unconnected CC pin when required
Protect the CC pins against overvoltage
•
•
•
•
•
•
The CC control logic block is used to:
• Execute the Type-C FSM relative to the Type-C power mode supported
Determine the electrical state for each CC pin relative to the detected thresholds
Evaluate the conditions relative to the CC pin states and the V
BUS to another in the Type-C FSM
voltage value to transition from one state
Detect and establish a valid source-to-sink connection
Determine the attached device mode: source, sink or accessory
•
Determine cable orientation to allow external routing of the USB data
Manage V
BUS
power capability: USB default, Type-C medium or Type-C high current mode
Handle hardware faults
•
•
The CC control logic block implements the Type-C FSMs corresponding to the following Type-C power modes:
• Source power role with accessory support
• Sink power role with accessory support
Sink power role without accessory support
Dual power role with accessory support
The default Type-C power mode is selected through NVM programming (see
Section 6 Start-up configuration
) and can be changed by software during operation through the I²C interface.
BMC interface
Figure 3. BMC interface
DS11254 - Rev 5 page 8/39
3.2.1
3.2.2
3.2.3
3.3
3.3.1
STUSB1602
VBUS power path control
BMC interface behavior
When a connection is established on the STUSB1602 (any attached state), the CC line used for connection is also internally connected to BMC block which allows the communication on this line.
The CC line is primary managed by CC control logic. BMC communication on the CC line must not interact with this control logic, as driving times of the line are short and are related to denounce times of the CC logic.
BMC block handles BMC encoding and decoding. It also handles CC line activity detection, discharging the external MCU of such operations.
The default state of the BMC block is to listen to the line (RX mode). TX mode is enabled only by assertion of the
TX_EN signal via the external MCU.
TX mode
•
•
When the TX_EN signal is asserted via MCU, BMC block goes to the TX state:
• NSS signal is driven low, indicating to the SPI/MSP slave interface of the MCU that data are being transmitted on the CC line. MCU provides the data
• The STUSB1602 drives the NSS signal low, informing SPI/MSP slave interface of the MCU that data are requested on the MISO line
The STUSB1602 clocks the SCLK signal
•
MCU presents data to be transmitted on the MISO line and data are sampled on the rising edge of SCLK
(data must be stable on this edge)
Sampled data (from MISO line) are encoded by the BMC, and the resulting values drive the CC line according to USB PD standard
When all data are transmitted, MCU drives the TX_EN pin low, and lists the end of transmission. The STUSB1602 ends transmission with a corresponding trailing edge termination. It then goes back into to default state and releases the CC line from the BMC driver to the pull-up/pull-down CC line interfaces.
RX mode
RX mode is the default state of the BMC interface.
In this mode, the receiver listens to the connected CC line. It does not interface with the CC line interfaces or the
CC control logic.
•
•
When all data are detected and received on the CC line, according to the activity described in the USB Power
Delivery Standard, the BMC interface:
•
Drives NSS signal low
Outputs the clock on the SCLK signal which is recovered from the BMC signal
Outputs recovered data (from the BMC signal) on the MOSI line to the connected MCU. Data are valid on the SCLK falling edge and are sampled on this edge by the SPI/MSP interface of MCU
When no more data are detected on the CC line, the NSS goes back to “high” which is its default state. This informs the MCU that no more activity is present on the bus.
V
BUS
power path control
V
BUS
monitoring
The V
BUS
monitoring block supervises from the VBUS_SENSE pin the V
BUS receptacle side.
voltage on the USB Type-C
•
•
It is used to check that the V
BUS
is within a valid voltage range:
To establish a valid source-to-sink connection according to USB Type-C standard specifications
To safely enable the VBUS power path through the VBUS_EN_SRC pin or VBUS_EN_SNK pin depending on the power role.
DS11254 - Rev 5 page 9/39
STUSB1602
VBUS power path control
3.3.2
3.3.3
It allows detection of unexpected V
BUS
voltage conditions such as undervoltage or overvoltage relative to the valid
V
BUS
voltage range. When such conditions occur, the STUSB1602 reacts as follows:
•
•
At attachment, it prevents the source-to-sink connection and the V
BUS
power path assertion
After attachment, it deactivates the source-to-sink connection and disables the V
BUS
power path. In source power role, the device goes into error recovery state. In sink power role, the device goes into unattached state.
The V
BUS
voltage value is adjusted automatically at attachment (vSafe5V) and via MCU at each PDO transition.
Monitoring is then disabled during T_PDO_transition (i.e. the default value of 300 ms is changed through NVM programming). Additionally, if a transition occurs to a lower voltage, the discharge path is activated during this time.
The valid V
BUS
voltage range is defined from the V
BUS
nominal voltage by a high threshold voltage and a low threshold voltage whose nominal values are respectively V
BUS
+5% and V
BUS
-5%. The nominal threshold limits can be shifted by a fraction of V
BUS
from +1% to +15% for the high threshold voltage and from -1% to -15% for the low threshold voltage. This means the threshold limits can vary from V
BUS
+5% to V
BUS
+20% for the high limit and from V
BUS
-5% to V
BUS
-20% for the low limit.
). The threshold limits can be changed independently through NVM programming (see
Section 6 Start-up configuration
) and also by software during attachment through the I²C interface.
V
BUS
discharge
The monitoring block also handles the internal V
BUS
discharge path connected to the VBUS_SENSE pin. The discharge path is activated at detachment, or when the device goes into the error recovery state whatever the power role (see
Section 3.7 Hardware fault management ).
The V
BUS
discharge path is enabled by default in NVM and can be disabled through NVM programming only
(see
Section 6 Start-up configuration
). The discharge time duration is also preset by default in NVM (see
Section 8.3 Electrical and timing characteristics
). The discharge time duration can be changed through NVM
programming (see Section 6 Start-up configuration ) and also by software through the I²C interface.
V
BUS
power path assertion
The STUSB1602 can control the assertion of the V
BUS
power path on the USB Type-C port, directly or indirectly, through the VBUS_EN_SRC pin and VBUS_EN_SNK pins according to the system power role.
The tables below summarize the configurations and the operation conditions that determine the electrical value of the VBUS_EN_SRC and VBUS_EN_SNK pins during system operations.
Pin
VBUS_EN_SRC
Electrical value
0
HiZ
Table 5. Conditions for V
BUS
power path assertion in source power role
Type-C attached state
Attached.SRC or
UnorientedDebug
Accessory.SRC
or OrientedDebug
Accessory.SRC
Any other state
Operation conditions
VDD pin monitoring
VDD > UVLO if
VDD_UVLO enabled and/or
VDD < OVLO if
VDD_OVLO enabled
VDD < UVLO if
VDD_UVLO enabled and/or
VDD > OVLO if
VDD_OVLO enabled
Comment
VBUS_SENSE pin monitoring
V
BUS
is within valid voltage range if
VBUS_VALID_RANGE enabled or
V
BUS
> UVLO if
V
BUS
_VALID_RANGE disabled
The signal is asserted only if all the valid operation conditions are met
V
BUS
is out of valid voltage range if
VBUS_VALID_RANGE enabled or
VBUS < UVLO if
V
BUS
_VALID_RANGE disabled
The signal is deasserted when at least one non valid operation condition is met
As specified in the USB Type-C standard specification, the attached state “Attached.SRC” is reached only if the voltage on the V
BUS
receptacle side is at vSafe0V condition when a connection is detected.
DS11254 - Rev 5 page 10/39
STUSB1602
VCONN supply
3.4
Pin
VBUS_EN_SNK
Table 6. Conditions for VBUS power path assertion in sink power role
Electrical value
0
Hiz
Type-C attached state
Attached.SNK
or
Debug
Accessory.SNK
Any other state
Operation conditions
VDD pin monitoring
Not applicable
Not applicable
VBUS_SENSE pin monitoring
VBUS is within valid voltage range if
VBUS
_VALID_RANGE enabled or
VBUS > UVLO if
VBUS
_VALID_RANGE disabled
VBUS is out of valid voltage range if
VBUS
_VALID_RANGE enabled or
VBUS < UVLO if
VBUS
_VALID_RANGE disabled
Comment
The signal is asserted only if all the valid operation conditions are met
The signal is deasserted when at least one non valid operation condition is met
“Type-C attached state” refers to the Type-C FSM states as defined in the USB Type-C standard specification and as described in the I²C register CC_OPERATION_STATUS.
“VDD pin monitoring” is valid only in source power role. Activation of the UVLO and OVLO threshold detections
can be done through NVM programming (see Section 6 Start-up configuration
) and also by software through the I²C interface. When UVLO and/or OVLO threshold detection is activated, VBUS_EN_SRC pin is asserted only if the device is attached and the valid threshold conditions on VDD are met. Once the VBUS_EN_SRC pin is asserted, the V
BUS
monitoring is done on VBUS_SENSE pin instead of the VDD pin.
“VBUS_SENSE pin monitoring” relies, by default, on a valid V
BUS
voltage range. The voltage range condition can be disabled to consider UVLO threshold detection instead. The monitoring condition of the V
BUS
voltage can be changed through NVM programming (see
Section 6 Start-up configuration ) and also by software through the
I²C interface. VBUS_EN_SRC pin is maintained asserted as long as the device is attached and a valid voltage condition on the V
BUS
is met.
3.4.1
3.4.2
V
CONN
supply
V
CONN
input voltage
V
CONN
is a regulated supply used to power circuits in the plug of USB3.1 full-featured cables and other accessories. V
CONN
nominal operating voltage is 5.0 V +/- 5%.
V
CONN
application conditions
V
CONN
pin of the STUSB1602 is connected to each CC pin (CC1 and CC2) across independent power switches.
The STUSB1602 applies V
CONN
only to the CC pin not connected to the CC wire when all below conditions are met:
DS11254 - Rev 5 page 11/39
3.4.3
3.4.4
3.4.5
3.4.6
STUSB1602
VCONN supply
•
•
•
•
•
The device is configured in source power role
V
CONN
power switches are enabled
A valid connection to a sink is achieved
R a
presence is detected on the unwired CC pin
A valid power source is applied to the V
CONN
pin with respect to a predefined UVLO threshold
The STUSB1602 does not provide V
CONN
when it is in sink power role.
V
CONN
monitoring
The V
CONN
monitoring block detects if V
CONN
power supply is available on the V
CONN
pin. It is used to check that
V
CONN
voltage is above a pre-defined undervoltage lockout (UVLO) threshold to allow the enabling of the V
CONN power switches.
The default value of the UVLO threshold is 4.65 V typical for powered cables operating at 5 V. This value can be changed by software to 2.65 V typical to support V
CONN
-powered accessories that operate down to 2.7 V.
V
CONN
discharge
The behavior of Type-C FSMs is extended to an internal V
CONN
discharge path capability on the CC pins in source power mode only. The discharge path is activated during 250 ms from sink detachment detection.
) and also by software through the I²C interface.
V
CONN
control and status
The supplying conditions of V
CONN
across the STUSB1602 are managed through the I²C interface. Different I²C registers and bits are used specifically for this purpose.
V
CONN
power switches
Features
•
•
•
•
•
The STUSB1602 integrates two current limited high-side power switches with protection that tolerates high voltage up to 22 V on the CC pins.
Each V
CONN
power switch presents the following features:
• Soft-start to limit inrush current
Constant current mode overcurrent protection
Adjustable current limit
Thermal protection
Undervoltage and overvoltage protections
Reverse current and reverse voltage protections
DS11254 - Rev 5 page 12/39
Figure 4. V
CONN
to CC1 and CC2 power switch protections
STUSB1602
VCONN supply
DS11254 - Rev 5
Current limit programming
The current limit can be set within the range 100 mA to 600 mA by a step of 50 mA. The default current limit is programmed through NVM programming (see
Section 6 Start-up configuration
) and can be changed by software through the I²C interface. At power-on or after a reset, the current limit takes the default value preset in the NVM.
Fault management
The table below summarizes the different fault conditions that could occur during switch operation and the associated responses. An I²C alert is generated when a fault condition happens.
Table 7. Fault management conditions
Fault types
Short-circuit
Overcurrent
Overheating
Undervoltage
Overvoltage
Reverse current
Fault conditions
CC output pin shorted to ground via very low resistive path causing rapid current surge
Expected actions
Power switch limits the current and reduces the output voltage. I²C alert is asserted immediately thanks to VCONN_SW_OCP_FAULT bits
CC output pin connected to a load that sinks current above programmed limit
Power switch limits the current and reduces the output voltage. I²C alert is asserted immediately thanks to VCONN_SW_OCP_FAULT bits
Junction temperature exceeding 145
°C due to any reason
Power switch is disabled immediately until the temperature falls below 145 °C minus hysteresis of 15 °C. I²C alert is asserted immediately thanks to THERMAL_FAULT bit. The STUSB1602 goes into transient error recovery state
V
CONN
input voltage drops below
UVLO threshold minus hysteresis
CC output pin voltage exceeds maximum operating limit of 6.0 V
CC output pin voltage exceeds
V
CONN input voltage when the power switch is turned off
Power switch is disabled immediately until the input voltage rises above the UVLO threshold. I²C alert is asserted immediately thanks to VCONN_PRESENCE bit
Power switch is opened immediately until the voltage falls below the voltage limit. I²C alert is asserted immediately thanks to
VCONN_SW_OVP_FAULT bits
The reverse biased body diode of the back- to-back MOS switches is naturally disabled preventing current from flowing from CC output pin to the input page 13/39
3.5
3.6
3.7
STUSB1602
High voltage protection
Fault types Fault conditions Expected actions
Reverse voltage
CC output pin voltage exceeds
V
CONN
input voltage of more than
0.35 V for 5 V when the power switch is turned on
Power switch is opened immediately until the voltage difference falls below the voltage limit. I²C alert is asserted immediately thanks to
VCONN_SW_RVP_FAULT bits
High voltage protection
The STUSB1602 can be safely used in systems or connected to systems that handle high voltage on the V
BUS power path. The device integrates an internal circuitry on the CC pins that tolerates high voltages and ensures protection up to 22 V in case of unexpected short-circuits with the V
BUS
or in the case of a connection to a device supplying high voltage on the V
BUS
.
Dead battery
Dead battery mode allows systems powered by a battery to be supplied by the VBUS when the battery is discharged and to start the battery charging process. This mode is also used in systems that are powered through the VBUS only.
Dead battery mode is only supported in sink power role and dual power role configurations. It operates only if the
CC1DB and CC2DB pins are connected respectively to the CC1 and CC2 pins. Thanks to these connections, the
STUSB1602 presents a pull down termination on its CC pins and advertises itself as a sink even if the device is not supplied.
When a source system connects to a USB Type-C port with the STUSB1602 configured in dead battery mode, it can detect the pull down termination, establish the source-to-sink connection, and provide the VBUS. The
STUSB1602 is then supplied thanks to the VDD pin connected to the VBUS on the USB Type-C receptacle side.
The STUSB1602 can finalize the source-to-sink connection and enable the power path on the VBUS thanks to the
VBUS_EN_SNK pin which allows the system to be powered.
Hardware fault management
•
•
•
The STUSB1602 handles hardware fault conditions related to the device itself and to the V
BUS
power path during system operation.
When such conditions occur, the circuit goes into a transient error recovery state named ErrorRecovery in the
Type-C FSM. In this state, the device de-asserts the V
BUS
power path by disabling the VBUS_EN_SRC pin and it removes the terminations from the CC pins during several tens of milliseconds. Then, it goes to the unattached source state.
The STUSB1602 goes into error recovery state when at least one condition listed below is met:
• If an overtemperature is detected, the “THERMAL_FAULT” flag is asserted
• If an internal pull-up voltage on the CC pins is below the UVLO threshold, the “VPU_VALID” flag is asserted
•
If an overvoltage is detected on the CC pins, the “VPU_OVP_FAULT” flag is asserted
If the VBUS voltage is out of the valid voltage range during attachment, the “VBUS_VALID” flag is asserted
If an undervoltage is detected on the VDD pin during attachment when UVLO detection is enabled, the
“VDD_UVLO_DISABLE” flag is asserted
If an overvoltage is detected on the VDD pin during attachment when OVLO detection is enabled, the
“VDD_OVLO_DISABLE” flag is asserted
The I²C register bits mentioned above give either the state of the hardware fault when it occurs or the setting condition to detect the hardware fault.
DS11254 - Rev 5 page 14/39
STUSB1602
Accessory mode detection
3.8
3.8.1
3.8.2
Accessory mode detection
•
•
•
•
The STUSB1602 supports the detection of audio accessory mode and debug accessory mode as defined
):
Source power role with accessory support
Sink power role with accessory support
Sink power role without accessory support
Dual power role with accessory support
Audio accessory mode detection
The STUSB1602 detects an audio accessory device when both CC1 and CC2 pins are pulled down to ground by an R a
resistor from the connected device. The audio accessory detection is advertised through the
CC_ATTACHED_MODE bits of the I²C register CC_CONNECTION_STATUS.
Debug accessory mode detection
The STUSB1602 detects a connection to a debug and test system (DTS) when it operates either in sink power role or in source power role. The debug accessory detection is advertised by the DEBUG1 and DEBUG2 pins as well as through the CC_ATTACHED_MODE bits of the I²C register CC_CONNECTION_STATUS.
• In sink power role, a debug accessory device is detected when both the CC1 and CC2 pins are pulled up by an Rp resistor from the connected device. The voltage levels on the CC1 and CC2 pins give the orientation and current capability as described in the table below. The DEBUG1 pin is asserted to advertise the DTS detection and the A_B_SIDE pin indicates the orientation of the connection. The current capability of the
DTS is given through the SINK_POWER_STATE bits of the I²C register CC_OPERATION_STATUS.
#
1
2
3
CC1 pin
(CC2 pin)
R p
3 A
R p
1.5 A
R p
3 A
4 R p def/1.5 A/ 3 A
Table 8. Orientation and current capability detection in sink power role
CC2 pin (CC1 pin)
R p
1.5 A
R p
default
R p
default
R p def/1.5 A/ 3 A
Charging current configuration
A_B_SIDE pin
CC1/CC2
(CC2/CC1)
Default
1.5 A
3.0 A
Default
HiZ (0)
HiZ (0)
HiZ (0)
HiZ (HiZ)
Current capability state
SINK_POWER_STATE bit values
PowerDefault.SNK (source supplies default USB current)
Power1.5.SNK (source supplies 1.5 A USB Type-C current)
Power3.0.SNK (source supplies 3.0 A USB Type-C current)
PowerDefault.SNK (source supplies default USB current)
• In source power role, a debug accessory device is detected when both the CC1 and
CC2 pins are pulled down to ground by an Rd resistor from the connected device. The orientation detection is performed in two steps as described in the table below. The DEBUG2 pin is asserted to advertise the
DTS detection and the A_B_SIDE pin indicates the orientation of the connection. The orientation detection is advertised through the TYPEC_FSM_STATE bits of the I²C register CC_OPERATION_STATUS.
DS11254 - Rev 5 page 15/39
#
1
2
STUSB1602
Accessory mode detection
CC1 pin
(CC2 pin)
Table 9. Orientation detection in source power role
CC1 pin
(CC2 pin)
Detection process
A_B_SIDE pin
CC1/CC2
(CC2/CC1)
Rd
Rd
Rd
≤Ra
1st step: debug accessory mode detected
2nd step: orientation detected (DTS presents a resistance to GND with a value ≤ Ra on its CC2 pin)
HiZ (HiZ)
HiZ (0)
Orientation detection state
TYPEC_FSM_STATE bits value
UnorientedDebugAcc essory.SRC
OrientedDebugAcces sory.SRC
DS11254 - Rev 5 page 16/39
4
STUSB1602
Managing USB PD transactions
Managing USB PD transactions
•
•
•
•
Due to specific HW/SW partitioning, the STUSB1602 requires a specific alignment between the lower protocol stack (managed by the STUSB1602) and the higher protocol stack (managed by the external MCU). Therefore, dedicated read and write I²C accesses are needed to perform the following actions:
•
Acknowledge a HW reset request
Request a HW reset
Perform a V
CONN
SWAP
Perform a data role SWAP
Acknowledge a power role SWAP request
• Request a power role SWAP
DS11254 - Rev 5 page 17/39
STUSB1602
I²C interface
5
I²C interface
5.1
•
•
Read and write operations
The I²C interface is used to configure, control and read the operation status of the device. It is compatible with the
Philips I²C BUS® (version 2.1). The I²C is a slave serial interface based on two signals:
SCL - serial clock line: input clock used to shift data
SDA - serial data line: input/output bidirectional data transfers
A filter rejects the potential spikes on the bus data line to preserve data integrity.
The bidirectional data line supports transfers up to 400 Kbit/s (fast mode). The data are shifted to and from the chip on the SDA line, MSB first.
The first bit must be high (START) followed by the 7-bit device address and the read/write control bit.
Two 7-bit device addresses are available for the STUSB1602 thanks to external programming of DevADDR0 through ADDR0 pin setting, i.e. 0x28 or 0x29. This allows two STUSB1602 devices to be connected on the same
I²C bus.
Bit7
DevADDR6
0
Bit6
DevADDR5
1
Table 10. Device address format
Bit5
DevADDR4
0
Bit4
DevADDR3
1
Bit3
DevADDR2
0
Bit2
DevADDR1
0
Bit1
DevADDR0
ADDR0
Bit0
R/W
0/1
Table 11. Register address format
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RegADDR7 RegADDR6 RegADDR5 RegADDR4 RegADDR3 RegADDR2 RegADDR1 RegADDR0
Bit7
DATA7
Bit6
DATA6
Bit5
DATA5
Table 12. Register data format
Bit4
DATA4
Bit3
DATA3
Bit2
DATA2
Bit1
DATA1
Bit0
DATA0
Figure 5. Read operation
Master Slave
Start Device addr
7 bits
W A Reg address
8 bits
A Restart Device addr
7 bits
R A Reg data
8 bits
A Reg data
8 bits
Address n+1
A Reg data
8 bits
Address n+2 Start bit = SDA falling when SCL= 1
Stop bit = SDA rising when SCL= 1
Restart bit = start after a start
Acknowledge = SDA forced low during a SCL clock
A
Stop
DS11254 - Rev 5 page 18/39
STUSB1602
Timing specifications
Figure 6. Write operation
Start Device addr
7 bits
W A Reg address
8 bits
Start bit = SDA falling when SCL = 1
Stop bit = SDA rising when SCL = 1
Restart bit = start after a start
A Reg data
8 bits
A Reg data
8 bits
Address n+1
A Reg data
8 bits
Address n+2
A Stop
5.2
Timing specifications
The device uses a standard slave I²C channel at speed up to 400 kHz.
Symbol
F scl t hd,sta t low t high t su,dat t hd,dat t su,dat t r t f t su,sto t buf
C b
Table 13. I²C timing parameters - V
DD
= 5 V
Parameter
SCL clock frequency
Hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for repeated START condition
Data hold time
Data setup time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Min.
0
0.6
1.3
0.6
0.6
0.04
100
20 + 0.1 C b
20 + 0.1 C b
0.6
1.3
-
Figure 7. I²C timing diagram
V ih
SDA
V il t f t hd,st a t r t su,dat t high
SCL t low t hd,dat t su,sta
300
300
-
-
0.9
-
-
400
Max.
400
-
-
-
-
-
-
-
-
-
-
-
Typ.
-
-
-
-
Unit kHz
μs ns
μs pF
DS11254 - Rev 5 page 19/39
STUSB1602
Start-up configuration
6
Start-up configuration
6.1
6.2
User-defined parameters
The STUSB1602 has a set of user-defined parameters that can be customized by NVM reprogramming and/or by software through the I²C interface. This feature allows the customer to change the preset configuration of the USB
Type-C interface and to define a new configuration to meet specific customer requirements addressing various applications, use cases, or specific implementations.
The NVM re-programming overrides the initial default setting to define a new default setting that is used at power-up or after a reset. The default value is copied at power-up, or after a reset, from the embedded NVM into dedicated I²C register bits. The NVM re-programming is possible only once with a customer password.
When a default value is changed during functioning by software, the new setting remains in effect as long as the STUSB1602 runs or when it is changed again. But after power- off and power-up, or after a reset, the
STUSB1602 takes back the default values defined in the NVM.
Default start-up configuration
•
•
The table below lists the user-defined parameters and indicates the default start-up configuration of the
STUSB1602.
Three types of user-defined parameters are specified in the table with respect to the “Customization type” column:
• SW: indicates parameters that can be customized only by software through the I²C interface during system operation
NVM: indicates parameters that can be customized only by NVM re-programming
NVM/SW: indicates parameters that can be customized by NVM re-programming and/or by software through the I²C interface during system operation
Table 14. STUSB1602 user-defined parameters and default setting
Customization type
NVM/SW
NVM/SW
NVM/SW
NVM
NVM/SW
NVM/SW
NVM/SW
NVM/SW
NVM/SW
SW
SW
NVM/SW
NVM/SW
Parameter Default value and description
CC_CONNECTION_STATUS_AL_MASK 1b: interrupt masked
MONITORING_STATUS_AL_MASK 1b: interrupt masked
HW_FAULT_STATUS_AL_MASK
STANDBY_POWER_MODE_DISABLE
1b: interrupt masked
1b: disables standby power mode
CC_POWER_MODE
CC_CURRENT_ADVERTISED
CC_VCONN_DISCHARGE_EN
CC_VCONN_SUPPLY_EN
CC_VCONN_SWITCH_ILIM
VCONN_MONITORING_EN
011b: dual power role with accessory support
01b: 1.5 A
0b: V
CONN
discharge disabled on CC pin
1b: V
CONN
CC pin
supply capability enabled on
0000b: 350 mA
1b: enables UVLO threshold detection on
VCONN pin
VCONN_UVLO_THRESHOLD
SHIFT_HIGH_VBUS_LIMIT_SOURCE
SHIFT_LOW_VBUS_LIMIT_SOURCE
0b: high UVLO threshold of 4.65 V
0101b: in source power role, shifts nominal high voltage limit by 5% of V
BUS
0101b: in source power role, shifts nominal low voltage limit by -5% of V
BUS
18h
1Eh
20h
20h
22h
I²Cregister address
0Ch
0Ch
0Ch n.a.
28h
18h
18h
22h
DS11254 - Rev 5 page 20/39
STUSB1602
Default start-up configuration
Customization type
SW
NVM/SW
NVM/SW
NVM
NVM/SW
NVM/SW
NVM/SW
NVM/SW
NVM/SW
Parameter Default value and description
SW_RESET_EN
VBUS_DISCHARGE_DISABLE
0b: device reset is performed from hardware RESET pin
VBUS_DISCHARGE_TIME_TO_0V 1010b: 840 ms discharge time
VBUS_DISCHARGE_TIME_TRANSITION 1010b: 200 ms discharge time
0b: enables V
BUS
discharge path
CC_POWER_MODE
VDD_OVLO_DISABLE
VBUS_VALID_RANGE_DISABLE
VBUS_VSAFE0V_THRESHOLD
VDD_UVLO_DISABLE
011b: dual power role with accessory support
0b: enables OVLO threshold detection on
VDD pin
0b: enables valid V
BUS
voltagerange detection
00b: V
BUS
vSafe0Vthreshold = 0.6 V
1b: disables UVLO threshold detection on
VDD pin
I²Cregister address
23h
25h
25h n. a.
28h
2Eh
2Eh
2Eh
2Eh
DS11254 - Rev 5 page 21/39
7
7.1
7.1.1
7.1.2
STUSB1602
Application
Application
The sections below are not part of the ST product specifications. They are intended to give a generic application overview to be used by the customer as a starting point for further implementation and customization. ST does not warrant compliancy with customer specifications. Full system implementation and validation are under the customer’s responsibility.
General description
•
•
•
Power supplies
The STUSB1602 can be supplied in three different ways depending on the targeted application:
Through the VDD pin only for applications powered by V
BUS
that operate either in source power role
Through the VSYS pin only for AC powered applications with a system power supply delivering 3.3 V or 5 V
Through the VDD and VSYS pins for applications powered by V
BUS
with a system power supply delivering
3.3 V or 5 V. When both VDD and VSYS power supplies are present, the low power supply VSYS is selected when VSYS voltage is above 3.1 V. Otherwise VDD is selected
Connection to MCU or application processor
The I²C interface is used to provide extensive functionality during system operation. For instance:
1.
Define the port configuration during system boot (in case NVM parameters are not customized during manufacturing)
2.
Change the default configuration at any time during operation
3.
Adjust the port power capability in source power role according to contextual power availability and/or the power partitioning with other ports
4.
Save system power by shutting down the DC-DC converter according to the attachment detection state
5.
Provide a diagnostic of the Type-C connection and the V
BUS
power path in real time
DS11254 - Rev 5 page 22/39
7.2
7.2.1
STUSB1602
USB Type-C typical applications
USB Type-C typical applications
Source type application schematic
Figure 8. Typical STUSB1602 implementation in source type application
Power
Management
Unit
VBUS
3V3
VI O
C2
1µF
STL9P3LLH6
R1
10K
STL9P3LLH6
C1
10µF
R2
1K
GND
VI O
Application
Processor
SPC5 Power Architecture
32-bit MCUs
To Super Speed M UX
To GND/VIO
MI SO
MOSI
NSS
SCLK
TX_EN
SCL
SDA
ALERT#
RESET
R10
10K
R4
10K
R5
10K
R6
10K
R7
10K
R8
10K
R9
10K
R3
10K
A_B_Side
ADDR0
R11
10K
GND
R12
100K
GND
24
U1
14
11
MISO
MOSI
12
16
15
NSS
SCLK
TX_EN
7
8
9
SCL
SDA
AL ERT#
6
RESET
I²C
SSI
STUSB1602
VBUS_SENSE 18
CC1GND
1
CC1
2
CC2
4
CC2GND 5
VReg_1V2 21
GND
GND
VReg_2V7 23
5V
C3
1µF
C4
1µF
GND
17
A_B_SIDE
13
ADDR0
VCONN
3
GND
10
EP
0
C5 10µF
GND GND
VBUS
CC1
CC2
D1
D2
GND
GND
Type C connector
Table 15. Default setting for a source type application
22h
25h
25h
26h
28h
2Eh
2Eh
2Eh
I²C register address
0Eh
18h
18h
18h
1Eh
20h
20h
22h
I²C register field name I²C register reset value/description
START_UP_POWER_MODE
CC_CURRENT_ADVERTISED
CC_VCONN_DISCHARGE_EN
0b: device starts in normal mode
01b: 1.5 A
CC_VCONN_SUPPLY_EN
CC_VCONN_SWITCH_ILIM
VCONN_MONITORING_EN
VCONN_UVLO_THRESHOLD
0b: V
CONN
discharge disabled on CC pin
1b: V
CONN
supply capability enabled on CC pin
0000b: 350 mA
1b: enables UVLO threshold detection on V
0b: high UVLO threshold of 4.65 V
CONN
pin
SHIFT_HIGH_VBUS_LIMIT_SOURCE
SHIFT_LOW_VBUS_LIMIT_SOURCE
VBUS_DISCHARGE_TIME_TO_0V
0101b: in source power role, shifts nominal high voltage limit by +5% of V
BUS
0101b: in source power role, shifts nominal low voltage limit by -5% of V
BUS
1010b: 840 ms discharge time
VBUS_DISCHARGE_TIME_TRANSITION 1010b: 200 ms discharge time
VBUS_DISCHARGE_EN
POWER_MODE
1b: enables the V
BUS
discharge path
000b: source power role with accessory support
VDD_OVLO_DISABLE
VBUS_RANGE_DISABLE
VBUS_VSAFE0V_THRESHOLD
0b: enables OVLO threshold detection on VDD pin
0b: enables V
BUS
voltage range detection
00b: V
BUS
vSafe0V threshold = 0.6 V
Customization type
NVM/SW
NVM/SW
NVM/SW
NVM/SW
NVM/SW
SW
SW
NVM/SW
NVM/SW
NVM/SW
NVM/SW
NVM/SW
SW
SW
SW
DS11254 - Rev 5 page 23/39
STUSB1602
USB Type-C typical applications
I²C register address
2Eh
I²C register field name
VDD_UVLO_DISABLE
I²C register reset value/description
1b: disables UVLO threshold detection on VDD pin
1. Italic text indicates this parameter is customized by NVM re-programming.
Customization type
SW
Pin
VBUS_EN_SRC
Table 16. Conditions for V
BUS
power path assertion in source power role
Operation conditions
Electrical value
Type-C attached state VDD pin monitoring
VBUS_SENSEpin monitoring
0
Attached.SRC or
UnorientedDebug
Accessory.SRC
or OrientedDebug
Accessory.SRC
VDD < OVLO if VDD pin is supplied
V
BUS
within valid voltage range
Comment
The signal is asserted only if all the valid operation conditions are met
HiZ Anyother state
VDD > OVLO if VDD pin is supplied
V
BUS
is out ofvalid voltage range
The signal is de-asserted when at least one non valid operation condition is met.
Connection state
CC1 pin
CC2 pin
Nothing attached Open Open
Rd Open
Sink attached
Open Rd
Powered cable withoutsink attached
Powered cable with sink attached or
VCONNpowered accessory attached
Open Ra
Ra
Rd
Ra
Open
Ra
Rd
Debug accessory mode attached source role
Debug accessory mode attached sink role
Debug accessory mode attached sink role
Audio adapter accessory mode attached
Rp
Rd
Rd
≤ Ra
Ra
Rp
Rd
≤Ra
Rd
Ra
Table 17. Source power role with accessory support
Type-C device state
CC_OPERATION_STATUS register @11h
Unattached.SRC
A_B_SIDE pin
VCONN supply
VBUS_EN_SRC pin
Attached.SRC
Unattached.SRC
HiZ
HiZ
0
HiZ
HiZ
HiZ
OFF
OFF
OFF
OFF
OFF
CC2
HiZ
0
0
HiZ
HiZ
0
CC_CONNECTION_STATUS register @0Eh
00h
2Dh
2Dh
00h
00h
2Fh
Attached.SRC
Unattached.SRC
UnorientedDebug
Accessory.SRC
OrientedDebug
Accessory.SRC
AudioAccessory
0
HiZ
HiZ
HiZ
0
HiZ
CC1
OFF
OFF
OFF
OFF
OFF
0
HiZ
0
0
0
HiZ
2Fh
00h
6Dh
6Dh
6Dh
81h
DS11254 - Rev 5 page 24/39
STUSB1602
USB Type-C typical applications
The value of the CC1 and CC2 pins is defined from a termination perspective and corresponds to the termination presented by the connected device. The CC_CONNECTION_STATUS register can report other values than the
one presented in Table 17. Source power role with accessory support
. In this table, it reflects the state transitions in Type-C FSM that can be ignored from the application stand point.
DS11254 - Rev 5 page 25/39
STUSB1602
Electrical characteristics
8
Electrical characteristics
8.1
8.2
Note:
Absolute maximum ratings
All voltages are referenced to GND.
Symbol
V
DD
V
SYS
V
CC1
, V
CC2
, V
CC1DB
, V
CC2DB
V
VBUS_EN_SRC
, V
VBUS_EN_SNK
, V
VBUS_SENSE
V
SCL
, V
SDA
, V
ALERT#
, V
RESET
, V
A_B_SIDE
V
MOSI
, V
MISO
, V
NSS
, V
TX_EN
, V
SCLK
V
CONN
T
STG
T
J
ESD
Table 18. Absolute maximum ratings
Supply voltage
Parameter
Supply voltage on VSYS pin
High voltage on CC pins
High voltage on V
BUS
pins
Operating voltage on I/O pins
V
CONN
voltage
Storagetemperature
Maximum junction temperature
HBM
CDM
Value
28
6
22
28
-0.3 to 6
6
-55 to 150
145
4
1.5
Unit
V
°C kV
Operating conditions
Table 19. Operating conditions
Symbol
V
DD
V
SYS
V
CC1
, V
CC2
, V
CC1DB
, V
CC2DB
V
VBUS_EN_SRC
, V
VBUS_EN_SNK
,V
VBUS_SENSE
V
SCL
, V
SDA
, V
ALERT#
, V
RESET
, V
A_B_SIDE
V
MOSI
, V
MISO
, V
NSS
, V
TX_EN
, V
SCLK
V
CONN
I
CONN
T
A
Parameter
Supply voltage
Supply voltage on V
SYS
pin
CC pins
High voltage pins
Operating voltage on I/O pins
V
CONN
voltage
V
CONN
rated current (default = 0.35 A)
Operating temperature
The transient voltage on the CC1 and CC2 pins drops to -0.3 during BMC communication.
Value
4.1 to 22
3.0 to 5.5
-0.3 to 5.5
0 to 22
Unit
V
0 to 4.5
2.7 to 5.5
0.1 to 0.6
-40 to 105
A
°C
DS11254 - Rev 5 page 26/39
8.3
STUSB1602
Electrical and timing characteristics
Electrical and timing characteristics
Unless otherwise specified: V
DD
= 5 V, T
A
= +25 °C, all voltages are referenced to GND.
V
TH0.4
V
TH0.66
V
TH0.8
V
TH1.23
V
TH1.6
V
TH2.6
Symbol
I
DD (SRC)
I
DD (SNK)
I
STDBY
I
P-USB
I
P-1.5
I
P-3.0
V
CCO
R d
V
CCDB-1.5
V
CCDB-3.0
R
INCC
V
TH0.2
R
VCONN
I
OCP
Parameter
Current consumption
Current consumption
Standby current consumption
Table 20. Electrical characteristics
Conditions
Device idle as a SOURCE (not connected, no communication)
Device idle as a SINK (not connected, no communication)
Device in standby (not connected, low power)
V
SYS
@ 3.3 V
V
DD
@ 5.0 V
V
SYS
@ 3.3 V
V
DD
@ 5.0 V
V
SYS
@ 3.3 V
V
DD
@ 5.0 V
CC1 and CC2 pins
Min.
CC current sources
CC pin voltage, V
40 °C < T
CC
A
= -0.3 to 2.6 V,
< 105 °C
CC open pin voltage
CC pull-down resistors
CC pin voltage in dead battery condition
CC input impedance
Detection threshold 1
CC unconnected, V
DD
= 3.0 to 5.5 V
40 °C < T
A
< 105 °C
External IP = 180 μA applied into CC,
VDD = 0 V, dead-battery function enabled
External IP = 330 μA applied into CC,
VDD = 0 V, dead-battery function enabled
Pull-up and pull-down resistors off
Max. R a
detection by DFP at I
P detection by UFP on R d
, min CC voltage for connected
UFP
= I
P-USB
, min. I
P_USB
Max. R a
detection by DFP at I
P
= I
P-1.5
Detection threshold 2
Detection threshold 3
Detection threshold 4
Detection threshold 5
Detection threshold 6
Detection threshold 7
V
CONN
power path resistance
Overcurrent protection
Min. IP_1.5 detection by UFP on R
Max. R a
detection by DFP at I
Min. I
P_3.0
P
= I
P-3.0
detection by UFP on R d d
Max. R d
detection by DFP at I
P
= I
P-USB
and I
P
= I
P-1.5
Max. R d
detection by DFP at I
P-3.0
, max. CC voltage for connected UFP
V
CONN
protection
I
VCONN
= 0.2 A-
Programmable current limit threshold
(from 100 mA to 600 mA by step of 50 mA)
-20%
-8%
-8%
2.75
-10%
200
0.15
0.35
0.61
0.75
1.16
1.50
2.45
0.25
85
300
Typ.
158
188
113
140
33
53
Max.
Unit
µA
µA
80
180
330
+20%
+8%
+8%
µA
V
5.1
10% kΩ
1.2
2.0
V kΩ
0.20
0.25
V
0.40
0.45
V
0.66
0.80
1.23
1.60
0.70
V
0.85
V
1.31
V
1.65
V
2.60
2.75
V
0.50
100
350
0.975
Ω
125
400 mA
DS11254 - Rev 5 page 27/39
DS11254 - Rev 5
STUSB1602
Electrical and timing characteristics
T
V
V
Symbol
V
R
V
I
V
V
OCP
THUSB
TH0V
DISUSB
DISUSB
MONUSBH
MONUSBL
V
V
V
OVP
UVP
IH
IL
OL
V
OL
1. T
DISPARAM
Parameter
Overcurrent protection
Conditions
Programmable current limit threshold
(from 100 mA to 600 mA by step of 50 mA)
Min.
550
Typ.
600
Output overvoltage protection
Input undervoltage protection
Low UVLO threshold
High UVLO threshold (default)
5.9
2.6
4.6
6.0
V
BUS
monitoring and driving
V
BUS
presence threshold
V
SYS
= 3.0 to 5.5 V 3.8
3.9
V
BUS
safe 0
V threshold
(vSafe0V)
V
SYS
= 3.0 to 5.5 V
Programmable threshold
Programmable threshold from 0.6 V to 1.8 V
Default V
THOV
= 0.6 V
0.5
0.8
1.1
1.7
0.6
0.9
1.2
1.8
V
BUS
discharge resistor
V
BUS
discharge time to 0V
V
BUS
discharge time to PDO
V
BUS
monitoring high voltage threshold
Default T
DISPARAM
= 840 ms, the coefficient T is programmable by NVM
DISPARAM
Default T
DISPARAM
= 200 ms, the coefficient T is programmable by NVM from +5 % to +20 %
DISPARAM
V
BUS
= nominal target value, default V
MONUSBH
= V
BUS
+10 %, the threshold limit is programmable by NVM
600
70
20
1.2
V
700
84
24
BUS
10%
+
V
BUS
monitoring low voltage threshold
V
BUS
= nominal target value, default V
MONUSBL
= V
BUS
-10 %, the threshold limit is programmable by NVM from
-20 % to -5 %
V
BUS
10%
Digital input/output (SCL, SDA, ALERT#, A_B_SIDE, MOSI, MISO, NSS, TX_EN, SCLK)
-
High level input voltage
Low level input voltage
Low level output voltage
Ioh = 3 mA
20 V open drain outputs (VBUS_EN_SRC, VBUS_EN_SNK)
Low level output voltage
Ioh = 3 mA
Max.
Unit
650
6.1
2.7
4.8
4.0
0.7
1
1.3
1.9
800
100
28
0.35
0.4
0.4
mA
V
V
V
V
V
V
V
Ω ms
V
V
V
V
V
V page 28/39
9
9.1
STUSB1602
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
QFN24 EP 4x4 mm package information
Figure 9. QFN24 EP 4x4 mm package outline
DS11254 - Rev 5 page 29/39
Ref.
E
E2 e
K
L
A
A1 b
D
D2
STUSB1602
QFN24 EP 4x4 mm package information
Min.
3.95
2.55
0.45
0.15
0.30
0.80
0.00
0.18
3.95
2.55
Table 21. QFN24 EP 4x4 mm mechanical data
Dimensions (mm)
Typ.
0.90
0.02
0.25
4.00
2.70
4.00
2.70
0.50
0.40
Max.
1.00
0.05
0.30
4.05
2.80
4.05
2.80
0.55
0.50
Min.
0.156
0.100
0.018
0.006
0.012
0.031
0.000
0.007
0.156
0.100
Inches
Typ.
0.035
0.001
0.010
0.157
0.106
0.157
0.106
0.020
0.016
Figure 10. QFN24 EP 4x4 mm recommended footprint
Max.
0.039
0.002
0.012
0.159
0.110
0.159
0.110
0.022
0.020
DS11254 - Rev 5 page 30/39
9.2
QFN24 EP 4x4 mm packing information
Figure 11. Reel outline
STUSB1602
QFN24 EP 4x4 mm packing information
9.3
Package
QFN24 EP 4x4
Table 22. Tape dimensions
Pitch
8 mm
Carrier width
12 mm
Thermal Information
Symbol
R
θJA
R
θJC
Table 23. Thermal information
Parameter
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
Reel
13"
Value
37
5
Unit
°C/W
°C/W
DS11254 - Rev 5 page 31/39
10
STUSB1602
Terms and abbreviations
Terms and abbreviations
Term
Accessory modes
DFP
DRP
Sink
Source
UFP
Table 24. List of terms and abbreviations
Description
Audio adapter accessory mode. It is defined by the presence of R a
/R a
on the CC1/CC2 pins.
Debug accessory mode. It is defined by the presence of R d
/R d
on CC1/CC2 pins in source power role or R p
/R p
on CC1/CC2 pins in sink power role.
Downstream facing port, specifically associated with the flow of data in a USB connection.
Typically, the ports on a HOST or the ports on a hub to which devices are connected. In its initial state, DFP sources V
BUS
and V
CONN
, and supports data.
Dual-role port. A port that can operate as either a source or a sink. The port role may be changed dynamically.
Port asserting R d device.
on the CC pins and consuming power from the V
BUS
; most commonly a
Port asserting R p or hub DFP.
on the CC pins and providing power over the V
BUS
; most commonly a host
Upstream facing port, specifically associated with the flow of data in a USB connection. The port on a device or a hub that connects to a host or the DFP of a hub. In its initial state, the
UFP sinks the V
BUS
and supports data.
DS11254 - Rev 5 page 32/39
STUSB1602
Revision history
Date
27-Jan-2017
05-Apr-2017
04-Aug-2017
19-Nov-2020
19-Jul-2021
Revision
1
2
3
4
5
Table 25. Document revision history
Changes
Initial release.
Updated Features section and ESD reference in Table 28: Absolute maximum ratings.
Updated Table 1: Device summary.
Updated Table 18, Table 21 and Table 24.
Updated Section Features , Section Applications
, Section 1 Functional description ,
Figure 2. STUSB1602 pin connections
, Section 6.2 Default start-up configuration
.
Updated Table 1. Pin functions list ,
Table 18. Absolute maximum ratings
and
Table 19. Operating conditions
.
DS11254 - Rev 5 page 33/39
STUSB1602
Contents
Contents
DS11254 - Rev 5 page 34/39
STUSB1602
Contents
DS11254 - Rev 5 page 35/39
STUSB1602
Contents
DS11254 - Rev 5 page 36/39
STUSB1602
List of tables
List of tables
Table 13. I²C timing parameters - V
DS11254 - Rev 5 page 37/39
STUSB1602
List of figures
List of figures
DS11254 - Rev 5 page 38/39
STUSB1602
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS11254 - Rev 5 page 39/39
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