STMicroelectronics L5300AH7 Datasheet
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L5300AH7
Automotive 5 V low drop voltage regulator
HPAK
GA P GC FT001 35
Features
Max DC supply voltage
Max output voltage tolerance
Max dropout voltage
Output current
Quiescent current
1.
Typical value with regulator disabled
2.
Typical value with regulator enabled
V s
V
0
V dp
I
0
I qn
40 V
+/-2 %
500 mV
300 mA
5 µA
(1)
55 µA
(2)
AEC-Q100 qualified
Operating DC supply voltage range 5.6 V to 40 V
Low dropout voltage
300 mA current capability
Low quiescent current
Very low consumption mode
Package
HPAK
Table 1. Device summary
Order codes
Tube
L5300AH7
Datasheet
-
production data
Precision output voltage 5 V +/-2%
Reset circuit sensing the output voltage
Programmable reset pulse delay with external capacitor
Thermal shutdown and short circuit protection
Wide temperature range (Tj = -40°C to 150°C)
Enable input for enabling / disabling the voltage regulator
Description
L5300AH7 is a low dropout linear regulator with microprocessor control functions such as power on reset, low voltage reset, ON/OFF control. In addition, only low value ceramic capacitor is required for stability (above or equal 220 nF).
Typical quiescent current is 60 µA at output current equal to 0 and enable high. It drops to
10 µA in “not enabled” mode.
On chip trimming results in high output voltage accuracy (+/-2%). Accuracy is kept over wide temperature range, line and load variation.
The maximum input voltage is 40 V. The max output current is internally limited. Internal temperature protection disables the voltage regulator output.
Tape and reel
L5300AH7TR
September 2018
This is information on a product in full production.
DS6143 Rev 13 1/24 www.st.com
Contents
Contents
L5300AH7
Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/24 DS6143 Rev 13
L5300AH7
List of tables
List of tables
DS6143 Rev 13 3/24
3
List of figures
List of figures
L5300AH7
Figure 3.
Output voltage vs T j
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current consumption vs input voltage (I
= 0.1 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current consumption vs input voltage (I
= 100 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11.
Current limitation vs T j
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
j
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
vs T j
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
vs T
vs T j j
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
vs T
cr
vs T j j
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
dr
vs T j
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4/24 DS6143 Rev 13
L5300AH7
1
Block diagram and pins description
Block diagram and pins description
Figure 1. Block diagram
9R
JQG
9
V
(
Q
9
FU
67$5783
9ROWDJH
5HIHUHQFH
3RZHU
'ULYHU
7KHUPDO
6KXWGRZQ
&XUUHQW
/LPLWHU
P9
/RZ9ROWDJH
5HVHW
5HV
*$3*&)7
Figure 2.Configuration diagram (top view)
DS6143 Rev 13
*$3*&)7
5/24
23
Block diagram and pins description
3
4
5
6
7
N°
1
2
L5300AH7
R es
GND
V cr
V os
V o
Name
V
S
E n
Table 2. Pins description
Function
Supply voltage, block directly to GND on the I
C
with a capacitor.
Enable input. A high signal switches the regulator ON. Connect to
V
S
if not needed.
Reset output. Internally connected to V o
through a 20 K
pull up resistor. This pin is pulled low when V o
< V o_th
. Keep open if not needed.
Ground reference.
Reset delay. Connect an external capacitor between V cr
pin and ground to adjust the reset delay time. Keep open if not needed.
Output voltage sensing: this pin must be connected to V o
.
5 V regulated output. Block to GND with a ceramic capacitor
(
220 nF for regulator stability).
6/24 DS6143 Rev 13
L5300AH7 Electrical specifications
2.1
Symbol
V sdc
I sdc
V odc
I odc
V od Res
I od Res
V cr
V
En
T j
V
ESD HBM
V
ESD CDM
Absolute maximum ratings
Stressing the device above the rating listed in Table 3: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Table 3. Absolute maximum ratings
Parameter
DC supply voltage
Input current
DC output voltage
DC output current
Open drain output voltage R es
Open drain output current R es
V cr
voltage
Enable input
Junction temperature
ESD HBM voltage level (HBM-MIL STD 883C)
ESD CDM voltage level (CDM AEC-Q100-011)
Value
-0.3 to 40
Internally limited
-0.3 to 6
Internally limited
-0.3 to V
Vodc
+ 0.3
Internally limited
-0.3 to V
Vo
+ 0.3
-0.3 to 40
-40 to 150
+/- 2
+/- 750
Unit
V
V
V
V
V
°C kV
V
m
Symbol
Table 4. Thermal data
Parameter Value Unit
R thj-case
R thj-amb
Thermal resistance junction to case
Thermal resistance junction to ambient
4.8
45
(1)
°C/W
K/W
1.
The values quoted are for PCB 77 mm x 86 mm x 1.6 mm, FR4, double layer with thermal vias (one copper heatsink layer, thickness 0.070 mm, area 8 cm
2
).
DS6143 Rev 13 7/24
23
Electrical specifications L5300AH7
8/24
Values specified in this section are for V
S
= 5.6 V to 31 V, T j
= -40 °C to 150 °C, unless otherwise stated.
Table 5. General
V
V
V
Pin
S
S
S
V
V
V
V
V
, V
V o o o o o o
, V
, V
V o o o o
Symbol
I
V
V
V
I
V o_ref o_ref o_ref short
I
V lim line load
V dp oth_H
Parameter Test condition
Output voltage
Output voltage
Output voltage
Short circuit current
Output current limitation
(1)
Line regulation voltage
Load regulation voltage
Drop voltage
(2)
V
S
= 8 to 18 V
I
O
= 8 to 300 mA
V
S
= 5.6 to 31 V
I
O
= 8 to 300 mA
V
S
= 5.6 to 31 V
I
O
= 0.1 mA to 8 mA
V
S
= 13.5 V
V
S
= 13.5 V
V
S
= 6 V to 28 V
I
O
= 50 mA
I
V
S
O
= 13.5 V
= 8 mA to 300 mA
T j
= 25 °C
V
I
O
S
= 8 V to 18 V
= 8 mA to 300 mA
I
O
= 300 mA f r
= 100 Hz
(3)
Normal consumption mode output current
V o
I oth_L
Very low consumption mode output current
V
S
V o
, V o
V
S
, V o
V
S
, V
— o
I oth_Hyst
I
I
I qs qn_1 qn_300
T w
Output current switching threshold hysteresis
V
S
= 13.5 V,
T j
= 25 °C
Current consumption with regulator disabled
I qs
= I
V s
– I
O
Current consumption with regulator enabled
I qn_1
= I
V s
– I
O
Current consumption with regulator enabled
I qn_300
= I
V s
– I
O
Thermal protection temperature
V
S
= 13.5 V,
E n
= low
I
V
S
O
= 13.5 V,
< 1 mA,
E n
= high
I
V
S
O
= 13.5 V,
= 300 mA,
E n
= high
Min Typ Max Unit
4.9
4.85
5.0
5.15
4.75
5.0
5.25
0.8
0.6
8
150
5.0
5.1
1.8
2.6
1.6
2.5
60
0.8
5
55
3
40
40
55
A
A
500 mV dB
1.1
mA
10
80
V
V
V mV mV mV mA mA
µA
µA
4.2
mA
190 °C
— T w_hy
Thermal protection temperature hysteresis
10
1.
Measured output current when the output voltage has dropped 100 mV from its nominal value obtained at
13.5 V and I o
= 75 mA.
°C
DS6143 Rev 13
L5300AH7 Electrical specifications
2.
V
S
- V o
measured dropout when the output voltage has dropped 100 mV from its nominal value obtained at
13.5 V and I o
= 75 mA.
3.
Guaranteed by design
Table 6. Reset
Pin Symbol
R
R
R
R es es es es
I
V
Res_l
Res_lkg
R
V
Res o_th
Parameter
Reset output low voltage
R ext
= 5 k
V o
> 1 V
Reset output high leakage current
V
Res
= V o
Pull up internal resistance Versus V o
V o
out of regulation threshold
V o
decreasing
V cr
V cr
V cr
V cr
R es
R es
V
Rlth
V
Rhth
I cr
I dr
T rr
T rd
Reset timing low threshold V
S
= 13.5 V
Reset timing high threshold V
S
=13.5 V
Charge current V
S
= 13.5 V
Reset reaction time
Reset delay time
V
S
= 13.5 V
V o
= V o_th
- 100 mV
V
S
= 13.5 V,
C tr
= 1 nF
1 µA
10 20 40 k
6% 8% 10%
Below
V o_ref
16% 19% 22% V o_ref
47% 50% 53% V o_ref
10 20 30 µA
10 20 30 µA
2 µs
2 4
0.4
6
V ms
Pin Symbol
E n
E n
E n
E n
V
V
V
I
En_low
En_high
En_hyst
_leak
Table 7. Enable
Parameter
E n
input low voltage
E n
input high voltage
E n
input hysteresis
Pull down current
Test Typ.
Max.
Unit
V
En
= 5 V
3
500
3
1
10
V
V mV
µA
DS6143 Rev 13 9/24
23
Electrical specifications L5300AH7
Figure 3. Output voltage vs T j
9RBUHI9
9V 9
,R P$
Figure 4. Output voltage vs V
S
9RBUHI9
7F &
,R P$
7M&
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Figure 5. Output voltage vs V
En
9V9
*$3*&)7
Figure 6. Drop voltage vs output current
9GS9
7L &
7L &
,RP$
*$3*&)7
*$3*&)7
10/24 DS6143 Rev 13
L5300AH7
Figure 7. Current consumption vs output current
,TQP$
Electrical specifications
Figure 8. Current consumption vs output current (at light load condition)
9V 9
(Q +LJK
7M &
,RP$
*$3*&)7
*$3*&)7
Figure 9. Current consumption vs input voltage
(I
O
= 0.1 mA)
Figure 10. Current consumption vs input voltage (I
O
= 100 mA)
,TQ$
,TQP$
(Q +LJK
7M &
(Q +LJK
7M &
,RP$
*$3*&)7
,RP$
*$3*&)7
DS6143 Rev 13 11/24
23
Electrical specifications
Figure 11. Current limitation vs T j
,OLPP$
9V 9
L5300AH7
Figure 12. Current limitation vs input voltage
,OLPP$
7M &
7M &
7M&
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*$3*&)7
Figure 13. Short-circuit current vs T j
VKRUWP$
Figure 14.Short-circuit current vs input voltage
,VKRUWP$
9V 9
7M &
7M &
9HQBKLJK9
7M&
*$3*&)7
Figure 15. V
En_high
vs T j
9HQBORZ9
9V9
Figure 16. V
En_low
vs T j
*$3*&)7
9V 9WR9
9V 9WR9
12/24
7M&
*$3*&)7
DS6143 Rev 13
7M&
*$3*&)7
L5300AH7
9UKWK9RBUHI
Figure 17. V
Rhth
vs T j
9V 9WR9
Electrical specifications
9UOWK9RBUHI
Figure 18. V
Rlth
vs T j
9V 9WR9
,FU$
7M&
*$3*&)7
Figure 19. I cr
vs T j
,GU$
9V 9WR9
7M&
*$3*&)7
Figure 20. I dr
vs T j
9V 9WR9
7M&
*$3*&)7
7M&
*$3*&)7
DS6143 Rev 13 13/24
23
Application information L5300AH7
The voltage regulator uses a P-channel MOS transistor as a regulating element. With this structure a very low dropout voltage at current up to 300 mA is obtained. The output voltage is regulated up to input supply voltage of 40 V. The high-precision of the output voltage
(+/-2%) is obtained with a pre-trimmed reference voltage. The voltage regulator automatically adapts its own quiescent current to the output current level. In light load conditions the quiescent current goes down to 55 µA only (low consumption mode). This procedure features a certain hysteresis on the output current (see
protection to GND and a thermal shutdown are provided.
Figure 21.Application schematic
9
%$77 9V
9R
567
& & (Q
/$+
&R
9FU
*1'
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The input capacitor C
1
100 µF is necessary as backup supply for negative pulses which may occur on the line. The second input capacitor C
2
220 nF is needed when the C
1
is too distant from the V
S
pin and it compensates smooth line disturbances. The C
0 ceramic capacitor, connected to the output pin, is for bypassing to GND the high-frequency noise and it guarantees stability even during sudden line and load variations. Suggested value is
C
0
= 220 nF with ESR
100 m
.
Stability region is reported in Figure 22 .
14/24 DS6143 Rev 13
L5300AH7
Figure 22.Stability region
Application information
67$%,/,7<5(*,21
(65PLQ
817(67('5(*,21
&R)
*$3*36
Note:
The curve which describes the minimum ESR is derived from characterization data on the regulator with connected ceramic capacitors which feature low ESR values (at 100 kHz). Any capacitor with further lower ESR than the given plot value must be evaluated in each and every case.
Figure 23.Maximum load variation response
I
V o o
= 50 mV/div
= 100 mA/div
I
V
S o
= 13.5 V
= 8 to 300 mA
T c
C o
= 25 °C
= 220 nF
DS6143 Rev 13
GAPGCFT00128
15/24
23
Application information L5300AH7
3.2 Reset
The reset circuit monitors the output voltage V o
. If the output voltage becomes lower than
V o_th
then R
V o_th
then R es es
goes low with a delay time (t rr
). When the output voltage becomes higher than
goes high with a delay time T oscillator. The oscillator period is given by: rd
. This delay is obtained by 512 periods of
Equation 1
T osc
= [( V
Rhth
V
Rlth
) x C tr
] / I cr
+ [( V
Rhth
V
Rlth
) x C tr
] / I dr and reset pulse delay T rd
is given by:
Equation 2 t rd
= 32 x T osc
Where:
I cr
= 20 µA is an internally generated charge current,
I dr
= 20 µA is an internally generated discharge current,
V
Rhth
= 2.5V (typ) and V
Rlth
= 0.95V (typ) are two voltage thresholds,
C tr
is an external capacitor put between V cr
pin and GND.
Figure 24.Reset time diagram
9
R
9
FU
W
UU
W
UU
7
RVF
9
RXWBWO
9
UKWK
9
UOWK
W
UG
5
HV
*$3*&)7
3.3 Enable
L5300AH7 is also provided by an enable input, a high signal switches the regulator ON. In standby mode the output is disabled and the current consumption of the device (quiescent current) is less than 10 µA.
16/24 DS6143 Rev 13
L5300AH7
4
Package and PC board thermal data
Package and PC board thermal data
4.1 HPAK thermal data
Figure 25.PC board
*$3*&)7
Note:
Layout condition of R th
and Z th
measurements (Board finish thickness 1.6 mm +/- 10 %; Board double layer; Board dimension
78 mm x 86 mm; Board Material FR4; Cu thickness 0.070 mm (front and back side); Thermal vias separation 1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm; Footprint dimension 6.4 mm x 7 mm).
Figure 26.R
thj-amb
vs PCB copper area in open box free air condition
RTHjamb
90
80
70
60
50
40
30
0 2 4 6
RTHjamb
8 10
GAPGCFT00131
DS6143 Rev 13 17/24
23
Package and PC board thermal data
Figure 27.HPAK thermal impedance junction ambient single pulse
ZTH (°C/W)
100
Cu=8 cm2
Cu=2 cm2
Cu=f oot print
L5300AH7
10
1
0.01
0.1
1
Time (s)
10 100 1000
GAPGCFT00132
Figure 28.Thermal fitting model of a single-channel HSD in HPAK
18/24
GAPGCFT 00133
Note:
The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
DS6143 Rev 13
L5300AH7 Package and PC board thermal data
Equation 3: pulse calculation formula
Z
TH
= R
TH
+ Z
THtp
1 –
where
= t
P
/T
Area/island (cm
2
)
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Table 8. Thermal parameter
Footprint
6
7
3
4
28
31
0.0005
0.001
0.005
0.05
0.8
3
4
18.5
22
2
6
8
3
9
11
14
DS6143 Rev 13 19/24
23
Package and packing information
5 Package and packing information
L5300AH7
5.1 ECOPACK
®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
5.2 HPAK mechanical data
Figure 29.HPAK dimension
20/24 DS6143 Rev 13
GAPGCFT00134
L5300AH7
Dim
D1
E
E1 e e1 e2 b4 c c2
D
A
A1
A1 b e3
H
L
(L1)
L2
L4
R
V2
Package and packing information
Table 9. HPAK mechanical data
Millimeter
Nom Min
5.20
0.45
0.48
6.00
2.20
0.90
0.03
0.45
5.10
6.40
5.20
0.85
1.60
3.30
5.00
9.35
1
2.80
0.80
0.60
0.20
0°
Max
5.40
0.60
0.60
6.20
2.40
1.10
0.23
0.60
6.60
1.80
3.50
5.20
10.10
1.00
8°
DS6143 Rev 13 21/24
23
Revision history L5300AH7
Date
09-Aug-2007
15-Oct-2007
12-Mar-2009
23-Jul-2010
02-Sep-2010
15-Sep-2010
12-Oct-2010
Revision
Table 10. Document revision history
Changes
1
2
3
4
5
6
7
Initial release.
Changed features table on the cover page:
- quiescent current with regulator disabled changed from 10 to 5 µA.
- quiescent current with regulator enabled changed from 60 to 55 µA.
- Added typical value of I qs and I qn_1
parameters.
Changed features table on the cover page
– V o_ref
: deleted row and added 3 new rows
– I
Res_lkg
: deleted Test condition
– V o_th
: deleted I
O
= 1 to 300 mA and V decreasing“ for test condition
S
= 5.6 to 31V, added “V o
– V
Rlth
: changed min/typ/max values
– T rd
: changed min/typ/max values
Updated
– t rd
: changed coefficient
– V
Rlth
: changed coefficient
Changed status from target specification to preliminary data.
Updated following tables:
–
–
Added
Section 2.4: Electrical characteristics curves .
Added
Chapter 4: Package and PC board thermal data
Updated
Figure 27: HPAK thermal impedance junction ambient single pulse
Updated
Updated
Section 3.1: Voltage regulator
22/24 DS6143 Rev 13
L5300AH7 Revision history
Date
09-Mar-2011
18-Nov-2011
26-Jan-2012
07-Feb-2012
13-Sep-2013
21-Sep-2018
Table 10. Document revision history (continued)
Revision Changes
8
9
10
11
12
13
Updated following tables:
:
– Updated pins sequence
Table 3: Absolute maximum ratings :
– I sdc
: changed symbol from I
Vsdc
– I odc
: changed symbol from I
Vodc
:
– I short
: changed min/typ/max value
– I lim
: changed min/typ/max value, changed parameter
– V line
: changed test condition
– I qn_300
: changed typ value
– Updated tablefootnote
:
– V
Res_l
: changed test condition
– V
Res_lkg
: added test condition
:
– I leak
: changed typ value
Updated
Table 9: HPAK mechanical data :
– b: updated values
Updated
Figure 22: Stability region on page 15 .
Modified
Figure 22: Stability region on page 15 .
Updated disclaimer.
Updated template.
Updated title and
DS6143 Rev 13 23/24
23
L5300AH7
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