STMicroelectronics L4988 Datasheet

L4988

Automotive low drop voltage regulator

*$3*&)7

SO-8

*$3*&)7

SO-20

Features

Max DC supply voltage

Max output voltage tolerance

Max dropout voltage

Output current

Quiescent current

1.

Typical value with watchdog disabled.

V

S

∆ V o

V dp

I o

I qn

40V

+/-2%

500 mV

200 mA

75 µA

(1)



AEC-Q100 qualified



Operating DC supply voltage range 5.6 V to 31 V



Reset circuit sensing the output voltage down to 1V



Programmable reset pulse delay with external capacitor



Watchdog

Table 1.

Device summary

Package

SO8

SO20 (16+2+2)

Tube

L4988D

L4988MD

Datasheet

-

production data









Programmable watchdog timer with external capacitor

Enable input for enabling/disabling the watchdog functionality

Thermal shutdown and short circuit protection

Wide temperature range (Tj = -40°C to 150°C)

Description

The L4988 is a monolithic integrated 5V voltage regulator with a low drop voltage at currents up to

200mA. The output voltage regulating element consists in a p-channel MOS and the regulation is performed regardless of input voltage transients up to 40V. The high precision of the output voltage is obtained with a pre-trimmed reference voltage. The L4988 is protected against short circuit and an over-temperature protection switches off the device in case of extremely high power dissipation. The L4988 is active when the

Enable is high. State of the art features like reset and watchdog make this device particularly suitable to supply microprocessor systems in automotive applications.

Order codes

Tape & reel

L4988DTR

September 2018

This is information on a product in full production.

DS5334 Rev 8 1/32 www.st.com

1

2

Contents

Contents

3

4

5

6

L4988

Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.5

Test circuit and waveforms plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.1

Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1

SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2

SO-20 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1

ECOPACK

®

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2

SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3

SO-20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.4

SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.5

SO-20 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/32 DS5334 Rev 8

L4988

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Watchdog Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9.

SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10.

SO-20 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 11.

SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 12.

SO-20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 13.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DS5334 Rev 8 3/32

3

List of figures

List of figures

L4988

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

Output voltage vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4.

Output voltage vs. Vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5.

Drop Voltage vs. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6.

Current consumption vs. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7.

Current consumption vs. Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 8.

Current limitation vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 9.

Current limitation vs. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 10.

Short Circuit Current vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 11.

Short Circuit Current vs. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 12.

V

WEn_high

vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 13.

V

WEN_LOW

vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 14.

Vrhth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 15.

Vrlth vs.Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 16.

Vwhth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 17.

Vwlth vs. T

j

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 18.

Icr & Icwc vs. T j

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 19.

Idr & Icwd vs.T

j

Figure 20.

Twop vs. T

j

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 21.

PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 22.

Load regulation test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 23.

Maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 24.

L4988 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 25.

Behavior of output current versus regulated voltage Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 26.

Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 27.

Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 28.

SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 29.

SO-8 Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . 19

Figure 30.

SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 31.

SO-8 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 32.

SO-20 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 33.

SO-20 Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . 22

Figure 34.

SO-20 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 35.

SO-20 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 36.

SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 37.

SO-20 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 38.

SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 39.

SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 40.

SO-20 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4/32 DS5334 Rev 8

L4988

1

Block diagram and pin configuration

Block diagram and pin configuration

Figure 1.Block diagram

,

6

9P$

,

2

9

6

,

&:

,

ZL

9

&:

9

:L

,

:(Q

9

:(Q

,

FU

9

FU

,

5HV

9

5HV

9

2

*QG

("1(3*

DS5334 Rev 8 5/32

31

Block diagram and pin configuration

Pin name

WEn

Gnd

Gnd

Res

Vcr

Vcw

Wi

Vo

Vs

N.C.

8&/

*1'

5(6

9 FU

L4988

SO8(D)

1

2

3

4

5

6

7

8

Table 2. Pins description

S020(MD) Function

1

4

5, 6, 15, 16

7

10

11

Watchdog Enable input

If high watchdog functionality is active

Ground reference

Ground.

Connected these pins to a heat spreader ground

Reset output.

It is pulled down when output voltage goes below Vo_th or frequency at Wi is too low.

Reset timing adjust.

A capacitor between Vcr pin and gnd, sets the reset delay time (trd)

Watchdog timer adjust

A capacitor between Vcw pin and gnd, sets the time response of the watchdog monitor.

14

17

20

Watchdog input.

If the frequency at this input pin is too low, the Reset output is activated.

Voltage regulator output

Block to ground with a capacitor >100nF (needed for regulator stability)

Supply voltage

Block to ground directly at IC pin with a capacitor

2, 3, 8, 9, 12,

13, 18, 19

Not connected

62

Figure 2.Pins configuration

9

9

2

:L

9

6

FZ

*$3*5,

*1'

5(6

1&

1 &

9FU

:(1

1&

1&

*1'

*1'

62

9

6

1&

1&

9

2

*1'

*1'

:L

1&

1 &

9FZ

*$3*5,

6/32 DS5334 Rev 8

L4988 Electrical specifications

2.1 Absolute maximum ratings

Symbol

Table 3. Absolute maximum ratings

Parameter Value Unit

V cw

V

WEn

T j

V

ESD

V

ESD

V

Vsdc

I

Vsdc

V

Vo

I

Vo

V

Wi

V od

I od

V cr

DC supply voltage

Input current

DC output voltage

DC output current

Watchdog input voltage

Open Drain output voltage

Open Drain output current

Reset delay voltage

Watchdog delay voltage

Watchdog Enable input voltage

Junction temperature

ESD voltage level (HBM-MIL STD 883C)

ESD voltage level (CDM AEC-Q100-011)

-0.3 to 40

Internally

-0.3 to 6

Internally limited

-0.3 to V

-0.3 to V

Internally limited

-0.3 to V limited

Vo

Vo

Vo

-0.3 to V

Vo

-0.3 to V

Vo

(1)

+ 0.3

+ 0.3

+ 0.3

+ 0.3

+0.3

-40 to 150

±2

750

1.

Using the typical application schematic with Cout= 10 µF and Iout=0 A, when the regulator is switched-on, an overshoot exceeding 6 V could occur.This behavior does not impact the reliability of the regulator.

V

V

V

V

V

V

V

“C kV

V

Symbol

Table 4. Thermal data

Parameter

R th-jamb

Thermal resistance junction to ambient

1.

With copper area 2 cm

2

; for details see

Figure 29

.

2.

With copper area 6 cm

2

; for details see

Figure 33

.

S08

130

(1)

S016+2+2

51

(2)

Unit

°C/W

DS5334 Rev 8 7/32

31

Electrical specifications L4988

V s

=5.6V to 31V, T j

= -40°C to +150°C unless otherwise specified.

Pin Symbol Parameter

Table 5. General

Test condition Min.

Typ.

Max.

Unit

Vo

Vo

Vo

Vs, Vo

Vo

Vs, Vo

Vs, Vo

Vs, Vo

Vs, Vo

Vs, Vo

I

I

V

I

I short lim

(2)

V o_ref line

V load

V dp

(3)

V dp

(3)

SVR qn_200 qn_50

Output voltage

Short circuit current

Output current limitation

Line regulation voltage

Load regulation voltage

Drop voltage

Drop voltage

Ripple rejection

Quiescent current

Quiescent current

Vs = 6 to 31V

Io = 1 to 200mA

Vs = 13.5V

(1)

Vs = 13.5V

(1)

Vs = 6 to 31V

Io = 1 to 200mA

Io = 1 to 200mA

Io = 200mA

Io = 150mA fr = 100 Hz

(4)

Vs=13.5V, Io=200mA,

WEn = high

Vs=13.5V,

Io= 50mA,

WEn = high

4.9

200

200

5.0

280

350

270

200

60

1.9

500

5.1

500

600

25

25

500

400

2.5

700

V mA mA mV mA

µA

Vs, Vo

Vs, Vo I

I q_1_we q_1_wd

Quiescent current

Quiescent current

Vs=13.5V,

Io< 1mA,

WEn = high

Vs=13.5V,

Io< 1mA,

WEn = low

93

75

200

150

µA

µA

Tw

Tw_hy

Thermal protection temperature

Thermal protection temperature hysteresis

150

10

190 °C

°C

1.

See

Figure 3 .

2.

Measured output current when the output voltage has dropped 100mV from its nominal value obtained at Vs=13.5V and

Io= 75mA .

3.

Vs-Vo measured when the output voltage has dropped 100mV from its nominal value obtained at Vs=13.5V and Io= 75mA .

4.

Guaranteed by design.

mV mV mV dB

8/32 DS5334 Rev 8

L4988 Electrical specifications

Pin

Wi

Wi

Wi

Wi

Vcw

Vcw

Vcw

Pin

Res

Res

Res

Res

Vcr

Vcr

Vcr

Vcr

Res

Res

Symbol

Vres_l

I

Res_h

R_p_u

Vo_th

Vrlth

Vrhth

Icr

Idr

Trr_2

Trd

Table 6. Reset

Parameter

Reset output low voltage

Test condition

R ext

= 5 k



to Vo,

Vo > 1 V

Reset output high leakage current

V

Res

= 5 V

Pull up internal resistance With respect to Vo

Vo out of regulation threshold

Vs = 6 to 31V,

Io = 1 to 200mA

Reset timing low threshold Vs = 13.5V

Reset timing high threshold Vs =13.5V

Charge current

Discharge current

Reset reaction time

(1)

Reset delay time

Vs = 13.5V

Vs = 13.5V

Vo = V o_ th

-100mV

Vs = 13.5V,

Ctr = 1nF

Min.

Typ.

Max.

Unit

12 25 50 k



6% 8% 10%

Below

V o_ref

10% 13% 16% V o_ref

44% 47% 50% V o_ref

8 17.6

30 µA

8 17.6

30 µA

100 275 1000 µs

65

0.4

1

150

1.

When Vo becomes lower than 4V, the reset reaction time decreases down to 2µs assuring a faster reset condition in this particular case.

V

µA ms

Vcw

Vcw

Res

Symbol

Vih

Vil

Vih

Ii

Vwhth

Vwlth

Icwc

Icwd

Twop twol

Table 7. Watchdog

Parameter Test condition

Input high voltage

Input low voltage

Input hysteresis

Pull down current

High threshold

Low threshold

Charge current

Discharge current

Watchdog period

Watchdog output low time

Vs = 13.5V

Vs = 13.5V

Vs = 13.5V

Vs = 13.5V

Vs = 13.5V

Vs = 13.5V

Vs = 13.5V,

Vcw = 0.1V

Vs = 13.5V,

Vcw = 2.5V

Vs = 13.5V,

Ctw = 47nF

Vs = 13.5V,

Ctw = 47nF

Min.

Typ.

Max.

Unit

3.5

1.5

V

V mV 500

10 20 µA

44% 47% 50% V o_ref

10% 13% 16% V o_ref

4 8 14 µA

1.0

2.1

4.5

µA

25

6

50 90 ms

10.5

22 ms

DS5334 Rev 8 9/32

31

Electrical specifications

Pin

WEn

WEn

WEn

WEn

Symbol

V

En_l

V

En_h

V

En_hy

I_leak

Table 8. Watchdog Enable

Parameter Test condition

Enable input low voltage

Enable input high voltage

Enable input hysteresis

Pull down current WEn = 5V

L4988

Min.

Typ.

Max.

Unit

3

500

2

1 V

V

800 1100 mV

8 20 µA

10/32 DS5334 Rev 8

L4988

Figure 3. Output voltage vs. Tj

9RBUHI9

9V 9

, P$

Electrical specifications

Figure 4. Output voltage vs. Vs

9RBUHI9

, P$

7M ƒ&

7Mƒ&

("1(3*

Figure 5. Drop Voltage vs. Output Current

9GS9

9V9

("1(3*

Figure 6. Current consumption vs. Output

Current

,TQ—$

9V 9

7M ƒ&

:(Q +LJK

7M ƒ&

7M ƒ&

,RP$

("1(3*

Figure 7. Current consumption vs. Input Voltage

,TQ—$

7M ƒ&

:(Q +LJK

,R P$

,R P$

,R P$

,R P$

9V9

("1(3*

,RP$

("1(3*

Figure 8. Current limitation vs. Tj

,OLPP$

9V 9

7Mƒ&

("1(3*

DS5334 Rev 8 11/32

31

Electrical specifications

Figure 9. Current limitation vs. Input Voltage

,OLPP$

Figure 10. Short Circuit Current vs. Tj

,VKRUWP$

L4988

7M ƒ&

7M ƒ&

9V 9

9V9

("1(3*

Figure 11. Short Circuit Current vs. Input

Voltage

,VKRUWP$

7M ƒ&

7M ƒ&

7Mƒ&

("1(3*

Figure 12. V

WEn_high vs. Tj

9ZHQBKLJK9

9V 9WR9

9V9

("1(3*

Figure 13. V

WEN_LOW

vs. Tj

9ZHQBORZ9

9V 9WR9

7Mƒ&

("1(3*

Figure 14. Vrhth vs. Tj

9UKWK9RBUHI

9V 9WR9

12/32

7Mƒ&

("1(3*

DS5334 Rev 8

7Mƒ&

("1(3*

L4988

Figure 15. Vrlth vs.Tj

9UOWK9RBUHI

9V 9WR9

Electrical specifications

Figure 16. Vwhth vs. Tj

9ZKWK9RBUHI

9V 9WR9

7Mƒ&

("1(3*

Figure 17. Vwlth vs. T j

9ZOWK9RBUHI

9V 9WR9

Figure 19. Idr & Icwd vs.T

j

,GU ,FZG—$

,GU

,FZG

9V 9WR9

7Mƒ&

("1(3*

Figure 18. Icr & Icwc vs. T j

,FU ,FZF—$

9V 9WR9

,FU

,FZF

7Mƒ&

Figure 20. Twop vs. T j

7ZRSPV

9V 9WR9

&WZ Q)

7Mƒ&

("1(3*

DS5334 Rev 8 13/32

31

Electrical specifications

& —)

Figure 21. PSRR

3655>G%@

L4988

2.5

)5(48(1&<>.+]@

Test circuit and waveforms plot

("1(3*

Figure 22. Load regulation test circuit

*$3*5,

14/32 DS5334 Rev 8

L4988 Electrical specifications

Figure 23.Maximum load variation response

V

0

[1

I

0

[50

0,00E+00 5,00E-05 1,50E-04 2,00E-04

Time [s]

2,50E-04 3,00E-04 3,50E-04 4,00E-04

DS5334 Rev 8 15/32

31

Application information L4988

Figure 24.L4988 application schematic

9L 9V

&V

&WZ

9FZ

:L

9R

& &

Note:

:(Q

5HV

9FU

&WU

*QG

*$3*5,

The input capacitor Cs > 200nF is necessary for the smoothing of line disturbances. The output capacitor Co1 > 100nF is necessary for the stability of the regulation loop. In order to damp output voltage oscillations during high load current surges, it is recommended to put an additional electrolytic capacitor Co2 > 10µF at the output pin.

Voltage regulator uses a p-channel mos transistor as a regulating element. With this structure a very low dropout voltage at currents up to 200mA is obtained. The output voltage is regulated up to transient input supply voltage of 40V. No functional interruption due to over-voltage pulses is generated. A short circuit protection to GND is provided.



The high precision of the output voltage is obtained with a pre-trimmed reference voltage.

16/32 DS5334 Rev 8

L4988 Application information

Figure 25.Behavior of output current versus regulated voltage Vo

("1($'5

3.2 Reset

The reset circuit supervises the output voltage Vo. The Vo_th reset threshold is defined with the internal reference voltage and a resistor output divider. If the output voltage becomes lower than Vo_th then Res goes low with a reaction time trr. The reset low signal is guaranteed for an output voltage Vo greater than 1V.

When the output voltage becomes higher than Vo_th then Res goes high with a delay trd.

This delay is obtained by an internal oscillator.

The oscillator period is given by:

Tosc = [(Vrhth-Vrlth) x Ctr] / Icr + [(Vrhth-Vrlth) x Ctr] / Idr where:

Icr: is an internally generated charge current

Idr: is an internally generated discharge current

Vrhth, Vrlth: are two voltages defined with the output voltage and a resistor output

 divider

Ctr: is an external capacitance.

trd is given by: trd = 512 x Tosc

Reset is active when En is high.

DS5334 Rev 8 17/32

31

Application information L4988

Figure 26.Reset timing diagram

: L

9 R

9 FU

WUU

5HV

WUU

7 RVF

WUG 7 RVF

9 RXWBWK

9 UKWK

9 UOWK

*$3*&)7

3.3 Watchdog

A connected microcontroller is monitored by the watchdog input Wi. If pulses are missing, the Reset output pin is set to low. The pulse sequence time can be set within a wide range with the external capacitor, C tw constant current I cwd

. The watchdog circuit discharges the capacitor C

. If the lower threshold V wlth tw

, with the

is reached, a watchdog reset is generated.

To prevent this the microcontroller must generate a positive edge during the discharge of the capacitor before the voltage has reached the threshold V wlth

. In order to calculate the minimum time t, during which the micro-controller must output the positive edge, the following equation can be used:

(V whth

-V wlth

) x C tw

= I cwd

x t

Every Wi positive edge switches the current source from discharging to charging. The same happens when the lower threshold is reached. When the voltage reaches the upper threshold, V whth

, the current switches from charging to discharging. The result is a saw-tooth voltage at the watchdog timer capacitor C tw

.

Figure 27.Watchdog timing diagram

:L

9FZ

5HV

WZRO

7ZRS

9ZKWK

9ZOWK

9ZOWK

*$3*5,

18/32 DS5334 Rev 8

L4988

4

4.1

Package and PCB thermal data

SO-8 thermal data

Figure 28.SO-8 PC board

Package and PCB thermal data

Note:

*$3*&)7

Layout condition of R th

and Z th

measurements (PCB FR4 area= 58mm x 58mm, PCB thickness = 2mm, Cu thickness = 35µm , Copper areas: from minimum pad lay-out to 8cm

2

)

Figure 29.SO-8 R thj-amb

Vs. PCB copper area in open box free air condition

57+MBDPEYV&XKHDWVLQNDUHD

57+MDPE

3&%&XKHDWVLQNDUHDFPA

*$3*&)7

DS5334 Rev 8 19/32

31

20/32

3 D F N D J H D Q G 3 & % W K H U P D O G D

L4988

Figure 30.SO-8 thermal impedance junction ambient single pulse

=7+ƒ&:

FP

7LPHV

*$3*5,

Equation 1: pulse calculation formula

Z

TH

 = R

TH

 

+ Z

THtp



1 –

  where



= t

P

/T

Figure 31.SO-8 thermal fitting model of a single channel

*$3*&)7

DS5334 Rev 8

L4988 Package and PCB thermal data

Area/island (cm

2

)

Table 9. SO-8 thermal parameter

Footprint

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1 (W.s/°C)

C2 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

4.21

2.11

2

41

40

58

0.00029

0.0024

0.03

0.04

0.1

1.05

2

40

2

DS5334 Rev 8 21/32

31

Package and PCB thermal data

4.2 SO-20 thermal data

Figure 32.SO-20 PC board

L4988

Note:

.

*$3*&)7

Layout condition of R th

and Z th

measurements (PCB FR4 area= 58mm x 58mm,PCB thickness = 2mm, Cu thickness=35

 m , Copper areas: from minimum pad lay-out to 8cm

2

).

Figure 33.SO-20 R thj-amb

Vs. PCB copper area in open box free air condition

57+MBDPEYV&XKHDWVLQNDUHD

57+MDPE

22/32

3&%&XKHDWVLQNDUHDFPA

("1($'5

DS5334 Rev 8

L4988 Package and PCB thermal data

Figure 34.SO-20 thermal impedance junction ambient single pulse

=7+ƒ&:

&X FP

&X IRRWSULQW

7LPHV

("1($'5

Equation 2: pulse calculation formula

Z

TH

 = R

TH where



= t

P

/T

 

+ Z

THtp



1 –

 

Figure 35. SO-20 thermal fitting model of a single channel

DS5334 Rev 8

*$3*&)7

23/32

31

Package and PCB thermal data

Table 10. SO-20 thermal parameter

Area/island (cm

2

) Footprint

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1 (W.s/°C)

C2 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

4.21

2.11

2.2

10

15

35

0.00029

0.0024

0.015

0.15

1.5

4

18

7

2

L4988

24/32 DS5334 Rev 8

L4988

5

Package and packing information

Package and packing information

5.1 ECOPACK

®

packages

In order to meet environmental requirements, ST offers these devices in ECOPACK

® packages. These packages have a Lead-free second-level interconnect. The category of

Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

5.2 SO-8 package information

Figure 36.SO-8 package dimensions

DS5334 Rev 8

*$3*&)7

25/32

31

Package and packing information L4988

Table 11. SO-8 mechanical data

Millimeters

Symbol

Min.

Typ.

Max.

A

A1

1.75

0.25

A2 b

0.10

1.25

0.28

0.48

0.23

c

D

(1)

E

E1

(2)

0.17

4.80

5.80

3.80

4.90

6.00

3.90

1.27

5.00

6.20

4.00

e h 0.25

0.40

0.50

1.27

L

L1 k

1.04

0° 8° ccc 0.10

1.

Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm in total (both side).

2.

Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side.

26/32 DS5334 Rev 8

L4988

5.3

Package and packing information

SO-20 package information

Figure 37.SO-20 package dimensions

Symbol

H h

E e

L

A

A1

B

C

D

(1)

Table 12. SO-20 mechanical data

Millimeters

Typ.

Min.

2.35

0.10

0.33

0.23

12.60

7.40

1.27

10.0

0.25

0.40

DS5334 Rev 8

("1($'5

Max.

2.65

0.30

0.51

0.32

13.00

7.60

10.65

0.75

1.27

27/32

31

Package and packing information L4988

Table 12. SO-20 mechanical data (continued)

Millimeters

Symbol

Min.

Typ.

Max.

k 0° 8° ddd 0.10

1.

“D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.

5.4 SO-8 packing information

%

Figure 38.SO-8 tube shipment (no suffix)

&

$

Base q.ty

Bulk q.ty

Tube length (± 0.5)

A

B

C (± 0.1)

All dimensions are in mm.

100

2000

532

3.2

6

0.6

*$3*5,

28/32 DS5334 Rev 8

L4988 Package and packing information

Figure 39.SO-8 tape and reel shipment (suffix “TR”)

DS5334 Rev 8 29/32

31

Package and packing information

5.5 SO-20 packing information

Figure 40.SO-20 tube shipment (no suffix)

&

$

%

Base Q.ty

Bulk Q.ty

Tube length (± 0.5)

A

B

C (± 0.1)

All dimensions are in mm.

40

800

532

3.5

13.8

0.6

*$3*5,

L4988

30/32 DS5334 Rev 8

L4988 Revision history

Date

01-Jun-2007

30-Aug-2007

13-Feb-2008

04-Jun-2008

05-Apr-2012

20-Sep-2013

13-Sep-2018

18-Sep-2018

Revision

1

2

3

4

5

6

7

8

Table 13. Document revision history

Changes

Initial release

Added features table.

Added list of tables and figures.

Updated Section 2.3: Electrical characteristics .

Added Section 4: Package and PCB thermal data

.

Added SO-8 packing information and

SO-20 packing information

.

Update

Section 2.3: Electrical characteristics

.

Document restructured.

Changed

Figure 1: Block diagram

.

Updated features table on cover page: changed quiescent current value from

80 to 75 µA.

Updated Table 5: General

:

– changed I short

typical value from 250 to 280 mA

– changed I qn_50 typical value from 550 to 500 µA

– changed I q_1_we typical value from 130 to 93 µA

– changed I q_1_wd typical value from 80 to 75 µA.

Updated Table 7: Watchdog :

– changed Vwlth values in V o_ref percentages

– changed Vwhth values in V o_ref percentages.

Added Figure 24: L4988 application schematic .

Added Section 2.4: Electrical characteristics curves

.

Added Section 2.5: Test circuit and waveforms plot .

Update

Table 3: Absolute maximum ratings .

Updated disclaimer.

Updated title and Features

.

Minor text changes.

Typo errors.

DS5334 Rev 8 31/32

31

L4988

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32/32 DS5334 Rev 8