STMicroelectronics L4993 Datasheet

L4993

Automotive low drop voltage regulator

Datasheet

-

production data

*$3*&)7

SO-8 SO-20

*$3*&)7

Features

Max DC supply voltage

Max output voltage tolerance

Max dropout voltage

Output current

Quiescent current

1. Typical value with watchdog disabled.

V

S

∆ V

0

V dp

I

0

I qn

40 V

+/-2%

400 mV

150 mA

79 μ A

(1)

Description

The L4993 is a monolithic integrated 5 V Voltage regulator with a low drop voltage at currents up to

150 mA.The output voltage regulating element consists in a p-channel MOS and the regulation is performed regardless of input voltage transients up to 40 V. The high precision of the output voltage is obtained with a pre-trimmed reference voltage. The L4993 is protected against short circuit and an over-temperature protection switches off the device in case of extremely high power dissipation. The L4993 watchdog is active when the Enable is high. State of the art features like reset and watchdog make this device particularly suitable to supply microprocessor systems in automotive applications.

 AEC-Q100 qualified

 Operating DC supply voltage range 5.6 V to 31 V

 Reset circuit sensing the output voltage down to 1 V

 Programmable reset pulse delay with external capacitor

 Watchdog

 Programmable watchdog timer with external

 Enable input for enabling/disabling the watchdog functionality

 Thermal shutdown and short circuit protection

 Wide temperature range (Tj = -40°C to 150°C)

Table 1. Device summary

Order codes

Package

Tube

SO-8

SO-20 (16+2+2)

—

L4993MD

Tape & reel

L4993DTR

L4993MDTR

September 2018

This is information on a product in full production.

DS5285 Rev 10

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www.st.com

1

2

Contents

Contents

3

4

5

6

L4993

Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.5

Test circuit and waveforms plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.1

Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1

SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2

SO-20 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1

ECOPACK

®

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2

SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3

SO-20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.4

SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.5

SO-20 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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DS5285 Rev 10

L4993

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Watchdog Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9.

SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10.

SO-20 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 11.

SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 12.

SO-20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 13.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

DS5285 Rev 10

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3

List of figures

List of figures

L4993

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

Output voltage vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4.

Output voltage vs. Vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5.

Drop Voltage vs. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6.

Current consumption vs. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7.

Current consumption vs. Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 8.

Current limitation vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 9.

Current limitation vs. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 10.

Short Circuit Current vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 11.

Short Circuit Current vs. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 12.

V

WEn_high

vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 13.

V

WEN_LOW

vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 14.

Vrhth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 15.

Vrlth vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 16.

Vwhth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 17.

Vwlth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 18.

Icr & Icwc vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 19.

Idr & Icwd vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 20.

Twop vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 21.

PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 22.

Load regulation test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 23.

Maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 24.

L4993 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 25.

Behavior of output current versus regulated voltage Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 26.

Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 27.

Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 28.

SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 29.

Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 19

Figure 30.

SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 31.

Thermal fitting model of Vreg in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 32.

SO-20 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 33.

Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 22

Figure 34.

SO-20 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 35.

Thermal fitting model of Vreg in SO-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 36.

SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 37.

SO-20 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 38.

SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 39.

SO-20 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 40.

SO-20 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4/31

DS5285 Rev 10

L4993

1

Block diagram and pins description

Block diagram and pins description

Figure 1. Block diagram

,

6

9P$

,

2

9

6

,

&:

,

ZL

9

&:

9

:L

,

:(Q

9

:(Q

,

FU

9

FU

*QG

9

2

,

5HV

9

5HV

("1(3*

DS5285 Rev 10

5/31

30

Block diagram and pins description

Pin name

WEn

Gnd

Gnd

Res

Vcr

Vcw

Wi

Vo s

Vs

N.C.

L4993

SO-8 (D)

1

2

3

4

5

6

7

8

Table 2. Pins description

SO-20 (MD) Function

1

4

5, 6, 15, 16

7

10

Watchdog Enable input

If high watchdog functionality is active

Ground reference

Ground

Connected these pins to a heat spreader ground

Reset output.

It is pulled down when output voltage goes below Vo_th or frequency at Wi is too low.

Leave floating if not used.

Reset timing adjust.

A capacitor between Vcr pin and gnd, sets the reset delay time (trd)

11

14

17

Watchdog timer adjust

A capacitor between Vcw pin and gnd, sets the time response of the watchdog monitor.

Watchdog input.

If the frequency at this input pin is too low, the Reset output is activated.

Connect to ground if not used

Voltage regulator output

Block to ground with a capacitor >100 nF (needed for regulator stability)

20

Supply voltage

Block to ground directly at IC pin with a capacitor

2, 3, 8, 9, 12,

13, 18, 19

Not connected

8&/

*1'

5(6

9 FU

62

Figure 2. Pins configuration

9

6

9

26

:L

9 FZ

*$3*5,

:(1

1&

1&

*1'

*1'

*1'

5(6

1&

1 &

9FU

62

9

6

1&

1&

9

26

*1'

*1'

:L

1&

1 &

9FZ

*$3*5,

6/31

DS5285 Rev 10

L4993 Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in Table 3: Absolute maximum ratings may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in the table below for extended periods may affect device reliability.

Symbol

Table 3. Absolute maximum ratings

Parameter Value Unit

V

Vsdc

I

Vsdc

V

Vo

I

Vo

V

Wi

V od

I od

V cr

V cw

V

WEn

T j

V

ESD

V

ESD

DC supply voltage

Input current

DC output voltage

DC output current

Watchdog input voltage

Open drain output voltage

Open drain output current

Reset delay voltage

Watchdog delay voltage

Watchdog Enable input voltage

Junction temperature

ESD voltage level (HBM-MIL STD 883C)

ESD voltage level (CDM AEC-Q100-011)

-0.3 to 40

Internally limited

-0.3 to 6

(1)

Internally limited

-0.3 to V

-0.3 to V

Internally limited

-0.3 to V

-0.3 to V

-0.3 to V

Vo

Vo

Vo

Vo

Vo

+ 0.3

+ 0.3

+ 0.3

+ 0.3

+0.3

-40 to 150

±2

750

V

V

V

V

V

V

V

°C kV

V

1. Using the typical application schematic with Cout= 10 µF and Iout=0 A, when the regulator is switched-on, an overshoot exceeding 6 V could occur.This behavior does not impact the reliability of the regulator.

For details, please refer to Section 4.1: SO-8 thermal data

and Section 4.2: SO-20 thermal data .

Table 4. Thermal data

(1)

Parameter Symbol Value Unit

R th-jamb

Thermal resistance Junction to Ambient:

SO-8

SO-20

130

51

°C/W

°C/W

1. The values quoted are for PCB FR4 area= 58mm x 58mm, PCB thickness = 2 mm, Cu thickness = 35 µm,

Copper areas: SO-8= 2 cm

2

, SO-20= 6 cm .

DS5285 Rev 10

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30

Electrical specifications L4993

Values specified in this section are for V s otherwise stated.

=5.6 V to 31 V, T j

= -40°C to +150°C unless

Pin Symbol

Table 5. General

Parameter Test condition Min.

Typ.

Max.

Unit

Vo

Vo

Vo

Vs, Vo

Vo

Vs, Vo

Vs, Vo

Vs, Vo

Vs, Vo

Vs, Vo

Vs, Vo

I

I

V

I

I

V

V

V qn_150

I o_ref short lim

(2) dp

(3)

SVR qn_50 qn_1

I line load qs

Output voltage

Short circuit current

Output current limitation

Line regulation voltage

Load regulation voltage

Drop voltage

Ripple rejection

Quiescent current

Quiescent current

Quiescent current

Quiescent current with watchdog regulator disabled

Vs = 6 to 31 V

Io = 1 to 150 mA

Vs = 13.5 V (1)

Vs = 13.5 V

(1)

Vs = 6 to 31 V

Io = 1 to 150 mA

Io = 1 to 150 mA

Io = 150 mA fr = 100 Hz

(4)

Vs=13.5 V,

Io=150 mA,

WEn = high

Vs=13.5 V,

Io= 50 mA,

WEn = high

Vs=13.5 V,

Io< 1mA,

WEn = high

Vs=13.5 V,

Io< 1mA,

WEn = low

4.9

150

150

55

5.0

280

320

1.25

470

100

79

5.1

400

500

25

25

2

1000

180

125

V mA mA mV mV

200 400 mV dB mA

µA

µA

µA

Tw

Tw_hy

Thermal protection temperature

Thermal protection temperature hysteresis

150

10

190 °C

°C

1. See

Figure 25

.

2. Measured output current when the output voltage has dropped 100 mV from its nominal value obtained at

Vs=13.5 V and Io= 75 mA .

3. Vs-Vo measured when the output voltage has dropped 100mV from its nominal value obtained at

Vs=13.5 V and Io= 75 mA .

4. Guaranteed by design.

8/31

DS5285 Rev 10

L4993 Electrical specifications

Pin

Res

Res

Res

Res

Vcr

Vcr

Parameter

Table 6. Reset

Test condition Symbol

Vres_l Reset output low voltage

R ext

= 5 k  to Vo,

Vo > 1 V

I

Res_h

Reset output high leakage current

V

Res

= 5 V

R_p_u

Vo_th

Pull up internal resistance

Vo out of regulation threshold

With respect to Vo

Vs = 6 to 31 V,

Io = 1 to 150 mA

Vrlth

Vrhth

Reset delay circuit low threshold

Reset delay circuit high threshold

Vs = 13.5 V

Vs =13.5 V

Icr Charge current Vs = 13.5 V

Min.

Typ.

Max.

Unit

0.4

1

V

µA

12 25 50 k 

6% 8% 10%

Below

V o_ref

10% 13% 16% V o_ref

44% 47% 50% V o_ref

8 17.6

30 µA Vcr

Vcr Idr Discharge current Vs = 13.5 V 8 17.6

30 µA

Res Trr_2 Reset reaction time

(1)

Vo = V o_ th

-100 mV 100 275 1000 µs

Res Trd Reset delay time

Vs = 13.5 V,

Ctr = 1 nF

65 150 ms

1. When Vo becomes lower than 4 V, the reset reaction time decreases down to 2 µs assuring a faster reset condition in this particular case.

Pin

Wi

Wi

Wi

Wi

Vcw

Vcw

Vcw

Symbol

Vih

Table 7. Watchdog

Parameter

Input high voltage

Vil Input low voltage

Vih_hyst Input hysteresis

Ii Pull down current

Vwhth High threshold

Vwlth Low threshold

Icwc Charge current

Test condition Min.

Typ.

Max.

Unit

Vs = 13.5 V

Vs = 13.5 V

Vs = 13.5 V

Vs = 13.5 V

Vs = 13.5 V

Vs = 13.5 V

Vs = 13.5 V,

Vcw = 0.1 V

3.5

V

500

1.5

V mV

10 20 µA

44% 47% 50% V o_ref

10% 13% 16% V o_ref

4 8 14 µA

DS5285 Rev 10

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30

Electrical specifications L4993

Pin

Vcw

Vcw

Res

Symbol

Icwd

Twop twol

Table 7. Watchdog (continued)

Parameter Test condition Min.

Typ.

Max.

Unit

Discharge current

Watchdog period

Watchdog output low time

Vs = 13.5 V,

Vcw = 2.5 V

Vs = 13.5 V,

Ctw = 47 nF

Vs = 13.5 V,

Ctw = 47 nF

1.0

2.13

4.5

25 50 90

6 10.5

22

µA ms ms

Table 8. Watchdog Enable

Parameter Test condition Min.

Typ.

Max.

Unit Pin Symbol

WEn

WEn

WEn

WEn

W

En_low

Enable input low voltage

W

En_high

Enable input high voltage

W

En_hyst

Enable input hysteresis

I leak

Pull down current WEn = 5 V

3 V

500 800 1100 mV

2 8

1

20

V

µA

10/31

DS5285 Rev 10

L4993 Electrical specifications

0,25

0,2

0,15

0,1

0,05

0

-50

Figure 3. Output voltage vs. Tj

Vo_ref (V)

5,5

5,4

5,3

5,2

5,1

5

4,9

4,8

4,7

4,6

4,5

-50 -25 0

Vs= 13.5V

I0 = 75mA

25 50

Tj(°C )

75 100 125 150

Figure 5. Drop Voltage vs. Output Current

Vdp (V)

0,3

0

Tj= 125 °C

Tj= 25 °C

50

Io (mA)

100 150 200

Figure 7. Current consumption vs. Input Voltage

Iqn(µA )

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

0 5

Io= 100mA

10

Io =50mA

Io = 1mA

15

Vs (V )

20

Tj = 25 °C

En = High

25 30 35

Figure 4. Output voltage vs. Vs

Vo_ref (V)

10

5

4

3

2

7

6

9

8

1

0

0 5

I 0 = 75 mA

Tj = 25 °C

10 15

Vs (V )

20 25 30 35

Figure 6. Current consumption vs. Output

Current

Iqn (µA)

1500

1200

Vs= 13.5 V

Tj= 25 °C

En= High

900

600

300

0

-50 0 50

Io (mA)

100 150

Figure 8. Current limitation vs. Tj

200

Ilim (mA)

600

500

400

300

Vs= 13.5V

200

100

0

-50 -25 0 25 50

Tj(°C )

75 100 125 150

DS5285 Rev 10

11/31

30

Electrical specifications

Figure 9. Current limitation vs. Input Voltage

Ilim (mA)

350

325

300

275

250

225

Tj = 25 °C

Tj = 125 °C

200

0 5 10 15

Vs (V )

20 25 30 35

Figure 11. Short Circuit Current vs. Input

Voltage

Ishort (mA )

350

300

250

200

Tj = 25 °C

Tj = 150 °C

150

0 5 10 15

Vs (V )

20 25 30

Figure 13. V

WEN_LOW

vs. Tj

Vwen_low (V)

2

35

1,9

1,8

1,7

1,6

1,5

Vs= 5.6V to 31V

1,4

-50 -25 0 25 50

Tj(°C )

75 100 125 150

Figure 10. Short Circuit Current vs. Tj

Ishort (mA)

600

500

400

300

200

100

Vs= 13.5V

0

-50 -25 0 25 50

Tj(°C )

75 100 125 150

Figure 12. V

WEn_high

vs. Tj

Vwen_high (V)

4

3,5

3

2,5

Vs= 5.6V to 31V

2

1,5

1

-50 -25 0 25 50 75 100 125 150

Figure 14. Vrhth vs. Tj

Vrhth (% Vo_ref )

60

55

50

45

40

35

Vs= 5.6V to 31V

30

-50 -25 0 25 50

Tj(°C )

75 100 125 150

L4993

12/31

DS5285 Rev 10

L4993

Figure 15. Vrlth vs. Tj

Vrlth (% Vo_ref)

50

40

Vs= 5.6V to 31V

30

20

10

0

-50 -25 0 25 50

Tj(°C )

75 100 125 150

Figure 17. Vwlth vs. Tj

Vwlth (% Vo_ref)

50

40

Vs= 5.6V to 31V

30

20

10

0

-50 -25 0 25 50

Tj(°C )

75 100 125 150

Figure 19. Idr & Icwd vs. Tj

Idr & Icwd (µA)

30

Vs= 5.6V to 31V

25

20

Idr

15

10

5

Icwd

0

-50 -25 0 25 50

Tj(°C )

75 100 125 150

DS5285 Rev 10

Electrical specifications

55

50

45

40

35

Figure 16. Vwhth vs. Tj

Vwhth (% Vo_ref )

60

Vs= 5.6V to 31V

30

-50 -25 0 25 50

Tj(°C )

75 100 125 150

Figure 18. Icr & Icwc vs. Tj

Icr & Icwc (µA)

30

Vs= 5.6V to 31V

25

20

15

10

5

Icr

Icwc

0

-50 -25 0 25 50

Tj(°C )

75 100 125 150

Figure 20. Twop vs. Tj

Twop (ms)

80

70

60

50

40

30

Vs= 5.6V to 31V

Ctw= 47nF

20

-50 -25 0 25 50

Tj(°C )

75 100 125 150

13/31

30

Electrical specifications

2.5

Figure 21. PSRR

0,1

C

0

= 4.7µF

1 10 100

FREQUENCY [KHz]

1000

PSRR [dB]

80

70

60

50

40

30

20

10

0

10000

Test circuit and waveforms plot

Figure 22. Load regulation test circuit

L4993

*$3*5,

14/31

DS5285 Rev 10

L4993 Electrical specifications

Figure 23. Maximum load variation response

V

0

[1

I

0

[50

0,00E+00 5,00E-05 1,50E-04 2,00E-04

Time [s]

2,50E-04 3,00E-04 3,50E-04 4,00E-04

DS5285 Rev 10

15/31

30

Application information L4993

Figure 24. L4993 application schematic

9L 9V

&V

&WZ

9FZ

:L

9R

& &

Note:

&WU

:(Q

9FU

5HV

*QG

*$3*5,

The input capacitor Cs > 200 nF is necessary for the smoothing of line disturbances. The output capacitor C01 > 100 nF is necessary for the stability of the regulation loop. In order to damp output voltage oscillations during high load current surges, it is recommended put an additional electrolytic capacitor C02 > 10 µF at the output pin.

Voltage regulator uses a p-channel transistor as a regulating element. With this structure, very low dropout voltage at current up to 500 mA is obtained. The output voltage is regulated up to transient input supply voltage of 40 V. No functional interruption due to overvoltage pulses is generated. A short circuit protection to GND is provided. The voltage regulator watchdog functionality can be disabled by putting WEn low.

16/31

DS5285 Rev 10

L4993 Application information

Figure 25. Behavior of output current versus regulated voltage Vo

("1($'5

3.2 Reset

The reset circuit supervises the output voltage Vo. The Vo_th reset threshold is defined with the internal reference voltage and a resistor output divider. If the output voltage becomes lower than Vo_th then Res goes low with a reaction time trr. The reset low signal is guaranteed for an output voltage Vo greater than 1 V.

When the output voltage becomes higher than Vo_th then Res goes high with a delay trd.

This delay is obtained by an internal oscillator.

The oscillator period is given by:

Tosc = [(Vrhth-Vrlth) x Ctr] / Icr + [(Vrhth-Vrlth) x Ctr] / Idr where:

Icr: is an internally generated charge current

Idr: is an internally generated discharge current

Vrhth, Vrlth: are two voltages defined with the output voltage and a resistor output  divider

Ctr: is an external capacitance.

trd is given by: trd = 512 x Tosc

Reset is active when En is high.

DS5285 Rev 10

17/31

30

Application information L4993

Figure 26. Reset timing diagram

: L

9 R

9 FU

WUU

5HV

WUU

7 RVF

WUG 7 RVF

9 RXWBWK

9 UKWK

9 UOWK

*$3*&)7

3.3 Watchdog

A connected microcontroller is monitored by the watchdog input Wi. If pulses are missing, the Reset output pin is set to low. The pulse sequence time can be set within a wide range with the external capacitor, Ctw. The watchdog circuit discharges the capacitor Ctw, with the constant current Icwd. If the lower threshold Vwlth is reached, a watchdog reset is generated. To prevent this the microcontroller must generate a positive edge during the discharge of the capacitor before the voltage has reached the threshold Vwlth. In order to calculate the minimum time t, during which the micro-controller must output the positive edge, the following equation can be used:

(Vwhth-Vwlth) x Ctw = Icwd x t

Every Wi positive edge switches the current source from discharging to charging. The same happens when the lower threshold is reached. When the voltage reaches the upper threshold, Vwhth, the current switches from charging to discharging. The result is a saw-tooth voltage at the watchdog timer capacitor Ctw.

Figure 27. Watchdog timing diagram

:L

7ZRS

9FZ

5HV

WZRO

9ZKWK

9ZOWK

9ZOWK

*$3*5,

18/31

DS5285 Rev 10

L4993

4

4.1

Package and PCB thermal data

Package and PCB thermal data

SO-8 thermal data

Figure 28. SO-8 PC board

Note:

*$3*&)7

Layout condition of R th

and Z th

measurements (PCB FR4 area= 58mm x 58mm, PCB thickness = 2 mm, Cu thickness = 35 µm, Copper areas: from minimum pad lay-out to

2 cm

2

).

Figure 29. R thj-amb

Vs. PCB copper area in open box free air condition

57+MBDPEYV&XKHDWVLQNDUHD

57+MDPE

3&%&XKHDWVLQNDUHDFPA

DS5285 Rev 10

*$3*&)7

19/31

30

20/31

3 D F N D J H D Q G 3 & % W K H U P D O

L4993

Figure 30. SO-8 thermal impedance junction ambient single pulse

=7+ƒ&:

FP

7LPHV

Equation 1: pulse calculation formula

ZTH

 =

RTH where  = t

P

/T

 

+ –

 

Figure 31. Thermal fitting model of Vreg in SO-8

*$3*5,

*$3*&)7

DS5285 Rev 10

L4993 Package and PCB thermal data

Area/island (cm

2

)

Table 9. SO-8 thermal parameter

Footprint

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1 (W.s/°C)

C2 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

4.21

2.11

2

41

40

58

0.00029

0.0024

0.03

0.04

0.1

1.05

2

40

2

DS5285 Rev 10

21/31

30

Package and PCB thermal data

4.2 SO-20 thermal data

Figure 32. SO-20 PC board

L4993

Note:

.

*$3*&)7

Layout condition of R

6 cm

2

). th

and Z th

measurements (PCB FR4 area= 58mm x 58mm,PCB thickness = 2 mm, Cu thickness=35

 m, Copper areas: from minimum pad lay-out to

Figure 33. R thj-amb

Vs. PCB copper area in open box free air condition

57+MBDPEYV&XKHDWVLQNDUHD

57+MDPE

22/31

3&%&XKHDWVLQNDUHDFPA

("1($'5

DS5285 Rev 10

L4993 Package and PCB thermal data

Figure 34. SO-20 thermal impedance junction ambient single pulse

=7+ƒ&:

&X FP

&X IRRWSULQW

7LPHV

Equation 2: pulse calculation formula

ZTH

 = RTH where  = t

P

/T

 

+ –

 

Figure 35. Thermal fitting model of Vreg in SO-20

("1($'5

DS5285 Rev 10

*$3*&)7

23/31

30

Package and PCB thermal data

Table 10. SO-20 thermal parameter

Area/island (cm

2

) Footprint

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1 (W.s/°C)

C2 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

4.21

2.11

2.2

10

15

35

0.00029

0.0024

0.015

0.15

1.5

4

18

7

2

L4993

24/31

DS5285 Rev 10

L4993

5

Package and packing information

Package and packing information

5.1 ECOPACK

®

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

5.2 SO-8 package information

Figure 36. SO-8 package dimensions

Symbol

A

A1

A2 b

Table 11. SO-8 mechanical data

Millimeters

Min.

Typ.

0.10

1.25

0.28

DS5285 Rev 10

*$3*&)7

Max.

1.75

0.25

0.48

25/31

30

Package and packing information L4993

Table 11. SO-8 mechanical data (continued)

Millimeters

Symbol c

D

(1)

E

E1

(2) e

Min.

0.17

4.80

5.80

3.80

Typ.

4.90

6.00

3.90

1.27

Max.

0.23

5.00

6.20

4.00

h

L

0.25

0.40

0.50

1.27

L1 k 0°

1.04

8° ccc 0.10

1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both side).

2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side.

26/31

DS5285 Rev 10

L4993

5.3

Package and packing information

SO-20 package information

Figure 37. SO-20 package dimensions

Symbol

A

A1

B

C

D

(1)

E e

H h

L

Table 12. SO-20 mechanical data

Millimeters

Typ.

Min.

2.35

0.10

0.33

0.23

12.60

7.40

1.27

10.0

0.25

0.40

DS5285 Rev 10

("1($'5

Max.

2.65

0.30

0.51

0.32

13.00

7.60

10.65

0.75

1.27

27/31

30

Package and packing information L4993

Table 12. SO-20 mechanical data (continued)

Millimeters

Symbol k ddd

Min.

0°

Typ.

Max.

8°

0.10

1. “D” dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side.

5.4 SO-8 packing information

Figure 38. SO-8 tape and reel shipment (suffix “TR”)

28/31

DS5285 Rev 10

L4993

5.5

Package and packing information

SO-20 packing information

Figure 39. SO-20 tube shipment (no suffix)

&

%

Base Q.ty

Bulk Q.ty

Tube length (± 0.5)

A

B

C (± 0.1)

40

800

532

3.5

13.8

0.6

$

*$3*5,

Figure 40. SO-20 tape and reel shipment (suffix “TR”)

Reel dimensions

Base Q.ty

Bulk Q.ty

A (max)

B (min)

C (± 0.2)

D

G (+ 2 / -0)

N (min)

T (max)

1000

1000

330

1.5

13

20.2

24.4

60

30.4

Tape dimensions

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

W

P0 (± 0.1)

P

D (+ 0.1/-0)

D1 (min)

F (± 0.05)

K (max)

P1 (± 0.1)

24

4

12

1.5

1.5

11.5

6.5

2

All dimensions are in mm.

End

Top cover tape

No components

500mm min

Components No components

Empty components pockets saled with cover tape.

500mm min

User direction of feed

Start

GAPGRI00080

DS5285 Rev 10

29/31

30

Revision history L4993

Date

June-2004

18-Jan-2007

01-Jun-2007

22-Aug-2007

29-Aug-2007

08-Apr-2008

09-Mar-2012

20-Sep-2013

01-Mar-2018

19-Sep-2018

Revision

Table 13. Document revision history

Changes

7

8

1

2

3

4

5

6

9

10

Initial release.

Updated

Table 5.

,

6

,

7

and

8

.

Document put in corporate technical literature template.

Updated

Table 4.

Table 5: General

: updated I short

, I lim

, I q,

T rr2,

V ih_hist parameters.

Added list of tables and figures.

Added

Section 4: Package and PCB thermal data

.

Document restructured.

Changed Figure 1: Block diagram .

Updated

Table 5: General

:

– changed I short max value from 4000 mA to 400 mA

– changed I qn_150 typ. value from 1.45 mA to 1.25 mA

– changed I qn_50 typ. value from 538 µA to 470 µA

– changed I qn_1 typ. value from 120 µA to 100 µA.

Updated

Table 6: Reset

:

– corrected trd formula.

Updated

Table 7: Watchdog

:

– changed Vwlth values in V o_ref percentages

– changed Vwhth values in V o_ref percentages.

Added

Figure 24: L4993 application schematic

.

Added Section 2.4: Electrical characteristics curves .

Added

Section 2.5: Test circuit and waveforms plot

.

Updated

Table 3: Absolute maximum ratings .

Updated disclaimer.

Updated template.

Removed the tube version on the SO-8 package on the Table 1:

Device summary

.

Updated

Section 2.1: Absolute maximum ratings

.

Removed Figure “SO-8 tube shipment (no suffix)”.

Typo errors.

30/31

DS5285 Rev 10

L4993

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2018 STMicroelectronics – All rights reserved

DS5285 Rev 10

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