STMicroelectronics STM32F733ZE Datasheet

Table 69.

ADC static accuracy at f

Table 70.

ADC static accuracy at f

ADC dynamic accuracy at f

= 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

= 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

= 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 71.

ADC dynamic accuracy at f

Table 72.

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

= 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 157

= 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 157

Table 73.

Table 74.

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 75.

internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 76.

Table 77.

Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 78.

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 79.

Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 80.

I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 81.

SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 82.

2 S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 83.

SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 84.

USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 85.

USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 86.

USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 87.

USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 88.

USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 89.

Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 90.

USB OTG high speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 91.

USB OTG high speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 92.

USB FS PHY BCD electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 93.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 178

8/228 DS11854 Rev 5

STM32F732xx STM32F733xx List of tables

Table 94.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 178

Table 95.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 179

Table 96.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 180

Table 97.

Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 98.

Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 181

Table 99.

Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 100. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 183

Table 101. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 102. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 103. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 104. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 105. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 106. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 107. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 108. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 109. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 110. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 111. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 112. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 113. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 199

Table 114. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 200

Table 115. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 116. LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 117. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 118. LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 119. UFBGA144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 120. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 215

Table 121. UFBGA176+25 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Table 122. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 218

Table 123. WLCSP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Table 124. WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 222

Table 125. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 126. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 127. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 226

Table 128. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

DS11854 Rev 5 9/228

List of figures

List of figures

STM32F732xx STM32F733xx

Figure 1.

Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2.

Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 3.

Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 4.

Compatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5.

STM32F732xx and STM32F733xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6.

STM32F732xx and STM32F733xx AXI-AHB bus matrix architecture

(1)

. . . . . . . . . . . . . . 23

Figure 7.

VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 8.

VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 9.

Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 30

Figure 10.

PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 11.

Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 12.

Startup in regulator OFF: slow V

slope

- power-down reset risen after V

CAP_1

CAP_2

slope stabilization . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13.

Startup in regulator OFF mode: fast V

- power-down reset risen before V

CAP_1

CAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 34

Figure 14.

STM32F732xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 15.

STM32F732xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 16.

STM32F733xx WLCSP100 ballout (with OTG PHY HS) . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 17.

STM32F732xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 18.

STM32F733xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 19.

STM32F733xx UFBGA144 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 20.

STM32F732xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 21.

STM32F733xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 22.

STM32F733xx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 23.

STM32F733xx UFBGA176 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 24.

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 25.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 26.

STM32F732xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 27.

STM32F733xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 28.

Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

current consumption (RTC ON/BKP SRAM OFF and

LSE in low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 31.

current consumption (RTC ON/BKP SRAM OFF and

LSE in medium low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 32.

current consumption (RTC ON/BKP SRAM OFF and

LSE in medium high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 33.

current consumption (RTC ON/BKP SRAM OFF and

LSE in high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 34.

High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

current consumption (RTC ON/BKP SRAM OFF and

LSE in high medium drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 35.

Figure 36.

Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 37.

Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 38.

Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 39.

ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 40.

LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 41.

PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

10/228 DS11854 Rev 5

STM32F732xx STM32F733xx List of figures

Figure 42.

PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 43.

FT I/O input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 44.

I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 45.

Figure 46.

ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 47.

Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 48.

Power supply and reference decoupling (V

REF+

Figure 49.

Power supply and reference decoupling (V

REF+ not connected to V

DDA connected to V

DDA

). . . . . . . . . . . . . 159

). . . . . . . . . . . . . . . . 159

Figure 50.

12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 51.

SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 52.

SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 53.

SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 54.

2 S slave timing diagram (Philips protocol) (1)

Figure 55.

2 S master timing diagram (Philips protocol)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 56.

SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 57.

SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 58.

USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 173

Figure 59.

ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 60.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 177

Figure 61.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 179

Figure 62.

Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 63.

Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 64.

Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 65.

Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 66.

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 67.

Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 68.

NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 69.

NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 70.

NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 191

Figure 71.

NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 192

Figure 72.

SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 73.

SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 74.

Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 75.

Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 76.

SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 77.

SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 78.

LQFP64 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 79.

Figure 80.

LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 81.

LQFP100 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 82.

Figure 83.

LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 84.

LQFP144 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 85.

Figure 86.

LQFP144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 87.

LQFP176 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 88.

Figure 89.

LQFP176 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 90.

UFBGA144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 91.

Figure 92.

UFBGA144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Figure 93.

UFBGA176 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

DS11854 Rev 5 11/228

List of figures STM32F732xx STM32F733xx

Figure 94.

UFBGA176+25 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 95.

UFBGA176 top view example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Figure 96.

WLCSP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Figure 97.

Figure 98.

WLCSP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

12/228 DS11854 Rev 5

STM32F732xx STM32F733xx

1 Introduction

Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32F732xx and STM32F733xx microcontrollers.

This document should be ready in conjunction with the STM32F72xxx and STM32F73xxx advanced Arm ® -based 32-bit MCUs reference manual (RM0431). The reference manual is available from the STMicroelectronics website www.st.com.

For information on the Arm ®(a) Cortex ® -M7 core, refer to the Cortex reference manual available from the http://www.arm.com website.

® -M7 technical a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS11854 Rev 5 13/228

Description

2 Description

STM32F732xx STM32F733xx

The STM32F732xx and STM32F733xx devices are based on the high-performance Arm ®

Cortex ® -M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex ® -M7 core features a single floating point unit (SFPU) precision which supports Arm ® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security.

The STM32F732xx and STM32F733xx devices incorporate high-speed embedded memories with a Flash memory up to 512 Kbytes, 256 Kbytes of SRAM (including

64 Kbytes of data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM

(for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memories access.

All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, thirteen generalpurpose 16-bit timers including two PWM timers for motor control, two general-purpose 32bit timers, a true random number generator (RNG). They also feature standard and advanced communication interfaces.

• Up to three I

• Five SPIs, three I

Ss in half duplex mode. To achieve the audio class accuracy, the I

2 to allow synchronization.

S peripherals can be clocked via a dedicated internal audio PLL or via an external clock

• Four USARTs plus four UARTs

• An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the

ULPI or with the integrated HS PHY depending on the part number)

• One CAN

• Two SAI serial audio interfaces

• Two SDMMC host interfaces

Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC) interface, a Quad-SPI Flash memory interface.

The STM32F732xx and STM32F733xx devices operate in the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for the USB (OTG_FS and

OTG_HS) and the SDMMC2 (clock, command and 4-bit data) are available on all the packages except LQFP100 and LQFP64 for a greater power supply choice.

The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F732xx and STM32F733xx devices offer devices in 7 packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen.

14/228 DS11854 Rev 5

STM32F732xx STM32F733xx Description

These features make the STM32F732xx and STM32F733xx microcontrollers suitable for a wide range of applications:

• Motor drive and application control,

• Medical equipment,

• Industrial applications: PLC, inverters, circuit breakers,

• Printers, and scanners,

• Alarm systems, video intercom, and HVAC,

• Home audio appliances,

• Mobile applications, Internet of Things,

• Wearable devices: smartwatches.

The following table lists the peripherals available on each part number.

Table 2. STM32F732xx and STM32F733xx features and peripheral counts

Peripherals STM32F73xRx STM32F73xVx STM32F73xZx STM32F73xIx

Flash memory in Kbytes

SRAM in Kbytes

Communication interfaces

System

Instruction

Backup

FMC memory controller

Quad-SPI

Timers

General-purpose

Advanced-control

Basic

Low-power

Random number generator

SPI / I 2 S

USART/UART

USB OTG FS

USB OTG HS (4)

USB OTG PHY HS controller (USBPHYC)

CAN

SAI

SDMMC1

SDMMC2

AES

GPIOs

12-bit ADC

Number of channels

12-bit DAC

Number of channels

256

3/3 (simplex) (3)

4/2

512 256 512 256

256(176+16+64)

Yes

(1)

512

Yes

(2)

Yes

4/3 (simplex) (3)

256

5/3 (simplex) (3)

4/4

Yes

(10)

512

Yes

82 in STM32F732xx

79 in STM32F733xx

Yes

114 in STM32F732xx

112 in STM32F733xx

Yes

(5)(6)

140 in STM32F732xx

138 in STM32F733xx

Yes

DS11854 Rev 5 15/228

Description STM32F732xx STM32F733xx

Maximum CPU frequency

Operating voltage

Operating temperatures

Package

Table 2. STM32F732xx and STM32F733xx features and peripheral counts (continued)

Peripherals STM32F73xIx STM32F73xRx

LQFP64

(9)

STM32F73xVx STM32F73xZx

216 MHz

(7)

1.7 to 3.6 V (8)

Ambient temperatures: –40 to +85 °C /–40 to +105 °C

Junction temperature: –40 to + 125 °C

LQFP100

(9)

WLCSP100

(10)

LQFP144

UFBGA144

(10)

UFBGA176

LQFP176

1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.

2. On the STM32F733xx device packages, except the 176-pin ones, the TIM12 is not available, so there are 9 generalpurpose timers.

3. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.

4. USB OTG HS with the ULPI in the STM32F732xx devices and with integrated HS PHY in the STM32F733xx devices.

5. The SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144 pin package.

6. The SDMMC2 is not available on the STM32F733Vx devices.

7. 216 MHz maximum frequency for - 40°C to + 85°C ambient temperature range (200 MHz maximum frequency for - 40°C to

+ 105°C ambient temperature range).

8. V

DDA

minimum value of 1.7 V is obtained when the internal reset is OFF (refer to

Section 3.15.2: Internal reset OFF

9. Available only on the STM32F732xx devices.

10. Available only on the STM32F733xx devices.

16/228 DS11854 Rev 5

STM32F732xx STM32F733xx Description

The STM32F732xx devices are fully pin-to-pin, compatible with the STM32F7x5xx,

STM32F7x6xx, STM32F7x7xx devices.

The STM32F732xx devices are partially pin-to-pin, compatible with the STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher performances

(higher frequency) for a greater degree of freedom during the development cycle.

Figure 1

and Figure 2

give compatible board designs between the STM32F732xx, with

LQFP64 and LQFP100 packages, and STM32F4xx families.

Figure 1. Compatible board design for LQFP100 package

STM32F427xx / STM32F437xx

STM32F429xx / STM32F439xx

STM32F415xx / STM32F417xx

STM32F405xx / STM32F407xx

PC3

VDD

VSSA

VREF+

VDDA

PA0-WKUP

PA1

PA2

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

PC3

VSSA

VREF+

VDDA

PA0-WKUP

PA1

PA2

PA3

STM32F73xxx

Pins 19 to 49 are not compatible

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

MSv41002V2

DS11854 Rev 5 17/228

Description STM32F732xx STM32F733xx

Figure 2. Compatible board design for LQFP64 package

53 52 51 50 49

STM32F405/

STM32F415 line

28 29 30 31 32

39 PC8

PC7

PC6

PB15

PB14

PB13

PB12

VDD

VCAP_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

VSS

VDD

53 52 51 50 49

STM32F4x1

PB11 not available anymore

Replaced by VCAP_1

28 29 30 31 32

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

VSS

VDD

ESR 1 ohm or below 1 ohm

VSS VDD

57 56 55 54 53 52 51 50 49

STM32F732xx

PC5 not available anymore

Replaced by VCAP_1 35

17 18 19 20 21 22 23 24 25 26 27 28

29 30 31 32

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VDD

VSS

PA13

PA12

PA11

PA10

PA9

VSS

VDD

Not compatible STM32F732xx pins with either

STM32F4x1 or STM32F405/F415 or both

ESR between 0.1 ohm and 0.2 ohm

VSS VDD

MSv42019V1

The STM32F732xx LQFP144, UFBGA176 and LQFP176 packages are fully pin to pin compatible with the STM32F4xx devices.

18/228 DS11854 Rev 5

STM32F732xx STM32F733xx Description

LQFP176 packages

Figure 3. Compatible board design for LQFP144 package

STM32F732xx

PG8

PG7

90 PG5

89 PG4

PG6

PG3

PG2

PD15

PD14

VDD

VSS

PD13 82

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

STM32F733xx

PG8

PG5

PG4

PG3

89 PG2

88 PD15

PD14

VDD

VSS

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

VDD12OTGHS

OTG_HS_REXT

PB13

PB12

PG6, PG7 removed on the STM32F733xx

Not compatible pins

MSv42021V1

Figure 4. Compatible board design for LQFP176 package

STM32F732xx

112

111

110

109

PG8

PG7

PG6

PG5

108 PG4

107 PG3

106 PG2

105 PD15

104

103

PD14

VDD

102

101

100

VSS

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

VDD

VSS

PH12

STM32F733xx

112

111

110

109

108

107

106

105

104

103

102

101

100

PG8

PG5

PG4

PG3

PG2

PD15

PD14

VDD

VSS

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

VDD12OTGHS

OTG_HS_REXT

PB13

PB12

VDD

VSS

PH12

PG6, PG7 removed on the STM32F733xx

Not compatible pins

MSv42074V1

Figure 5 shows the general block diagram of the device family.

DS11854 Rev 5 19/228

Description STM32F732xx STM32F733xx

JTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

TRACECK

TRACED[3:0]

DP, DM

ULPI:CK, D[7:0], DIR, STP, NXT

SCL/SDA, INT, ID, VBUS

PA[15:0]

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

PH[15:0]

PI[11:0]

168 AF

D[7:0]

CMD, CK as AF

D[7:0]

CMD, CK as AF

4 compl. chan. (TIM1_CH1[1:4]N),

4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF

4 compl. chan.(TIM8_CH1[1:4]N),

4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF

2 channels as AF

1 channel as AF

RX, TX, SCK,

CTS, RTS as AF

RX, TX, SCK,

CTS, RTS as AF

MOSI, MISO,

SCK, NSS as AF

MOSI, MISO,

SCK, NSS as AF

MOSI, MISO,

SCK, NSS as AF

SD, SCK, FS, MCLK as AF

ULPI:CK, D[7:0], DIR, STP, NXT

SCL, SDA, INT, ID, VBUS

VDDREF_ADC

8 analog inputs common to the 3 ADCs

8 analog inputs common to the ADC1 & 2

8 analog inputs for ADC3

Figure 5. STM32F732xx and STM32F733xx block diagram

JTAG & SW

ETM

ARM CPU

Cortex-M7

216MHz

I-Cache

8KB

D-Cache

8KB

MPU FPU

NVIC

DTCM

ICTM

AXIM

AHBP

AHBS

DTCM RAM 64KB

ITCM RAM 16KB

ACCEL/

CACHE

FLASH 512KB

AES128

RNG

USB HS

(2)

PHY

LDO

BGR

USB OTG HS

PLL

GPIO PORT A

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

GPIO PORT F

GPIO PORT G

GPIO PORT H

GPIO PORT I

EXT IT. WKUP

SDMMC1

SDMMC2

SAI1

SAI2

LDO

GP-DMA2

GP-DMA1

TIM1 / PWM

16b

TIM8 / PWM 16b

16b TIM9

TIM10

TIM11

16b

16b smcard irDA smcard irDA

USART1

USART6

SPI1/I2S1

SPI4

SPI5

OTG HS PHY

(2)

CONTROLLER

@VDDA

U S AR T 2 M B p s

ADC1

ADC2

ADC3

PLL1

PLL2

DMA/

FIFO

8 Streams

FIFO

8 Streams

FIFO

GPDMA2

AHB/APB2

SYSCFG

SRAM1 176KB

SRAM2 16KB

AHB2 216 MHz

EXT MEM CTL (FMC)

SRAM, SDRAM, NOR-Flash,

NAND-Flash, SDRAM

Quad-SPI

AHB1 216 MHz

USB

OTG FS

@VDDA

RC HS

RC LS

PLL1+PLL2+PLL3

POR reset

Int

@VDDA

SUPPLY

SUPERVISION

POR/PDR

BOR

PVD

VDD12

@VDD33

BBgen + POWER MNGT

VOLT. REG

3.3V TO 1.2V

AHB/

APB1

WWDG

LPTIM1

TIM6

TIM7

RCC

CRC

GPDMA1

16b

@VDD33

XTAL OSC

4- 16MHz

WDG32K

Standby interface

@VSW

XTAL 32 kHz

RTC

AWU

Backup register

4 KB BKPRAM

TIM2

TIM3

TIM4

TIM5

32b

16b

TIM12

TIM13

32b

16b

TIM14

USART2

USART3

16b smcard irDA smcard irDA

UART4

UART5

UART7

UART8

SPI2/I2S2

SPI3/I2S3

I2C1/SMBUS

I2C2/SMBUS

I2C3/SMBUS

@VDDA

DAC1

DAC2

ITF bxCAN1

SCL, SDA, INT, ID, VBUS

CLK, NE [3:0], A[23:0],

D[31:0], NOEN, NWEN,

NBL[3:0], SDCLKE[1:0]

SDNE[1:0], SDNWE, NL

NRAS, NCAS, NADV

NWAIT, INTN

CLK, CS,D[7:0]

VDDA, VSSA

NRESET

WKUP[4:0]

VDDMMC33 = 3.0 to 3.6V

VDDUSB33 = 3.0 to 3.6 V

VDD = 1.8 to 3.6 V

VSS

VCAP1

OSC_IN

OSC_OUT

VBAT = 1.8 to 3.6 V

OSC32_IN

OSC32_OUT

RTC_TS

RTC_TAMPx

RTC_OUT

4 channels, ETR as AF

4 channels

2 channels as AF

1 channel as AF

RX, TX, SCK

CTS, RTS as AF

RX, TX, SCK

CTS, RTS as AF

RX, TX as AF

MOSI, MISO, SCK

NSS as AF

MOSI, MISO, SCK

NSS as AF

SCL, SDA, SMBAL as AF

TX, RX

DAC1 as AF

DAC2 as AF

MSv41003V3

1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.

20/228 DS11854 Rev 5

STM32F732xx STM32F733xx Functional overview

3.1 Arm

®

Cortex

®

-M7 with FPU

The Arm

Cortex

-M7 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and low interrupt latency.

The Cortex

-M7 processor is a highly efficient high-performance featuring:

– Six-stage dual-issue pipeline

– Dynamic branch prediction

– Harvard caches (8 Kbytes of I-cache and 8 Kbytes of D-cache)

– 64-bit AXI4 interface

– 64-bit ITCM interface

– 2x32-bit DTCM interfaces

Note:

The processor supports the following memory interfaces:

• Tightly Coupled Memory (TCM) interface.

• Harvard instruction and data caches and AXI master (AXIM) interface.

• Dedicated low-latency AHB-Lite peripheral (AHBP) interface.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

It supports single precision FPU (floating point unit), speeds up software development by using metalanguage development tools, while avoiding saturation.

Figure 5 shows the general block diagram of the STM32F732xx and STM32F733xx family.

Cortex ® -M7 with FPU core is binary compatible with the Cortex ® -M4 core.

3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

DS11854 Rev 5 21/228

Functional overview

3.3 Embedded Flash memory

STM32F732xx STM32F733xx

The STM32F732xx and STM32F733xx devices embed a Flash memory of up to 512 Kbytes available for storing programs and data.

The flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: No access (read, erase, program) to the Flash memory or backup SRAM can be performed while the debug feature is connected or while booting from RAM or system memory bootloader

– Level 2: debug/chip read protection disabled.

• Write protection (WRP): the protected area is protected against erasing and programming.

• Proprietary code readout protection (PCROP): Flash memory user sectors (0 to 7) can be protected against D-bus read accesses by using the proprietary readout protection

(PCROP). The protected area is execute-only.

3.4 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

22/228

All the devices feature:

• System SRAM up to 256 Kbytes:

– SRAM1 on AHB bus Matrix: 176 Kbytes

– SRAM2 on AHB bus Matrix: 16 Kbytes

– DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 64 Kbytes for critical real-time data.

• Instruction RAM (ITCM-RAM) 16 Kbytes:

– It is mapped on TCM interface and reserved only for CPU Execution/Instruction useful for critical real-time routines.

The Data TCM RAM is accessible by the GP-DMAs and peripheral DMAs through the specific AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is accessed at CPU clock speed with 0 wait states.

• 4 Kbytes of backup SRAM

This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or V BAT mode.

DS11854 Rev 5

STM32F732xx STM32F733xx

3.6 AXI-AHB bus matrix

Functional overview

The STM32F732xx and STM32F733xx system architecture is based on 2 sub-systems:

• An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:

– 3x AXI to 32-bit AHB bridges connected to AHB bus matrix

– 1x AXI to 64-bit AHB bridge connected to the embedded Flash memory

• A multi-AHB Bus-Matrix

– The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, USB

HS) and the slaves (Flash memory, RAM, FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

Figure 6. STM32F732xx and STM32F733xx AXI-AHB bus matrix architecture (1)

Arm Cortex-M7

8KB

I/D Cache

DMA1

DMA2

USB OTG

AXI to

multi-AHB

DTCM RAM

64KB

ITCM RAM

16KB

ITCM

64-bit AHB

64-bit BuS Matrix

FLASH

512KB

SRAM1

176KB

SRAM2

16KB

AHB

Periph1

AHB periph2

FMC external

MemCtl

Quad-SPI

APB1

APB2

32-bit Bus Matrix - S

1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus.

MSv41005V1

DS11854 Rev 5 23/228

Functional overview STM32F732xx STM32F733xx

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth

(AHB/APB).

The two DMA controllers support a circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. The configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals:

• SPI and I 2 S

• I

• USART

• General-purpose, basic and advanced-control timers TIMx

• DAC

• SDMMC

• ADC

• SAI

• Quad-SPI

24/228 DS11854 Rev 5

STM32F732xx STM32F733xx

3.8 Flexible memory controller (FMC)

Functional overview

The Flexible memory controller (FMC) includes three memory controllers:

• The NOR/PSRAM memory controller

• The NAND/memory controller

• The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller

The main features of the FMC controller are the following:

• Interface with static-memory mapped devices including:

– Static random access memory (SRAM)

– NOR Flash memory/OneNAND Flash memory

– PSRAM (4 memory banks)

– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories

• 8-, 16-, 32-bit data bus width

• Independent Chip Select control for each memory bank

• Independent configuration for each memory bank

• Write FIFO

• Read FIFO for SDRAM controller

• The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is

HCLK/2

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.

All the devices embed a Quad-SPI memory interface, which is a specialized communication interface targetting Single, Dual or Quad-SPI Flash memories. It can work in:

• Direct mode through registers

• External Flash status register polling mode

• Memory mapped mode.

Up to 256 Mbytes of external Flash are memory mapped, supporting 8, 16 and 32-bit access. The code execution is supported.

The opcode and the frame format are fully programmable. The communication can be either in Single Data Rate or Dual Data Rate.

DS11854 Rev 5 25/228

Functional overview STM32F732xx STM32F733xx

3.10 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex

M7 with FPU core.

• Closely coupled NVIC gives low-latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving, higher-priority interrupts

• Support tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with a minimum interrupt latency.

The external interrupt/event controller consists of 24 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs in the

STM32F732xx devices (138 GPIOs in the STM32F733xx devices) can be connected to the

16 external interrupt lines.

3.12 Clocks and startup

On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source.

This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled).

This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz.

Similarly, a full interrupt management of the PLL clock entry is available when necessary

(for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 216 MHz while the maximum frequency of the high-speed APB domains is

108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz.

The devices embed two dedicated PLLs (PLLI2S and PLLSAI) which allow to achieve audio class performance. In this case, the I 2 S and SAI master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.

The STM32F733xx devices embed two PLLs inside the PHY HS controller: PLL1 and PLL2.

The PLL1 allows to output 60 MHz used as an input for PLL2 which itself allows to generate the 480 Mbps in the USB OTG High Speed mode.

The PLL1 has as input HSE clock.

26/228 DS11854 Rev 5

STM32F732xx STM32F733xx Functional overview

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes:

• All Flash address space mapped on ITCM or AXIM interface

• All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface

• The System memory bootloader

The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface.

Note:

• V

= 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through V

pins.

• V

SSA

, V

DDA

= 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. V

DDA

and V

SSA

must be connected to V

and V

, respectively.

• V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

is not present.

The V

DDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to

Section 3.15.2: Internal reset OFF ). Refer to

Table 3: Voltage regulator configuration mode versus device operating mode to identify the packages supporting this option.

• The V

DDSDMMC

can be connected either to V

or an external independent power supply (1.8 to 3.6V) for the SDMMC2 pins (clock, command, and 4-bit data). For example, when the device is powered at 1.8V, an independent power supply 2.7V can be connected to V

DDSDMMC

.When the V supply, it is independent from V

DDSDMMC

is connected to a separated power

or V

DDA

but it must be the last supply to be provided and the first to disappear. The following conditions V

DDSDMMC must be respected:

– During the power-on phase (V

< V

DD_MIN

), V than V

DDSDMMC

should be always lower

– During the power-down phase (V

< V

DD_MIN

), V lower than V

DDSDMMC

should be always

– The V

DDSDMMC

rising and falling time rate specifications must be respected

– In the operating mode phase, V

DDSDMMC

could be lower or higher than V

DD:

All associated GPIOs powered by V

DDSDMMC

DDSDMMC_MIN

and V

DDSDMMC_MAX.

are operating between

• The V

DDUSB

can be connected either to V

or an external independent power supply

(3.0 to 3.6V) for USB transceivers (refer to

Figure 7 and Figure 8

). For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to the V

DDUSB

. When the V

DDUSB independent from V

or V

DDA

is connected to a separated power supply, it is

but it must be the last supply to be provided and the first to disappear. The following conditions V

DDUSB must be respected:

– During the power-on phase (V

< V

DD_MIN

), V than V

DDUSB

should be always lower

– During the power-down phase (V

< V

DD_MIN

), V than V

DDUSB

should be always lower

DS11854 Rev 5 27/228

Functional overview STM32F732xx STM32F733xx

– The V

DDUSB

rising and falling time rate specifications must be respected

– In the operating mode phase, V

DDUSB

could be lower or higher than V

DD:

- If the USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by

DDUSB are operating between V

DDUSB_MIN

and V

DDUSB_MAX

- The V

DDUSB

supplies both USB transceiver (USB OTG_HS and USB OTG_FS).

If only one USB transceiver is used in the application, the GPIOs associated to the other USB transceiver are still supplied by V

DDUSB

- If the USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by V

DDUSB are operating between V

DD_MIN

and V

DD_MAX

Figure 7. V

DDUSB

connected to V

power supply

VDD

DD_MAX

= V

DDA

= V

DDUSB

DD_MIN

DDUSB_MAX

Power-on Operating mode Power-down time

MS37591V1

Figure 8. V

DDUSB

connected to external power supply

USB functional area

DDUSB

DDUSB_MIN

USB non functional area

DD_MIN

= V

DDA

USB non functional area

Power-on Operating mode Power-down time

MS37590V1

28/228 DS11854 Rev 5

STM32F732xx STM32F733xx Functional overview

On the STM32F7x3xx devices, the USB OTG HS sub-system uses one or two additional power supply pins depending on the package:

• The VDD12OTGHS pin is the output of PHY HS regulator (1.2V). An external capacitor of 2.2 µF must be connected on the VDD12OTGHS pin.

• On the LQFP100 only, a second power pin VDDPHYHS is used to supply the USB

OTG PHY HS and associated GPIOs.The VDDPHYHS follows the same rules provided for the VDDUSB power pin.

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled.

The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when V

POR/PDR

or V

BOR

is below a specified threshold,

, without the need for an external reset circuit.

The device also features an embedded programmable voltage detector (PVD) that monitors the V

DDA

power supply and compares it to the V

PVD generated when V

DDA higher than the V

PVD

drops below the V

PVD

threshold. An interrupt can be

threshold and/or when V

DDA message and/or put the MCU into a safe state. The PVD is enabled by software.

threshold. The interrupt service routine can then generate a warning

This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.

An external power supply supervisor should monitor V

DD the device in reset mode as long as V

DD connected to V

reset OFF

and NRST and should maintain

is below a specified threshold. PDR_ON should be

. Refer to

Figure 9: Power supply supervisor interconnection with internal

DS11854 Rev 5 29/228

Functional overview STM32F732xx STM32F733xx

Figure 9. Power supply supervisor interconnection with internal reset OFF

External V

power supply supervisor

Ext. reset controller active when

< 1.7 V

NRST

Application reset signal

PDR_ON

MS31383V4

The V

specified threshold, below which the device must be maintained under reset, is

1.7 V (see Figure 10 ).

A comprehensive set of power-saving mode allows to design low-power applications.

When the internal reset is OFF, the following integrated features are no more supported:

• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled

• The brownout reset (BOR) circuitry must be disabled

• The embedded programmable voltage detector (PVD) is disabled

• V

BAT

functionality is no more available and V

BAT

pin should be connected to V

All packages, except for the LQFP100, allow to disable the internal reset through the

PDR_ON signal when connected to V

Figure 10. PDR_ON control with internal reset OFF

V DD

PDR = 1.7 V time

Reset by other source than power supply supervisor

NRST

30/228

PDR_ON

DS11854 Rev 5

PDR_ON time

MS19009V7

STM32F732xx STM32F733xx Functional overview

The regulator has four operating modes:

• Regulator ON

– Main regulator mode (MR)

– Low power regulator (LPR)

– Power-down

• Regulator OFF

On packages embedding the BYPASS_REG pin, the regulator is enabled by holding

BYPASS_REG low. On all other packages, the regulator is always enabled.

There are three power modes configured by software when the regulator is ON:

• MR mode used in Run/sleep modes or in Stop modes

– In Run/Sleep modes

The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). A different voltage scaling is provided to reach the best compromise between maximum frequency and dynamic power consumption.

The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling.

– In Stop modes

The MR can be configured in two ways during stop mode:

MR operates in normal mode (default mode of MR in stop mode)

MR operates in under-drive mode (reduced leakage mode).

• LPR is used in the Stop modes:

The LP regulator mode is configured by software when entering Stop mode.

Like the MR mode, the LPR can be configured in two ways during stop mode:

– LPR operates in normal mode (default mode when LPR is ON)

– LPR operates in under-drive mode (reduced leakage mode).

• Power-down is used in Standby mode.

The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost.

Refer to Table 3

for a summary of voltage regulator modes versus device operating modes.

The V

CAP_1

and V

CAP_2

pins must be connected to 2*2.2 µF, ESR < 2 Ω (or 1*4.7 µF, ESR between 0.1

Ω and 0.2

Ω if only the V

CAP_1

pin is provided (on LQFP64 package)).

All the packages have the regulator ON feature.

DS11854 Rev 5 31/228

Functional overview STM32F732xx STM32F733xx

Table 3. Voltage regulator configuration mode versus device operating mode (1)

Voltage regulator configuration

Run mode Sleep mode Stop mode Standby mode

MR or LPR Normal mode

Over-drive mode (2)

Under-drive mode

Power-down mode

1. ‘-’ means that the corresponding configuration is not available.

2. The over-drive mode is not available when V

= 1.7 to 2.1 V.

MR or LPR

Yes

This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V

voltage source through V

CAP_1

and V

CAP_2

pins.

Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency.The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors.

When the regulator is OFF, there is no more internal monitoring on V

12 supply supervisor should be used to monitor the V

. An external power

of the logic power domain. The PA0 pin should be used for this purpose, and act as power-on reset on V

power domain.

In regulator OFF mode, the following features are no more supported:

• PA0 cannot be used as a GPIO pin since it allows to reset a part of the V

12 domain which is not reset by the NRST pin.

logic power

• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required.

• The over-drive and under-drive modes are not available.

• The Standby mode is not available.

32/228 DS11854 Rev 5

STM32F732xx STM32F733xx

V12

Figure 11. Regulator OFF

External V

CAP_1/2

power supply supervisor

Ext. reset controller active when V

CAP_1/2

< Min V

Application reset signal (optional)

Functional overview

Note:

PA0

NRST

BYPASS_REG

V12

CAP_1

CAP_2 ai18498V3

The following conditions must be respected:

• V

should always be higher than V between power domains.

CAP_1

and V

CAP_2 to avoid current injection

• If the time for V

CAP_1

and V and V

CAP_2 reach V

CAP_2 to reach V

12 minimum value is faster than the time for

to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V

CAP_1 minimum value and until V

reaches 1.7 V (see Figure 12

• Otherwise, if the time for V

CAP_1 than the time for V

Figure 13

and V

CAP_2 to reach V

12 minimum value is slower

to reach 1.7 V, then PA0 could be asserted low externally (see

• If V

CAP_1

and V

CAP_2

go below V

12 minimum value and V reset must be asserted on PA0 pin.

is higher than 1.7 V, then a

The minimum value of V

12 depends on the maximum frequency targeted in the application.

On the LQFP64 pin package, the V

CAP_2 is not available.

DS11854 Rev 5 33/228

Functional overview STM32F732xx STM32F733xx

Figure 12. Startup in regulator OFF: slow V

- power-down reset risen after V

CAP_1

CAP_2

slope stabilization

PDR = 1.7 V or 1.8 V

Min V

CAP_1

/ V

CAP_2 time

NRST

1. This figure is valid whatever the internal reset mode (ON or OFF).

Figure 13. Startup in regulator OFF mode: fast V

- power-down reset risen before V

CAP_1

CAP_2

slope stabilization

DD time ai18491f

PDR = 1.7 V or 1.8 V

Min V

CAP_1

/ V

CAP_2 time

NRST

PA0 asserted externally time ai18492e

1. This figure is valid whatever the internal reset mode (ON or OFF).

34/228 DS11854 Rev 5

STM32F732xx STM32F733xx Functional overview

3.16.3 Regulator ON/OFF and internal reset ON/OFF availability

Table 4. Regulator ON/OFF and internal reset ON/OFF availability

Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF

LQFP64,

LQFP100

Yes No

LQFP144

LQFP176,

UFBGA144,

UFBGA176

Yes

BYPASS_REG set to V

Yes

BYPASS_REG set to V

Yes

PDR_ON set to V

Yes

PDR_ON set to V

3.17 Real-time clock (RTC), backup SRAM and backup registers

The RTC is an independent BCD timer/counter. It supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

• Two programmable alarms.

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.

• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy.

• Three anti-tamper detection pins with programmable filter.

• Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to

BAT

mode.

• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period.

The RTC and the 32 backup registers are supplied through a switch that takes power either from the V

DD supply when present or from the V

BAT pin.

The backup registers are 32-bit registers used to store 128 bytes of user application data when V DD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode.

The RTC clock sources can be:

• A 32.768 kHz external crystal (LSE)

• An external resonator or oscillator(LSE)

• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)

• The high-speed external clock (HSE) divided by 32

The RTC is functional in V

BAT

mode and in all low-power modes when it is clocked by the

LSE. When clocked by the LSI, the RTC is not functional in V

BAT all low-power modes.

mode, but is functional in

DS11854 Rev 5 35/228

Functional overview STM32F732xx STM32F733xx

All the RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes.

The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

The Stop mode achieves the lowest power consumption while retaining the contents of

SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled.

The voltage regulator can be put either in main regulator mode (MR) or in low-power

mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator modes in stop mode ):

– Normal mode (default mode when MR or LPR is enabled)

– Under-drive mode.

The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup and the LPTIM1 asynchronous interrupt).

Table 5. Voltage regulator modes in stop mode

Voltage regulator configuration

Main regulator (MR) Low-power regulator (LPR)

Normal mode

Under-drive mode

MR ON

MR in under-drive mode

LPR ON

LPR in under-drive mode

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected.

The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11), or an RTC alarm / wakeup / tamper /time stamp event occurs.

The Standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power.

36/228 DS11854 Rev 5

STM32F732xx STM32F733xx Functional overview

3.19 V

BAT

operation

The V

BAT

pin allows to power the device V supercapacitor, or from V present.

BAT

domain from an external battery, an external when no external battery and an external supercapacitor are

Note:

The V

BAT

operation is activated when V

is not present.

The V

BAT

pin supplies the RTC, the backup registers and the backup SRAM.

When the microcontroller is supplied from V

BAT do not exit it from V

BAT operation.

, external interrupts and RTC alarm/events

When the PDR_ON pin is connected to V

SS no more available and the V

BAT

(Internal Reset OFF), the V pin should be connected to V DD .

BAT functionality is

3.20 Timers and watchdogs

The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers.

All timer counters can be frozen in debug mode.

Table 6 compares the features of the advanced-control, general-purpose and basic timers.

DS11854 Rev 5 37/228

Functional overview STM32F732xx STM32F733xx

Timer type

Timer

Table 6. Timer feature comparison

Counter resolution

Counter type

Prescaler factor

DMA request generation

Capture/ compare channels

Complem entary output

Max interface clock

(MHz)

Max timer clock

(MHz)

(1)

Advanced

-control

General purpose

Basic

TIM1,

TIM8

TIM2,

TIM5

TIM3,

TIM4

TIM9

TIM10,

TIM11

TIM12

TIM13,

TIM14

TIM6,

TIM7

16-bit

32-bit

16-bit

Up,

Down,

Up/down

Any integer between 1 and 65536

Up,

Down,

Up/down

Any integer between 1 and 65536

Up,

Down,

Up/down

Any integer between 1 and 65536

Yes

108

1. The maximum timer clock is either 108 or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.

216

108/216

216

108/216

38/228 DS11854 Rev 5

STM32F732xx STM32F733xx Functional overview

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.

Their 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge- or center-aligned modes)

• One-pulse mode output

If configured as standard 16-bit timers, they have the same features as the general-purpose

TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-

100%).

The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

The TIM1 and TIM8 support independent DMA request generation.

There are ten synchronizable general-purpose timers embedded in the STM32F732xx and

STM32F733xx devices (see

Table 6 for differences).

• TIM2, TIM3, TIM4, TIM5

The STM32F732xx and STM32F733xx include 4 full-featured general-purpose timers:

TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit autoreload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages.

The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the

Timer Link feature for synchronization or event chaining.

Any of these general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.

• TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

These timers are mainly used for the DAC trigger and waveform generation. They can also be used as a generic 16-bit time base.

The TIM6 and TIM7 support independent DMA request generation.

DS11854 Rev 5 39/228

Functional overview STM32F732xx STM32F733xx

The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.

This low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output: pulse, PWM

• Continuous / one-shot mode

• Selectable software / hardware input trigger

• Selectable clock source:

• Internal clock source: LSE, LSI, HSI or APB clock

• External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application)

• Programmable digital glitch filter

• Encoder mode

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features:

• A 24-bit downcounter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0

• Programmable clock source

40/228 DS11854 Rev 5

STM32F732xx STM32F733xx Functional overview

circuit interface (I

2

C)

The devices embed 3 I

Cs. Refer to Table 7: I2C implementation for the features

implementation.

The I

C bus interface handles communications between the microcontroller and the serial

C bus. It controls all I

C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

• I 2 C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Optional clock stretching

• System Management Bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (Packet Error Checking) generation and verification with ACK control

– Address resolution protocol (ARP) support

– SMBus alert

• Power System Management Protocol (PMBus TM ) specification rev 1.1 compatibility

• Independent clock: a choice of independent clock sources allowing the I

2 communication speed to be independent from the PCLK reprogramming.

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

Table 7. I

C implementation

C features

(1)

Standard-mode (up to 100 kbit/s)

Fast-mode (up to 400 kbit/s)

Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)

Programmable analog and digital noise filters

SMBus/PMBus hardware support

Independent clock

1. X: supported.

I2C1

I2C2

I2C3

DS11854 Rev 5 41/228

Functional overview STM32F732xx STM32F733xx

(USART)

The devices embed USARTs. Refer to Table 8: USART implementation

for the features implementation.

The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard

NRZ asynchronous serial data format.

The USART peripheral supports:

• Full-duplex asynchronous communications

• Configurable oversampling method by 16 or 8 to give flexibility between speed and clock tolerance

• Dual clock domain allowing convenient baud rate programming independent from the

PCLK reprogramming

• A common programmable transmit and receive baud rate of up to 27 Mbit/s when

USART clock source is system clock frequency (max is 216 MHz) and oversampling by

8 is used.

• Auto baud rate detection

• Programmable data word length (7 or 8 or 9 bits) word length

• Programmable data order with MSB-first or LSB-first shifting

• Progarmmable parity (odd, even, no parity)

• Configurable stop bits (1 or 1.5 or 2 stop bits)

• Synchronous mode and clock output for synchronous communications

• Single-wire half-duplex communications

• Separate signal polarity control for transmission and reception

• Swappable Tx/Rx pin configuration

• Hardware flow control for modem and RS-485 transceiver

• Multiprocessor communications

• LIN master synchronous break send capability and LIN slave break detection capability

• IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode

• Smartcard mode ( T=0 and T=1 asynchronous protocols for Smartcards as defined in the ISO/IEC 7816-3 standard)

• Support for Modbus communication

Table 8 summarizes the implementation of all U(S)ARTs instances

Table 8. USART implementation features (1) USART1/2/3/6 UART4/5/7/8

7, 8 and 9 bits Data Length

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

42/228 DS11854 Rev 5

STM32F732xx STM32F733xx Functional overview

Table 8. USART implementation (continued) features (1) USART1/2/3/6

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

1. X: supported.

UART4/5/7/8

3.23 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I

2

S)

The devices feature up to five SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4, and SPI5 can communicate at up to 50 Mbit/s, SPI2 and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces support the

NSS pulse mode, TI mode and Hardware CRC calculation. All the SPIs can be served by the DMA controller.

Three standard I

S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio

I sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the

S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

All I

Sx can be served by the DMA controller.

3.24 Serial audio interface (SAI)

The devices embed two serial audio interfaces.

The serial audio interface is based on two independent audio subblocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I 2 S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be configured in master or in slave mode.

In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency.

The two sub-blocks can be configured in synchronous mode when full-duplex mode is required.

DS11854 Rev 5 43/228

Functional overview

SAI1 and SAI2 can be served by the DMA controller

STM32F732xx STM32F733xx

The devices feature an additional dedicated PLL for audio I

S and SAI applications. It allows to achieve an error-free I

S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals.

The PLLI2S configuration can be modified to manage an I

S/SAI sample rate change without disabling the main PLL (PLL) used for CPU and USB interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz.

In addition to the audio PLL, a master clock input pin can be used to synchronize the

S/SAI flow with an external PLL (or Codec output).

An additional PLL dedicated to audio is used for the SAI1 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.

3.27 SD/SDIO/MMC card host interface (SDMMC)

SDMMC host interfaces are available, that support MultiMediaCard System Specification

Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory

Card Specification Version 2.0.

The SDMMC Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a stack of MMC4.1 or previous.

The SDMMC can be served by the DMA controller

3.28 Controller area network (bxCAN)

The CAN is compliant with the 2.0A and B (active) specifications with a bit rate up to 1

Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive

FIFOs with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

CAN is used). 256 bytes of SRAM are allocated to the CAN.

44/228 DS11854 Rev 5

STM32F732xx STM32F733xx Functional overview

3.29 Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.

The major features are:

• Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing

• Supports the session request protocol (SRP) and host negotiation protocol (HNP)

• 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints

• 12 host channels with periodic OUT support

• Software configurable to OTG1.3 and OTG2.0 modes of operation

• USB 2.0 LPM (Link Power Management) support

• Internal FS OTG PHY support

• HNP/SNP/IP inside (no need for any external resistor)

• BCD support

For the OTG/Host modes, a power switch is needed in case bus-powered devices are connected

3.30 Universal serial bus on-the-go high-speed (OTG_HS)

The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s).

The STM32F732xx devices feature a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required.

The STM32F733xx devices feature an integrated PHY HS.

The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG

2.0 specification. It has a software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.

The major features are:

• Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing

• Supports the session request protocol (SRP) and host negotiation protocol (HNP)

• 8 bidirectional endpoints

• 16 host channels with periodic OUT support

• Software configurable to OTG1.3 and OTG2.0 modes of operation

• USB 2.0 LPM (Link Power Management) support

DS11854 Rev 5 45/228

Functional overview STM32F732xx STM32F733xx

• Internal FS OTG PHY support

• For the STM32F732xx devices: External HS or HS OTG operation supporting ULPI in

SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output.

• For the STM32F733xx devices: Internal HS OTG PHY support.

• Internal USB DMA

• HNP/SNP/IP inside (no need for any external resistor)

• For OTG/Host modes, a power switch is needed in case bus-powered devices are connected

Universal Serial Bus controller on-the-go High-Speed PHY controller

(USBPHYC) only on STM32F733xx devices.

The USB HS PHY controller:

– Sets the PHYPLL1/2 values for the PHY HS

– Sets the other controls on the PHY HS

– Controls and monitors the USB PHY’s LDO

3.31 Random number generator (RNG)

All the devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.

3.32 Advanced encryption standard hardware accelerator (AES)

The devices embed an AES hardware accelerator which can be used to both encipher and decipher data using AES algorithm.

46/228 DS11854 Rev 5

STM32F732xx STM32F733xx Functional overview

The AES peripheral supports:

• Encryption/Decryption using AES Rijndael Block Cipher algorithm

• NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm

• 128-bit and 256-bit register for storing the encryption, decryption or derivation key

(4x 32-bit registers)

• Electronic codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois

Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher

Message Authentication Code mode (CMAC) supported.

• Key scheduler

• Key derivation for decryption

• 128-bit data block processing

• 128-bit, 256-bit key length

• 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer.

• Register access supporting 32-bit data width only.

• One 128-bit Register for the initialization vector when AES is configured in CBC mode or for the 32-bit counter initialization when CTR mode is selected, GCM mode or

CMAC mode.

• Automatic data flow control with support of direct memory access (DMA) using 2 channels, one for incoming data, and one for outcoming data.

• Suspend a message if another message with a higher priority needs to be processed

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission.

The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers.

A Fast I/O handling allows a maximum I/O toggling up to 108 MHz.

3.34 Analog-to-digital converters (ADCs)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In the scan mode, an automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

• Simultaneous sample and hold

• Interleaved sample and hold

The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

DS11854 Rev 5 47/228

Functional overview STM32F732xx STM32F733xx

To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,

TIM2, TIM3, TIM4, TIM5, or TIM8 timer.

The temperature sensor has to generate a voltage that varies linearly with the temperature.

The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as V

BAT

, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and V

BAT conversion are enabled at the same time, only V

BAT

conversion is performed.

As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used.

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs.

This dual digital Interface supports the following features:

• Two DAC converters: one for each output channel

• 8-bit or 12-bit monotonic output

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• External triggers for conversion

• Input voltage reference V

REF+

Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams.

3.37 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

48/228 DS11854 Rev 5

STM32F732xx STM32F733xx Functional overview

3.38 Embedded Trace Macrocell™

The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32F732xx and STM32F733xx device through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using the USB or any other high-speed channel. The real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. The TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell operates with third party debugger software tools.

DS11854 Rev 5 49/228

Pinouts and pin description

4 Pinouts and pin description

STM32F732xx STM32F733xx

Figure 14. STM32F732xx LQFP64 pinout

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VDDA

PA0-WKUP

PA1

PA2

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

2 47

3 46

4 45

5 44

6 43

7 42

8 41

LQFP64

10 39

11 38

12 37

13 36

14 35

15 34

17 18 19 20 21 22 23 24 25 26 27 28

29 30 31 32

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VDD

VSS

PA13

PA12

PA11

PA10

PA9

MS40455V3

1. The above figure shows the package top view.

50/228 DS11854 Rev 5

STM32F732xx STM32F733xx Pinouts and pin description

Figure 15. STM32F732xx LQFP100 pinout

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VSS

VDD

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

V SSA

VREF+

VDDA

PA0-WKUP

PA1

PA2

PA3

LQFP100

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

VDD

VSS

VCAP_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PD15

MSv40457V1

1. The above figure shows the package top view.

DS11854 Rev 5 51/228

Pinouts and pin description STM32F732xx STM32F733xx

Figure 16. STM32F733xx WLCSP100 ballout (with OTG PHY HS)

VDD

VSS

PC10

PD1

PA13

PA11

PA12 VCAP_2 PA15

PA10 PA9 PA14

PC9

PC6

PC8 PA8 PC7

PE10 PD15 PD13

PD14 PD12 PD11

VDD12

OTGHS

OTG_HS

_REXT

PB10

PB15 PB13 PB11

PB14

VDD

USB

PB12

VDD

VCAP_1

VSS

PE15

PE11

PE12

PE13

PE14

PD5

PB3

PD0 PD4

PC11 PD3

PC12 PD6

PD2 PD7

PB0 PA5

PB1 PA6

PE8

PC4

PE7

PE9

PC5

PB2

PB6

PE0

PC3

PA4

7 8

BOOT0 VSS

PB4

PB5

VDD

PE3

PB7

PB8

PB9

PE5

PC0

PA0

PE1

PE2 VBAT

PC13

PE4

PC14

PC15

VSS VDD

NRST

PE6

PH0

PA3

VDD

PA7

PA2

PA1

PC1

VREF+

VSS VDDA

PH1

PC2

VSSA

MSv42002V2

1. The above figure shows the package top view.

52/228 DS11854 Rev 5

STM32F732xx STM32F733xx Pinouts and pin description

Figure 17. STM32F732xx LQFP144 pinout

PF7

PF8

PF9

PF10

PH0

PH1

NRST

PC0

PC1

PC2

PC3

SSA

REF+

DDA

PA0

PA1

PA2

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14

PC15

PF0

PF1

PF2

PF3

PF4

PF5

PF6

1. The above figure shows the package top view.

LQFP144

108

107

106

105

104

103

102

101

100

PG6

PG5

PG4

PG3

PG2

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

CAP_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

DDUSB

PG8

PG7

MS39132V1

DS11854 Rev 5 53/228

Pinouts and pin description STM32F732xx STM32F733xx

Figure 18. STM32F733xx LQFP144 pinout

PF6

PF7

PF8

PF9

PF10

PF0

PF1

PF2

PF3

PF4

PF5

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14

PC15

PH0

PH1

NRST

PC0

PC1

PC2

PC3

SSA

REF+

DDA

PA0

PA1

PA2

1. The above figure shows the package top view.

LQFP144 with HS PHY

108

107

106

105

104

103

102

101

100

CAP_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

DDUSB

PG8

PG5

PG4

PG3

PG2

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

VDD12OTGHS

OTG_HS_REXT

PB13

PB12

MS41014V1

54/228 DS11854 Rev 5

STM32F732xx STM32F733xx Pinouts and pin description

Figure 19. STM32F733xx UFBGA144 ballout (with OTG PHY HS)

PF10

PC0

VSSA

VREF-

VREF+

VDDA

1 2

PC13

PC14-

OSC32_IN

PC15-

OSC32_OUT

PH0 -

OSC_IN

PH1 -

OSC_OUT

PE3

PE4

VBAT

VSS

PF3

NRST PF7

PF9

PC1

PA0

PA1

PA2

PA3

PE2

PE5

PF0

VDD

PF4

PF6

PF8

PC2

PA4

PA5

PA6

PA7

PE0

PB9

PB8

BOOT0

PDR_ON

VDD

BYPASS_

REG

PB2

PF13

PF12

PF11

PE1

VDD

VSS

PC3

PC4

PC5

PB0

PB1

PE6

PF1

PF2

PF5

PB4

VDD

VSS

PG1

PG0

PF15

PF14

PB5

PB6

PB7

VSS

VDD

PB3

VDD

VCAP_1

PE10

PE9

PE8

PE7

PG15

PG14

PG13

VSS

VDD

PD6

VDD

VSS

PE11

PE12

PE13

PE14

PE15

PG12

PG11

PG10

PG9

PD7

PA15

PA14

PD5

PD4

PD3

PD2

PC11

PC12

PD1

PD0

PC10

VDDUSB

PA10

PC9

VDD VDD PC8

VCAP_2

PD11

VSS PG8

VDD12OTG

OTG_HS

_REXT

PD10 PG4 PG3

PD9 PD13 PD14

PD8

PB10

PD12

PB11

PB14

PB12

PA13

PC7

PC6

PG5

PG2

PD15

PB15

PB13

PA12

PA11

PA9

PA8

MSv42000V1

1. The above figure shows the package top view.

DS11854 Rev 5 55/228

VSSA

VREF+

VDDA

PA0

PA1

PA2

PH2

PH3

PF6

PF7

PF8

PF9

PF10

PH0

PH1

NRST

PC0

PC1

PC2

PC3

VDD

PF0

PF1

PF2

PF3

PF4

PF5

VSS

VDD

PE2

PE3

PE4

PE5

PE6

VBAT

PI8

PC13

PC14

PC15

PI9

PI10

PI11

VSS

VDD

Pinouts and pin description

Figure 20. STM32F732xx LQFP176 pinout

STM32F732xx STM32F733xx

LQFP176

140 139

107

106

105

104

103

102

101

100

126

125

124

123

122

121

120

119

118

117

132

131

130

129

128

127

116

115

114

113

112

111

110

109

108

PG7

PG6

PG5

PG4

PG3

PG2

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

PH12

PI1

PI0

PH15

PH14

PH13

CAP_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

DDUSB

PG8

MS41015V1

1. The above figure shows the package top view.

56/228 DS11854 Rev 5

VSSA

VREF+

VDDA

PA0

PA1

PA2

PH2

PH3

PF6

PF7

PF8

PF9

PF10

PH0

PH1

NRST

PC0

PC1

PC2

PC3

VDD

PF0

PF1

PF2

PF3

PF4

PF5

VSS

VDD

PE2

PE3

PE4

PE5

PE6

VBAT

PI8

PC13

PC14

PC15

PI9

PI10

PI11

VSS

VDD

STM32F732xx STM32F733xx

Figure 21. STM32F733xx LQFP176 pinout

Pinouts and pin description

LQFP176 with HS PHY

140 139

107

106

105

104

103

102

101

100

126

125

124

123

122

121

120

119

118

117

132

131

130

129

128

127

116

115

114

113

112

111

110

109

108

PG5

PG4

PG3

PG2

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

VDD12OTGHS

OTG_HS_REXT

PB13

PB12

PH12

PI1

PI0

PH15

PH14

PH13

CAP_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

DDUSB

PG8

MS41082V1

1. The above figure shows the package top view.

DS11854 Rev 5 57/228

Pinouts and pin description STM32F732xx STM32F733xx

Figure 22. STM32F733xx UFBGA176 ballout

PE3

PE2

PE4 PE5

3 4 5 6 7 8 9 10 11 12 13 14 15

PE1 PE0 PB8 PB5

PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13

PE6

PB9 PB7

PB6

PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12

VBAT

PC13

PI7

PI8

E PC14

PF0

PI6

PI9

PI5

PI4

VDD PDR_ON

VDD

SDMMC

VDD

VSS BOOT0

VSS VSS VSS

PG9 PD5 PD1

PD4 PD3 PD2

PI3

PH15

PI2

PI1

PA11

PA10

PI10 PI11

PC15

VSS VDD PH2

VSS

VSS VSS VSS VSS

PH13

VSS

PH14

VCAP2

PI0

PC9

PA9

PA8

PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7

PH1

PF2 PF1 PH4

NRST PF3 PH5

VSS VSS VSS VSS VSS VSS VDDUSB PG8 PC6

VSS

VSS VSS VSS VSS VDD VDD PG7 PG6

PF7

PF6

PF5

VDD VSS

VSS VSS VSS VSS PH12 PG5 PG4 PG3

PF10

PF9

VSSA PC0

PF8

BYPASS_

REG

PC1 PC2 PC3

PH11 PH10 PD15 PG2

PB2 PG1 VSS VSS VCAP_1 PH6 PH8 PH9 PD14 PD13

VREF-

PA1 PA0

PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10

VREF+

PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8

R VDDA PA3 PA7 PB1 PB0 PF11

PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15

MS39130V1

1. The above figure shows the package top view.

58/228 DS11854 Rev 5

STM32F732xx STM32F733xx Pinouts and pin description

Figure 23. STM32F733xx UFBGA176 ballout (with OTG PHY HS)

PE3

PE2

PE4 PE5

VBAT

PC13

PI7

PI8

3 4 5 6 7 8 9 10 11 12 13 14 15

PE1 PE0

PE6

PB9

PB8 PB5

PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13

PB7

PB6

PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12

PI6

PI9

PI5

PI4

VDD

PDR_ON VDD

VDD

SDMMC

VDD

VSS BOOT0

VSS VSS VSS

PG9 PD5 PD1

PD4 PD3 PD2

PI3

PH15

PI2

PI1

PA11

PA10

E PC14

PF0

PI10 PI11

PC15

VSS VDD PH2

VSS

VSS VSS VSS VSS

PH13

VSS

PH14

VCAP2

PI0

PC9

PA9

PA8

PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7

PH1

PF2 PF1 PH4

NRST PF3 PH5

VSS

VSS VDDUSB PG8 PC6

VDD VDD

VDD12

OTGHS

OTG_HS

_REXT

PF7

PF6 PF5 VDD VSS

VSS VSS VSS VSS PH12 PG5 PG4 PG3

PF10

PF9

VSSA PC0

PF8

BYPASS_

REG

PC1 PC2 PC3

PH11 PH10 PD15 PG2

PB2 PG1 VSS VSS VCAP_1 PH6 PH8 PH9 PD14 PD13

VREF-

PA1 PA0

PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10

VREF+

PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8

R VDDA PA3 PA7 PB1 PB0 PF11

PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15

MS42001V1

1. The above figure shows the package top view.

DS11854 Rev 5 59/228

Pinouts and pin description STM32F732xx STM32F733xx

Name

Pin name

Pin type

I/O structure

Table 9. Legend/abbreviations used in the pinout table

Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

FTf

TTa

RST

Input / output pin

5 V tolerant I/O

5V tolerant I/O, I2C Fm+ option.

3.3 V tolerant I/O directly connected to ADC

Dedicated BOOT pin

Bidirectional reset pin with weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Notes

Alternate functions

Additional functions

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

60/228 DS11854 Rev 5

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

1 1 A2 1 C9 A2 A3 1 1

2 2 A1 2 A10 A1 A2 2 2

3 3 B1 3 D9 B1 B2 3 3

4 4 B2 4 E8 B2 B3 4 4

5 5 B3 5 B10 B3 B4 5 5

1 6 6 C1 6 C10 C1 C2 6 6

PE2

PE3

PE4

PE5

PE6

VBAT

I/O FT -

TRACECLK, SPI4_SCK,

SAI1_MCLK_A,

QUADSPI_BK1_IO2, FMC_A23,

EVENTOUT

I/O FT -

TRACED0, SAI1_SD_B,

FMC_A19, EVENTOUT

I/O FT -

TRACED1, SPI4_NSS,

SAI1_FS_A, FMC_A20,

EVENTOUT

I/O FT -

S -

TRACED2, TIM9_CH1,

SPI4_MISO, SAI1_SCK_A,

FMC_A21, EVENTOUT

TRACED3, TIM1_BKIN2,

TIM9_CH2, SPI4_MOSI,

SAI1_SD_A, SAI2_MCK_B,

FMC_A22, EVENTOUT

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

D2 7 D2 -

7 D1 8 D10 D1 A1

D3 11

E3 12

E4 13

F2 14

F3 15 -

D3 -

F3 -

PI8

PC13

PI9

PI10

PI11

VSS

VDD

I/O FT

(2)

(3)

I/O FT

(2)

(3)

3 8

4 9

8 E1 9 E9 E1 B1

9 F1 10 E10 F1 C1

PC14-

OSC32_IN(PC1

I/O FT

PC15-

OSC32_OUT(P

C15)

I/O FT

(2)

(3)

(5)

(2)

(3)

(5)

I/O FT -

I/O FT

(4)

S -

EVENTOUT

UART4_RX, CAN1_RX,

FMC_D30, EVENTOUT

FMC_D31, EVENTOUT

OTG_HS_ULPI_DIR,

EVENTOUT

RTC_TAMP2/

RTC_TS,

WKUP5

RTC_TAMP1/

RTC_TS/

RTC_OUT,

WKUP4

OSC32_IN

OSC32_OUT

WKUP6

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

12 H2 18 H2 D4 12 18

13 J2 19

14 J3 20

15 K3 21 -

J2 E2 13 19

J3 E3 14 20

K3 E4 15 21

10 16 G2 22 F9 G2 D2 16 22

11 17 G3 23 F10 G3 D3 17 23

18 K2 24 K2 F3 18 24

19 K1 25 K1 F2 19 25

PF0

PF1

PF2

PF3

PF4

PF5

VSS

VDD

PF6

PF7

I/O

FTf

I/O FT -

I2C2_SDA, FMC_A0,

EVENTOUT

I2C2_SCL, FMC_A1,

EVENTOUT

I2C2_SMBA, FMC_A2,

EVENTOUT

FMC_A3, EVENTOUT

FMC_A4, EVENTOUT

FMC_A5, EVENTOUT

TIM10_CH1, SPI5_NSS,

SAI1_SD_B, UART7_RX,

QUADSPI_BK1_IO3,

EVENTOUT

I/O FT -

TIM11_CH1, SPI5_SCK,

SAI1_MCLK_B, UART7_TX,

QUADSPI_BK1_IO2,

EVENTOUT

ADC3_IN9

ADC3_IN14

ADC3_IN15

ADC3_IN4

ADC3_IN5

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

20 L3 26 L3 G3 20 26 PF8 I/O FT -

SPI5_MISO, SAI1_SCK_B,

UART7_RTS, TIM13_CH1,

QUADSPI_BK1_IO0,

EVENTOUT

PF9

PC1

I/O

FT -

G10

H10

PF10

PH0-OSC_IN

I/O FT -

I/O FT

(5)

PH1-OSC_OUT I/O FT

(5)

7 14 25 J1 31 G9 J1 F1 25 31 NRST I/O

8 15 26 M2 32 F8 M2 H1 26 32 PC0 I/O FT

(4)

SPI5_MOSI, SAI1_FS_B,

UART7_CTS, TIM14_CH1,

QUADSPI_BK1_IO1,

EVENTOUT

SAI2_FS_B,

OTG_HS_ULPI_STP,

FMC_SDNWE, EVENTOUT

TRACED0,

SPI2_MOSI/I2S2_SD,

SAI1_SD_A, EVENTOUT

ADC3_IN6

ADC3_IN7

ADC3_IN8

OSC_IN

OSC_OUT

ADC1_IN10,

ADC2_IN10,

ADC3_IN10

ADC1_IN11,

ADC2_IN11,

ADC3_IN11,

RTC_TAMP3,

WKUP3

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

10 17 28 M4 34 J10 M4 H3 28 34 PC2 I/O FT

(4)

SPI2_MISO,

OTG_HS_ULPI_DIR,

FMC_SDNE0, EVENTOUT

ADC1_IN12,

ADC2_IN12,

ADC3_IN12

11 18 29 M5 35 F7 M5 H4 29 35

30 36 J7 F10 30 36

12 19 31 M1 37 K10 M1 J1 31 37

N1 -

13 20 32 P1 38 J9

21 33 R1 39 K9 R1 M1 33 39

PC3

VDD

VSSA

VREF-

VREF+

VDDA

I/O FT

(4)

SPI2_MOSI/I2S2_SD,

OTG_HS_ULPI_NXT,

FMC_SDCKE0, EVENTOUT

14 22 34 N3 40 G8 N3 J2 34 40 PA0-WKUP I/O FT

(6)

TIM2_CH1/TIM2_ETR,

TIM5_CH1, TIM8_ETR,

USART2_CTS, UART4_TX,

SAI2_SD_B, EVENTOUT

ADC1_IN13,

ADC2_IN13,

ADC3_IN13

ADC1_IN0,

ADC2_IN0,

ADC3_IN0,

WKUP1

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

15 23 35 N2 41 J8 N2 K2 35 41 PA1 I/O FT -

TIM2_CH2, TIM5_CH2,

USART2_RTS, UART4_RX,

QUADSPI_BK1_IO3,

SAI2_MCK_B, EVENTOUT

ADC1_IN1,

ADC2_IN1,

ADC3_IN1

16 24 36 P2 42 H8 P2 L2 36 42 PA2 I/O FT -

TIM2_CH3, TIM5_CH3,

TIM9_CH1, USART2_TX,

SAI2_SCK_B, EVENTOUT

PH2

PH3

PH4

PH5

PA3

VSS

48 BYPASS_REG

I/O

FTf

FT -

(4)

LPTIM1_IN2,

QUADSPI_BK2_IO0,

SAI2_SCK_B, FMC_SDCKE0,

EVENTOUT

QUADSPI_BK2_IO1,

SAI2_MCK_B, FMC_SDNE0,

EVENTOUT

I2C2_SCL, OTG_HS_ULPI_NXT,

EVENTOUT

I2C2_SDA, SPI5_NSS,

FMC_SDNWE, EVENTOUT

TIM2_CH4, TIM5_CH4,

TIM9_CH2, USART2_RX,

OTG_HS_ULPI_D0, EVENTOUT

ADC1_IN2,

ADC2_IN2,

ADC3_IN2,

WKUP2

ADC1_IN3,

ADC2_IN3,

ADC3_IN3

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

19 27 39 K4 49 K4 F4 39 49

20 28 40 N4 50 G7 N4 J3 40 50

23 31 43 R3 53 K7 R3 M3 43 53

24 32 44 N5 54 H6 N5 J4 44 54

33 45 P5 55 J6 P5 K4 45 55

VDD

PA4

PA5

PA6

PA7

PC4

PC5

S -

I/O TTa

I/O

FT -

(4)

SPI1_NSS/I2S1_WS,

SPI3_NSS/I2S3_WS,

USART2_CK, OTG_HS_SOF,

EVENTOUT

TIM2_CH1/TIM2_ETR,

TIM8_CH1N,

SPI1_SCK/I2S1_CK,

OTG_HS_ULPI_CK, EVENTOUT

TIM1_BKIN, TIM3_CH1,

TIM8_BKIN, SPI1_MISO,

TIM13_CH1, EVENTOUT

TIM1_CH1N, TIM3_CH2,

TIM8_CH1N,

SPI1_MOSI/I2S1_SD,

TIM14_CH1, FMC_SDNWE,

EVENTOUT

I/O FT -

I2S1_MCK, FMC_SDNE0,

EVENTOUT

I/O FT FMC_SDCKE0, EVENTOUT

ADC1_IN4,

ADC2_IN4,

DAC_OUT1

ADC1_IN5,

ADC2_IN5,

DAC_OUT2

ADC1_IN6,

ADC2_IN6

ADC1_IN7,

ADC2_IN7

ADC1_IN14,

ADC2_IN14

ADC1_IN15,

ADC2_IN15

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

25 34 46 R5 56 F5 R5 L4 46 56

26 35 47 R4 57 G5 R4 M4 47 57

27 36 48 M6 58 K6 M6 J5 48 58

49 R6 59

50 P6 60

51 M8 61

52 N8 62

53 N6 63

54 R7 64

55 P7 65

56 N7 66

57 M7 67

R6 M5 49 59

P6 L5 50 60

M8 51 61

N8 G5 52 62

N6 K5 53 63

R7 M6 54 64

P7 L6 55 65

N7 K6 56 66

M7 J6 57 67

PB0

PB1

PB2

PF11

PF12

VSS

VDD

PF13

PF14

PF15

PG0

PG1

I/O FT

(4)

TIM1_CH2N, TIM3_CH3,

TIM8_CH2N, UART4_CTS,

OTG_HS_ULPI_D1, EVENTOUT

I/O

(4)

TIM1_CH3N, TIM3_CH4,

TIM8_CH3N,

OTG_HS_ULPI_D2, EVENTOUT

SAI1_SD_A,

SPI3_MOSI/I2S3_SD,

QUADSPI_CLK, EVENTOUT

I/O

SPI5_MOSI, SAI2_SD_B,

FMC_SDNRAS, EVENTOUT

FMC_A6, EVENTOUT

FMC_A7, EVENTOUT

FMC_A8, EVENTOUT

FMC_A9, EVENTOUT

FMC_A10, EVENTOUT

FMC_A11, EVENTOUT

ADC1_IN8,

ADC2_IN8

ADC1_IN9,

ADC2_IN9

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

37 58 R8 68 J5 R8 M7 58 68

38 59 P8 69 H5 P8 L7 59 69

39 60 P9 70 K5 P9 K7 60 70

72 -

M9 H6 61 71

N9 G6 62 72

40 63 R9 73 E4 R9 J7 63 73

41 64 P10 74 G4 P10 H8 64 74

42 65 R10 75 H4 R10 J8 65 75

43 66 N11 76 J4 N11 K8 66 76

PE11

PE12

PE13

PE7

PE8

PE9

VSS

VDD

PE10

I/O FT -

TIM1_ETR, UART7_Rx,

QUADSPI_BK2_IO0, FMC_D4,

EVENTOUT

TIM1_CH1N, UART7_Tx,

QUADSPI_BK2_IO1, FMC_D5,

EVENTOUT

TIM1_CH1, UART7_RTS,

QUADSPI_BK2_IO2, FMC_D6,

EVENTOUT

TIM1_CH2N, UART7_CTS,

QUADSPI_BK2_IO3, FMC_D7,

EVENTOUT

TIM1_CH2, SPI4_NSS,

SAI2_SD_B, FMC_D8,

EVENTOUT

TIM1_CH3N, SPI4_SCK,

SAI2_SCK_B, FMC_D9,

EVENTOUT

TIM1_CH3, SPI4_MISO,

SAI2_FS_B, FMC_D10,

EVENTOUT

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

44 67 P11 77 K4 P11 L8 67 77

45 68 R11 78 F4 R11 M8 68 78

28 46 69 R12 79 G3 R12 M9 69 79

29 47 70 R13 80 H3 R13 M10 70 80

30 48 71 M10 81 J3 M10 H7 71 81

31 49 K3 -

32 50 72 N10 82 K2 N10 G7 72 82

M11 83 M11 83

N12 84 N12 -

M12 85 M12 -

PE14

PE15

PB10

PB11

VCAP_1

VSS

VDD

PH6

PH7

PH8

I/O

FTf

(4)

TIM1_CH4, SPI4_MOSI,

SAI2_MCK_B, FMC_D11,,

EVENTOUT

TIM1_BKIN, FMC_D12,

EVENTOUT

TIM2_CH3, I2C2_SCL,

SPI2_SCK/I2S2_CK,

USART3_TX,

OTG_HS_ULPI_D3, EVENTOUT

I/O FTf

(4)

TIM2_CH4, I2C2_SDA,

USART3_RX,

OTG_HS_ULPI_D4, EVENTOUT

I/O

FTf

FTf -

I2C2_SMBA, SPI5_SCK,

TIM12_CH1, FMC_SDNE1,

EVENTOUT

I2C3_SCL, SPI5_MISO,

FMC_SDCKE1, EVENTOUT

I2C3_SDA, FMC_D16,

EVENTOUT

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

M13

L13

L12

K12

H12 90 -

M13

L13

L12

K12

H12 -

J12 91 K2 J12 -

P12

P13

P12 M11

P13 M12

PH9

PH10

PH11

PH12

VSS

VDD

PB12

PB13

I/O

G2 J15 H11 75 94 OTG_HS_REXT -

G1 J14 H10 76 95 VDD12OTGHS -

(4)

I2C3_SMBA, TIM12_CH2,

FMC_D17, EVENTOUT

TIM5_CH1, FMC_D18,

EVENTOUT

TIM5_CH2, FMC_D19,

EVENTOUT

TIM5_CH3, FMC_D20,

EVENTOUT

TIM1_BKIN, I2C2_SMBA,

SPI2_NSS/I2S2_WS,

USART3_CK,

OTG_HS_ULPI_D5,

OTG_HS_ID, EVENTOUT

I/O FT

(4)

TIM1_CH1N,

SPI2_SCK/I2S2_CK,

USART3_CTS,

OTG_HS_ULPI_D6, EVENTOUT

OTG_HS_VBUS

USB HS OTG PHY calibration resistor

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

R14

R15

95 -

J1 R14 L11 77 96

PB14

PB15

H1 R15 L12 78 97

55 77 P15 96

56 78 P14 97

57 79 N15 98

P15 L9 79 98

P14 K9 80 99

N15 J9 81 100

PB15

PD8

PD9

PD10

I/O FT -

TIM1_CH2N, TIM8_CH2N,

SPI2_MISO, USART3_RTS,

TIM12_CH1, SDMMC2_D0,

OTG_HS_DM, EVENTOUT

I/O FT OTG_HS_DM

I/O FT -

RTC_REFIN, TIM1_CH3N,

TIM8_CH3N,

SPI2_MOSI/I2S2_SD,

TIM12_CH2, SDMMC2_D1,

OTG_HS_DP, EVENTOUT

I/O FT OTG_HS_DP

I/O

FT -

USART3_TX, FMC_D13,

EVENTOUT

USART3_RX, FMC_D14,

EVENTOUT

USART3_CK, FMC_D15,

EVENTOUT

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

59 81 N13 100 F2 N13 L10 83 102 PD12

N14 99

M15 101

N14 H9

M15 K10

101

103

102

J13 103

J13

104

105

61 85 M14 104 F1 M14 K11 87 106

62 86 L14 105 E2 L14 K12 88 107

L15 106

K15 107 -

L15

K15

J12

J11

108

109

PD11

PD13

VSS

VDD

PD14

PD15

PG2

PG3

I/O FT -

I/O FT

I/O FT -

USART3_CTS,

QUADSPI_BK1_IO0,

SAI2_SD_A,

FMC_A16/FMC_CLE,

EVENTOUT

TIM4_CH1, LPTIM1_IN1,

USART3_RTS,

QUADSPI_BK1_IO1,

SAI2_FS_A,

FMC_A17/FMC_ALE,

EVENTOUT

TIM4_CH2, LPTIM1_OUT,

QUADSPI_BK1_IO3,

SAI2_SCK_A, FMC_A18,

EVENTOUT

TIM4_CH3, UART8_CTS,

FMC_D0, EVENTOUT

TIM4_CH4, UART8_RTS,

FMC_D1, EVENTOUT

FMC_A12, EVENTOUT

FMC_A13, EVENTOUT

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

89 K14 108 K14 J10 91 110

90 K13 109

91 J15 110

92 J14 111

K13 H12 92 111

93 H14 112 H14 G11 93 112

94 G12 113

G12

F10

113

95 H13 114 K1 H13 C11 95 114

37 63 96 H15 115 E1 H15 G12 96 115

38 64 97 G15 116 D4 G15 F12 97 116

PG4

PG5

PG6

PG7

PG8

VSS

VDD

VDDUSB

PC6

PC7

I/O FT -

I/O

I/O FT -

FMC_A14/FMC_BA0,

EVENTOUT

FMC_A15/FMC_BA1,

EVENTOUT

USART6_CK, FMC_INT,

EVENTOUT

USART6_RTS, FMC_SDCLK,

EVENTOUT

TIM3_CH1, TIM8_CH1,

I2S2_MCK, USART6_TX,

SDMMC2_D6, SDMMC1_D6,

EVENTOUT

TIM3_CH2, TIM8_CH2,

I2S3_MCK, USART6_RX,

SDMMC2_D7, SDMMC1_D7,

EVENTOUT

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

G14 117

F14 118

100 F15 119

101 E15 120

102 D15 121

103 C15 122

104 B15 123

G14 F11

F14 E11

117

118

F15 E12 100 119

E15 D12 101 120

D15 D11 102 121

C15 C12 103 122

B15 B12 104 123

PC8

PC9

PA8

PA9

PA10

PA11

PA12

46 72 105 A15 124 B1 A15 A12 105 124

PA13(JTMS-

SWDIO)

I/O FT -

I/O FTf -

I/O FT -

TRACED1, TIM3_CH3,

TIM8_CH3, UART5_RTS,

USART6_CK, SDMMC1_D0,

EVENTOUT

MCO2, TIM3_CH4, TIM8_CH4,

I2C3_SDA, I2S_CKIN,

UART5_CTS,

QUADSPI_BK1_IO0,

SDMMC1_D1, EVENTOUT

MCO1, TIM1_CH1, TIM8_BKIN2,

I2C3_SCL, USART1_CK,

OTG_FS_SOF, EVENTOUT

TIM1_CH2, I2C3_SMBA,

SPI2_SCK/I2S2_CK,

USART1_TX, EVENTOUT

OTG_FS_VBUS

TIM1_CH3, USART1_RX,

OTG_FS_ID, EVENTOUT

TIM1_CH4, USART1_CTS,

CAN1_RX, OTG_FS_DM,

EVENTOUT

TIM1_ETR, USART1_RTS,

SAI2_FS_B, CAN1_TX,

OTG_FS_DP, EVENTOUT

I/O FT JTMS-SWDIO, EVENTOUT -

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

73 106 F13 125 B3 F13 G9 106 125

47 74 107 F12 126 A2 F12 G10 107 126

48 75 108 G13 127 A1 G13 F9 108 127

E12 128 E12 128

VCAP_2

VSS

VDD

PH13

D13 130 D13 -

E14 131 E14 -

E13 129

D14 132 -

E13 -

D14 -

C14 133 C14 -

C13 134 C13 -

D9 135 D9 -

129

130

131

132

133

134

135

PH14

PH15

PI0

PI1

PI2

PI3

VSS

I/O

TIM8_CH1N, UART4_TX,

CAN1_TX, FMC_D21,

EVENTOUT

TIM8_CH2N, UART4_RX,

CAN1_RX, FMC_D22,

EVENTOUT

TIM8_CH3N, FMC_D23,

EVENTOUT

I/O FT -

TIM5_CH4, SPI2_NSS/I2S2_WS,

FMC_D24, EVENTOUT

I/O FT -

S -

TIM8_BKIN2,

SPI2_SCK/I2S2_CK, FMC_D25,

EVENTOUT

TIM8_CH4, SPI2_MISO,

FMC_D26, EVENTOUT

TIM8_ETR,

SPI2_MOSI/I2S2_SD, FMC_D27,

EVENTOUT

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

C9 136 C9 136

49 76 109 A14 137 C4 A14 A11 109 137

VDD

PA14(JTCK-

SWCLK)

110 A13 138

111 B14 139

112 B13 140

113 A12 141

114 B12 142

115 C12 143

A13 A10

B14 B11

B13 B10

B12 E10

110 138

111 139

112 140

A12 C10 113 141

114 142

C12 D10 115 143

PA15(JTDI)

PC10

PC11

PC12

PD0

PD1

I/O

I/O FT -

JTCK-SWCLK, EVENTOUT

JTDI, TIM2_CH1/TIM2_ETR,

SPI1_NSS/I2S1_WS,

SPI3_NSS/I2S3_WS,

UART4_RTS, EVENTOUT

SPI3_SCK/I2S3_CK,

USART3_TX, UART4_TX,

QUADSPI_BK1_IO1,

SDMMC1_D2, EVENTOUT

SPI3_MISO, USART3_RX,

UART4_RX,

QUADSPI_BK2_NCS,

SDMMC1_D3, EVENTOUT

TRACED3,

SPI3_MOSI/I2S3_SD,

USART3_CK, UART5_TX,

SDMMC1_CK, EVENTOUT

CAN1_RX, FMC_D2,

EVENTOUT

CAN1_TX, FMC_D3,

EVENTOUT

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

116 D12 144

117 D11 145

118 D10 146

D12

D11

D10

116 144

117 145

118 146

86 119 C11 147 A5 C11 B9 119 147

120 D8 148

121 C8 149

D8 E7 120 148

PD5

VSS

C8 F7 121 149 VDDSDMMC

122 B11 150

123 A11 151

124 C10 152

B11

A11

C10

122 150

123 151

124 152

PD2

PD3

PD4

PD6

PD7

PG9

I/O FT -

I/O

I/O FT -

TRACED2, TIM3_ETR,

UART5_RX, SDMMC1_CMD,

EVENTOUT

SPI2_SCK/I2S2_CK,

USART2_CTS, FMC_CLK,

EVENTOUT

USART2_RTS, FMC_NOE,

EVENTOUT

USART2_TX, FMC_NWE,

EVENTOUT

SPI3_MOSI/I2S3_SD,

SAI1_SD_A, USART2_RX,

SDMMC2_CK, FMC_NWAIT,

EVENTOUT

USART2_CK SDMMC2_CMD,

FMC_NE1, EVENTOUT

USART6_RX,

QUADSPI_BK2_IO2,

SAI2_FS_B, SDMMC2_D0,

FMC_NE2/FMC_NCE,

EVENTOUT

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

125 B10 153 B10 D8 125 153 PG10 I/O FT -

SAI2_SD_B, SDMMC2_D1,

FMC_NE3, EVENTOUT

126 B9 154 B9 C8 126 154 PG11 I/O FT -

SDMMC2_D2, FMC_INT,

EVENTOUT

127 B8 155 B8 B8 127 155 PG12 I/O FT -

LPTIM1_IN1, USART6_RTS,

SDMMC2_D3, FMC_NE4,

EVENTOUT

128 A8 156 A8 D7 128 156 PG13

129 A7 157 -

130 D7 158 -

A7 C7 129 157

D7 130 158

PG14

VSS

I/O FT -

TRACED0, LPTIM1_OUT,

USART6_CTS, FMC_A24,

EVENTOUT

I/O FT -

TRACED1, LPTIM1_ETR,

USART6_TX,

QUADSPI_BK2_IO3, FMC_A25,

EVENTOUT

S -

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

131

132

159

160

133 A10 161

A10

131 159

132 160

133 161

VDD

PG15

PB3(JTDO/TRA

CESWO)

I/O

56 90 134 A9 162 B7 A9 A6 134 162 PB4(NJTRST) I/O FT -

USART6_CTS, FMC_SDNCAS,

EVENTOUT

JTDO/TRACESWO, TIM2_CH2,

SPI1_SCK/I2S1_CK,

SPI3_SCK/I2S3_CK,

SDMMC2_D2, EVENTOUT

NJTRST, TIM3_CH1,

SPI1_MISO, SPI3_MISO,

SPI2_NSS/I2S2_WS,

SDMMC2_D3, EVENTOUT

57 91 135 A6 163 C7 A6 B6 135 163 PB5 I/O FT

(4)

TIM3_CH2, I2C1_SMBA,

SPI1_MOSI/I2S1_SD,

SPI3_MOSI/I2S3_SD,

OTG_HS_ULPI_D7,

FMC_SDCKE1, EVENTOUT

58 92 136 B6 164 D7 B6 C6 136 164 PB6 I/O FTf -

TIM4_CH1, I2C1_SCL,

USART1_TX,

QUAD SPI_BK1_NCS,

FMC_SDNE1, EVENTOUT

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

59 93 137 B5 165 B8 B5 D6 137 165

60 94 138 D6 166 A7 D6 D5 138 166

61 95 139 A5 167 C8 A5 C5 139 167

PB7

BOOT

PB8

140

141

142

168

169

170

63 99 D5 -

140 168

141 169

142 170

A8 D5 E6 -

PB9

PE0

PE1

VSS

I/O FTf -

I B

I/O FTf -

TIM4_CH2, I2C1_SDA,

USART1_RX, FMC_NL,

EVENTOUT

TIM4_CH3, TIM10_CH1,

I2C1_SCL, CAN1_RX,

SDMMC2_D4, SDMMC1_D4,

EVENTOUT

I/O FTf -

TIM4_CH4, TIM11_CH1,

I2C1_SDA, SPI2_NSS/I2S2_WS,

CAN1_TX, SDMMC2_D5,

SDMMC1_D5, EVENTOUT

I/O FT -

TIM4_ETR, LPTIM1_ETR,

UART8_Rx, SAI2_MCK_A,

FMC_NBL0, EVENTOUT

I/O FT -

S -

LPTIM1_IN2, UART8_Tx,

FMC_NBL1, EVENTOUT

VPP

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

143 C6 171 C6 E5 143 171

64 100 144 C5 172 A9 C5 F5 144 172

D4 173 D4 173

PDR_ON

VDD

PI4

S -

I/O FT -

TIM8_BKIN, SAI2_MCK_A,

FMC_NBL2, EVENTOUT

C4 174 C4 174 PI5 I/O FT -

TIM8_CH1, SAI2_SCK_A,

FMC_NBL3, EVENTOUT

C3 175 C3 175 PI6

C2 176 C2 176

F10 -

PI7

VSS

I/O FT -

TIM8_CH2, SAI2_SD_A,

FMC_D28, EVENTOUT

TIM8_CH3, SAI2_FS_A,

FMC_D29, EVENTOUT

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

G10 -

H7 -

H10 -

J6 -

J10 -

G10 -

H7 -

H10 -

J6 -

J10 -

VSS

STM32F732xx

Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued)

Pin Number

STM32F733xx

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

K10 -

VSS

1. Function availability depends on the chosen device.

2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to

PC15 and PI8 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These I/Os must not be used as a current source (e.g. to drive an LED).

3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset).

4. ULPI signals not available on the STM32F733xx devices.

5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).

6. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal reset (active low).

STM32F732xx STM32F733xx Pinouts and pin description

Pin name

PG14

PD14

PD15

PD0

PD1

PE7

PG5

PD11

PD12

PD13

PE3

PE4

PE5

PE6

PE2

PG13

PE8

PE9

PE10

PF13

PF14

PF15

PG0

PG1

PG2

PG3

PG4

PF0

PF1

PF2

PF3

PF4

PF5

PF12

Table 11. FMC pin definition

NOR/PSRAM/SR

NOR/PSRAM

Mux

NAND16

A25

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A11

A12

A13

A14

A10

A25

DA0

DA1

DA2

DA3

DA4

A16

A17

A18

A19

A20

A21

A22

A23

A24

DA5

DA6

DA7

CLE

ALE

DS11854 Rev 5

SDRAM

BA1

A11

A12

BA0

A10

85/228

Pin name

PI10

PD7

PG9

PG10

PG11

PG12

PI1

PI2

PI3

PI6

PI7

PI9

PD3

PD4

PD5

PD6

PB7

PD10

PH8

PH9

PH10

PH11

PH12

PH13

PH14

PH15

PI0

PE11

PE12

PE13

PE14

PE15

PD8

PD9

Pinouts and pin description STM32F732xx STM32F733xx

Table 11. FMC pin definition (continued)

NOR/PSRAM/SR

NOR/PSRAM

Mux

NAND16

D31

NE1

NE2

NE3

NE4

D25

D26

D27

D28

D29

D30

CLK

NOE

NWE

NWAIT

NADV

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D10

D11

D12

D13

D14

NE1

NE2

NE3

NE4

DA15

DA8

DA9

DA10

DA11

DA12

DA13

DA14

CLK

NOE

NWE

NWAIT

NADV

NCE

NOE

NWE

NWAIT

D15

D10

D11

D12

D13

D14

SDRAM

D31

D25

D26

D27

D28

D29

D30

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D10

D11

D12

D13

D14

86/228 DS11854 Rev 5

Pin name

PE0

PE1

PI4

PI5

PG8

PC0

PF11

PG15

PH2

PH3

PF6

PF7

PF8

PF9

PF10

PG6

PG7

PH6

PH7

PH5

PC2

PC3

PB5

PB6

STM32F732xx STM32F733xx Pinouts and pin description

Table 11. FMC pin definition (continued)

NOR/PSRAM/SR

NOR/PSRAM

Mux

NAND16

NBL0

NBL1

NBL2

NBL3

NBL0

NBL1

INT

SDRAM

NBL0

NBL1

NBL2

NBL3

SDCLK

SDNWE

SDNRAS

SDNCAS

SDCKE0

SDNE0

SDNE1

SDCKE1

SDNWE

SDNE0

SDCKE0

SDCKE1

SDNE1

DS11854 Rev 5 87/228

Port

PA0

AF0

SYS

Table 12. STM32F732xx and STM32F733xx alternate function mapping

AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF1 AF10 AF11 AF12 AF15

TIM1/2 TIM3/4/5

TIM8/9/10/1

1/LPTIM1

I2C1/2/3/U

SART1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5

SPI2/I2S2/

SPI3/I2S3/

SAI1/

UART4

SPI2/I2S2/S

PI3/I2S3/US

ART1/2/3/UA

RT5

SAI2/USART

6/UART4/5/7/

8/OTG1_FS

CAN1/TIM1

2/13/14/QU

ADSPI/

FMC/

OTG2_HS

SAI2/QUAD

SPI/SDMM

C2/OTG2_

HS/OTG1_

SDMMC2

UART7/F

MC/SDM

MC1/

OTG2_FS

TIM2_CH1

/TIM2_ET

TIM5_CH1 TIM8_ETR -

USART2_CT

UART4_ TX SAI2_SD_B -

SYS

EVEN

TOUT

PA1 TIM2_CH2 TIM5_CH2 -

USART2_RT

UART4_RX

QUADSPI_

BK1_IO3

SAI2_MCK

PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX SAI2_SCK_B

Port A

PA3

PA4

PA5

PA6

PA7

PA8

PA9

PA10

PA11 -

MCO1

TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX

SPI1_NSS

/I2S1_WS

SPI3_NSS

/I2S3_WS

USART2_CK

TIM2_CH1

/TIM2_ET

TIM1_BKI

TIM1_CH1

TIM1_CH2

TIM8_CH1

TIM3_CH1 TIM8_BKIN

TIM3_CH2

TIM8_CH1

SPI1_SCK

/I2S1_CK

SPI1_MIS

SPI1_MO

SI/I2S1_S

TIM8_BKIN

I2C3_SCL

I2C3_SMB

SPI2_SCK

/I2S2_CK

USART1_CK

USART1_TX

TIM1_CH3 -

TIM1_CH4 -

USART1_RX

USART1_CT

TIM13_CH1

TIM14_CH1

OTG_HS_U

LPI_D0

OTG_HS_U

LPI_CK

OTG_FS_S

CAN1_RX

OTG_FS_I

OTG_FS_D

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

OTG_HS_

SOF

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

FMC_SDN

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

AF1

Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued)

AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF0 AF11 AF12 AF15

Port

Port B

PA12

PA13

Port A

PA14

PA15

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PB8

SYS

JTMS-

SWDIO

JTCK-

SWCLK

JTDI

JTDO/TR

ACESWO

NJTRST

TIM1/2

TIM1_ETR

TIM2_CH2

TIM3/4/5

TIM3_CH1

TIM3_CH2

TIM8/9/10/1

1/LPTIM1

I2C1/2/3/U

SART1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5

SPI2/I2S2/

SPI3/I2S3/

SAI1/

UART4

SPI2/I2S2/S

PI3/I2S3/US

ART1/2/3/UA

RT5

SAI2/USART

6/UART4/5/7/

8/OTG1_FS

CAN1/TIM1

2/13/14/QU

ADSPI/

FMC/

OTG2_HS

SAI2/QUAD

SPI/SDMM

C2/OTG2_

HS/OTG1_

SDMMC2

UART7/F

MC/SDM

MC1/

OTG2_FS

USART1_RT

SAI2_FS_B CAN1_TX

OTG_FS_D

SYS

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

TIM2_CH1

/TIM2_ET

TIM1_CH2

TIM3_CH3

TIM1_CH3

TIM3_CH4

TIM8_CH2

TIM8_CH3

I2C1_SMB

SPI1_NSS

/I2S1_WS

SPI3_NSS

/I2S3_WS

SAI1_SD_

SPI3_MOSI/I

2S3_SD

SPI1_SCK

/I2S1_CK

SPI3_SCK

/I2S3_CK

SPI1_MIS

SPI1_MO

SI/I2S1_S

SPI3_MIS

SPI3_MO

SI/I2S3_S

SPI2_NSS/I2

S2_WS

UART4_RTS

UART4_CTS

QUADSPI_

CLK

OTG_HS_U

LPI_D1

OTG_HS_U

LPI_D2

SDMMC2_

OTG_HS_U

LPI_D7

FMC_SDC

KE1

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

TIM4_CH1

TIM4_CH2 -

TIM4_CH3

TIM10_CH

I2C1_SCL

I2C1_SDA

I2C1_SCL -

USART1_TX

USART1_RX

CAN1_RX

QUADSPI_

BK1_NCS

SDMMC2_

FMC_SDN

EVEN

TOUT

FMC_NL

SDMMC1

_D4

EVEN

TOUT

EVEN

TOUT

Port

PB9

PB10

PB11

PC1 TRACED0

Port C

PC2 -

PC3

AF0

SYS

Port B

PB12

PB13

PB14 -

TIM1_BKI

TIM1_CH1

TIM1_CH2

PB15

RTC_REF

TIM1_CH3

PC0 -

AF1

Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued)

AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15

TIM1/2 TIM3/4/5

TIM8/9/10/1

1/LPTIM1

I2C1/2/3/U

SART1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5

SPI2/I2S2/

SPI3/I2S3/

SAI1/

UART4

SPI2/I2S2/S

PI3/I2S3/US

ART1/2/3/UA

RT5

SAI2/USART

6/UART4/5/7/

8/OTG1_FS

CAN1/TIM1

2/13/14/QU

ADSPI/

FMC/

OTG2_HS

SAI2/QUAD

SPI/SDMM

C2/OTG2_

HS/OTG1_

SDMMC2

UART7/F

MC/SDM

MC1/

OTG2_FS

TIM2_CH3

TIM4_CH4 TIM11_CH1 I2C1_SDA

I2C2_SCL

SPI2_NSS

/I2S2_WS

SPI2_SCK

/I2S2_CK

USART3_TX -

CAN1_TX

SDMMC2_

OTG_HS_U

LPI_D3

SDMMC1

_D5

SYS

EVEN

TOUT

EVEN

TOUT

TIM2_CH4 I2C2_SDA USART3_RX -

OTG_HS_U

LPI_D4

EVEN

TOUT

TIM8_CH2

TIM8_CH3

I2C2_SMB

SPI2_NSS

/I2S2_WS

SPI2_SCK

/I2S2_CK

SPI2_MIS

SPI2_MO

SI/I2S2_S

SPI2_MO

SI/I2S2_S

SPI2_MIS

SPI2_MO

SI/I2S2_S

SAI1_SD_

USART3_CK

USART3_CT

USART3_RT

TIM12_CH1

OTG_HS_U

LPI_D5

OTG_HS_U

LPI_D6

SDMMC2_

SAI2_FS_B

TIM12_CH2

SDMMC2_

OTG_HS_U

LPI_STP

OTG_HS_U

LPI_DIR

OTG_HS_U

LPI_NXT

OTG_HS_

EVEN

TOUT

EVEN

TOUT

OTG_HS_

EVEN

TOUT

OTG_HS_

EVEN

TOUT

FMC_SDN

EVEN

TOUT

EVEN

TOUT

FMC_SDN

EVEN

TOUT

FMC_SDC

KE0

EVEN

TOUT

Port

PC4

PC5

PC6

PC7

PC9

Port C

PC10

AF0

SYS

PC8 TRACED1

PC11

PC13

PC14

PC15

MCO2

PC12 TRACED3

AF1

Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued)

AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10

TIM1/2

AF11 AF12 AF15

TIM3/4/5

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

TIM8/9/10/1

1/LPTIM1

I2C1/2/3/U

SART1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5

SPI2/I2S2/

SPI3/I2S3/

SAI1/

UART4

SPI2/I2S2/S

PI3/I2S3/US

ART1/2/3/UA

RT5

SAI2/USART

6/UART4/5/7/

8/OTG1_FS

CAN1/TIM1

2/13/14/QU

ADSPI/

FMC/

OTG2_HS

SAI2/QUAD

SPI/SDMM

C2/OTG2_

HS/OTG1_

SDMMC2

UART7/F

MC/SDM

MC1/

OTG2_FS

TIM8_CH1

TIM8_CH2

TIM8_CH3

TIM8_CH4

I2C3_SDA

I2S1_MCK

I2S2_MCK

I2S_CKIN

I2S3_MCK

SPI3_SCK

/I2S3_CK

SPI3_MIS

SPI3_MO

SI/I2S3_S

UART5_RTS

UART5_CTS

USART3_TX

USART3_RX

USART6_TX

USART6_RX

USART6_CK

UART4_TX

UART4_RX

USART3_CK UART5_TX

QUADSPI_

BK1_IO0

QUADSPI_

BK1_IO1

QUADSPI_

BK2_NCS

SDMMC2_

FMC_SDN

EVEN

TOUT

FMC_SDC

KE0

EVEN

TOUT

SDMMC1

_D6

SDMMC1

_D7

SDMMC1

_D0

SDMMC1

_D1

SDMMC1

_D2

SDMMC1

_D3

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

SDMMC1

_CK

SYS

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

Port

Port D

PD0

PD1

PD3

PD4

PD5

PD6

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

Port D

PD15

AF0

SYS

PD2 TRACED2

AF1

Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued)

AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10

TIM1/2

AF11 AF12 AF15

TIM3/4/5

TIM3_ETR

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_CH4

TIM8/9/10/1

1/LPTIM1

I2C1/2/3/U

SART1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5

SPI2/I2S2/

SPI3/I2S3/

SAI1/

UART4

SPI2/I2S2/S

PI3/I2S3/US

ART1/2/3/UA

RT5

SAI2/USART

6/UART4/5/7/

8/OTG1_FS

CAN1/TIM1

2/13/14/QU

ADSPI/

FMC/

OTG2_HS

SAI2/QUAD

SPI/SDMM

C2/OTG2_

HS/OTG1_

SDMMC2

UART7/F

MC/SDM

MC1/

OTG2_FS

LPTIM1_IN

LPTIM1_O

SYS

SPI2_SCK

/I2S2_CK

USART2_CT

USART2_RT

USART2_TX

UART5_RX

CAN1_RX

CAN1_TX

FMC_D2

FMC_D3

SDMMC1

_CMD

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

FMC_CLK

FMC_NO

FMC_NW

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

SPI3_MO

SI/I2S3_S

SAI1_SD_

USART2_RX

SDMMC2

_CK

FMC_NW

AIT

EVEN

TOUT

USART2_CK

USART3_TX

USART3_RX

USART3_CK

USART3_CT

USART3_RT

UART8_CTS

UART8_RTS -

QUADSPI_

BK1_IO0

QUADSPI_

BK1_IO1

SAI2_SD_A

SAI2_FS_A

QUADSPI_

BK1_IO3

SAI2_SCK_

SDMMC2

_CMD

FMC_NE1

EVEN

TOUT

FMC_D13

FMC_D14

FMC_D15

FMC_A16/

FMC_CLE

FMC_A17/

FMC_ALE

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

FMC_A18

FMC_D0

FMC_D1

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

AF1

Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued)

AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF0 AF11 AF12 AF15

Port

Port E

PE0

PE1

PE2

PE3

PE4

PE5

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

SYS

TRACECL

TRACED0

TRACED1

TRACED2

PE6 TRACED3

TIM1/2

TIM1_BKI

TIM1_ETR

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM1_BKI

TIM3/4/5

TIM8/9/10/1

1/LPTIM1

I2C1/2/3/U

SART1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5

SPI2/I2S2/

SPI3/I2S3/

SAI1/

UART4

SPI2/I2S2/S

PI3/I2S3/US

ART1/2/3/UA

RT5

SAI2/USART

6/UART4/5/7/

8/OTG1_FS

CAN1/TIM1

2/13/14/QU

ADSPI/

FMC/

OTG2_HS

SAI2/QUAD

SPI/SDMM

C2/OTG2_

HS/OTG1_

SDMMC2

UART7/F

MC/SDM

MC1/

OTG2_FS

TIM4_ETR

LPTIM1_ET

LPTIM1_IN

TIM9_CH1

TIM9_CH2

SPI4_SCK

SPI4_NSS

SPI4_SCK

SPI4_MIS

SPI4_MO

SAI1_MCL

K_A

SAI1_SD_

SPI4_NSS

SPI4_MIS

SAI1_FS_

SAI1_SCK

SPI4_MO

SAI1_SD_

UART8_Rx

UART8_Tx

UART7_Rx

UART7_Tx

UART7_RTS

UART7_CTS

QUADSPI_

BK1_IO2

SAI2_MCK

QUADSPI_

BK2_IO0

QUADSPI_

BK2_IO1

QUADSPI_

BK2_IO2

QUADSPI_

BK2_IO3

SAI2_SD_B

SAI2_SCK_

SAI2_FS_B

SAI2_MCK

SYS

FMC_NBL

EVEN

TOUT

FMC_NBL

EVEN

TOUT

FMC_A23

FMC_A19

FMC_A20

FMC_A21

FMC_A22

FMC_D4

FMC_D5

FMC_D6

FMC_D7

FMC_D8

FMC_D9

FMC_D10

FMC_D11

FMC_D12

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

Port

PF3

PF4

PF5

Port F PF6

PF0

PF1

PF2

PF7

PF8

PF9

PF10

PF11

PF12

PF13

Port F PF14

PF15

AF0

SYS

AF1

Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued)

AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10

TIM1/2

AF11 AF12 AF15

TIM3/4/5

TIM8/9/10/1

1/LPTIM1

I2C1/2/3/U

SART1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5

SPI2/I2S2/

SPI3/I2S3/

SAI1/

UART4

SPI2/I2S2/S

PI3/I2S3/US

ART1/2/3/UA

RT5

SAI2/USART

6/UART4/5/7/

8/OTG1_FS

CAN1/TIM1

2/13/14/QU

ADSPI/

FMC/

OTG2_HS

SAI2/QUAD

SPI/SDMM

C2/OTG2_

HS/OTG1_

SDMMC2

UART7/F

MC/SDM

MC1/

OTG2_FS

TIM10_CH

TIM11_CH1

I2C2_SDA

I2C2_SCL

I2C2_SMB

SPI5_NSS

SPI5_SCK

SPI5_MIS

SPI5_MO

SAI1_SD_

SAI1_MCL

K_B

SAI1_SCK

SAI1_FS_

UART7_Rx

UART7_Tx

QUADSPI_

BK1_IO3

QUADSPI_

BK1_IO2

UART7_RTS TIM13_CH1

UART7_CTS TIM14_CH1

QUADSPI_

BK1_IO0

QUADSPI_

BK1_IO1

SAI2_SD_B

SYS

FMC_A0

FMC_A1

FMC_A2

FMC_A3

FMC_A4

FMC_A5

FMC_SDN

RAS

EVEN

TOUT

FMC_A6

EVEN

TOUT

FMC_A7

FMC_A8

FMC_A9

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

Port

PG3

PG4

Port G

PG5

PG6

PG0

PG1

PG2

PG7

PG8

PG9

PG10

AF0

SYS

AF1

Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued)

AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10

TIM1/2

AF11 AF12 AF15

TIM3/4/5

TIM8/9/10/1

1/LPTIM1

I2C1/2/3/U

SART1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5

SPI2/I2S2/

SPI3/I2S3/

SAI1/

UART4

SPI2/I2S2/S

PI3/I2S3/US

ART1/2/3/UA

RT5

SAI2/USART

6/UART4/5/7/

8/OTG1_FS

CAN1/TIM1

2/13/14/QU

ADSPI/

FMC/

OTG2_HS

SAI2/QUAD

SPI/SDMM

C2/OTG2_

HS/OTG1_

SDMMC2

UART7/F

MC/SDM

MC1/

OTG2_FS

SYS

USART6_CK

USART6_RT

USART6_RX

QUADSPI_

BK2_IO2

SAI2_FS_B

SAI2_SD_B

FMC_A10

FMC_A11

FMC_A12

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

FMC_A13

FMC_A14/

FMC_BA0

FMC_A15/

FMC_BA1

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

SDMMC2

_D0

SDMMC2

_D1

FMC_INT

FMC_SDC

FMC_NE2

/FMC_NC

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

FMC_NE3

EVEN

TOUT

Port

PG11

AF0

SYS

PG12 -

Port G

PG13 TRACED0

PG14 TRACED1

PG15

PH0

PH1

PH2

Port H

PH3

PH4

PH5

PH6

PH7

AF1

Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued)

AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10

TIM1/2

AF11 AF12 AF15

TIM3/4/5

TIM8/9/10/1

1/LPTIM1

I2C1/2/3/U

SART1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5

SPI2/I2S2/

SPI3/I2S3/

SAI1/

UART4

SPI2/I2S2/S

PI3/I2S3/US

ART1/2/3/UA

RT5

SAI2/USART

6/UART4/5/7/

8/OTG1_FS

CAN1/TIM1

2/13/14/QU

ADSPI/

FMC/

OTG2_HS

SAI2/QUAD

SPI/SDMM

C2/OTG2_

HS/OTG1_

SDMMC2

UART7/F

MC/SDM

MC1/

OTG2_FS

SYS

LPTIM1_IN

LPTIM1_O

LPTIM1_ET

LPTIM1_IN

I2C2_SCL

I2C2_SDA SPI5_NSS

I2C2_SMB

SPI5_SCK

I2C3_SCL

SPI5_MIS

SDMMC2_

EVEN

TOUT

USART6_RT

USART6_CT

USART6_TX

USART6_CT

QUADSPI_

BK2_IO3

TIM12_CH1

QUADSPI_

BK2_IO0

SAI2_SCK_

QUADSPI_

BK2_IO1

SAI2_MCK

OTG_HS_U

LPI_NXT

SDMMC2

_D3

FMC_NE4

EVEN

TOUT

FMC_A24

EVEN

TOUT

FMC_A25

EVEN

TOUT

FMC_SDN

CAS

EVEN

TOUT

EVEN

TOUT

FMC_SDC

KE0

EVEN

TOUT

EVEN

TOUT

FMC_SDN

EVEN

TOUT

EVEN

TOUT

FMC_SDN

EVEN

TOUT

FMC_SDN

EVEN

TOUT

FMC_SDC

KE1

EVEN

TOUT

Port

PH8

PH9

PH10

PH11

Port H

PH12

PH13

PH14

PH15

PI0

PI1

PI2

Port I PI3

PI4

PI5

PI6

AF0

SYS

AF1

Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued)

AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10

TIM1/2

AF11 AF12 AF15

TIM3/4/5

TIM5_CH1

TIM5_CH2

TIM5_CH3

TIM5_CH4

TIM8/9/10/1

1/LPTIM1

I2C1/2/3/U

SART1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5

SPI2/I2S2/

SPI3/I2S3/

SAI1/

UART4

SPI2/I2S2/S

PI3/I2S3/US

ART1/2/3/UA

RT5

SAI2/USART

6/UART4/5/7/

8/OTG1_FS

CAN1/TIM1

2/13/14/QU

ADSPI/

FMC/

OTG2_HS

SAI2/QUAD

SPI/SDMM

C2/OTG2_

HS/OTG1_

SDMMC2

UART7/F

MC/SDM

MC1/

OTG2_FS

TIM8_CH1

TIM8_CH2

TIM8_CH3

TIM8_BKIN

TIM8_CH4

TIM8_ETR

I2C3_SDA

I2C3_SMB

SPI2_NSS

/I2S2_WS

SPI2_SCK

/I2S2_CK

SPI2_MIS

SPI2_MO

SI/I2S2_S

UART4_TX

UART4_RX

TIM12_CH2

CAN1_TX

CAN1_RX

FMC_D16

FMC_D17

FMC_D18

FMC_D19

FMC_D20

FMC_D21

FMC_D22

FMC_D23

FMC_D24

FMC_D25

FMC_D26

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

FMC_D27

SYS

EVEN

TOUT

TIM8_BKIN

TIM8_CH1

TIM8_CH2 -

SAI2_MCK

SAI2_SCK_

SAI2_SD_A -

FMC_NBL

EVEN

TOUT

FMC_NBL

EVEN

TOUT

FMC_D28

EVEN

TOUT

Port

PI7

PI8

PI9

PI10

Port I PI11

PI12

PI13

PI14

PI15

AF0

SYS

AF1

Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued)

AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10

TIM1/2

AF11 AF12 AF15

TIM3/4/5

TIM8/9/10/1

1/LPTIM1

I2C1/2/3/U

SART1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5

SPI2/I2S2/

SPI3/I2S3/

SAI1/

UART4

SPI2/I2S2/S

PI3/I2S3/US

ART1/2/3/UA

RT5

SAI2/USART

6/UART4/5/7/

8/OTG1_FS

CAN1/TIM1

2/13/14/QU

ADSPI/

FMC/

OTG2_HS

SAI2/QUAD

SPI/SDMM

C2/OTG2_

HS/OTG1_

SDMMC2

UART7/F

MC/SDM

MC1/

OTG2_FS

TIM8_CH3

UART4_RX

CAN1_RX

SAI2_FS_A

OTG_HS_U

LPI_DIR

SYS

FMC_D29

FMC_D30

FMC_D31

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

STM32F732xx STM32F733xx Memory mapping

Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals.

DS11854 Rev 5 99/228

Electrical characteristics STM32F732xx STM32F733xx

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 σ ).

Unless otherwise specified, typical data are based on T

= 25 °C, V

1.7 V ≤ tested.

= 3.3 V (for the

≤ 3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 24

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 25 .

Figure 24. Pin loading conditions Figure 25. Pin input voltage

MCU pin

C = 50 pF VIN

MS19011V2

MS19010V2

100/228 DS11854 Rev 5

STM32F732xx STM32F733xx

6.1.6 Power supply scheme

Electrical characteristics

Figure 26. STM32F732xx power supply scheme

VBAT

VBAT =

1.65 to 3.6V

Power switch

Backup circuitry

(OSC32K,RTC,

Wakeup logic

Backup registers, backup RAM)

OUT

DDSDMMC

GP I/O s

DDSDMMC

Logic

100 nF

+ 1 μF

OUT

PG[9..12], PD[6,7]

Logic

12 × 100 nF

+ 1 × 4.7 μF

2 × 2.2 μF

CAP_1

CAP_2

1/2/...11/12

VSS

1/2/...11/12

Voltage regulator

Kernel logic

(CPU, digital

& RAM)

DDUSB

BYPASS_REG

DDUSB

100 nF

+ 1 μF

VDD

100 nF

+ 1 μF

100 nF

+ 1 μF

VREF

PDR_ON

VDDA

VREF+

VREF-

VSSA

OTG FS

PHY

Reset controller

ADC

Analog:

RCs, PLL,

...

Flash memory

MSv42076V2

1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF.

2. The 4.7 µF ceramic capacitor must be connected to one of the V

pin.

3. V

DDA

and V

SSA

DS11854 Rev 5 101/228

200

Electrical characteristics STM32F732xx STM32F733xx

Figure 27. STM32F733xx power supply scheme

VBAT

VBAT =

1.65 to 3.6V

Power switch

Backup circuitry

(OSC32K,RTC,

Wakeup logic

Backup registers, backup RAM)

100 nF

+ 1 μF

DDSDMMC

GP I/O s

DDSDMMC

PG[9..12], PD[6,7]

OUT

Logic

OUT

Logic

102/228

100 nF

+ 1 μF

DDUSB

PA[11,12], PB[14,15]

DDUSB

OUT

Logic

12 × 100 nF

+ 1 × 4.7 μF

2 × 2.2 μF

CAP_1

CAP_2

1/2/...11/12

BYPASS_REG

OTG FS

PHY

Voltage regulator

Kernel logic

(CPU, digital

& RAM)

Flash memory

OTG HS PHY

voltage regulator

VDD

100 nF

+ 1 μF

2.2 μF

100 nF

+ 1 μF

VREF

DD12OTGHS

OTG_HS_REXT

3 Kohm +/-1%

PDR_ON

VDDA

VREF+

VREF-

VSSA

OTG HS PHY

Reset controller

ADC

Analog:

RCs, PLL,

...

MSv42069V1

1. In all the packages (except LQFP100), the V

DDUSB

allows supplying the PHY FS in PA11/PA12 and the

PHY HS on PB14/PB15. In the LQFP100, the PHY HS on PB14/PB15 is supplied by V

DDPHYHS

DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF.

3. The 4.7 µF ceramic capacitor must be connected to one of the V

pin.

4. V

DDA

and V

SSA

Caution: Each power supply pair (V

, V

DDA

SSA

...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.

This might cause incorrect operation of the device.

Figure 28. Current consumption measurement scheme

IDD_VBAT

VBAT

6.2

IDD

VDD

VDDA ai14126

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 13: Voltage characteristics

Table 14: Current characteristics

, and

Table 15: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are available on demand.

Symbol

–V

Table 13. Voltage characteristics

Ratings

External main supply voltage (including V

BAT

, V

DDUSB

, V

DDPHYHS and V

DDSDMMC

)

Input voltage on FT pins

(2)

Input voltage on TTa pins

Input voltage on any other pin

Input voltage on BOOT pin

, V

DD,

Min Max

− 0.3

4.0

− 0.3 V

+4.0

− 0.3

4.0

9.0

Unit

DS11854 Rev 5 103/228

200

Electrical characteristics STM32F732xx STM32F733xx

Symbol

Table 13. Voltage characteristics (continued)

Ratings Min Max Unit

| Δ V

SSX

DDx

− V

ESD(HBM)

Variations between different V

power pins

| Variations between all the different ground pins (3)

Electrostatic discharge voltage (human body model)

see Section 6.3.18:

Absolute maximum ratings (electrical sensitivity)

1. All main power (V

, V

DDA

, V

DDSDMMC

, V

DDPHYHS

, V

DDUSB

) and ground (V

, V

SSA

) pins must always be

2. V

maximum value must always be respected. Refer to Table 14 for the values of the maximum allowed

injected current.

3. Include VREF- pin.

Symbol

Table 14. Current characteristics

Ratings Max.

Unit

Σ I

VDD

VSS

VDDUSB

VDDSDMMC

VDD

VDDSDMMC

VSS

Total current into sum of all V

DD_x power lines (source)

(1)

Total current out of sum of all V

SS_x ground lines (sink)

(1)

Total current into V

DDUSB

power line (source)

Total current into V

DDSDMMC

power line (source)

Maximum current into each V

DD_x power line (source) (1)

Maximum current into V

DDSDMMC power line (source): PG[12:9], PD[7:6]

Maximum current out of each V

SS_x ground line (sink)

(1)

Output current sunk by any I/O and control pin

Output current sourced by any I/Os and control pin

Total output current sunk by sum of all I/O and control pins

(2)

−

300

100

−

100

25 mA

120

Σ I

Total output current sunk by sum of all USB I/Os

Total output current sourced by sum of all I/Os and control pins

(2)

Injected current on FT, FTf, RST and B pins

(3)

− 120

− 5/+0

INJ(PIN)

Σ I

INJ(PIN)

(4)

Injected current on TTa pins

(4)

Total injected current (sum of all I/O and control pins)

(5)

±5

±25

1. All main power (V permitted range.

, V

DDA

) and ground (V

, V

SSA

) pins must always be connected to the external power supply, in the

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.

3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

4. A positive injection is induced by V

DDA

while a negative injection is induced by V

. I

INJ(PIN)

must never be exceeded. Refer to

Table 13: Voltage characteristics

for the values of the maximum allowed input voltage.

5. When several inputs are submitted to a current injection, the maximum negative injected currents (instantaneous values).

Σ I

INJ(PIN)

is the absolute sum of the positive and

104/228 DS11854 Rev 5

STM32F732xx STM32F733xx

Symbol

STG

Electrical characteristics

Table 15. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

− 65 to +150

125

Unit

°C

6.3.1 General operating conditions

Symbol f

HCLK f

PCLK1 f

PCLK2

Table 16. General operating conditions

Parameter Conditions (1)

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Power Scale 3 (VOS[1:0] bits in

PWR_CR register = 0x01), Regulator

ON, over-drive OFF

Power Scale 2 (VOS[1:0] bits in PWR_CR register = 0x10),

Regulator ON

Overdrive

OFF

Overdrive

Power Scale 1 (VOS[1:0] bits in PWR_CR register= 0x11),

Regulator ON

Overdrive

OFF

Overdrive

Over-drive OFF

Over-drive ON

Over-drive OFF

Over-drive ON

Min Typ Max Unit

144

168

180

216 (2)

108

MH z

DS11854 Rev 5 105/228

200

Electrical characteristics STM32F732xx STM32F733xx

Symbol

Table 16. General operating conditions (continued)

Parameter Conditions (1) Min Typ Max Unit

DDA

(4)(5)

DDUSB

Standard operating voltage

Analog operating voltage

(ADC limited to 1.2 M samples)

Must be the same potential as V

(6)

Analog operating voltage

(ADC limited to 2.4 M samples)

USB supply voltage (supply voltage for PA11,PA12, PB14 and

PB15 pins)

USB not used

USB used

1.7

(3)

1.7

(3)

2.4

1.7

3.0

3.3

DDSPHYHS

USB PHY HS supply voltage in the STM32F723 LQFP100 (supply voltage for PB14 and PB15)

USB PHY HS not used

USB PHY HS used

BAT

Backup operating voltage -

DDSDMMC

SDMMC2 supply voltage (supply voltage for PG[12:9] and PD6 pins)

It can be different from V

Power Scale 3 ((VOS[1:0] bits in

PWR_CR register = 0x01), 144 MHz

HCLK max frequency

1.7

3.3

3.0

1.65

1.7

1.08 1.14

3.6

2.4

3.6

1.20

Regulator ON: 1.2 V internal voltage on V

CAP_1

CAP_2 pins

Regulator OFF: 1.2 V external voltage must be supplied from external regulator on

CAP_1

CAP_2 pins

(7)

Input voltage on RST and FT pins

(8)

Input voltage on TTa pins

Input voltage on BOOT pin

Power Scale 2 ((VOS[1:0] bits in

PWR_CR register = 0x10), 168 MHz

HCLK max frequency with over-drive

OFF or 180 MHz with over-drive ON

Power Scale 1 ((VOS[1:0] bits in

PWR_CR register = 0x11), 180 MHz

HCLK max frequency with over-drive

OFF or 216 MHz with over-drive ON

Max frequency 144 MHz

Max frequency 168MHz

Max frequency 180 MHz

2 V ≤ V

≤ 3.6 V

≤ 2 V

1.20 1.26

1.26 1.32

1.32

1.40

1.10 1.14

1.20

1.20 1.26

1.32

1.26 1.32

1.38

− 0.3

5.5

5.2

− 0.3

0 -

DDA

0.3

106/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Symbol

Table 16. General operating conditions (continued)

Parameter Conditions (1) Min Typ Max Unit

LQFP64

LQFP100

Power dissipation at T

A suffix 6 or T

(9)

= 85 °C for

= 105 °C for suffix

WLCSP100

LQFP144

LQFP176

UFBGA144

881

1117

558

1587 mW

1869

476

Ambient temperature for 6 suffix version

Ambient temperature for 7 suffix version

Junction temperature range

UFBGA176

Maximum power dissipation

Low power dissipation

(10)

Maximum power dissipation

Low power dissipation

(10)

6 suffix version

7 suffix version

− 40 -

485

105

125

105

125

1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.

2. 216 MHz maximum frequency for 6 suffix version (200 MHz maximum frequency for 7 suffix version).

3. V

DDA

minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:

Internal reset OFF ).

4. When the ADC is used, refer to

Table 67: ADC characteristics

5. If V

REF+

pin is present, it must respect the following condition: V

DDA

-V

REF+

< 1.2 V.

6. It is recommended to power V and V from the same source. A maximum difference of 300 mV between V can be tolerated during power-up and power-down operation.

DD and V

DDA

7. The over-drive mode is not supported when the internal regulator is OFF.

8. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled

9. If T

is lower, higher P

values are allowed as long as T

does not exceed T

Jmax

10. In low power dissipation state, T

can be extended to this range as long as T

does not exceed T

Jmax

°C

=1.7 to

2.1 V

(3)

= 2.1 to

2.4 V

Table 17. Limitations depending on the operating power supply range

Operating power supply range

ADC operation

Conversion time up to 1.2 Msps

Maximum Flash memory access frequency with no wait states

Flashmax

)

Maximum HCLK frequency vs Flash memory wait states

(1)(2)

20 MHz

22 MHz

I/O operation

180 MHz with 8 wait states and over-drive

OFF

No I/O compensation

216 MHz with 9 wait states and over-drive

No I/O compensation

Possible Flash memory operations

8-bit erase and program operations only

16-bit erase and program operations

DS11854 Rev 5 107/228

200

Electrical characteristics STM32F732xx STM32F733xx

Table 17. Limitations depending on the operating power supply range (continued)

Operating power supply range

ADC operation

Maximum Flash memory access frequency with no wait states

Flashmax

)

Maximum HCLK frequency vs Flash memory wait states

(1)(2)

I/O operation

Possible Flash memory operations

= 2.4 to

2.7 V

= 2.7 to

3.6 V

(4)

Conversion time up to 2.4 Msps

24 MHz

30 MHz

216 MHz with 8 wait states and over-drive

I/O compensation works

216 MHz with 7 wait states and over-drive

I/O compensation works

16-bit erase and program operations

32-bit erase and program operations

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required.

2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator or L1-cache allows to achieve a performance equivalent to 0-wait state program execution.

3. V

DDA

minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to

Section 3.15.2:

Internal reset OFF

4. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+ pins will be degraded between 2.7 and 3 V.

6.3.2

Note:

VCAP1/VCAP2 external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor C the VCAP1/VCAP2 pins. C

EXT

is specified in

Table 18 .

EXT

The VCAP2 pin is not available on the LQFP64 package.

Figure 29. External capacitor C

EXT

ESR

Leak

MS19044V2

1. Legend: ESR is the equivalent series resistance.

Symbol

Table 18. VCAP1/VCAP2 operating conditions (1)

Parameter Conditions

CEXT Capacitance of external capacitor 2.2 µF

ESR ESR of external capacitor < 2 Ω

1. When bypassing the voltage regulator, the two 2.2 µF V replaced by two 100 nF decoupling capacitors.

CAP

capacitors are not required and should be

108/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Symbol

Table 19. VCAP1 operating conditions in the LQFP64 package (1)

Parameter Conditions

CEXT Capacitance of external capacitor 4.7 µF

ESR ESR of external capacitor between 0.1

Ω and 0.2

1. When bypassing the voltage regulator, the 4.7 µF V by two 100 nF decoupling capacitors.

CAP

capacitor is not required and should be replaced

Subject to general operating conditions for T

Table 20. Operating conditions at power-up / power-down (regulator ON)

Symbol Parameter Min Max Unit t

VDD

rise time rate

fall time rate

∞

µs/V

6.3.5

Subject to general operating conditions for T

Table 21. Operating conditions at power-up / power-down (regulator OFF) (1)

Symbol Parameter Conditions Min Max Unit t t

VDD

VCAP

rise time rate

fall time rate

Power-up

Power-down

CAP_1

and V

CAP_2 rise time rate Power-up

CAP_1

and V

CAP_2

fall time rate Power-down

∞

1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V

1.08 V.

reach below

µs/V

Reset and power control block characteristics

The parameters given in

Table 22 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

The over-drive switching characteristics are given in Table 23

DS11854 Rev 5 109/228

200

Electrical characteristics STM32F732xx STM32F733xx

Symbol

Table 22. reset and power control block characteristics

Parameter Conditions

PVD

PVDhyst

(1)

POR/PDR

PDRhyst

(1)

BOR1

BOR2

BOR3

Programmable voltage detector level selection

PVD hysteresis

Power-on/power-down reset threshold

PDR hysteresis

Brownout level 1 threshold

Brownout level 2 threshold

Brownout level 3 threshold

BORhyst

(1)

BOR hysteresis

POR reset temporization

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

PLS[2:0]=111 (falling edge)

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Min Typ

0.5

1.5

Max Unit

2.09

2.14

2.19

1.98

2.04

2.08

2.23

2.30

2.37

2.13

2.19

2.25

2.39

2.45

2.51

2.29

2.35

2.39

2.54

2.60

2.65

2.44

2.51

2.56

2.70

2.76

2.82

2.59

2.66

2.71

2.86

2.93

2.99

2.65

2.84

2.92

2.96

3.03

3.10

2.85

2.93

2.99

3.07

3.14

3.21

2.95

3.03

3.09

100 -

1.60

1.68

1.76

1.64

1.72

1.80

40 -

2.13

2.19

2.24

2.23

2.29

2.33

2.44

2.50

2.56

2.53

2.59

2.63

2.75

2.83

2.88

2.85

2.92

2.97

100 -

3.0

V mV

RUSH

(1)

RUSH

(1)

InRush current on voltage regulator poweron (POR or wakeup from Standby)

InRush energy on voltage regulator poweron (POR or wakeup from Standby)

= 1.7 V, T

= 105 °C,

RUSH

= 171 mA for 31 µs

160 250 mA

5.4

µC

110/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

1. Guaranteed by design.

2. The reset temporization is measured from the power-on (POR reset or wakeup from V when first instruction is read by the user application code.

BAT

) to the instant

6.3.7

When the over-drive mode switches from enabled to disabled or disabled to enabled, the system clock is stalled during the internal voltage set-up.

. They are sbject to general operating conditions for T

Symbol

Table 23. Over-drive switching characteristics

(1)

Parameter Conditions

Tod_swen

Tod_swdis

HSI

Over_drive switch enable time

HSE max for 4 MHz and min for 26 MHz

External HSE

50 MHz

HSI

Over_drive switch disable time

HSE max for 4 MHz and min for 26 MHz.

External HSE

50 MHz

1. Guaranteed by design.

Min

Typ

Max

100

Unit

µs

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 28: Current consumption measurement scheme

All the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.

DS11854 Rev 5 111/228

200

Electrical characteristics STM32F732xx STM32F733xx

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

or V

(no load).

• All peripherals are disabled except if it is explicitly mentioned.

• The Flash memory access time is adjusted both to f

HCLK

frequency and V

(see Table 17: Limitations depending on the operating power supply range ).

range

• When the regulator is ON, the voltage scaling and over-drive mode are adjusted to f

HCLK

frequency as follows:

– Scale 3 for f

HCLK

≤ 144 MHz

– Scale 2 for 144 MHz < f

HCLK

≤ 168 MHz

– Scale 1 for 168 MHz < f

HCLK

≤ 216 MHz. The over-drive is only ON at 216 MHz.

• When the regulator is OFF, the V12 is provided externally as described in

Table 16:

General operating conditions :

• The system clock is HCLK, f

PCLK1

= f

HCLK

/4, and f

PCLK2

= f

HCLK

/2.

• External clock frequency is 25 MHz and PLL is ON when f

HCLK

is higher than 25 MHz.

• The typical current consumption values are obtained for 1.7 V ≤ V

≤ 3.6 V voltage range and for T

= 25 °C unless otherwise specified.

• The maximum values are obtained for 1.7 V ≤ V ≤ 3.6 V voltage range and a

• maximum ambient temperature (T

) unless otherwise specified.

For the voltage range 1.7 V ≤ V

≤ 3.6 V, the maximum frequency is 180 MHz.

Table 24. Typical and maximum current consumption in Run mode, code with data processing

running from ITCM RAM, regulator ON

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) Typ Unit

= 25 °C T

= 85 °C T

= 105 °C

216 156 170

(4)

180

200

200 144

All peripherals enabled

(2)(3)

180

168

127

113

154

134

119

164.6

143

127.4

183

158

141

144 86 96 112.6

126

Supply current in RUN mode

All peripherals disabled

(3)

216

200

180

168

144

110

102

90 (4)

52.8

33.5

119.6

113.1

96.7

86.5

77.1

38.5

26.3

138.5

132

125 (4)

100.1

90.8

50.3

38.1

1. Guaranteed by characterization results.

112/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part.

4. Guaranteed by test in production.

Table 25. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator ON

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) Typ Unit

= 25 °C T

= 85 °C T

= 105 °C

All peripherals enabled

(2)(3)

216

200

180

168

144

155.3

144.7

127.3

113.1

86.9

41.2

21.7

164

153.6

135

119.1

91.6

43.6

175.8

165.2

143.5

127.8

99.5

53.1

33.6

185

176

154

138

110

43.8

Supply current in RUN mode

All peripherals disabled

(3) mA

216

200

180

168

144

106

86.6

120.4

113.8

97.3

68.2

130

124

107

13.6

38.8

26.4

36.8

1. Guaranteed by characterization results.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part.

DS11854 Rev 5 113/228

200

Electrical characteristics STM32F732xx STM32F733xx

Table 26. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) Typ Unit

TA= 25 °C TA=85 °C TA=105 °C

Supply current in RUN mode

All peripherals enabled

(2)(3)

All peripherals disabled

(3)

216

200

180

168

144

216

200

180

168

144

129.3

122

108

73.3

137.6

128

117

104.5

84.7

23.4

82.3

63.6

53.3

162.8

153.2

136.4

122.3

99.3

59.5

37.8

107.4

101.8

90.2

81.4

67.9

45.1

30.6

1. Guaranteed by characterization results.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part.

119

113.5

101

92.1

41.2

173

163.3

146

132

109.2

114/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Table 27. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory on ITCM interface (ART disabled), regulator ON

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) Typ Unit

TA= 25 °C TA=85 °C TA=105 °C

Supply current in

RUN mode

All peripherals enabled

(2)(3)

All peripherals disabled

(3)

216

200

180

168

144

216

200

180

168

144

138

133

110

151

141

131

117

174.7

164.3

149.2

134

111.7

38.3

119.5

113.1

103.1

93.2

80.4

49.7

31.1

1. Guaranteed by characterization results.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part.

131

124

114

104

184

174

159

144

121

DS11854 Rev 5 115/228

200

Electrical characteristics STM32F732xx STM32F733xx

Table 28. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator OFF

Max

(1)

Typ

Symbol Parameter Conditions f

HCLK

(MHz)

TA= 25 °C TA= 85 °C TA= 105 °C

Unit

IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD

IDD12/

IDD

Supply current in RUN mode from

V12 and

VDD supply

All Peripherals

Enabled

(2)(3)

All Peripherals Disabled

(3)

180

168

144

180

168

144

112

110

1.4

120

1.4

106.4

1.3

82.5

1.1

1.4

1.3

1.1

1.2

37.6

18.5

132.7

118.7

93.6

49.3

30.4

89.3

80.1

63.5

35.2

23.2

142

130

103

35 mA

1. Guaranteed by characterization results.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part.

116/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Table 29. Typical and maximum current consumption in Sleep mode, regulator ON

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) Typ

TA= 25 °C TA=85 °C TA=105 °C

Unit

Supply current in

SLEEP mode

All peripherals enabled

(2)

All peripherals disabled

216

200

180

168

144

216

200

180

168

144

96 (3) 109.3

(3) 128.3

84 103.4

122.6

88.3

(3) 120 (3)

64 78.9

92.7

61.8

37.2

73.6

16 27 38.8

42.9

62.2

26 41.9

61.2

33.2

Table 61: I/O static characteristics

30.1

24.6

20.5

18.8

43.9

36.3

32.3

30.6

1. Guaranteed by characterization results.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.

3. Guaranteed by test in production.

Table 30. Typical and maximum current consumption in Sleep mode, regulator OFF

Max

(1)

Typ

Symbol Parameter Conditions f

HCLK

(MHz)

TA= 25 °C TA= 85 °C TA= 105 °C

IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD

IDD12/

IDD

Supply current in RUN mode from

V12 and V supply

All Peripherals

Enabled

(2)

All Peripherals Disabled

180

168

144

180

168

144

1.3

1.2

1.3

67.5

1.3

59.8

1.3

46.3

84.4

75.4

59.6

35.8

25.8

31.4

28.4

23.2

19.3

17.6

Unit mA

DS11854 Rev 5 117/228

200

Electrical characteristics STM32F732xx STM32F733xx

1. Guaranteed by characterization results.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.

Symbol

Table 31. Typical and maximum current consumptions in Stop mode

Max

(1)

Typ

Parameter Conditions

= 3.6 V

25 °C

85 °C

105 °C

Unit

DD_STOP_NM

(normal mode)

Supply current in Stop mode, main regulator in

Run mode

Flash memory in Stop mode, all oscillators OFF, no IWDG

Flash memory in Deep power down mode, all oscillators OFF

Supply current in Stop mode, main regulator in

Low-power mode

Flash memory in Stop mode, all oscillators OFF, no IWDG

Flash memory in Deep power down mode, all oscillators OFF, no

IWDG

DD_STOP_UDM

(under-drive mode)

Supply current in Stop mode, main regulator in

Low voltage and underdrive modes

Regulator in Run mode, Flash memory in Deep power down mode, all oscillators OFF, no

IWDG

Regulator in Low-power mode,

Flash memory in Deep power down mode, all oscillators OFF, no

IWDG

1. Data based on characterization, tested in production.

0.45

0.4

0.32

0.27

0.15

0.1

1.5

0.8

0.7

7 mA

118/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Table 32. Typical and maximum current consumptions in Standby mode

Typ

(1)

Max

(2)

Symbol Parameter Conditions

= 25 °C

25 °C

85 °C

105 °C

1.7 V

2.4 V

3.3 V

= 3.3 V

Backup SRAM OFF, RTC and

LSE OFF

Backup SRAM ON, RTC and

LSE OFF

Backup SRAM OFF, RTC ON and LSE in low drive mode

Backup SRAM OFF, RTC ON and LSE in medium low drive mode

DD_STBY

Supply current in Standby mode

Backup SRAM OFF, RTC ON and LSE in medium high drive mode

Backup SRAM OFF, RTC ON and LSE in high drive mode

Backup SRAM ON, RTC ON and LSE in low drive mode

Backup SRAM ON, RTC ON and LSE in Medium low drive mode

Backup SRAM ON, RTC ON and LSE in Medium high drive mode

Backup SRAM ON, RTC ON and LSE in High drive mode

1.09

1.85

1.65

1.67

1.8

1.92

2.39

2.41

2.67

2.68

1.13

1.88

1.86

1.88

2.01

2.13

2.6

2.64

2.89

2.9

1.4

2.17

2.43

2.46

2.61

2.73

3.23

3.25

2.53

3.51

7.5

47.5

50.5

95.5

102.5

107

127

128

139

138

1. PDR is OFF for V additional 1.2 µA.

=1.7V. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by

2. Guaranteed by characterization results.

Unit

µA

DS11854 Rev 5 119/228

200

Electrical characteristics STM32F732xx STM32F733xx

Table 33. Typical and maximum current consumptions in V

BAT

mode

Typ Max

(2)

Symbol Parameter Conditions

(1)

=25 °C

BAT

1.7 V

BAT

2.4 V

BAT

3.3 V

=85 °C T

=105 °C

Unit

BAT

= 3.6 V

Backup SRAM OFF, RTC and

LSE OFF

Backup SRAM ON, RTC and

LSE OFF

Backup SRAM OFF, RTC ON and LSE in low drive mode

Backup SRAM OFF, RTC ON and LSE in medium low drive mode

DD_VBAT

Supply current in V

BAT

mode

Backup SRAM OFF, RTC ON and LSE in medium high drive mode

Backup SRAM OFF, RTC ON and LSE in high drive mode

Backup SRAM ON, RTC ON and

LSE in low drive mode

Backup SRAM ON, RTC ON and

LSE in Medium low drive mode

Backup SRAM ON, RTC ON and

LSE in Medium high drive mode

Backup SRAM ON, RTC ON and

LSE in High drive mode

0.035

0.037

0.043

0.69

0.57

0.59

0.69

0.8

1.22

1.25

1.46

0.71

0.74

0.76

0.86

0.98

1.41

1.43

1.65

0.73

1.05

1.08

1.19

1.31

1.74

1.78

2.01

1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a C

of 6 pF for typical values.

2. Guaranteed by characterization results.

101

111

122

162

166

187

244

251

277

305

405

414

468

µA

120/228 DS11854 Rev 5

4.5

3.5

2.5

1.5

0.5

STM32F732xx STM32F733xx Electrical characteristics

Figure 30. Typical V

BAT

current consumption (RTC ON/BKP SRAM OFF and

LSE in low drive mode)

2.5

1.5

3.5

0.5

0 20 40 60

Temperature °C

80 100

Figure 31. Typical V

BAT

current consumption (RTC ON/BKP SRAM OFF and

LSE in medium low drive mode)

120

MS37585V1

1.65 V

1.7 V

1.8 V

2 V

2.4 V

2.7 V

3 V

3.3 V

3.6 V

20 40 100 60

Temperature °C

1.65 V

1.7 V

1.8 V

2 V

2.4 V

2.7 V

3 V

3.3 V

3.6 V

120

MS37586V1

DS11854 Rev 5 121/228

200

Electrical characteristics STM32F732xx STM32F733xx

4.5

3.5

2.5

1.5

0.5

4.5

3.5

2.5

1.5

0.5

Figure 32. Typical V

BAT

current consumption (RTC ON/BKP SRAM OFF and

LSE in medium high drive mode)

20 40 60

Temperature °C

80 100 120

1.65 V

1.7 V

1.8 V

2 V

2.4 V

2.7 V

3 V

3.3 V

3.6 V

MS37587V1

Figure 33. Typical V

BAT

current consumption (RTC ON/BKP SRAM OFF and

LSE in high drive mode)

20 40 60

Temperature °C

80 100 120

1.65 V

1.7 V

1.8 V

2 V

2.4 V

2.7 V

3 V

3.3 V

3.6 V

MS37588V1

122/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Figure 34. Typical V

BAT

current consumption (RTC ON/BKP SRAM OFF and

LSE in high medium drive mode)

1.65 V

1.7 V

1.8 V

2 V

2.4 V

2.7 V

3 V

3.3 V

3.6 V

20 40 60

Temperature( °C)

80 100 120

MS37589V1

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 35: Peripheral current consumption ), the I/Os used by an application also contribute to the current consumption.

When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O

DS11854 Rev 5 123/228

200

Electrical characteristics STM32F732xx STM32F733xx pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

=

×

Symbol

DDIO

Where

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

Table 34. Switching output I/O current consumption (1)

Parameter Conditions

I/O toggling

frequency (fsw)

MHz

Typ

= 3.3 V

I/O switching

Current

EXT

= 0 pF

C = C

INT

+ C

S +

EXT

= 10 pF

C = C

INT

+ C

S +

EXT

100

108

100

108

2 0.1

8 0.4

25 1.1

50 2.4

60 3.1

4.3

4.9

10.12

14.92

18.11

1.8

3.1

4.6

9.7

5.4

5.6

0.2

0.6

Typ

= 1.8 V

Unit mA

1.1

2.3

3.4

3.6

2.8

0.1

0.3

5.2

5.4

1.3

1.6

2.4

2.6

0.1

0.2

0.7

124/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Symbol

Table 34. Switching output I/O current consumption (1) (continued)

Parameter Conditions

I/O toggling

frequency (fsw)

MHz

Typ

= 3.3 V

Typ

= 1.8 V

DDIO

I/O switching

Current

C = C

EXT

INT

EXT

INT

= 22 pF

+ C

S +

EXT

= 33 pF

+ C

S +

EXT

1. CINT + C

PCB board capacitance including the pad pin is estimated to15 pF.

0.3

1.3

3.5

10.26

16.53

0.3

1.0

3.5

5.9

10.0

19.12

19.6

0.2

0.7

2.3

5.19

4.2

4.4

5.8

0.1

0.5

1.6

Unit mA

On-chip peripheral current consumption

The MCU is placed under the following conditions:

• At startup, all I/O pins are in analog input configuration.

• All peripherals are disabled unless otherwise mentioned.

• I/O compensation cell enabled.

• The ART/L1-cache is ON.

• Scale 1 mode selected, internal digital voltage V12 = 1.32 V.

• HCLK is the system clock. f

PCLK1

= f

HCLK

/4, and f

PCLK2

= f

HCLK

/2.

The given value is calculated by measuring the difference of current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

– f

HCLK f

HCLK

= 216 MHz (Scale 1 + over-drive ON), f

= 144 MHz (Scale 3)

HCLK

• Ambient operating temperature is 25 °C and V

=3.3 V.

= 168 MHz (Scale 2),

DS11854 Rev 5 125/228

200

Electrical characteristics STM32F732xx STM32F733xx

AHB1

(up to

216 MHz)

AHB2

(up to

216 MHz)

Peripheral

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOF

GPIOG

GPIOH

GPIOI

CRC

BKPSRAM

DMA1

DMA2

OTG_HS+ULPI

RNG

USB_OTG_FS

AES

Table 35. Peripheral current consumption

(Typ)

(1)

Scale 1 Scale 2 Scale 3

3.7

3.6

3.5

3.6

3.7

3.6

3.4

3.3

3.4

3.6

3.4

3.0

2.9

2.8

2.9

3.1

3.0

3.5

1.2

0.8

3.4

3.3

1.1

0.7

2.9

0.9

0.6

3.07 x N + 8.7

2.98 x N + 8.4

2.52 x N + 7.02

3.01 x N + 7.98

2.95 x N + 7.95

2.48 x N + 6.69

54.4

53.2

44.6

1.9

28.7

1.8

27.9

1.6

23.5

FMC

16.2

15.8

13.3

AHB3

(up to

216 MHz)

QSPI

16.9

16.3

13.8

Bus matrix

(2)

15.8

12.8

8.5

Unit

µA/MHz

126/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

APB1

(up to

54 MHz)

Table 35. Peripheral current consumption (continued)

(Typ) (1)

Peripheral

Scale 1 Scale 2 Scale 3

6.1

6.3

9.4

2.4

6.7

4.8

13.3

12.8

19.3

15.7

3.7

3.5

8.1

11.7

10.6

10.7

8.9

11.3

6.1

13.3

12.6

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

TIM12

TIM13

TIM14

LPTIM1

WWDG

SPI2/I2S2

(3)

SPI3/I2S3

(3)

USART2

USART3

UART4

UART5

I2C1

I2C2

I2C3

CAN1

PWR

DAC (4)

UART7

UART8

5.1

5.6

9.8

1.3

3.8

18.2

15.1

16.9

3.1

2.9

7.8

10.7

10.2

9.6

9.8

11.3

5.1

11.6

4.7

8.3

1.4

5.3

3.3

10.6

10.3

15.6

12.2

12.8

14.4

2.8

2.5

6.4

8.3

6.9

8.9

4.4

9.2

8.9

8.3

10.3

9.7

Unit

µA/MHz

DS11854 Rev 5 127/228

200

Electrical characteristics STM32F732xx STM32F733xx

Table 35. Peripheral current consumption (continued)

(Typ) (1)

Peripheral

Scale 1 Scale 2 Scale 3

Unit

APB2

(up to

108 MHz)

TIM1

TIM8

USART1

USART6

ADC1 (5)

ADC2

(5)

ADC3

(5)

SDMMC1

SDMMC2

SPI1/I2S1

(3)

SPI4

SYSCFG

TIM9

TIM10

TIM11

SPI5

SAI1

SAI2

USB PHY HS

Controller

24.9

24.5

12.4

12.3

6.3

6.4

9.1

3.2

2.9

9.9

7.2

4.8

5.6

5.4

8.3

23.8

23.7

11.6

11.7

5.8

5.6

5.8

8.3

7.2

3.2

2.9

9.1

6.4

6.8

4.1

4.9

4.7

7.9

6.7

µA/MHz

1. When the I/O compensation cell is ON, I

typical value increases by 0.22 mA.

2. The BusMatrix is automatically active when at least one master is ON.

3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.

4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of

0.75 mA per DAC channel for the analog part.

5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of

1.73 mA per ADC for the analog part.

7.1

2.6

2.2

0.7

7.8

5.6

5.7

3.6

4.2

4.9

128/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

USB OTG HS and USB OTG HS PHY current consumption (on STM32F733xx devices)

The MCU is placed under the following conditions:

• STM32 MCU is enumerated as a HID device.

• f

HCLK f

HCLK

= 216 MHz (Scale 1 + over-drive ON), f

= 144 MHz (Scale 3)

HCLK

= 168 MHz (Scale 2),

The given value is calculated by measuring the difference of current consumption in case:

– USB is configured but no transfer is done.

– USB is configured and there is a transmission on going.

• Ambient operating temperature is 25 °C, V

= V

DDUSB

= 3.3 V.

Table 36. USB OTG HS and USB OTG PHY HS current consumption

(Typ)

Scale 1 Scale 2 Scale 3

USB OTG HS and USB OTG HS PHY current consumption

50.16

44.92

38.98

Unit mA

6.3.8

Symbol t

WUSLEEP

(2)

Wakeup time from low-power modes

The wakeup times given in Table 37

are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:

• For Stop or Sleep modes: the wakeup event is WFE.

• WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.

All timings are derived from tests performed under ambient temperature and V

=3.3 V.

Table 37. Low-power mode wakeup timings

Parameter Conditions Typ

(1)

Max

(1)

Wakeup from Sleep 13 13

Unit

CPU clock cycles

Main regulator is ON 14 14.9

WUSTOP

(2)

Wakeup from Stop mode with MR/LP regulator in normal mode

Main regulator is ON and Flash memory in Deep power down mode

Low power regulator is ON

104.1

21.4

107.6

24.2

µ s

Low power regulator is ON and Flash memory in Deep power down mode

111.5

116.5

DS11854 Rev 5 129/228

200

Electrical characteristics STM32F732xx STM32F733xx

Symbol

Table 37. Low-power mode wakeup timings (continued)

Parameter Conditions Typ

(1)

Max

(1) t

WUSTOP

(2) tWUSTDBY

(2)

Wakeup from Stop mode with MR/LP regulator in

Under-drive mode

Main regulator in under-drive mode

(Flash memory in Deep power-down mode)

Low power regulator in under-drive mode

(Flash memory in Deep power-down mode)

Wakeup from Standby mode

Exit Standby mode on rising edge

Exit Standby mode on falling edge

107.4

112.7

308

307

113.2

120

313

1. Guaranteed by characterization results.

2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first

Unit

µ s

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The

external clock signal has to respect the Table 61: I/O static characteristics . However, the

The characteristics given in

Table 38 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

external clock signal has to respect the Table 61: I/O static characteristics . However, the

Symbol

Table 38. High-speed external user clock characteristics

Parameter f

HSE_ext

External user clock source frequency

(1)

HSEH

HSEL t w(HSE) t w(HSE) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

(1)

OSC_IN input capacitance

Duty cycle

(1)

OSC_IN Input leakage current

1. Guaranteed by design.

Conditions

≤ V

Min

0.7V

Typ

Max Unit

0.3V

±1

MHz

V ns pF

µA

130/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The

The characteristics given in

Table 39 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

the requirements of the crystal or resonator (see Figure 37

Symbol

Table 39. Low-speed external user clock characteristics

Parameter f

LSE_ext

LSEH

User External clock source frequency

(1)

OSC32_IN input pin high level voltage

LSEL t w(LSE) t f(LSE) t r(LSE) t f(LSE)

C in(LSE)

DuCy

(LSE)

OSC32_IN input pin low level voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

(1)

OSC32_IN input capacitance

Duty cycle

(1)

OSC32_IN Input leakage current

1. Guaranteed by design.

Conditions

≤ V

Min

0.7V

450

Typ

32.768

Max

1000

0.3V

±1

Unit kHz

V ns pF

µA

Figure 35. High-speed external clock source AC timing diagram

VHSEH

90 %

VHSEL

10 % tr(HSE)

THSE tf(HSE) tW(HSE) tW(HSE) t

External clock source fHSE_ext

OSC_IN

STM32F ai17528

DS11854 Rev 5 131/228

200

Electrical characteristics STM32F732xx STM32F733xx

Figure 36. Low-speed external clock source AC timing diagram

VLSEH

VLSEL

90%

10 % tr(LSE)

TLSE tf(LSE) tW(LSE) tW(LSE) t

External clock source fLSE_ext

OSC32_IN

STM32F ai17529

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in

Table 40 . In

the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 40. HSE 4-26 MHz oscillator characteristics (1)

Parameter Conditions Min Typ Max Unit f

OSC_IN

Oscillator frequency

Feedback resistor

200

26 MHz

k Ω

HSE current consumption

ACC

HSE

(2)

HSE accuracy

G m

_crit_max Maximum critical crystal g m t

SU(HSE

(3)

Startup time

=3.3 V,

ESR= 30 Ω ,

=5 pF@25 MHz

=3.3 V,

ESR= 30 Ω ,

=10 pF@25 MHz

Startup

−

500

450

530

500

µA ppm mA/V

is stabilized 2 ms

1. Guaranteed by design.

2. This parameter depends on the crystal used in the application. The minimum and maximum values must be respected to comply with USB standard specifications.

3. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is based on characterization results. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

132/228 DS11854 Rev 5

STM32F732xx STM32F733xx

Note:

Electrical characteristics

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 37. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

CL1

OSC_IN fHSE

8 MHz resonator

Bias controlled gain

REXT(1)

OSC_OU T

STM32F

CL2 ai17530

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in

Table 41 . In

Symbol

Table 41. LSE oscillator characteristics (f

LSE

= 32.768 kHz)

(1)

Parameter Conditions Min Typ Max Unit

LSE current consumption

LSEDRV[1:0]=00

Low drive capability

LSEDRV[1:0]=10

Medium low drive capability

LSEDRV[1:0]=01

Medium high drive capability

LSEDRV[1:0]=11

High drive capability

250

300

370

480 -

DS11854 Rev 5 133/228

200

Electrical characteristics STM32F732xx STM32F733xx

Table 41. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

LSEDRV[1:0]=00

Low drive capability

LSEDRV[1:0]=10

Medium low drive capability

G m

_crit_max Maximum critical crystal g m

LSEDRV[1:0]=01

Medium high drive capability

0.48

0.75

1.7

µA/V

LSEDRV[1:0]=11

High drive capability

2.7

(2) start-up time V

is stabilized 2 -

1. Guaranteed by design.

2. Guaranteed by characterization results. t

is the start-up time measured from the moment it is enabled

(by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. s

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST Microelectronics website www.st.com

Figure 38. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

C L1 fLSE OSC32_ IN

R F

Bias controlled gain

OSC32_ OU T

STM32F

C L2

32.768 kHz resonator ai17531a

134/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

6.3.10 Internal clock source characteristics

The parameters given in

Table 42 and

Table 43

are derived from tests performed under ambient temperature and V

High-speed internal (HSI) RC oscillator

Symbol

Table 42. HSI oscillator characteristics (1)

Parameter Conditions f

HSI

ACC

HSI

Frequency -

HSI user trimming step

(2)

Accuracy of the HSI oscillator

HSI oscillator startup time

= –40 to 105 °C

(3)

= –10 to 85 °C

= 25 °C

(4)

t su(HSI)

DD(HSI)

HSI oscillator power consumption -

1. V

= 3.3 V, PLL OFF, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Factory calibrated, parts not soldered.

Min Typ Max Unit

− 8

− 4

− 1

2.2

4.5

MHz

µs

µA

Figure 39. ACC

HSI

versus temperature

-2

-4

-6

-8

-40 0 25

Min

Max

Typical

105 125

TA (°C)

MSv41055V1

1. Guaranteed by characterization results.

DS11854 Rev 5 135/228

200

Electrical characteristics STM32F732xx STM32F733xx

Low-speed internal (LSI) RC oscillator

Table 43. LSI oscillator characteristics

(1)

Symbol Parameter f

LSI

(2) t su(LSI)

(3)

DD(LSI)

(3)

Frequency

LSI oscillator startup time

LSI oscillator power consumption

1. V

= 3 V, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by characterization results.

3. Guaranteed by design.

Min

Typ

0.4

Figure 40. LSI deviation versus temperature

8.0%

Max

0.6

Unit kHz

µs

µA

6.0%

4.0%

2.0%

0.0%

-2.0%

-4.0%

-6.0%

-8.0%

-40°C 0°C 25°C 85°C 105°C 125°C

Min

Max

Typical

Temperature (°C)

MS37554V1

The parameters given in

Table 44 and

Table 45

are derived from tests performed under temperature and V

supply voltage conditions summarized in

interferences (see Table 57: EMI characteristics

Symbol f

PLL_IN f

PLL_OUT f

PLL48_OUT f

VCO_OUT

Table 44. Main PLL characteristics

Parameter

PLL input clock

(1)

PLL multiplier output clock

48 MHz PLL multiplier output clock

PLL VCO output

Conditions

Min

0.95

(2)

100

Typ

Max

2.10

216

432

Unit

MHz

136/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Symbol

Table 44. Main PLL characteristics (continued)

Parameter Conditions Min Typ Max Unit t

LOCK

Jitter

(3)

PLL lock time

Cycle-to-cycle jitter

Period Jitter

VCO freq = 100 MHz

VCO freq = 432 MHz

System clock

216 MHz

RMS peak to peak

Cycle to cycle at 50 MHz on 1000 samples

Cycle to cycle at 25 MHz on 1000 samples

100

150

200

300

µs ps

Main clock output (MCO) for

RMII Ethernet

Main clock output (MCO) for MII

Ethernet

40 -

DD(PLL)

(4)

DDA(PLL)

(4)

Bit Time CAN jitter

PLL power consumption on V

Cycle to cycle at 1 MHz on 1000 samples

VCO freq = 100 MHz

VCO freq = 432 MHz

PLL power consumption on V

DDA

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.30

0.55

330

0.40

0.75

0.40

0.85

mA mA

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S.

2. Guaranteed by design.

3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.

4. Guaranteed by characterization results.

Symbol f

PLLI2S_IN f

PLLI2SQ_OUT f

PLLI2SR_OUT f

VCO_OUT t

LOCK

Parameter

Table 45. PLLI2S characteristics

Conditions

PLLI2S input clock

(1)

PLLI2S multiplier output clock for

SAI

PLLI2S multiplier output clock for

I2S

PLLI2S VCO output

PLLI2S lock time

VCO freq = 100 MHz

VCO freq = 432 MHz

Min

0.95

(2)

100

Typ

Max

2.10

216

432

200

300

Unit

MHz

µs

DS11854 Rev 5 137/228

200

Electrical characteristics STM32F732xx STM32F733xx

Symbol

Table 45. PLLI2S characteristics (continued)

Parameter Conditions Min Typ

Jitter

(3)

Master I2S clock jitter

WS I2S clock jitter

Cycle to cycle at

12.288 MHz on

48KHz period,

N=432, R=5

Average frequency of

12.288 MHz

N = 432, R = 5 on 1000 samples

Cycle to cycle at 48 KHz on 1000 samples

RMS

peak to peak

DD(PLLI2S)

(4)

DDA(PLLI2S)

(4)

PLLI2S power consumption on

DDA

VCO freq = 100 MHz

VCO freq = 432 MHz

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.30

0.55

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Guaranteed by characterization results.

± 280

400

Max

Unit ps ps

0.40

0.75

0.40

0.85

ps ps mA mA

Symbol f

PLLSAI_IN f

PLLSAIP_OUT f

PLLSAIQ_OUT f

VCO_OUT t

LOCK

Jitter

(3)

Table 46. PLLISAI characteristics

Parameter

PLLSAI input clock

(1)

PLLSAI multiplier output clock for 48 MHz

PLLSAI multiplier output clock for SAI

PLLSAI VCO output

Conditions

PLLSAI lock time

Master SAI clock jitter

FS clock jitter

VCO freq = 100 MHz

VCO freq = 432 MHz

Cycle to cycle at

12.288 MHz on

48KHz period,

N=432, R=5

Average frequency of

12.288 MHz

N = 432, R = 5 on 1000 samples

Cycle to cycle at 48 KHz on 1000 samples

RMS

peak to peak

Min

0.95

(2)

100

Typ

± 280

400

Max

2.10

216

432

200

300

Unit

MHz

µs ps ps

ps ps

138/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Symbol

Table 46. PLLISAI characteristics (continued)

Parameter Conditions Min

DD(PLLSAI)

(4)

DDA(PLLSAI)

(4)

PLLSAI power consumption on

DDA

VCO freq = 100 MHz

VCO freq = 432 MHz

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.30

0.55

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Guaranteed by characterization results.

Typ

Max

0.40

0.75

0.40

0.85

Unit mA mA

6.3.12 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic

). It is available only on the main PLL.

Symbol f

Mod md

MODEPER * INCSTEP

1. Guaranteed by design.

Table 47. SSCG parameters constraint

Parameter Min

Modulation frequency

Peak modulation depth

0.25

Typ

Max

(1)

2 15 − 1

Unit

KHz

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

MODEPER = round f

PLL_IN

⁄ (

Mod

) ] f

PLL_IN and f

Mod must be expressed in Hz.

As an example:

If f

PLL_IN

= 1 MHz, and f

MOD

= 1 kHz, the modulation depth (MODEPER) is given by equation 1:

MODEPER = [

⁄ ( ×

) ] = 250

Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

INCSTEP = round [ ( ( 2

– 1 ) × md PLLN ) ⁄ ( 100 5 × MODEPER ) ] f

VCO_OUT must be expressed in MHz.

With a modulation depth (md) = ± 2 % (4 % peak to peak), and PLLN = 240 (in MHz):

INCSTEP = round [ ( ( 2

– 1 ) × 2 240 ) ⁄ ( 100 5 × 250 ) ] = 126md(quantitazed)%

DS11854 Rev 5 139/228

200

Electrical characteristics STM32F732xx STM32F733xx

An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and

INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized

% = ( × 100 × 5 ) ⁄ ( ( 2

– 1 ) × PLLN )

As a result: md quantized

% = ( × 100 × 5 ) ⁄ ( ( 2

– 1 ) × 240 ) = 2.002%(peak)

Figure 41

and

Figure 42 show the main PLL output clock waveforms in center spread and

down spread modes, where:

F0 is f

PLL_OUT

nominal.

T mode

is the modulation period.

md is the modulation depth.

Figure 41. PLL output clock waveforms in center spread mode

Frequency (PLL_OUT) md

F0 md

Time tmode 2xtmode

Figure 42. PLL output clock waveforms in down spread mode

Frequency (PLL_OUT) ai17291

2xmd tmode 2xtmode

Time ai17292b

140/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

6.3.13 USB OTG HS PHY PLLs characteristics (on STM32F733xx devices)

The parameters given in

Table 48 are derived from tests performed under temperature and

supply voltage conditions summarized in

Symbol

Table 48. USB OTG HS PLL1 characteristics

(1)

Parameter f

PLL1_IN f

PLL1_OUT f

VCO_OUT t

LOCK

DD(PLL1)

DDA(PLL1)

PLL1 input clock

PLL1 output clock

PLL1 VCO output

PLL1 lock time

PLL1 digital power consumption

PLL1 analog power consumption

1. Guaranteed by design.

2. Based on test during characterization.

Conditions

Min Typ Max Unit

12, 12.5, 16, 24, 25

600

720

1.8

2.75

MHz

µs mA

Symbol

Table 49. USB OTG HS PLL2 characteristics

(1)

Parameter f

PLL2_IN f

PLL2_OUT f

VCO_OUT t

LOCK

DD(PLL2)

DDA(PLL2)

PLL2 input clock

PLL2 output clock

PLL2 VCO output

PLL2 lock time

Table 50 are derived from tests performed under temperature and

PLL2 digital power consumption

PLL2 analog power consumption

1. Guaranteed by design.

2. Based on test during characterization.

Conditions

Min Typ Max Unit

480

2.1

1.5

MHz

µs mA

6.3.14 USB OTG HS PHY regulator characteristics (on STM32F733xx devices)

The parameters given in

supply voltage conditions summarized in

Symbol

Table 50. USB OTG HS PHY regulator characteristics (1)

Parameter

DD12OTGHS

CEXT

DDPHYHSREG

1.2 V internal voltage on V

DD12OTGHS

External capacitor on V

DD12OTGHS

Regulator power consumption

1. Based on test during characterization.

Conditions Min Typ Max Unit

1.18

1.2

1.24

1.1

2.2

3.3

µF

100 120 125 µA

DS11854 Rev 5 141/228

200

Electrical characteristics STM32F732xx STM32F733xx

6.3.15 USB HS PHY external resistor characteristics

(on STM32F733xx devices)

Table 51. USB HS PHY external resistor characteristics (on STM32F733xx devices)

Symbol Parameter Conditions Min Typ Max Unit

REXT

External calibration resistor connected

(to GND) from OTG_HS_REXT

Required if using

USB HS PHY

2.97

3.00

3.03

k Ω

142/228

Flash memory

The characteristics are given at TA = –40 to 105 °C unless otherwise specified.

The devices are shipped to customers with the Flash memory erased.

Symbol

Parameter

Table 52. Flash memory characteristics

Conditions Min

Supply current

Write / Erase 8-bit mode, V

= 1.7 V

Write / Erase 16-bit mode, V

= 2.1 V

Write / Erase 32-bit mode, V

= 3.3 V

Typ

6.7

9.2

12.6

Max Unit

Symbol

Table 53. Flash memory programming

Parameter Conditions t t prog

ERASE16KB

Word programming time

Sector (16 KB) erase time

Program/erase parallelism

(PSIZE) = x 8/16/32

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

Program/erase parallelism

(PSIZE) = x 8 t

ERASE128KB

Sector (128 KB) erase time

Program/erase parallelism

(PSIZE) = x 16 t

ERASE64KB

Sector (64 KB) erase time

Program/erase parallelism

(PSIZE) = x 32

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

Min

(1)

Typ Max

(1)

Unit

16 100

(2)

346

252

208

675

505

418

312

265

1953 2500

1252 1639

927 1322

1027 1298

840

682

µs ms ms ms

DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Symbol

Table 53. Flash memory programming (continued)

Parameter Conditions

V t

ME prog

Mass erase time

Programming voltage

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

32-bit program operation

16-bit program operation

8-bit program operation

1. Guaranteed by characterization results.

2. The maximum programming time is measured after 10 K erase operations.

Min (1)

2.7

2.1

1.7

Typ Max (1)

7718 9883

4869 6379

3503 5180

3.6

Unit ms

Symbol

Table 54. Flash memory programming with V

Parameter Conditions Min

(1)

Typ Max

(1)

16 100

(2) t prog t

ERASE16KB t

ERASE128KB t

ERASE64KB t

V prog

Double word programming

Sector (16 KB) erase time

Sector (128 KB) erase time

Sector (64 KB) erase time

Mass erase time

Programming voltage

0 to +40 °C

= 3.3 V

= 8.5 V

VPP

(3)

voltage range

Minimum current sunk on the V

Cumulative time during which V

PP is applied

1. Guaranteed by design.

2. The maximum programming time is measured after 10 K erase operations.

3. V

should only be connected during programming/erasing.

2.7

180

900

450

6.9

3.6

Unit

µs ms s

V mA hour

Symbol

END t

RET

Table 55. Flash memory endurance and data retention

Value

Parameter Conditions

(1)

Min

(2)

Endurance

Data retention

= –40 to +85 °C (6 suffix versions)

= –40 to +105 °C (7 suffix versions)

1 kcycle

(3)

at T

= 85 °C

1 kcycle

at T

= 105 °C

10 kcycles

The test results are given in Table 56

at T

= 55 °C

Unit kcycles

Years

DS11854 Rev 5 143/228

200

Electrical characteristics

1. Tj can not go above 125°C (current consumption limitation).

2. Guaranteed by characterization results.

3. Cycling performed over the whole temperature range.

STM32F732xx STM32F733xx

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A burst of fast transient voltage (positive and negative) is applied to V

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

. They are based on the EMS levels and classes defined in application note AN1709.

Table 56. EMS characteristics

Symbol Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

= 3.3 V, T

= +25 °C, f

HCLK

= 216 MHz, conforms to IEC 61000-4-2

= 3.3 V, T

=+25 °C, f

HCLK

= 216 MHz, conforms to IEC 61000-4-2

As a consequence, it is recommended to add a serial resistor (1 k Ώ ) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB).

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

144/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.

Table 57. EMI characteristics

Symbol Parameter

EMI

Conditions

Monitored frequency band

Peak level

0.1 MHz to 30 MHz

= 3.6 V, T

= 25 °C, conforming to

IEC61967-2 ART/L1-cache OFF, over-drive ON, all peripheral clocks enabled, clock dithering disabled.

30 MHz to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

EMI Level

Max vs.

HSE

CPU

]

Unit

25/200 MHz

4 dBµV

6.3.18 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/ESDA/JEDEC JS-001-2012 and ANSI/ESD S5.3.1-2009 standards.

DS11854 Rev 5 145/228

200

Electrical characteristics STM32F732xx STM32F733xx

Ratings

Table 58. ESD absolute maximum ratings

Conditions Symbol

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage (human body model)

= +25 °C conforming to

ANSI/ESDA/JEDEC JS-001-2012

Electrostatic discharge voltage (charge device model)

= +25 °C conforming to ANSI/ESD

STM5.3.1-2009, all the packages excepted WLCSP100

1. Guaranteed by characterization results.

Class

Maximum value

(1)

Unit

2 2000

3 250

Symbol

Static latchup

Two complementary static tests are required on six parts to assess the latchup performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latchup standard.

Parameter

Static latch-up class

Table 59. Electrical sensitivities

Conditions

= +105 °C conforming to JESD78A

Class

II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –

5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.

The test results are given in Table 60

146/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Symbol

Table 60. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

Unit

INJ

Injected current on BOOT0, PDR_ON, BYPASS_REG,

OTG_HS_REXT

Injected current on NRST

Injected current on PF9, PF10, PH0_OSCIN, PH1_OSCOUT, PC0,

PC1, PC2, PC3, PB14

(2)

, PB15

Table 61: I/O static characteristics are

Injected current on any other FT or FTf pins

Injected current on any other pins

1. Injection is not possible.

2. PB14 and PB15 in the STM32F733xx devices.

-0

-5

(1)

+5 mA

Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

General input/output characteristics

Unless otherwise specified, the parameters given in

derived from tests performed under the conditions summarized in

Table 16 . All I/Os are

CMOS and TTL compliant.

Symbol Parameter

FT, TTa and NRST I/O input low level voltage

Table 61. I/O static characteristics

Conditions Min

1.7 V ≤ V

≤ 3.6 V -

BOOT I/O input low level voltage

FT, TTa and NRST I/O input high level voltage

(5)

BOOT I/O input high level voltage

1.75 V ≤ V

–40 °C ≤ T

≤

≤ 3.6 V,

105 °C

1.7 V ≤ V

0 °C ≤ T

≤

≤ 3.6 V,

105 °C

1.7 V ≤ V

≤ 3.6 V

0.45V

+0.3

(1)

0.7V

(2)

1.75 V ≤ V

–40 °C ≤ T

≤

≤ 3.6 V,

105 °C

1.7 V ≤ V

0 °C ≤ T

≤

≤ 3.6 V,

105 °C

0.17V

+0.7

(1)

Typ Max

0.35V

− 0.04

(1)

0.3V

(2)

Unit

0.1V

+0.1

(1)

DS11854 Rev 5 147/228

200

Electrical characteristics STM32F732xx STM32F733xx

Symbol

Table 61. I/O static characteristics (continued)

Parameter Conditions Min Typ Max Unit

FT, TTa and NRST I/O input hysteresis

1.7 V ≤ V

≤ 3.6 V 10%V

(3)

HYS lkg

BOOT I/O input hysteresis

I/O input leakage current

(4)

I/O FT input leakage current (5)

1.75 V ≤ V

–40 °C ≤ T

≤

≤ 3.6 V,

105 °C

1.7 V ≤ V

0 °C ≤ T

≤

≤ 3.6 V,

105 °C

≤ V

= 5 V

0.1

µA

Weak pull-up equivalent resistor

(6)

)

All pins except for

PA10/PB12

(OTG_FS_ID

,OTG_HS_ID

= V

30 40 50

PA10/PB12

)

(OTG_FS_ID

,OTG_HS_ID

7 10 14 k Ω

All pins except for

PA10/PB12

)

(OTG_FS_ID

,OTG_HS_ID

= V

30 40 50

Weak pulldown equivalent resistor

(7)

PA10/PB12

(OTG_FS_ID

)

,OTG_HS_ID

7 10 14

(8)

I/O pin capacitance 5 -

1. Guaranteed by design.

2. Tested in production.

3. With a minimum of 200 mV.

4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 60: I/O current injection susceptibility

5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to

Table 60: I/O current injection susceptibility

6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order).

7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order).

8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in

Figure 43

148/228 DS11854 Rev 5

STM32F732xx STM32F733xx

2.52

VIL/VIH (V)

Electrical characteristics

Figure 43. FT I/O input characteristics

TTL requirement

VIHmin = 2V

2.0

1.92

1.7

1.22

1.19

1.065

0.8

0.55

0.51

Tested in production - CMOS requirement VIHmin = 0.7VDD

Area not determined

Based on Design simulations, VIHmin= 0.45VDD+0.3

VILmax = 0.8V

Tested in production - CMOS requirement VILmax = 0.3VDD

VDD (V)

1.7

2.0

2.4

2.7

3.3

3.6

MS33746V2

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ± 8 mA, and sink or source up to ± 20 mA (with a relaxed V

) except PC13, PC14, PC15 and PI8 which can sink or source up to ± 3mA. When using the PC13 to PC15 and PI8 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

. In particular:

• The sum of the currents sourced by all the I/Os on V

DD, consumption of the MCU sourced on V

DD,

Σ I

VDD

(see

Table 14 ).

plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

SS consumption of the MCU sunk on V

Σ I

VSS

(see Table 14

plus the maximum Run

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in

Table 62 are derived from tests

performed under ambient temperature and V

Table 16 . All I/Os are CMOS and TTL compliant.

supply voltage conditions summarized in

DS11854 Rev 5 149/228

200

Electrical characteristics STM32F732xx STM32F733xx

Symbol

Table 62. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)

(3)

(1)

(3)

(1)

(3)

(1)

(3)

(1)

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin except PC14

Output high level voltage for PC14

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin except PC14

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin except PC14

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin except PC14

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin except PC14

Output high level voltage for PC14

CMOS port

(2)

= +8 mA

2.7 V ≤ V

≤ 3.6 V

CMOS port

(2)

= -8 mA

2.7 V ≤ V

≤ 3.6 V

CMOS port

(2)

= -2 mA

2.7 V ≤ V

≤ 3.6 V

TTL port

(2)

=+8mA

2.7 V ≤ V

≤ 3.6 V

TTL port

(2)

=-8mA

2.7 V ≤ V

≤ 3.6 V

= +20 mA

2.7 V ≤ V

≤ 3.6 V

= -20 mA

2.7 V ≤ V

≤ 3.6 V

= +6 mA

1.8 V ≤ V

≤ 3.6 V

= -6 mA

1.8 V ≤ V

≤ 3.6 V

= +4 mA

1.7 V ≤ V

≤ 3.6V

= -4 mA

1.7 V ≤ V

≤ 3.6V

= -1 mA

1.7 V ≤ V

≤ 3.6V

2.4

−

0.4

− 1.3

(4)

− 0.4

(4)

− 0.4

(5)

− 0.4

(5)

0.4

1.3

0.4

(4)

(5)

1. The I

current sunk by the device must always respect the absolute maximum rating specified in Table 14

. and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I

current sourced by the device must always respect the absolute maximum rating specified in

Table 14

and the sum of I

(I/O ports and control pins) must not exceed I

VDD

4. Based on characterization data.

5. Guaranteed by design.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 44

and

Table 63 , respectively.

150/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

OSPEEDRy

[1:0] bit value

(1)

Unless otherwise specified, the parameters given in

Table 63 are derived from tests

performed under the ambient temperature and V

DD in

3. The maximum frequency is defined in Figure 44 .

supply voltage conditions summarized

Table 63. I/O AC characteristics (1)(2)

Symbol Parameter Conditions Min Typ Max Unit

00 f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out

Output high to low level fall time and output low to high level rise time

= 50 pF, V

≥ 2.7 V -

= 50 pF, V

≥ 1.7 V -

= 10 pF, V

≥ 2.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

= 50 pF, V

3.6 V

= 1.7 V to

100

MHz ns

10 f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out

Output high to low level fall time and output low to high level rise time

= 50 pF, V

≥ 2.7 V

= 50 pF, V

≥ 1.8 V

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

= 50 pF, V

≥ 2.7 V

= 10 pF, V

≥ 2.7 V

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 1.7 V

= 40 pF, V

≥ 2.7 V

= 10 pF, V

≥ 2.7 V

= 40 pF, V

≥ 1.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

= 40 pF, V

≥ 2.7 V

= 10 pF, V

≥ 2.7 V

= 40 pF, V

≥ 1.7 V

= 10 pF, V

≥ 1.7 V

12.5

(4)

100

(4)

12.5

42.5

MHz ns

DS11854 Rev 5 151/228

200

Electrical characteristics STM32F732xx STM32F733xx

Table 63. I/O AC characteristics (1)(2) (continued)

OSPEEDRy

[1:0] bit value

(1)

Symbol Parameter Conditions Min Typ Max

11 f max(IO)out t t f(IO)out r(IO)out

Maximum frequency

(3)

Output high to low level fall time and output low to high level rise time

= 30 pF, V

≥ 2.7 V

= 30 pF, V

≥ 1.8 V

= 30 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

= 30 pF, V

≥ 2.7 V

= 30 pF, V

≥ 1.8 V

= 30 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

tEXTIpw

Pulse width of external signals detected by the EXTI controller

10 -

1. Guaranteed by design.

2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F72xxx and STM32F73xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register.

4. For maximum frequencies above 50 MHz and V

> 2.4 V, the compensation cell should be used.

2.5

3.5

100

(4)

42.5

180

(4)

100

72.5

Unit

MHz ns ns

Figure 44. I/O AC characteristics definition

90% 10%

50%

10%

50%

90%

EXTERNAL

OUTPUT

ON CL tr(IO)out tf(IO)out

Maximum frequency is achieved if (tr + tf) ≤ (2/3)T and if the duty cycle is (45-55%) when loaded by C L specified in the table “ I/O AC characteristics ”. ai14131d

152/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

6.3.21 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Table 61: I/O static characteristics ).

Unless otherwise specified, the parameters given in

Table 64 are derived from tests

performed under the ambient temperature and V

DD in

Table 61 . Otherwise the reset is not taken into account by the device.

supply voltage conditions summarized

Symbol

Table 64. NRST pin characteristics

Parameter Conditions Min Typ Max

F(NRST)

(2)

NF(NRST)

(2)

NRST_OUT

Weak pull-up equivalent resistor

(1)

NRST Input filtered pulse

NRST Input not filtered pulse

Generated reset pulse duration

= V

> 2.7 V

Internal Reset source

300

100

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order)

2. Guaranteed by design.

Unit k Ω ns ns

µs

Figure 45. Recommended NRST pin protection

External reset circuit (1)

NRST(2)

VDD

RPU

0.1 μF

Filter

Internal Reset

STM32F ai14132c

1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

DS11854 Rev 5 153/228

200

Electrical characteristics STM32F732xx STM32F733xx

The parameters given in

Table 65 are guaranteed by design.

Refer to Section 6.3.20: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 65. TIMx characteristics

(1)(2)

Parameter Conditions

(3) Min Max Unit t res(TIM)

Timer resolution time

AHB/APBx prescaler=1 or 2 or 4, f

TIMxCLK

216 MHz

AHB/APBx prescaler>4, f

TIMxCLK

108 MHz f

EXT

Timer external clock frequency on CH1 to CH4 f

TIMxCLK

= 216 MHz

Timer resolution Res

TIM t

MAX_COUNT

Maximum possible count with 32-bit counter

TIMxCLK

16/32

65536 ×

65536

/2 t t t

TIMxCLK

MHz bit

TIMxCLK

1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.

2. Guaranteed by design.

3. The maximum timer frequency on APB1 or APB2 is up to 216 MHz, by setting the TIMPRE bit in the

RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCLK, otherwise TIMxCLK =

4x PCLKx.

Symbol

Parameter

Table 66. RTC characteristics

Conditions f

PCLK1

/RTCCLK frequency ratio

Any read/write operation from/to an RTC register

Min

Max

Symbol

DDA

REF+

REFf

ADC

Unless otherwise specified, the parameters given in

Table 67 are derived from tests

performed under the ambient temperature, f

conditions summarized in Table 16

PCLK2 frequency and V

DDA

supply voltage

Table 67. ADC characteristics

Parameter Conditions Min Typ Max Unit

Power supply

Positive reference voltage

Negative reference voltage

ADC clock frequency

DDA

− V

REF+

< 1.2 V

DDA

= 1.7

(1)

to 2.4 V

DDA

= 2.4 to 3.6 V

1.7

(1)

1.7

(1)

0.6

3.6

DDA

MHz

154/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Symbol Parameter

Table 67. ADC characteristics (continued)

Conditions Min Typ Max f

TRIG

(2)

External trigger frequency f

ADC

= 30 MHz,

12-bit resolution

1764

AIN

Conversion voltage range

(3)

SSA or V

REFtied to ground)

REF+

AIN

(2) External input impedance

ADC

(2)(4)

Sampling switch resistance

ADC

(2)

Internal sample and hold capacitor t t t t t lat

(2) latr

(2)

STAB

(2)

CONV

(2) f

(2)

See Equation 1 for details

1.5

Injection trigger conversion latency

Regular trigger conversion latency

Sampling time

Power-up time

Sampling rate

ADC

= 36 MHz, and t

= 3 ADC cycles)

ADC

= 30 MHz f

ADC

= 30 MHz

ADC

= 30 MHz

ADC

= 30 MHz

12-bit resolution f

ADC

= 30 MHz

10-bit resolution

0.50

0.43

16.40

16.34

Total conversion time (including sampling time) f

ADC

= 30 MHz

8-bit resolution f

ADC

= 30 MHz

6-bit resolution

0.37

0.30

16.27

16.20

9 to 492 (t

for sampling +n-bit resolution for successive approximation)

12-bit resolution

Single ADC

12-bit resolution

Interleave Dual ADC mode

12-bit resolution

Interleave Triple ADC mode

0.100

2.4

4.5

7.2

0.100

(5)

0.067

(5)

480

Unit kHz

1/f

ADC

µs

1/f

ADC

Msps

κΩ

κΩ pF

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

DS11854 Rev 5 155/228

200

Electrical characteristics STM32F732xx STM32F733xx

Symbol Parameter

Table 67. ADC characteristics (continued)

Conditions Min Typ Max Unit

VREF+

(2)

VDDA

(2)

ADC V

REF

DC current consumption in conversion mode

ADC V

DDA

DC current consumption in conversion mode

300

1.6

500

1.8

1. V

DDA

minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:

Internal reset OFF ).

2. Guaranteed by characterization results.

3. V

REF+

is internally connected to V

DDA

and V

REF-

is internally connected to V

SSA

4. R

ADC

maximum value is given for V

=1.7 V, and minimum value for V

=3.3 V.

5. For external triggers, a delay of 1/f

PCLK2

must be added to the latency specified in

Table 67

µA mA

Equation 1: R

AIN

max formula

AIN

=

ADC

(

C k 0.5

ADC

× ln

)

( 2

N +

)

– R

ADC

The formula above ( Equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register.

Symbol

Table 68. ADC static accuracy at f

ADC

= 18 MHz

Parameter

ET Total unadjusted error

EO Offset error

EG Gain error

ED Differential linearity error

EL Integral linearity error

1. Guaranteed by characterization results.

Test conditions f

ADC

=18 MHz

DDA

= 1.7 to 3.6 V

REF

= 1.7 to 3.6 V

DDA

− V

REF

< 1.2 V

Typ

±3

±2

±1

±2

Max

(1)

±4

±3

±2

±3

Symbol

Table 69. ADC static accuracy at f

ADC

= 30 MHz

Parameter

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

1. Guaranteed by characterization results.

Test conditions f

ADC

= 30 MHz,

AIN

DDA

< 10 k

REF

DDA

Ω ,

= 2.4 to 3.6 V,

= 1.7 to 3.6 V,

− V

REF

< 1.2 V

Typ

±2

±1.5

±1

±1.5

Max

(1)

±5

±2.5

±4

±2

±3

Unit

LSB

Unit

LSB

156/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Symbol

Table 70. ADC static accuracy at f

ADC

= 36 MHz

Parameter

ET Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

1. Guaranteed by characterization results.

Test conditions f

ADC

=36 MHz,

DDA

= 2.4 to 3.6 V,

REF

= 1.7 to 3.6 V

DDA

− V

REF

< 1.2 V

Typ

±4

±2

±3

±2

±3

Max

(1)

±7

±3

±6

±3

±6

Unit

LSB

Symbol

Table 71. ADC dynamic accuracy at f

ADC

= 18 MHz - limited test conditions (1)

Parameter Test conditions Min Typ Max Unit bits ENOB

SINAD

SNR

THD

Effective number of bits

Signal-to-noise and distortion ratio

Signal-to-noise ratio

Total harmonic distortion

1. Guaranteed by characterization results.

ADC

=18 MHz

DDA

= V

REF+

= 1.7 V

Input Frequency = 20 KHz

Temperature = 25 °C

10.3

10.4

64 64.2

64 65

− 67 − 72

Symbol

Table 72. ADC dynamic accuracy at f

ADC

= 36 MHz - limited test conditions

(1)

Parameter Test conditions Min Typ Max Unit bits ENOB

SINAD

SNR

THD

Effective number of bits

Signal-to noise and distortion ratio

Signal-to noise ratio

Total harmonic distortion

1. Guaranteed by characterization results.

ADC

=36 MHz

DDA

= V

REF+

= 3.3 V

Input Frequency = 20 KHz

Temperature = 25 °C

10.6

10.8

66 67

64 68

− 70 − 72

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I

INJ(PIN)

Section 6.3.20

does not affect the ADC accuracy.

and Σ I

INJ(PIN)

DS11854 Rev 5 157/228

200

Electrical characteristics STM32F732xx STM32F733xx

Figure 46. ADC accuracy characteristics

[1LSB IDEAL =

V REF+

4096

V DDA

(or depending on package)]

4096

4095

4094

4093

VSSA

2 3 456

1L SBIDEAL

(2)

(3)

(1)

4093 4094 4095 4096

VDDA

1. See also Table 69 .

2. Example of an actual transfer curve.

3. Ideal transfer curve.

4. End point correlation line.

5. E

= Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

EO = Offset Error: deviation between the first actual transition and the first ideal one.

EG = Gain Error: deviation between the last ideal transition and the last actual one.

ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.

EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

Figure 47. Typical connection diagram using the ADC ai14395c

VAIN

RAIN(1)

AINx

Cparasitic

VDD

0.6 V

IL±1 μA

STM32F

Sample and hold ADC converter

RADC(1)

12-bit converter

CADC(1) ai17534

1. Refer to Table 67 for the values of R

AIN

, R

ADC

and C

ADC

2. C f pad capacitance (roughly 5 pF). A high C

ADC

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

should be reduced.

parasitic

value downgrades conversion accuracy. To remedy this,

158/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 48

Figure 49

, depending on whether V

REF+

is connected to V

DDA

or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 48. Power supply and reference decoupling (V

REF+ not connected to V

DDA

)

STM32

REF+

(1)

1 μF // 10 nF

DDA

1 μF // 10 nF

SSA

REF+

(1) ai17535c

1. V

REF+

input is available on all the packages except LQFP64, whereas the V

UFBGA176 and UFBGA144. When V

REF-

REF– is available only on is not available, it is internally connected to V

SSA

Figure 49. Power supply and reference decoupling (V

REF+ connected to V

DDA

)

STM32F

REF+

DDA

(1)

1 μF // 10 nF

REF-

SSA

(1)

1. V

REF+

input is available on all the packages except LQFP64, whereas the V

UFBGA176 and UFBGA144. When V

REF-

REF– is available only on is not available, it is internally connected to V

SSA

ai17536c

DS11854 Rev 5 159/228

200

Electrical characteristics STM32F732xx STM32F733xx

6.3.25 Temperature sensor characteristics

Symbol

Table 73. Temperature sensor characteristics

Parameter Min Typ Max

(1)

Avg_Slope

(1)

START

(2)

S_temp

(2)

SENSE

linearity with temperature

Average slope

Voltage at 25 °C

Startup time

ADC sampling time when reading the temperature (1 °C accuracy)

1. Guaranteed by characterization results.

2. Guaranteed by design.

± 1

2.5

0.76

± 2

Unit

°C mV/°C

µs

Symbol

Table 74. Temperature sensor calibration values

Parameter Memory address

TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, V

DDA

= 3.3 V 0x1FF0 7A2C - 0x1FF0 7A2D

TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, V

DDA

= 3.3 V 0x1FF0 7A2E - 0x1FF0 7A2F

6.3.26 V

BAT

monitoring characteristics

Symbol

Table 75. V

BAT

monitoring characteristics

Parameter Min

(1)

S_vbat

(2)(2)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q

ADC sampling time when reading the V

BAT

1 mV accuracy

1. Guaranteed by design.

2. Shortest sampling time can be determined in the application by multiple iterations.

–1

Typ

Max

Unit

K Ω

µs

The parameters given in

Table 76 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:

Symbol Parameter

Table 76. internal reference voltage

Conditions Min Typ Max

REFINT

S_vrefint

(1)

RERINT_s

(2)

Internal reference voltage

ADC sampling time when reading the internal reference voltage

Internal reference voltage spread over the temperature range

–40 °C < T

< +105 °C 1.18

1.21

1.24

= 3V ± 10mV

Unit

µs mV

160/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Symbol

Table 76. internal reference voltage (continued)

Parameter Conditions Min Typ

Coeff

(2) t

START

(2)

Temperature coefficient

Startup time -

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

Max Unit

50 ppm/°C

10 µs

Symbol

REFIN_CAL

Table 77. Internal reference voltage calibration values

Parameter Memory address

Raw data acquired at temperature of 30 °C

VDDA

= 3.3 V 0x1FF0 7A2A - 0x1FF0 7A2B

Symbol

DDA

REF+

SSA

LOAD

(2)

Parameter

Table 78. DAC characteristics

Min Typ Max Unit

Analog supply voltage 1.7

(1)

Reference supply voltage

Ground

Resistive load with buffer ON

Connected to

SSA

Connected to

DDA

1.7

(1)

3.6

V V

REF+

≤ V

DDA

V k Ω k Ω

Comments

(2)

Impedance output with buffer

OFF

LOAD

(2)

Capacitive load -

50 k Ω pF

When the buffer is OFF, the Minimum resistive load between DAC_OUT and

to have a 1% accuracy is 1.5 M Ω

Maximum capacitive load at DAC_OUT pin (when the buffer is ON).

DAC_OUT min

(2)

Lower DAC_OUT voltage with buffer ON

DAC_OUT max

(2)

Higher DAC_OUT voltage with buffer ON

DAC_OUT min

(2)

Lower DAC_OUT voltage with buffer OFF

DAC_OUT max

(2)

Higher DAC_OUT voltage with buffer OFF

0.2 -

DDA

0.2

−

It gives the maximum output excursion of the DAC.

It corresponds to 12-bit input code

(0x0E0) to (0xF1C) at V

REF+

(0x1C7) to (0xE38) at V

REF+

= 3.6 V and

= 1.7 V

0.5

REF+

−

1LSB mV

It gives the maximum output excursion of the DAC.

DS11854 Rev 5 161/228

200

Electrical characteristics STM32F732xx STM32F733xx

Symbol

DDA

(4)

Parameter

Table 78. DAC characteristics (continued)

VREF+

(4)

DAC DC V

REF

current consumption in quiescent mode (Standby mode)

DAC DC V

DDA

current consumption in quiescent mode

(3)

Min Typ Max Unit

170

280

475

240

380

625

µA

Comments

With no load, worst code (0x800) at

REF+

= 3.6 V in terms of DC consumption on the inputs

With no load, worst code (0xF1C) at

REF+

= 3.6 V in terms of DC consumption on the inputs

With no load, middle code (0x800) on the inputs

With no load, worst code (0xF1C) at

REF+

= 3.6 V in terms of DC consumption on the inputs

DNL

(4)

Differential non linearity

Difference between two consecutive code-1LSB)

INL

(4)

Integral non linearity

(difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023)

Offset

(4)

Offset error

(difference between measured value at Code

(0x800) and the ideal value =

REF+

/2)

Gain error

(4)

Gain error t

SETTLING

(4)

Settling time (full scale: for a

10-bit input code transition between the lowest and the highest input codes when

DAC_OUT reaches final value ±4LSB

THD

(4)

Update rate

(2)

Total Harmonic Distortion

Buffer ON

Max frequency for a correct

DAC_OUT change when small variation in the input code (from code i to i+1LSB)

±0.5 LSB Given for the DAC in 10-bit configuration.

±2 LSB Given for the DAC in 12-bit configuration.

±1 LSB Given for the DAC in 10-bit configuration.

±4

±10

±3 mV Given for the DAC in 12-bit configuration

LSB

Given for the DAC in 10-bit at V

REF+

3.6 V

±12 LSB

Given for the DAC in 12-bit at V

REF+

3.6 V

±0.5

% Given for the DAC in 12-bit configuration

LSB Given for the DAC in 12-bit configuration.

µs

LOAD

≤ 50 pF,

≥ 5 k Ω dB

LOAD

≤ 50 pF,

≥ 5 k Ω

MS/s

LOAD

≤ 50 pF,

≥ 5 k Ω

162/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Symbol Parameter

Table 78. DAC characteristics (continued)

Min Typ Max Unit Comments t

WAKEUP

(4)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

6.5

10 µs

LOAD

≤ 50 pF, R

LOAD

≥ 5 k Ω input code between lowest and highest possible ones.

PSRR+

(2)

Power supply rejection ratio

(to V

DDA

) (static DC measurement)

–67 –40 , C

LOAD

= 50 pF

1. V

DDA

Internal reset OFF ).

2. Guaranteed by design.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs.

4. Guaranteed by characterization results.

Figure 50. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)

R L

12-bit digital to analog converter

DAC_OUTx

C L ai17157V3

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

I

C interface characteristics

The I

C interface meets the timings requirements of the I

C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s.

• Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.

The I

C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0431 reference manual) and when the I2CCLK frequency is greater than the minimum shown in the table below:

DS11854 Rev 5 163/228

200

Electrical characteristics STM32F732xx STM32F733xx

Table 79. Minimum I2CCLK frequency in all I2C modes

Symbol Parameter Condition Min

Standard-mode 2 f(I2CCLK)

I2CCLK frequency

Fast-mode

Fast-mode Plus

Analog Filter ON

DNF=0

Analog Filter OFF

DNF=1

Analog Filter ON

DNF=0

Analog Filter OFF

DNF=1

22.5

Unit

MHz

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

is disabled, but is still present.

The 20mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load Cload supported in Fm+, which is given by these formulas:

• Tr(SDA/SCL)=0.8473xR

p xC load

• R p

(min)= (VDD-V

(max))/I

(max)

Where Rp is the I2C lines pull-up. Refer to

Section 6.3.20: I/O port characteristics

for the

I2C I/Os characteristics.

All I

C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

Symbol

Table 80. I2C analog filter characteristics (1)

Parameter t

Maximum pulse width of spikes that are suppressed by the analog filter

1. Guaranteed by characterization results.

2. Spikes with widths below t

AF(min) are filtered.

3. Spikes with widths above t

AF(max)

are not filtered

Min

(2)

Max

260

(3)

Unit ns

164/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

SPI interface characteristics

Unless otherwise specified, the parameters given in

Table 81 for the SPI interface are

derived from tests performed under the ambient temperature, f

PCLKx frequency and V

Refer to Section 6.3.20: I/O port characteristics

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5V

for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

SCK

1/t c(SCK) tsu(NSS) th(NSS) tw(SCKH) tw(SCKL)

Symbol Parameter

SPI clock frequency

NSS setup time

NSS hold time

Table 81. SPI dynamic characteristics

(1)

Conditions Min

SCK high and low time

Master mode

SPI1,4,5

2.7

≤ VDD ≤ 3.6

Master mode

SPI1,4,5

1.71

≤ VDD ≤ 3.6

Master transmitter mode

SPI1,4,5

1.71

≤ VDD ≤ 3.6

Slave receiver mode

SPI1,4,5

1.71

≤ VDD ≤ 3.6

Slave mode transmitter/full duplex

SPI1,4,5

2.7

≤ VDD ≤ 3.6

Slave mode transmitter/full duplex

SPI1,4,5

1.71

≤ VDD ≤ 3.6

Master & Slave mode

SPI2,3

1.71

≤ VDD ≤ 3.6

Slave mode, SPI presc = 2

Master mode

4xTpclk

2xTpclk

Tpclk-1

Typ

Max

(2)

(3)

Tpclk Tpclk+1

Unit

MHz ns

DS11854 Rev 5 165/228

200

Electrical characteristics STM32F732xx STM32F733xx

Table 81. SPI dynamic characteristics (1) (continued)

Symbol Parameter Conditions Min Typ Max Unit tsu(MI) tsu(SI) th(MI) th(SI)

Data input setup time

Data input hold time

Master mode

Slave mode

Master mode

Slave mode

3.5

1 -

ta(SO) tdis(SO) tv(SO)

Data output access time

Data output disable time

Slave mode

Slave mode 2.7

≤ VDD ≤ 3.6V -

Slave mode 1.71

≤ VDD ≤ 3.6V

6.5

13.5

Data output valid time tv(MO) th(SO) th(MO)

Data output hold time

Master mode

Slave mode

1.71

≤ VDD ≤ 3.6V

Master mode

4.5

1. Guaranteed by characterization results.

2. Excepting SPI1 with SCK IO=PA5. In this configuration, the maximum achievable frequency is 40 MHz.

3. Maximum frequency of the slave transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having

Tsu(MI)=0 while signal Duty(SCK)=50%.

Figure 51. SPI timing diagram - slave mode and CPHA = 0

NSS input t su(NSS) t w(SCKH) t c(SCK) t r(SCK) t h(NSS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(SO)

MISO output t w(SCKL)

First bit OUT t h(SI) t v(SO) t h(SO)

Next bits OUT t f(SCK)

Last bit OUT t dis(SO) t su(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

166/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Figure 52. SPI timing diagram - slave mode and CPHA = 1

NSS input t su(NSS) t w(SCKH) t c(SCK) t f(SCK) t h(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO output

MOSI input t a(SO) t w(SCKL) t v(SO) t su(SI)

First bit OUT t h(SI)

First bit IN t h(SO)

Next bits OUT

Next bits IN t r(SCK) t dis(SO)

Last bit OUT

Last bit IN

MSv41659V1

Figure 53. SPI timing diagram - master mode

NSS input

High tc(SCK)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

B I T1 OUT th(MO) tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136c

DS11854 Rev 5 167/228

200

Electrical characteristics STM32F732xx STM32F733xx

I

S interface characteristics

Unless otherwise specified, the parameters given in

Table 82 for the I

2 S interface are derived from tests performed under the ambient temperature, f

PCLKx frequency and V

Refer to Section 6.3.20: I/O port characteristics

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5V

for more details on the input/output alternate function characteristics (CK, SD, WS).

Symbol Parameter

Table 82. I

S dynamic characteristics

(1)

Conditions f

MCK f

I2S Main clock output

I2S clock frequency

Master data: 32 bits

Slave data: 32 bits

CK t v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t v(SD_MT) t h(SD_ST) t h(SD_MT)

I2S clock frequency duty cycle Slave receiver

WS valid time

WS hold time

WS setup time

WS hold time

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Master mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

1. Guaranteed by characterization results.

2. 256xFs maximum is 49.152 MHz (APB1 Maximum frequency).

Min Max

256 x 8K 256xFs (2)

2.5

3.5

64xFs

Unit

MHz

% ns

Note: Refer to RM0431 reference manual I2S section for more details on the sampling frequency

). f

MCK

, f

, and D

values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. D

depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of

(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F

S maximum value is supported for each mode/condition.

168/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Figure 54. I 2 S slave timing diagram (Philips protocol) (1) tc(CK)

CPOL = 0

CPOL = 1 tw(CKH) tw(CKL) th(WS)

WS input

SDtransmit tsu(WS)

LSB transmit

(1) tsu(SD_SR)

LSB receive

(1)

MSB transmit

MSB receive tv(SD_ST)

Bitn transmit th(SD_SR)

Bitn receive th(SD_ST)

LSB transmit

LSB receive SDreceive

MS46528V1

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 55. I 2 S master timing diagram (Philips protocol) (1) tf(CK) tr(CK) tc(CK)

CPOL = 0 tw(CKH)

CPOL = 1 tv(WS) tw(CKL) th(WS)

WS output

SDtransmit

LSB transmit

(1) tsu(SD_MR)

LSB receive

(1)

MSB transmit

MSB receive tv(SD_MT)

Bitn transmit th(SD_MR)

Bitn receive th(SD_MT)

LSB transmit

LSB receive SDreceive

MS46529V1

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

DS11854 Rev 5 169/228

200

Electrical characteristics STM32F732xx STM32F733xx

SAI characteristics

Unless otherwise specified, the parameters given in

Table 83

for SAI are derived from tests performed under the ambient temperature, f

PCLKx

frequency and VDD supply voltage

conditions summarized in Table 16

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C=30 pF

• Measurement points are performed at CMOS levels: 0.5V

Refer to Section 6.3.20: I/O port characteristics

for more details on the input/output alternate

function characteristics (SCK,SD,WS).

Table 83. SAI characteristics

(1)

Symbol Parameter Conditions t t t t t t f t t

MCKL

CK v(FS) su(FS) h(FS) su(SD_A_MR) su(SD_B_SR) h(SD_A_MR) h(SD_B_SR) v(SD_B_MT)

SAI Main clock output

SAI clock frequency

FS valid time

FS setup time

FS hold time

(2)

Data input setup time

Data input hold time

Data output valid time

Master data: 32 bits

Slave data: 32 bits

Master mode

2.7

≤ VDD ≤ 3.6V

Master mode

1.71

≤ VDD ≤ 3.6V

Slave mode

Master mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

2.7

≤ VDD ≤ 3.6V

Slave transmitter (after enable edge)

1.71

≤ VDD ≤ 3.6V

Slave transmitter (after enable edge) t h(SD_B_ST)

Data output hold time t v(SD_A_MT)

Data output valid time

Master transmitter (after enable edge)

2.7

≤ VDD ≤ 3.6V

Master transmitter (after enable edge)

1.71

≤ VDD ≤ 3.6V

t h(SD_A_MT)

Data output hold time Master transmitter (after enable edge)

1. Guaranteed by characterization results.

2. APB clock frequency must be at least twice SAI clock frequency.

3. With Fs = 192 KHz.

256x8K

0.5

2.5

3.5

0.5

7.5

256xFs

128xFs

(3)

128xFs

Table 89 for ULPI are derived from

18.5

MHz ns

170/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Figure 56. SAI master timing waveforms

1/fSCK

SAI_SCK_X th(FS)

SAI_FS_X

(output)

SAI_SD_X

(transmit) tv(FS)

SAI_SD_X

(receive) tsu(SD_MR) tv(SD_MT)

Slot n th(SD_MR)

Slot n+2

Slot n th(SD_MT)

MS32771V1

Figure 57. SAI slave timing waveforms

1/fSCK

SAI_SCK_X tw(CKH_X)

SAI_FS_X

(input)

SAI_SD_X

(transmit) tsu(FS)

SAI_SD_X

(receive) tw(CKL_X) th(FS) tsu(SD_SR) tv(SD_ST)

Slot n th(SD_SR)

Slot n+2

Slot n th(SD_ST)

MS32772V1

DS11854 Rev 5 171/228

200

Electrical characteristics

Note:

STM32F732xx STM32F733xx

USB OTG full speed (FS) characteristics

This interface is present in both the USB OTG HS and USB OTG FS controllers.

Symbol

Table 84. USB OTG full speed startup time

Parameter t

STARTUP

(1)

USB OTG full speed transceiver startup time

1. Guaranteed by design.

Max

Unit

µs

Symbol

Table 85. USB OTG full speed DC electrical characteristics

Parameter Conditions

Min.

(1)

Typ.

Max.

(

Unit

DDUSB

USB OTG full speed transceiver operating voltage

3.0

(2)

3.6

Input levels

Output levels

(3)

Differential input sensitivity

Differential common mode range

Single ended receiver threshold

Static output level low

Static output level high

PA11, PA12

(USB_FS_DP/DM)

PA9, PB13

(OTG_FS_VBUS,

OTG_HS_VBUS)

PA12 (USB_FS_DP)

PA9, PB13

(OTG_FS_VBUS,

OTG_HS_VBUS)

I(USB_FS_DP/DM,

USB_HS_DP/DM)

Includes V

= V

= V range

of 1.5 k Ω to 3.6 V

of 15 k Ω to V

(4)

SS, during idle

SS, during reception

0.2

0.8

1.3

2.8

14.25

2.4

0.9

0.55

5.2

2.5

2.0

0.3

3.6

24.8

1.25 1.575

0.95 1.35

1. All the voltages are measured from the local ground potential.

2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V V

DDUSB

voltage range.

3. Guaranteed by design.

4. R

is the load connected on the USB OTG full speed drivers.

When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state

(floating input), not as alternate function. A typical 200 µA current consumption of the sensing block (current to voltage conversion to determine the different sessions) can be observed on PA9 and PB13 when the feature is enabled.

172/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Figure 58. USB OTG full speed timings: definition of data signal rise and fall time

Cross over points

Differential data lines

CRS

SS t f t r ai14137b

Table 86. USB OTG full speed electrical characteristics (1)

Driver characteristics

Symbol

Z t t t r f rfm

CRS

DRV

Rise time

Fall time

(2)

Parameter

Rise/ fall time matching

Output signal crossover voltage

Output driver impedance (3)

Conditions

= 50 pF

= 50 pF t r

/t f

Driving high or low

Min

1.3

Max

111

2.0

Unit

1. Guaranteed by design.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver. ns ns

USB high speed (HS) characteristics (through ULPI in STM32F732xx devices)

Unless otherwise specified, the parameters given in

tests performed under the ambient temperature, f

HCLK and V

frequency summarized in

Table 88

supply voltage conditions summarized in

Table 87 , with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified

• Capacitive load C = 20 pF, unless otherwise specified

• Measurement points are done at CMOS levels: 0.5V

Refer to Section 6.3.20: I/O port characteristics for more details on the input/output

characteristics.

Symbol

Table 87. USB HS DC electrical characteristics

Parameter

Input level V

USB OTG HS operating voltage

1. All the voltages are measured from the local ground potential.

Min.

(1)

1.7

Max.

(1)

3.6

Unit

DS11854 Rev 5 173/228

200

Electrical characteristics STM32F732xx STM32F733xx

Symbol

Table 88. USB HS clock timing parameters (1)

Parameter t t t t

START_8BIT

STEADY

START_8BIT

STEADY

START_DEV

START_HOST

PREP

STEADY f

HCLK

value to guarantee proper operation of

USB HS interface

Frequency (first transition) 8-bit ±10%

Frequency (steady state) ±500 ppm

Duty cycle (first transition) 8-bit ±10%

Duty cycle (steady state) ±500 ppm

Time to reach the steady state frequency and duty cycle after the first transition

Clock startup time after the de-assertion of SuspendM

Peripheral

Host

PHY preparation time after the first transition of the input clock

1. Guaranteed by design.

Min

59.97

49.975

Typ

Figure 59. ULPI timing diagram

Clock

Control In

(ULPI_DIR,

ULPI_NXT) data In

(8-bit) tSC tSD tHC tHD tDC tDC

Control out

(ULPI_STP) data out

(8-bit) tDD

Max Unit

1.4

5.6

MHz

66 MHz

60.03

MHz

50.025

% ms ms

µs ai17361c

174/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Symbol t

SC t

HC t

SD t

HD t

Table 89. Dynamic characteristics: USB ULPI (1)

Parameter

Control in (ULPI_DIR, ULPI_NXT) setup time

Control in (ULPI_DIR, ULPI_NXT) hold time

Data in setup time

Data in hold time

Data/control output delay

Conditions

2.7 V < V

< 3.6 V,

= 20 pF and

OSPEEDRy[1:0] = 11

1.7 V < V

< 3.6 V,

= 15 pF and

OSPEEDRy[1:0] = 11

Min.

Typ.

Max.

Unit

1.5

9.5

7.5

11 ns

1. Guaranteed by characterization results.

USB high speed (HS) characteristics (embedded PHY High speed on

STM32F733xx devices)

Table 90. USB OTG high speed DC electrical characteristics

Symbol Parameter Conditions

V hssq

V hsdsc

V hsdif

V hscm

V hsoi

V hsoh

V hsol

V chirpj

V chirpk

High speed squelch detection threshold

High speed disconnect detection threshold

High speed differential detection threshold

High speed data signalling common mode voltage range

High speed idle level

High speed data signaling high

High speed data signaling low

Chirp J level

100 150 mV

525 625 mV

100 - - mV

-50 500 mV

-10 10 mV

360 440 mV

-10 10 mV

700 - 1100 mV

-900 - mV

Table 91. USB OTG high speed electrical characteristics

Parameter Comments Conditions t lr t lf

t lrfm

Z drv

Fall time

Setup time from INHSDRIVERENABLE=1 to the transition on INHSDATAP/INHSDATAN

Driver output impedance -

0.5

10 - ns ns

40.5

49.5

DS11854 Rev 5 175/228

200

Electrical characteristics STM32F732xx STM32F733xx

Table 92. USB FS PHY BCD electrical characteristics

Symbol Parameter Conditions

DDUSB

Primary detection mode consumption

Secondary detection mode consumption

DAT_LKG

Data line leakage resistance

Data line leakage voltage

DCP_DAT

Dedicated charging port resistance across D+/D-

LGC_HI

Logic low V

LGC_LOW

DAT_REF

DP_SRC

Logic threshold

Data detect voltage

D+ source voltage

D- source voltage V

DM_SRC

DM_SINK

DP_SINK

DP_SRC

D- sink current

D+ sink current

Data contact detect current source

300 -

0.0

300

3.6

2.0

200

3.6

0.8

2.0

0.25

0.5

3.6

175

µA k Ω

µA

CAN (controller area network) interface

Refer to Section 6.3.20: I/O port characteristics

for more details on the input/output alternate function characteristics (CANx_TX and CANx_RX).

176/228

Unless otherwise specified, the parameters given in

Table 93

to Table 106 for the FMC

interface are derived from tests performed under the ambient temperature, f

HCLK and V

DD frequency

supply voltage conditions summarized in

Table 16

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Measurement points are done at CMOS levels: 0.5V

Refer to Section 6.3.20: I/O port characteristics for more details on the input/output

characteristics.

Asynchronous waveforms and timings

Figure 60

through Figure 63 represent asynchronous waveforms and

Table 93 through

Table 100

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• AddressSetupTime = 0x1

• AddressHoldTime = 0x1

• DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)

• BusTurnAroundDuration = 0x0

• Capcitive load CL = 30 pF

In all timing tables, the T

HCLK

is the HCLK clock period

DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Figure 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms t w(NE)

FMC_NE t v(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

FMC_A[25:0] t v(A_NE) t v(BL_NE)

Address t h(A_NOE) t h(BL_NOE)

FMC_NBL[1:0] t h(Data_NE) t h(Data_NOE)

FMC_D[15:0] t su(Data_NOE) t su(Data_NE)

Data t v(NADV_NE) t w(NADV)

FMC_NADV (1)

FMC_NWAIT

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

th(NE_NWAIT) tsu(NWAIT_NE)

MS32753V1

DS11854 Rev 5 177/228

200

Electrical characteristics STM32F732xx STM32F733xx

Table 93. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)

Symbol Parameter Min Max Unit t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t h(A_NOE) t v(BL_NE) t h(BL_NOE) t su(Data_NE) t su(Data_NOE) t h(Data_NOE) t h(Data_NE) t v(NADV_NE) t w(NADV)

1. C

= 30 pF.

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NOE high

FMC_NEx low to FMC_BL valid

FMC_BL hold time after FMC_NOE high

Data to FMC_NEx high setup time

Data to FMC_NOEx high setup time

Data hold time after FMC_NOE high

Data hold time after FMC_NEx high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

2Thclk -1

Thclk -1.5

2Thclk +1

0.5

2Thclk +1

0.5

Thclk -0.5

Table 94. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings

(1)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time 7Thclk +1 7Thclk +1 t w(NOE) t w(NWAIT) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NWE low time

FMC_NWAIT low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. Guaranteed by characterization results.

5Thclk -1

Thclk -0.5

5Thclk +1.5

4Thclk +1

5Thclk +1

178/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Figure 61. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE)

FMC_NEx

FMC_NOE

FMC_NWE

FMC_A[25:0]

FMC_NBL[1:0]

FMC_D[15:0] tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) tv(Data_NE) th(A_NWE)

Address th(BL_NWE)

NBL th(Data_NWE)

Data t v(NADV_NE) tw(NADV) t h(NE_NWE)

FMC_NADV (1)

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32754V1

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 95. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)

Symbol Parameter Min Max Unit t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NE) t h(Data_NWE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_BL hold time after FMC_NWE high

Data to FMC_NEx low to Data valid

Data hold time after FMC_NWE high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1. Guaranteed by characterization results.

3Thclk +1 3Thclk +1

Thclk - 0.5

Thclk +0.5

Thclk - 1.5

Thclk +0.5

Thclk

Thclk - 0.5

0.5

Thclk - 0.5

Thclk +0.5

Thclk +1.5

Thclk - 0.5

DS11854 Rev 5 179/228

200

Electrical characteristics STM32F732xx STM32F733xx

Table 96. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings (1)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time t t t w(NWE) su(NWAIT_NE) h(NE_NWAIT)

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. Guaranteed by characterization results.

8Thclk -1 8Thclk +1

6Thclk -1.5

6Thclk +0.5

6Thclk -1 -

4Thclk + 2 ns

Figure 62. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE)

FMC_ NE tv(NOE_NE) t h(NE_NOE)

FMC_NOE tw(NOE)

FMC_NWE tv(A_NE) th(A_NOE)

FMC_ A[25:16]

Address tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL th(Data_NE)

FMC_ AD[15:0] t v(NADV_NE) t v(A_NE)

Address th(AD_NADV) tw(NADV) tsu(Data_NE) tsu(Data_NOE)

Data th(Data_NOE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32755V1

180/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Table 97. Asynchronous multiplexed PSRAM/NOR read timings (1)

Symbol Parameter Min Max t w(NE) t v(NOE_NE) t tw(NOE) t h(NE_NOE) t v(A_NE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low t h(AD_NADV)

FMC_NADV low time

FMC_AD(address) valid hold time after

FMC_NADV high) t h(A_NOE) t h(BL_NOE) t v(BL_NE) t su(Data_NE) t su(Data_NOE) t h(Data_NE) t h(Data_NOE)

Address hold time after FMC_NOE high

FMC_BL time after FMC_NOE high

FMC_NEx low to FMC_BL valid

Data to FMC_NEx high setup time

Data to FMC_NOE high setup time

Data hold time after FMC_NEx high

Data hold time after FMC_NOE high

1. Guaranteed by characterization results.

3Thclk -1

2Thclk

Thclk -1

Thclk -0.5

Thclk +0.5

Thclk -0.5

Thclk -1.5

3Thclk +1

2Thclk +0.5

Thclk +1

0.5

Thclk +1

0.5

Unit ns

Table 98. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings

(1)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time 8Thclk -1 t t t w(NOE) su(NWAIT_NE) h(NE_NWAIT)

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high 5Thclk +1.5

FMC_NEx hold time after FMC_NWAIT invalid

4Thclk +1

1. Guaranteed by characterization results.

5Thclk -1.5

8Thclk +1

8Thclk +0.5

DS11854 Rev 5 181/228

200

Electrical characteristics STM32F732xx STM32F733xx

Figure 63. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE)

FMC_ NEx

FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

FMC_ A[25:16]

FMC_ NBL[1:0]

FMC_ AD[15:0] t v(NADV_NE) tv(A_NE) tv(BL_NE) t v(A_NE)

Address th(A_NWE)

Address th(BL_NWE)

NBL tv(Data_NADV)

Data th(AD_NADV) tw(NADV) th(Data_NWE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32756V1

Table 99. Asynchronous multiplexed PSRAM/NOR write timings (1)

Symbol Parameter Min Max t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t v(NADV_NE) t w(NADV) t h(AD_NADV) t h(A_NWE) t h(BL_NWE) t v(BL_NE) t v(Data_NADV) t h(Data_NWE)

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low

FMC_NADV low time

FMC_AD(adress) valid hold time after

FMC_NADV high)

Address hold time after FMC_NWE high

FMC_BL hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_NADV high to Data valid

Data hold time after FMC_NWE high

4Thclk -1 4Thclk +1

Thclk -0.5

Thclk +0.5

2Thclk -0.5

2Thclk +0.5

Thclk -0.5

Thclk

0.5

Thclk +1

Thclk +0.5

Thclk -0.5

Thclk +0.5

0.5

Thclk +1.5

Unit ns

182/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

1. Guaranteed by characterization results.

Table 100. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings

(1)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time t t t w(NWE) su(NWAIT_NE) h(NE_NWAIT)

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. Guaranteed by characterization results.

9Thclk - 1 9Thclk + 1

7Thclk -0.5

7Thclk + 0.5

6Thclk + 2 -

4Thclk - 1 ns

Synchronous waveforms and timings

Figure 64

through Figure 67

represent synchronous waveforms and Table 101 through

Table 104

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• BurstAccessMode = FMC_BurstAccessMode_Enable;

• MemoryType = FMC_MemoryType_CRAM;

• WriteBurst = FMC_WriteBurst_Enable;

• CLKDivision = 1;

• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

• CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise specified.

In all timing tables, the T

HCLK

is the HCLK clock period.

– For 2.7 V ≤ V

≤ 3.6 V, maximum FMC_CLK = 108 MHz at CL=20 pF or 90 MHz at

CL=30 pF (on FMC_CLK).

– For 1.71 V ≤ V

<2.7 V, maximum FMC_CLK = 70 MHz at CL=10 pF (on FMC_CLK).

DS11854 Rev 5 183/228

200

Electrical characteristics STM32F732xx STM32F733xx

Figure 64. Synchronous multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK)

BUSTURN = 0

FMC_CLK

Data latency = 0 td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx t d(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE td(CLKL-ADV)

FMC_AD[15:0] td(CLKL-ADIV) tsu(ADV-CLKH)

AD[15:0] tsu(NWAITV-CLKH)

D1 th(CLKH-ADV) tsu(ADV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-ADV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) th(CLKH-NWAITV) th(CLKH-NWAITV)

MS32757V1

184/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Table 101. Synchronous multiplexed NOR/PSRAM read timings (1)

Symbol Parameter Min Max t w(CLK) t d(CLKL-NExL) t d(CLKH_NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t d(CLKL-ADV) t d(CLKL-ADIV)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid t su(ADV-CLKH)

FMC_A/D[15:0] valid data before FMC_CLK high t h(CLKH-ADV) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_A/D[15:0] valid data after FMC_CLK high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Guaranteed by characterization results.

2Thclk - 0.5

Thclk + 0.5

Thclk

Thclk - 0.5

0.5

3 -

Unit ns

DS11854 Rev 5 185/228

200

Electrical characteristics STM32F732xx STM32F733xx

Figure 65. Synchronous multiplexed PSRAM write timings tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0 td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx td(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16] td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE td(CLKL-ADV)

FMC_AD[15:0] td(CLKL-ADIV) td(CLKL-Data)

AD[15:0] td(CLKL-Data)

D1 D2

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKH-NBLH)

FMC_NBL

MS32758V1

186/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Symbol

Table 102. Synchronous multiplexed PSRAM write timings (1)

Parameter Min Max Unit t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t

(CLKH-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-DATA) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Guaranteed by characterization results.

2Thclk - 0.5

Thclk +0.5

Thclk

Thclk +0.5

1.5

2 ns

DS11854 Rev 5 187/228

200

Electrical characteristics STM32F732xx STM32F733xx

Figure 66. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK)

FMC_CLK td(CLKL-NExL)

Data latency = 0 td(CLKH-NExH)

FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE

FMC_D[15:0] tsu(DV-CLKH) tsu(NWAITV-CLKH)

D1 th(CLKH-DV) tsu(DV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-DV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V1

Table 103. Synchronous non-multiplexed NOR/PSRAM read timings (1)

Symbol Parameter Min Max t w(CLK) t

(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t su(DV-CLKH) t h(CLKH-DV) t

(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_D[15:0] valid data before FMC_CLK high

FMC_D[15:0] valid data after FMC_CLK high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

2Thclk - 0.5

Thclk +0.5

Thclk

Thclk -0.5

0.5

Unit ns

188/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

1. Guaranteed by characterization results.

Figure 67. Synchronous non-multiplexed PSRAM write timings tw(CLK) tw(CLK)

FMC_CLK td(CLKL-NExL)

FMC_NEx td(CLKL-NADVL)

FMC_NADV

Data latency = 0 td(CLKL-NADVH) td(CLKH-NExH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0] td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE

FMC_D[15:0] td(CLKL-Data)

D1 td(CLKL-Data)

FMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH)

FMC_NBL td(CLKH-NBLH) th(CLKH-NWAITV)

MS32760V1

DS11854 Rev 5 189/228

200

Electrical characteristics STM32F732xx STM32F733xx

Symbol

Table 104. Synchronous non-multiplexed PSRAM write timings (1)

Parameter Min Max t

(CLK) t d(CLKL-NExL) t

(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t d(CLKH-NWEH) t d(CLKL-Data) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Guaranteed by characterization results.

2Thclk - 0.5

Thclk +0.5

Thclk

Thclk +1

3.5

1.5

0.5

Unit ns

NAND controller waveforms and timings

Figure 68

through Figure 71 represent synchronous waveforms, and Table 105 and

Table 106

provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration:

• COM.FMC_SetupTime = 0x01;

• COM.FMC_WaitSetupTime = 0x03;

• COM.FMC_HoldSetupTime = 0x02;

• COM.FMC_HiZSetupTime = 0x01;

• ATT.FMC_SetupTime = 0x01;

• ATT.FMC_WaitSetupTime = 0x03;

• ATT.FMC_HoldSetupTime = 0x02;

• ATT.FMC_HiZSetupTime = 0x01;

• Bank = FMC_Bank_NAND;

• MemoryDataWidth = FMC_MemoryDataWidth_16b;

• ECC = FMC_ECC_Enable;

• ECCPageSize = FMC_ECCPageSize_512Bytes;

• TCLRSetupTime = 0;

• TARSetupTime = 0.

In all timing tables, the T

HCLK

is the HCLK clock period.

190/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

FMC_NCEx

Figure 68. NAND controller waveforms for read access

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE td(ALE-NOE) th(NOE-ALE)

FMC_NOE (NRE) tsu(D-NOE) th(NOE-D)

FMC_D[15:0]

MS32767V1

Figure 69. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16) td(ALE-NWE)

FMC_NWE th(NWE-ALE)

FMC_NOE (NRE) tv(NWE-D) th(NWE-D)

FMC_D[15:0]

MS32768V1

Figure 70. NAND controller waveforms for common memory read access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE

FMC_NOE td(ALE-NOE) tw(NOE) th(NOE-ALE) tsu(D-NOE) th(NOE-D)

FMC_D[15:0]

MS32769V1

DS11854 Rev 5 191/228

200

Electrical characteristics STM32F732xx STM32F733xx

Figure 71. NAND controller waveforms for common memory write access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16) td(ALE-NOE)

FMC_NWE tw(NWE) th(NOE-ALE)

FMC_N OE td(D-NWE) tv(NWE-D) th(NWE-D)

FMC_D[15:0]

MS32770V1

Symbol

Table 105. Switching characteristics for NAND Flash read cycles (1)

Parameter Min Max t w(N0E) t su(D-NOE) t h(NOE-D) t d(ALE-NOE) t h(NOE-ALE)

FMC_NOE low width

FMC_D[15-0] valid data before FMC_NOE high

FMC_D[15-0] valid data after FMC_NOE high

FMC_ALE valid before FMC_NOE low

FMC_NWE high to FMC_ALE invalid

1. Guaranteed by characterization results.

4Thclk -0.5

4Thclk +0.5

4Thclk - 2

3Thclk +1.5

Unit ns

Table 106. Switching characteristics for NAND Flash write cycles (1)

Symbol Parameter Min Max t w(NWE) t v(NWE-D) t h(NWE-D) t d(D-NWE) t d(ALE-NWE) t h(NWE-ALE)

FMC_NWE low width

FMC_NWE low to FMC_D[15-0] valid

FMC_NWE high to FMC_D[15-0] invalid

FMC_D[15-0] valid before FMC_NWE high

FMC_ALE valid before FMC_NWE low

FMC_NWE high to FMC_ALE invalid

1. Guaranteed by characterization results.

4Thclk -0.5

4Thclk +0.5

2Thclk - 1

5Thclk - 1

2Thclk - 2

3Thclk +1.5

Unit ns

192/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

SDRAM waveforms and timings

• CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise specified.

In all timing tables, the T

HCLK

is the HCLK clock period.

– For 3.0 V ≤ V

FMC_SDCLK).

≤ 3.6 V, maximum FMC_SDCLK= 100 MHz at CL=20 pF (on

– For 2.7 V ≤ V

FMC_SDCLK).

≤ 3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF (on

– For 1.71 V ≤ V

FMC_SDCLK).

<1.9 V, maximum FMC_SDCLK = 70 MHz at CL=10 pF (on

Figure 72. SDRAM read access waveforms (CL = 1)

FMC_SDCLK td(SDCLKL_AddR)

FMC_A[12:0] Row n td(SDCLKL_AddC) th(SDCLKL_AddR)

Col1 Col2 Coli th(SDCLKL_AddC)

Coln td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0] td(SDCLKL_NRAS)

FMC_SDNRAS th(SDCLKL_NRAS) td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS

FMC_SDNWE

FMC_D[31:0] tsu(SDCLKH_Data)

Data1 th(SDCLKH_Data)

Data2 Datai Datan

MS32751V2

DS11854 Rev 5 193/228

200

Electrical characteristics STM32F732xx STM32F733xx

Symbol

Table 107. SDRAM read timings (1)

Parameter t w(SDCLK) t su(SDCLKH _Data)

FMC_SDCLK period

Data input setup time t h(SDCLKH_Data) t d(SDCLKL_Add) t d(SDCLKL- SDNE) t h(SDCLKL_SDNE) t d(SDCLKL_SDNRAS) t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t h(SDCLKL_SDNCAS)

Data input hold time

Address valid time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

1. Guaranteed by characterization results.

Min

2Thclk -0.5

1.5

0.5

Symbol

Table 108. LPSDR SDRAM read timings (1)

Parameter t

W(SDCLK) t su(SDCLKH_Data) t h(SDCLKH_Data) t d(SDCLKL_Add) t d(SDCLKL_SDNE) t h(SDCLKL_SDNE) t d(SDCLKL_SDNRAS t h(SDCLKL_SDNRAS)

FMC_SDCLK period

Data input setup time

Data input hold time

Address valid time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time t d(SDCLKL_SDNCAS) t h(SDCLKL_SDNCAS)

SDNCAS valid time

SDNCAS hold time

1. Guaranteed by characterization results.

Min

2Thclk -0.5

4.5

Max

2Thclk +0.5

1.5

0.5

1.5

Max

2Thclk +0.5

1.5

Unit ns

194/228 DS11854 Rev 5

STM32F732xx STM32F733xx

FMC_SDCLK td(SDCLKL_AddR)

FMC_A[12:0]

Electrical characteristics

Figure 73. SDRAM write access waveforms

Row n td(SDCLKL_AddC) th(SDCLKL_AddR)

Col1 Col2 Coli th(SDCLKL_AddC)

Coln td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0] td(SDCLKL_NRAS)

FMC_SDNRAS th(SDCLKL_NRAS) td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS td(SDCLKL_NWE) th(SDCLKL_NWE)

FMC_SDNWE td(SDCLKL_Data)

FMC_D[31:0] td(SDCLKL_NBL)

FMC_NBL[3:0]

Data1 Data2 Datai th(SDCLKL_Data)

Datan

MS32752V2

Table 109. SDRAM write timings

(1) t w(SDCLK) t d(SDCLKL _Data

) t h(SDCLKL _Data) t d(SDCLKL_Add) t d(SDCLKL_SDNWE) t h(SDCLKL_SDNWE) t d(SDCLKL_ SDNE) t h(SDCLKL-_SDNE) t d(SDCLKL_SDNRAS) t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t d(SDCLKL_SDNCAS)

FMC_SDCLK period

Data output valid time

Data output hold time

Address valid time

SDNWE valid time

SDNWE hold time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

1. Guaranteed by characterization results.

0.5

2Thclk -0.5

0.5

2Thclk +0.5

1.5

DS11854 Rev 5 195/228

200

Electrical characteristics STM32F732xx STM32F733xx

Table 110. LPSDR SDRAM write timings (1) t w(SDCLK) t d(SDCLKL _Data

)

FMC_SDCLK period

Data output valid time t h(SDCLKL _Data) t d(SDCLKL_Add) t d(SDCLKL-SDNWE) t h(SDCLKL-SDNWE) t d(SDCLKL- SDNE) t h(SDCLKL- SDNE) t d(SDCLKL-SDNRAS) t h(SDCLKL-SDNRAS) t d(SDCLKL-SDNCAS) t d(SDCLKL-SDNCAS)

Data output hold time

Address valid time

SDNWE valid time

SDNWE hold time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

1. Guaranteed by characterization results.

2Thclk -0.5

2Thclk +0.5

1.5

0.5

Unless otherwise specified, the parameters given in

Table 111

and Table 112 for Quad-SPI

are derived from tests performed under the ambient temperature, f

AHB

frequency and V

supply voltage conditions summarized in Table 16: General operating conditions

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 20 pF

• Measurement points are done at CMOS levels: 0.5

ₓ V

Refer to Section 6.3.20: I/O port characteristics

for more details on the input/output alternate function characteristics.

Symbol

Fck1/t(CK)

Table 111. Quad-SPI characteristics in SDR mode (1)

Parameter Conditions Min Typ

Quad-SPI clock frequency

2.7 V ≤ V

<3.6 V

CL=20 pF

1.71 V<V

<3.6 V

CL=15 pF

Max

108

100

Unit

MHz

196/228 DS11854 Rev 5

STM32F732xx STM32F733xx Electrical characteristics

Table 111. Quad-SPI characteristics (continued)in SDR mode (1) (continued)

Symbol Parameter Conditions Min Typ Max Unit tw(CKH) tw(CKL)

Quad-SPI clock high and low time ts(IN) Data input setup time th(IN) Data input hold time

tv(OUT) Data output valid time th(OUT) Data output hold time

2.7 V<V

<3.6 V

1.71 V<V

<3.6 V

t(CK)/2 - 0.5

0.5

1. Guaranteed by characterization results.

1.5

t(CK)/2 + 0.5

2.5

Symbol

Table 112. Quad-SPI characteristics in DDR mode (1)

Parameter Conditions

Fck1/t(CK) Quad-SPI clock frequency

2.7 V<V

<3.6 V

CL=20 pF

1.8 V<V

<3.6 V

CL=15 pF

1.71 V<V

<3.6 V

CL=10 pF

Min

Typ

tw(CKH) tw(CKL) ts(IN), tsf(IN) thr(IN), thf(IN) tvr(OUT), tvf(OUT) thr(OUT), thf(OUT)

Quad-SPI clock high and low time

Data input setup time

Data input hold time

Data output valid time

Data output hold time

2.7 V<V

<3.6 V

1.71 V<V

<2 V

2.7 V<V

<3.6 V

1.71 V<V

<2 V

2.7 V<V

<3.6 V

1.71 V<V

<3.6 V

DHHC=0

DHHC=1

Pres=1, 2...

DHHC=0

DHHC=1

Pres=1, 2...

t(CK)/2 -

0.5

t(CK)/2 -

0.5

2.25

2.75

5.5

Thclk/2

+0.75

Thclk/2

9.5

Max

80 t(CK)/2 +

0.5

t(CK)/2 +

0.5

11.5

12.25

Thclk/2

+2.5

1. Guaranteed by characterization results.

Unit

MHz ns

DS11854 Rev 5 197/228

200

Electrical characteristics STM32F732xx STM32F733xx t r(CK)

Figure 74. Quad-SPI timing diagram - SDR mode t

(CK) t w(CKH) t w(CKL) t f(CK)

Clock

Data output

Data input t v(OUT) t h(OUT)

D0 t s(IN)

D1 t h(IN)

D2 t r(CK)

Figure 75. Quad-SPI timing diagram - DDR mode t

(CK) t w(CKH) t w(CKL) t f(CK)

MSv36878V1

Clock

Data output

Data input t vf(OUT) t hr(OUT)

D0 t vr(OUT)

D1 t sf(IN) t hf(IN)

D1 D2

D3 t hf(OUT)

D4 t sr(IN) t hr(IN)

D4 D5

MSv36879V1

6.3.32 SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in

Table 113 for the SDIO/MMC interface

are derived from tests performed under the ambient temperature, f

PCLK2 frequency and V