STMicroelectronics STM32F412RE Datasheet

Figure 4 shows the general block diagram of the STM32F412xE/G.

1024

Yes

CAN

Number of digital Filters for

Sigma-delta modulator

Number of channels

LCD parallel interface

Data bus size

GPIOs

114

12-bit ADC

Number of channels

10 16

Maximum CPU frequency

Operating voltage

100 MHz

1.7 to 3.6 V

Ambient temperatures: -40 to +85 °C / -40 to +105 °C/ -40 to +125 °C

Operating temperatures

Package

UFQ

FPN48

LQFP64

WLCSP64

Junction temperature: -40 to +130 °C

UFBGA

100

LQFP100

UFBGA

144

LQFP144

UFQ

FPN48

LQFP64

WLCSP

1. The FSMC can also be used to interface most graphic LCD controllers.

2. Limited application for the USART3 since RX is not available for the UFQFPN48.

UFBGA

100

LQFP100

UFBGA

144

LQFP144

DocID028087 Rev 7

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Description

2.1

STM32F412xE/G

Compatibility with STM32F4 series

The STM32F412xE/G are fully software and feature compatible with the STM32F4 series

(STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407)

The STM32F412xE/G can be used as drop-in replacement of the other STM32F4 products but some slight changes have to be done on the PCB board.

Figure 1. Compatible board design for LQFP100 package

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DocID028087 Rev 7

STM32F412xE/G Description

Figure 2. Compatible board design for LQFP64 package

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Description STM32F412xE/G

Figure 4. STM32F412xE/G block diagram

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1. The timers connected to APB2 are clocked from TIMxCLK up to 100 MHz, while the timers connected to APB1 are clocked from TIMxCLK up to 50 MHz.

18/201

DocID028087 Rev 7

STM32F412xE/G Functional overview

3.1 Arm

®

Cortex

SRAM

®

-M4 with FPU core with embedded Flash and

The Arm

Cortex

-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm

Cortex

-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.

Note:

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.

The STM32F412xE/G devices are compatible with all Arm tools and software.

Cortex

-M4 with FPU is binary compatible with Cortex

-M3.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm ® Cortex advantage of the Arm

-M4 with FPU processors. It balances the inherent performance

Cortex

-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies.

To release the processor full 125 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 100 MHz.

3.3 Batch Acquisition mode (BAM)

The Batch acquisition mode allows enhanced power efficiency during data batching. It enables data acquisition through any communication peripherals directly to memory using the DMA in reduced power consumption as well as data processing while the rest of the system is in low-power mode (including the flash and ART). For example in an audio system, a smart combination of PDM audio sample acquisition and processing from the

DFSDM directly to RAM (flash and ART

™

stopped) with the DMA using BAM followed by some very short processing from flash allows to drastically reduce the power consumption of the application. A dedicated application note (AN4515) describes how to implement the

STM32F412xE/G BAM to allow the best power efficiency.

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Functional overview

3.4 Memory protection unit

STM32F412xE/G

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 byte and the whole 4 Gbyte of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.5 Embedded Flash memory

The devices embed up to 1 Mbyte of Flash memory available for storing programs and data.

The Flash user area can be protected against reading by an entrusted code (Read

Protection, RDP) with different protection levels.

The flash user sectors can also be individually protected against write operation.

Furthermore the proprietary readout protection (PCROP) can also individually protect the flash user sectors against D-bus read accesses.

(Additional information can be found in the product reference manual).

To optimize the power consumption the Flash memory can also be switched off in Run or in

Sleep mode (see Section 3.21: Low-power modes ).

Two modes are available: Flash in Stop mode or in DeepSleep mode (trade off between power saving and startup time.

Before disabling the Flash, the code must be executed from the internal RAM.

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A one-time programmable area is available with16 OTP blocks of 32 bytes. Each block can be individually locked

(Additional information can be found in the product reference manual)

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

DocID028087 Rev 7

STM32F412xE/G Functional overview

All devices embed 256 Kbyte of system SRAM which can be accessed (read/write) at CPU clock speed with 0 wait states

3.9 Multi-AHB matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves

(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

Figure 5. Multi-AHB matrix

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3.10 DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth

(AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent.

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Functional overview STM32F412xE/G

The DMA can be used with the main peripherals:

• SPI and I

• I 2 C and I 2 CFMP

• USART

• General-purpose, basic and advanced-control timers TIMx

• SD/SDIO/MMC/eMMC host interface

• Quad-SPI

• ADC

• Digital Filter for sigma-delta modulator (DFSDM) with a separate stream for each filter.

The Flexible static memory controller (FSMC) includes a NOR/PSRAM memory controller. It features four Chip Select outputs supporting the following modes: SRAM, PSRAM and NOR

Flash memory.

The main functions are:

• 8-,16-bit data bus width

• Write FIFO

• Maximum FSMC_CLK frequency for synchronous accesses is 90 MHz.

LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.

All devices embed a Quad-SPI memory interface, which is a specialized communication interface targeting single, dual or quad-SPI Flash memories. It can work in direct mode through registers, external Flash status register polling mode and memory mapped mode.

Up to 256 Mbyte of external Flash memory are mapped. They can be accessed in 8, 16 or

32-bit mode. Code execution is also supported. The opcode and the frame format are fully programmable. Communication can be performed either in single data rate or dual data rate.

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STM32F412xE/G Functional overview

3.13 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the

Cortex

-M4 with FPU.

• Closely coupled NVIC gives low-latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving, higher-priority interrupts

• Support tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt latency.

The external interrupt/event controller consists of 21 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected to the 16 external interrupt lines.

3.15 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the three AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses and high-speed APB domains is 100 MHz. The maximum allowed frequency of the low-speed APB domain is 50 MHz.

The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I 2 S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.

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Functional overview STM32F412xE/G

At startup, boot pins are used to select one out of three boot options:

• Boot from user Flash memory

• Boot from system memory

• Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using one of the interface listed in the Table 3

or the USB OTG FS in device mode through

DFU (device firmware upgrade).

Package

UFQFPN48

WLCSP64

LQFP64

LQFP100

LQFP144

UFBGA100

UFBGA144

Table 3. Embedded bootloader interfaces

USART1

PA9/

PA10

USART2

PD6/

PD5

USART3

PB11/

PB10

I2C1

PB6/

PB7

I2C2

PF0/

PF1

I2C3

PA8/

PB4

I2C

FMP1

PB14/

PB15

SPI1

PA4/

PA5/

PA6/

PA7

SPI3

PA15/

PC10/

PC11/

PC12

SPI4

PE11/

PE12/

PE13/

PE14

CAN2

PB5/

PB13

USB

PA11

/P12

For more detailed information on the bootloader, refer to Application Note: AN2606,

STM32™ microcontroller system memory boot mode .

Note:

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• V

= 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor

(POR/PDR) disabled, provided externally through V

pins. Requires the use of an external power supply supervisor connected to the V

and NRST pins.

• V

SSA

, V

DDA

= 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL. V

DDA

and V decoupling technique.

SSA

must be connected to V

and V

, respectively, with

The V

DDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to

Section 3.18.2: Internal reset OFF ). Refer to

Table 4: Regulator ON/OFF and internal power supply supervisor availability

to identify the packages supporting this option.

• V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

is not present.

• V

DDUSB

can be connected either to VDD or an external independent power supply (3.0 to 3.6 V) for USB transceivers.

For example, when device is powered at 1.8 V, an independent power supply 3.3V can be connected to V

DDUSB

. When the V

DDUSB

is connected to a separated power supply,

DocID028087 Rev 7

STM32F412xE/G Functional overview it is independent from V

DD first to disappear.

or V

DDA

but it must be the last supply to be provided and the

The following conditions VDDUSB must be respected:

– During power-on phase (V

< V

DD_MIN

), V

DDUSB

should be always lower than

– During power-down phase (V

< V

DD_MIN

), V

DDUSB

should be always lower than

– V

DDUSB

rising and falling time rate specifications must be respected.

– In operating mode phase, V

DDUSB

could be lower or higher than VDD:

– If USB is used, the associated GPIOs powered by V

DDUSB between V

DDUSB_MIN and V

DDUSB_MAX

are operating

– If USB is not used, the associated GPIOs powered by V

DDUSB between V

DD_MIN

and V

DD_MAX

are operating

Figure 6. V

DDUSB

connected to an external independent power supply

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Functional overview STM32F412xE/G

This feature is available for V

operating voltage range 1.8 V to 3.6 V.

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other package, the power supply supervisor is always enabled.

The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes.

The device remains in reset mode when V

BOR

is below a specified threshold, V

, without the need for an external reset circuit.

POR/PDR

The device also features an embedded programmable voltage detector (PVD) that monitors the V

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be generated when V higher than the V

PVD

DDA

drops below the V

PVD

threshold and/or when V

DDA

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to low.

An external power supply supervisor should monitor V

DD mode when V

and should set the device in reset

is below 1.7 V. NRST should be connected to this external power supply

supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset

OFF .

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STM32F412xE/G Functional overview

Figure 7. Power supply supervisor interconnection with internal reset OFF (1)

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1. The PRD_ON pin is available only on WLCSP64, UFBGA100, UFBGA144 and LQFP144 packages.

A comprehensive set of power-saving mode allows to design low-power applications.

When the internal reset is OFF, the following integrated features are no longer supported:

• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.

• The brownout reset (BOR) circuitry must be disabled.

• The embedded programmable voltage detector (PVD) is disabled.

• V

BAT

functionality is no more available and VBAT pin should be connected to V

The regulator has three operating modes:

– Main regulator mode (MR)

– Low power regulator (LPR)

– Power-down

On packages embedding the BYPASS_REG pin, the regulator is enabled by holding

BYPASS_REG low. The WLCSP64 is available in two versions, one with the regulator internally enabled and one with the regulator internally disabled. On all other packages, the regulator is always enabled.

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Functional overview STM32F412xE/G

There are three power modes configured by software when the regulator is ON:

• MR is used in the nominal regulation mode (With different voltage scaling in Run mode)

In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption.

• LPR is used in the Stop mode

The LP regulator mode is configured by software when entering Stop mode.

• Power-down is used in Standby mode.

The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost.

Depending on the package, one or two external ceramic capacitors should be connected on the V CAP_1 and V CAP_2 pins. The V CAP_2 pin is only available for the 100 pins and 144 pins packages.

All packages have the regulator ON feature.

The regulator is disabled by holding BYPASS_REG pin high.

This feature is available only on UFBGA100 and UFBGA144 packages, which feature the

BYPASS_REG pin. The WLCSP64 is available in two versions, one with a fixed enabled

regulator and one with a fixed disabled regulator (see Table 4: Regulator ON/OFF and internal power supply supervisor availability

and

Section 8: Part numbering ). The regulator

OFF mode allows to supply externally a V pins.

voltage source through V

CAP_1

and V

CAP_2

Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency.

The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors.

When the regulator is OFF, there is no more internal monitoring on V

12 supply supervisor should be used to monitor the V

. An external power

of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V

power domain.

In regulator OFF mode, the following features are no more supported:

• PA0 cannot be used as a GPIO pin since it allows to reset a part of the V

12 domain which is not reset by the NRST pin.

logic power

• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required.

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STM32F412xE/G

Note:

Figure 8. Regulator OFF

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The following conditions must be respected:

• V

should always be higher than V between power domains.

CAP_1

and V

CAP_2 to avoid current injection

• If the time for V

CAP_1

and V and V

CAP_2 reach V

CAP_2 to reach V

12 minimum value is faster than the time for

to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V

CAP_1 minimum value and until V

reaches 1.7 V (see Figure 9

• Otherwise, if the time for V

CAP_1 than the time for V

Figure 10

and V

CAP_2 to reach V

12 minimum value is slower

to reach 1.7 V, then PA0 could be asserted low externally (see

• If V

CAP_1

and V

CAP_2

go below V

12 minimum value and V reset must be asserted on PA0 pin.

is higher than 1.7 V, then a

The minimum value of V

12 depends on the maximum frequency targeted in the application.

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Functional overview STM32F412xE/G

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Figure 9. Startup in regulator OFF: slow V

DD power-down reset risen after V

CAP_1

CAP_2

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Figure 10. Startup in regulator OFF mode: fast V

DD power-down reset risen before V

CAP_1

CAP_2

slope stabilization

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1. This figure is valid whatever the internal reset mode (ON or OFF).

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STM32F412xE/G Functional overview

3.19.3 Regulator ON/OFF and internal reset ON/OFF availability

Table 4. Regulator ON/OFF and internal power supply supervisor availability

Package Regulator ON Regulator OFF

Power supply supervisor ON

Power supply supervisor OFF

UFQFPN48

WLCSP64

WLCSP64 option P

(1)

LQFP64

LQFP100

LQFP144

UFBGA100

UFBGA144

Yes

PDR_ON set to V

Yes

PDR_ON set to V

Yes

BYPASS_REG set to

VSS

Yes

BYPASS_REG set to

VDD

Yes

BYPASS_REG set to

VSS

Yes

BYPASS_REG set to

VDD

Yes

PDR_ON set to VDD

1. Refer to Section 8: Part numbering .

Yes

PDR_ON set to V

Yes

PDR_ON set to V

Yes

PDR_ON set to V

The backup domain includes:

• The real-time clock (RTC)

• 20 backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC features a reference clock detection, a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from

Stop and Standby modes. The sub-seconds value is also available in binary format.

It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power

RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation.

Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.

A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

The backup registers are 32-bit registers used to store 80 byte of user application data when V

power is not present. Backup registers are not reset by a system, a power reset,

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Functional overview STM32F412xE/G or when the device wakes up from the Standby mode (see

Section 3.21: Low-power modes ).

Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.

The RTC and backup registers are supplied through a switch that is powered either from the

supply when present or from the V

BAT

pin.

The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

To further reduce the power consumption, the Flash memory can be switched off before entering in Sleep mode. Note that this requires a code execution from the RAM.

• Stop mode

The Stop mode achieves the lowest power consumption while retaining the contents of

SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm/ wakeup/ tamper/ time stamp events).

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, the SRAM and register contents are lost except for registers in the backup domain when selected.

The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on one of the WKUP pins, or an RTC alarm/ wakeup/ tamper/time stamp event occurs.

Standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power.

3.22 V

BAT

operation

The VBAT pin allows to power the device V

BAT super-capacitor, or from V present.

domain from an external battery, an external when no external battery and an external super-capacitor are

Note:

BAT

operation is activated when V

is not present.

The VBAT pin supplies the RTC and the backup registers.

When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from V

BAT

operation. When PDR_ON pin is not connected to V

(internal

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STM32F412xE/G Functional overview

Reset OFF), the V

BAT to V

functionality is no more available and VBAT pin should be connected

3.23 Timers and watchdogs

The devices embed two advanced-control timer, ten general-purpose timers, two basic timers, two watchdog timers and one SysTick timer.

All timer counters can be frozen in debug mode.

Table 5 compares the features of the advanced-control and general-purpose timers.

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Functional overview STM32F412xE/G

Timer type

Advance d-control

General purpose

Basic timers

Timer

TIM1,

TIM8

TIM2,

TIM5

TIM3,

TIM4

TIM9

TIM10,

TIM11

TIM12

TIM13,

TIM14

TIM6,

TIM7

Table 5. Timer feature comparison

Counter resolution

Counter type

Prescaler factor

DMA request generation

Capture/ compare channels

Complementary output

Max. interface clock

(MHz)

Max. timer clock

(MHz)

16-bit

32-bit

16-bit

Up,

Down,

Up/down

Any integer between 1 and

65536

Up,

Down,

Up/down

Any integer between 1 and

65536

Up,

Down,

Up/down

Any integer between 1 and

65536

Any integer between 1 and

65536

Any integer between 1 and

65536

Any integer between 1 and

65536

Any integer between 1 and

65536

Any integer between 1 and

65536

Yes

100

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The advanced-control timers (TIM1/8) can be seen as three-phase PWM generator multiplexed on 4 independent channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete generalpurpose timers. Their 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge- or center-aligned modes)

• One-pulse mode output

If configured as standard 16-bit timers, they have the same features as the general-purpose

TIMx timers. If configured as a 16-bit PWM generator, they have full modulation capability

(0-100%).

The advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

TIM1 and TIM8 support independent DMA request generation.

There are ten synchronizable general-purpose timers embedded in the STM32F412xE/G

(see Table 5 for differences).

• TIM2, TIM3, TIM4, TIM5

The STM32F412xE/G devices include 4 full-featured general-purpose timers: TIM2.

TIM3, TIM4 and TIM5. TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler while TIM3 and TIM4 timers are based on a 16- bit auto-reload up/downcounter plus a 16-bit prescaler. They all features four independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 15 input capture/output compare/PWMs

TIM2. TIM3, TIM4 and TIM5 general-purpose timers can operate together or in conjunction with the other general-purpose timers and TIM1 advanced-control timer via the Timer Link feature for synchronization or event chaining.

Any of these general-purpose timers can be used to generate PWM output.

TIM2. TIM3, TIM4 and TIM5 channels have independent DMA request generation.

They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.

• TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM10, TIM11, TIM13 and TIM14 feature one independent channel, whereas TIM9 and

TIM12 have two independent channels for input capture/output compare, PWM or onepulse mode output. They can be synchronized with TIM2. TIM3, TIM4 and TIM5 fullfeatured general-purpose timers or used as simple time bases.

3.23.3 Basic timer (TIM6, TIM7)

TIM6 and TIM7 timers are basic 16-bit timers. They support independent DMA request generation.

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Functional overview STM32F412xE/G

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features:

• A 24-bit downcounter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0

• Programmable clock source.

circuit interface (I 2 C)

The devices feature up to four I 2 C bus interfaces which can operate in multimaster and slave modes:

• One I

C interface supports the Standard mode (up to 100 kHz), Fast-mode (up to

400 kHz) modes and Fast-mode plus (up to 1 MHz).

• Three I 2 C interfaces support the Standard mode (up to 100 KHz) and the Fast mode

(up to 400 KHz). Their frequency can be increased up to 1 MHz. For more details on the complete solution, refer to the nearest STMicroelectronics sales office.

All I 2 C interfaces features 7/10-bit addressing mode and 7-bit addressing mode (as slave) and embed a hardware CRC generation/verification.

They can be served by DMA and they support SMBus 2.0/PMBus.

The devices also include programmable analog and digital noise filters (see

Table 6

Pulse width of suppressed spikes

Table 6. Comparison of I2C analog and digital filters

Analog filter Digital filter

≥ 50 ns Programmable length from 1 to 15 I2C peripheral clocks

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(USART)

The devices embed four universal synchronous/asynchronous receiver transmitters

(USART1, USART2, USART3 and USART6).

These four interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. USART1 and USART6 interfaces are able to communicate at speeds of up to 12.5 Mbit/s. USART2 and USART3 interfaces communicate at up to 6.25 bit/s.

All USART interfaces provide hardware management of the CTS and RTS signals, Smart

Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller.

USART name

Standard features

Modem

(RTS/CTS)

Table 7. USART feature comparison

LIN

SPI master irDA

Smartcard

(ISO 7816)

Max. baud rate in Mbit/s

(oversampling by 16)

Max. baud rate in Mbit/s

(oversampling by 8)

APB mapping

USART1

USART2

USART3

(1)

USART6

6.25

3.12

6.25

12.5

6.25

12.5

APB2

(max.

100 MHz)

APB1

(max.

50 MHz)

APB1

(max.

50 MHz)

APB2

(max.

100 MHz)

1. The RX is not available for the UFQFPN48 package.

3.26 Serial peripheral interface (SPI)

The devices feature five SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4 and SPI5 can communicate at up to 50 Mbit/s, SPI2 and

SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the

DMA controller.

The SPI interfaces can be configured to operate in TI mode for communications in master mode and slave mode.

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Functional overview STM32F412xE/G

3.27 Inter-integrated sound (I

2 S)

Five standard I

S interfaces (multiplexed with SPI1 to SPI5) are available. They can be operated in master or slave mode, in simplex communication mode, and full duplex mode for I2S2 and I2S3. All I

S interfaces can be configured to operate with a 16-/32-bit resolution as an input or output channel. I2Sx audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I

S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

All I

Sx interfaces can be served by the DMA controller.

3.28 Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I 2 S applications. It allows to achieve error-free I 2 S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals.

Different sources can be selected for the I2S master clock of the APB1 and the I2S master clock of the APB2. This gives the flexibility to work with two different audio sampling frequencies. The different possible sources are the main PLL, the PLLI2S, HSE or HSI clocks or an external clock provided through a pin (external PLL or Codec output)

The PLLI2S configuration can be modified to manage an I 2 S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz.

3.29 Digital filter for sigma-delta modulators (DFSDM)

The device embeds one DFSDM with 2 digital filters modules and 4 external input serial channels (transceivers) or alternately 2 internal parallel inputs support.

The amount of filters defines the number of conversions which can be performed simultaneously.

The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse

Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware. DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM).

DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution.

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The DFSDM peripheral supports:

• 4 multiplexed input digital serial channels:

– configurable SPI interface to connect various SD modulator(s)

– configurable Manchester coded 1 wire interface support

– PDM (Pulse Density Modulation) microphone input support

– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)

– clock output for SD modulator(s): 0...20 MHz

• alternative inputs from 4 internal digital parallel channels (up to 16 bit input resolution):

– internal sources: device memory data streams (DMA)

• 2 digital filter modules with adjustable digital signal processing:

– Sinc x filter: filter order/type (1...5), oversampling ratio (up to 1...1024)

– integrator: oversampling ratio (1...256)

• up to 24-bit output data resolution, signed output data format

• automatic data offset correction (offset stored in register by user)

• continuous or single conversion

• start-of-conversion triggered by

– software trigger

– internal timers

– external events

– start-of-conversion synchronously with first digital filter module (DFSDM1FLT0)

• analog watchdog feature:

– low value and high value data threshold registers

– dedicated configurable Sinc x digital filter (order = 1...3, oversampling ratio = 1...32

– input from digital output data or from selected input digital serial channels

– continuous monitoring independently from standard conversion

• short circuit detector to detect saturated analog input values (bottom and top range):

– up to 8-bit counter to detect 1...256 consecutive 0’s or 1’s on serial data stream

– monitoring continuously each input serial channel

• break signal generation on analog watchdog event or on short circuit detector event

• extremes detector:

– storage of minimum and maximum values of final conversion data

– refreshed by software

• DMA capability to read the final conversion data

• interrupts: end of conversion, overrun, analog watchdog, short circuit input serial channel clock absence

• “regulator” or injected” conversions:

– “regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions

– “injected” conversions for precise timing and with high conversion priority.

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Functional overview STM32F412xE/G

3.30 Secure digital input/output interface (SDIO)

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System

Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory

Card Specification Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.

In addition to SD/SDIO/MMC/eMMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1.

3.31 Controller area network (bxCAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1

Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive

FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

CAN is used). 256 byte of SRAM are allocated for each CAN.

3.32 Universal serial bus on-the-go full-speed (USB_OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The Battery Charging Detection

(BCD) can detect and identify the type of port, it is connected to (standard USB or charger).

The type of charging is also detected: Dedicated Charging Port (DCP), Charging

Downstream Port (CDP) and Standard Downstream Port (SDP). Some packages provide a dedicated USB power rail allowing a different supply for the USB and for the rest of the chip.

For instance the chip can be powered with the minimum specified supply and the USB running at the level defined by the standard. The major features are:

• Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing

• Supports the session request protocol (SRP) and host negotiation protocol (HNP)

• 6 bidirectional endpoints

• 12 host channels with periodic OUT support

• HNP/SNP/IP inside (no need for any external resistor)

• For OTG/Host modes, a power switch is needed in case bus-powered devices are connected

• Link Power Management (LPM)

• Battery Charging Detection (BCD) supporting DCP, CDP and SDP

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3.33 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission.

The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers.

Fast I/O handling allowing maximum I/O toggling up to 100 MHz.

3.35 Analog-to-digital converter (ADC)

One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,

TIM2, TIM3, TIM4 or TIM5 timer.

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the ADC_IN18 input channel which is used to convert the sensor output voltage into a digital value. Refer to the reference manual for additional information.

As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used.

3.37 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with

SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

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Functional overview STM32F412xE/G

3.38 Embedded Trace Macrocell™

The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32F412xE/G through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using any high-speed channel available. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell operates with third party debugger software tools.

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4 Pinouts and pin description

Pinouts and pin description

Figure 11. STM32F412xE/G WLCSP64 pinout

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Pinouts and pin description

4.2 UFQFPN48 pinout description

Figure 12. STM32F412xE/G UFQFPN48 pinout

STM32F412xE/G

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4.3 LQFP64 pinout description

Pinouts and pin description

Figure 13. STM32F412xE/G LQFP64 pinout

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Pinouts and pin description

4.4 LQFP100 pinout description

Figure 14. STM32F412xE/G LQFP100 pinout

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4.5 LQFP144 pinout description

Figure 15. STM32F412xE/G LQFP144 pinout

Pinouts and pin description

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Pinouts and pin description

4.6 UFBGA100 pinout description

Figure 16. STM32F412xE/G UFBGA100 pinout

STM32F412xE/G

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STM32F412xE/G Pinouts and pin description

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Figure 17. STM32F412xE/G UFBGA144 pinout

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Name

Pin name

Pin type

I/O structure

Notes

Table 8. Legend/abbreviations used in the pinout table

Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

NRST

Input/ output pin

5 V tolerant I/O

Standard 3.3 V I/O

Dedicated BOOT0 pin

Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

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Pinouts and pin description STM32F412xE/G

Name

Alternate functions

Table 8. Legend/abbreviations used in the pinout table (continued)

Abbreviation Definition

Functions selected through GPIOx_AFR registers

Additional functions

Functions directly selected/enabled through peripheral registers

Pin Number

Table 9. STM32F412xE/G pin definition

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

PE2

PE3

PE4

PE5

PE6

I/O

1 1 B7 6 E2 C2 6

2 2 B8 7 C1 A1 7

3 3 C8 8 D1 B1 8

VBAT

PC13

PC14-

OSC32_IN

I/O

(2)(3)(4)

TRACECLK,

SPI4_SCK/I2S4_CK,

SPI5_SCK/I2S5_CK,

QUADSPI_BK1_IO2,

FSMC_A23,

EVENTOUT

TRACED0, FSMC_A19,

EVENTOUT

TRACED1,

SPI4_NSS/I2S4_WS,

SPI5_NSS/I2S5_WS,

DFSDM1_DATIN3,

FSMC_A20,

EVENTOUT

TRACED2, TIM9_CH1,

SPI4_MISO,

SPI5_MISO,

DFSDM1_CKIN3,

FSMC_A21,

EVENTOUT

TRACED3, TIM9_CH2,

SPI4_MOSI/I2S4_SD,

SPI5_MOSI/I2S5_SD,

FSMC_A22,

EVENTOUT

VBAT

TAMP_1

EVENTOUT OSC32_IN

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Pin Number

Table 9. STM32F412xE/G pin definition (continued)

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

C1 9

C3 10

PC15-

OSC32_

OUT

PF0

I/O

C4 11

D4 12

PF1

PF2

I/O

E4 15

10 F2 D2 16

11 G2 D3 17

PF3

PF4

PF5

VSS

VDD

PF6

PF7

PF8

PF9

I/O

G1 22 PF10 I/O

5 5 D8 12 F1 D1 23

6 6 E8 13 G1 E1 24

7 7 D7 14 H2 F1 25

PH0 -

OSC_IN

PH1 -

OSC_OUT

NRST

I/O

RST

(2)(4)

EVENTOUT

OSC32_

OUT

I2C2_SDA, FSMC_A0,

EVENTOUT

I2C2_SCL, FSMC_A1,

EVENTOUT

I2C2_SMBA, FSMC_A2,

EVENTOUT

TIM5_CH1, FSMC_A3,

EVENTOUT

TIM5_CH2, FSMC_A4,

EVENTOUT

TIM5_CH3, FSMC_A5,

EVENTOUT

TRACED0, TIM10_CH1,

QUADSPI_BK1_IO3,

EVENTOUT

TRACED1, TIM11_CH1,

QUADSPI_BK1_IO2,

EVENTOUT

TIM13_CH1,

QUADSPI_BK1_IO0,

EVENTOUT

TIM14_CH1,

QUADSPI_BK1_IO1,

EVENTOUT

TIM1_ETR, TIM5_CH4,

EVENTOUT

OSC_IN

The input voltage measurement on a pin of the device is described in Figure 20 .

EVENTOUT

OSC_OUT

NRST

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Pinouts and pin description STM32F412xE/G

Pin Number

Table 9. STM32F412xE/G pin definition (continued)

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

8 D5 15 H1 H1 26

9 F8 16 J2 H2 27

10 E7 17 J3 H3 28 PC2 I/O FT

11 D6 18 K2 H4 29

10 14 E6 23 L2

12 16 H8 25 K3

J2 34

11 15 G7 24 M2 K2 35

L2 36

PC0

PC1

PC3

12 G8 20

VDD

VSSA/

VREF

VSSA

13 F7

VREF-

VDDA/

VREF+

L1 32 VREF+

22 M1 M1 33 VDDA

PA0

PA1

PA2

I/O

EVENTOUT

ADC1_10,

WKUP2

ADC1_11,

WKUP3

SPI2_MISO,

I2S2ext_SD,

DFSDM1_CKOUT,

FSMC_NWE,

EVENTOUT

SPI2_MOSI/I2S2_SD,

FSMC_A0, EVENTOUT

ADC1_12

ADC1_13

TIM2_CH1/TIM2_ETR,

TIM5_CH1, TIM8_ETR,

USART2_CTS,

EVENTOUT

TIM2_CH2, TIM5_CH2,

SPI4_MOSI/I2S4_SD,

USART2_RTS,

QUADSPI_BK1_IO3,

EVENTOUT

TIM2_CH3, TIM5_CH3,

TIM9_CH1, I2S2_CKIN,

USART2_TX,

FSMC_D4/FSMC_DA4,

EVENTOUT

ADC1_0,

WKUP1

ADC1_1

ADC1_2

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STM32F412xE/G Pinouts and pin description

Pin Number

Table 9. STM32F412xE/G pin definition (continued)

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

13 17 F6 26 L3 M2 37

14 20 G6 29 M3 J3 40

15 21 F5 30 K4 K3 41

16 22 H6 31 L4 L3 42

17 23 E5 32 M4 M3 43

PA3

19 H7 28 -

G4 38

H5 -

F4 39

VSS

BYPASS_

REG

VDD

PA4

PA5

PA6

PA7

I/O

24 E4 33 K5 J4 44 PC4 I/O FT

TIM2_CH4, TIM5_CH4,

TIM9_CH2, I2S2_MCK,

USART2_RX,

FSMC_D5/FSMC_DA5,

EVENTOUT

ADC1_3

SPI1_NSS/I2S1_WS,

SPI3_NSS/I2S3_WS,

USART2_CK,

DFSDM1_DATIN1,

FSMC_D6/FSMC_DA6,

EVENTOUT

TIM2_CH1/TIM2_ETR,

TIM8_CH1N,

SPI1_SCK/I2S1_CK,

DFSDM1_CKIN1,

FSMC_D7/FSMC_DA7,

EVENTOUT

TIM1_BKIN, TIM3_CH1,

TIM8_BKIN,

SPI1_MISO, I2S2_MCK,

TIM13_CH1,

QUADSPI_BK2_IO0,

SDIO_CMD,

EVENTOUT

TIM1_CH1N,

TIM3_CH2,

TIM8_CH1N,

SPI1_MOSI/I2S1_SD,

TIM14_CH1,

QUADSPI_BK2_IO1,

EVENTOUT

I2S1_MCK,

QUADSPI_BK2_IO2,

FSMC_NE4,

EVENTOUT

ADC1_4

ADC1_5

ADC1_6

ADC1_7

ADC1_14

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Pinouts and pin description STM32F412xE/G

Pin Number

Table 9. STM32F412xE/G pin definition (continued)

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

25 G5 34 L5 K4 45

18 26 H5 35 M5 L4 46

19 27 F4 36 M6 M4 47

PC5

PB0

PB1

I/O

20 28 G4 37 L6 J5 48

M5 49

L5 50

G5 52

K5 53

M6 54

L6 55

PF14

PF15

PG0

PG1

PB2

PF11

PF12

VSS

VDD

PF13

I/O

I2CFMP1_SMBA,

USART3_RX,

QUADSPI_BK2_IO3,

FSMC_NOE,

EVENTOUT

TIM1_CH2N,

TIM3_CH3,

TIM8_CH2N,

SPI5_SCK/I2S5_CK,

EVENTOUT

TIM1_CH3N,

TIM3_CH4,

TIM8_CH3N,

SPI5_NSS/I2S5_WS,

DFSDM1_DATIN0,

QUADSPI_CLK,

EVENTOUT

DFSDM1_CKIN0,

QUADSPI_CLK,

EVENTOUT

TIM8_ETR, EVENTOUT

TIM8_BKIN, FSMC_A6,

EVENTOUT

I2CFMP1_SMBA,

FSMC_A7, EVENTOUT

I2CFMP1_SCL,

FSMC_A8, EVENTOUT

I2CFMP1_SDA,

FSMC_A9, EVENTOUT

CAN1_RX, FSMC_A10,

EVENTOUT

CAN1_TX, FSMC_A11,

EVENTOUT

ADC1_15

ADC1_8

ADC1_9

BOOT1

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STM32F412xE/G Pinouts and pin description

Pin Number

Table 9. STM32F412xE/G pin definition (continued)

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

38 M7 M7 58 PE7 I/O FT

39 L7 L7 59 PE8 I/O FT

40 M8 K7 60

G6 62

PE9

VSS

VDD

I/O

41 L8 J7 63 PE10 I/O

42 M9 H8 64 PE11 I/O FT

43 L9 J8 65 PE12 I/O FT

44 M10 K8 66 PE13 I/O FT

45 M11 L8 67 PE14 I/O FT

TIM1_ETR,

DFSDM1_DATIN2,

QUADSPI_BK2_IO0,

FSMC_D4/FSMC_DA4,

EVENTOUT

TIM1_CH1N,

DFSDM1_CKIN2,

QUADSPI_BK2_IO1,

FSMC_D5/FSMC_DA5,

EVENTOUT

TIM1_CH1,

DFSDM1_CKOUT,

QUADSPI_BK2_IO2,

FSMC_D6/FSMC_DA6,

EVENTOUT

TIM1_CH2N,

QUADSPI_BK2_IO3,

FSMC_D7/FSMC_DA7,

EVENTOUT

TIM1_CH2,

SPI4_NSS/I2S4_WS,

SPI5_NSS/I2S5_WS,

FSMC_D8/FSMC_DA8,

EVENTOUT

TIM1_CH3N,

SPI4_SCK/I2S4_CK,

SPI5_SCK/I2S5_CK,

FSMC_D9/FSMC_DA9,

EVENTOUT

TIM1_CH3, SPI4_MISO,

SPI5_MISO,

FSMC_D10/FSMC_DA1

0, EVENTOUT

TIM1_CH4,

SPI4_MOSI/I2S4_SD,

SPI5_MOSI/I2S5_SD,

FSMC_D11/FSMC_DA1

1, EVENTOUT

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Pinouts and pin description STM32F412xE/G

Pin Number

Table 9. STM32F412xE/G pin definition (continued)

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

46 M12 M8 68 PE15 I/O FT

21 29 H4 47 L10 M9 69 PB10 I/O FT

K9 M10 70 PB11 I/O

22 30 H3 48 L11 H7 71 VCAP_1

23 31 H2 49 F12 H6 VSS

24 32 H1 50 G12 G7 72 VDD

25 33 G3 51 L12 M11 73 PB12 I/O FT

26 34 G2 52 K12 M12 74 PB13 I/O FT

TIM1_BKIN,

FSMC_D12/FSMC_DA1

2, EVENTOUT

TIM2_CH3, I2C2_SCL,

SPI2_SCK/I2S2_CK,

I2S3_MCK,

USART3_TX,

I2CFMP1_SCL,

SDIO_D7, EVENTOUT

TIM2_CH4, I2C2_SDA,

I2S2_CKIN,

USART3_RX,

EVENTOUT

TIM1_BKIN,

I2C2_SMBA,

SPI2_NSS/I2S2_WS,

SPI4_NSS/I2S4_WS,

SPI3_SCK/I2S3_CK,

USART3_CK,

CAN2_RX,

DFSDM1_DATIN1,

FSMC_D13/FSMC_DA1

3, EVENTOUT

TIM1_CH1N,

I2CFMP1_SMBA,

SPI2_SCK/I2S2_CK,

SPI4_SCK/I2S4_CK,

USART3_CTS,

CAN2_TX,

DFSDM1_CKIN1,

EVENTOUT

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STM32F412xE/G Pinouts and pin description

Pin Number

Table 9. STM32F412xE/G pin definition (continued)

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

27 35 G1 53 K11 L11 75 PB14 I/O FT

28 36 F2 54 K10 L12 76 PB15 I/O FT

55 L9 77 PD8 I/O FT

56 K8 K9 78 PD9

57 J12 J9 79 PD10

I/O

58 J11 H9 80 PD11 I/O FT

59 J10 L10 81 PD12 I/O FT

TIM1_CH2N,

TIM8_CH2N,

I2CFMP1_SDA,

SPI2_MISO,

I2S2ext_SD,

USART3_RTS,

DFSDM1_DATIN2,

TIM12_CH1,

FSMC_D0/FSMC_DA0,

SDIO_D6, EVENTOUT

RTC_50Hz,

TIM1_CH3N,

TIM8_CH3N,

I2CFMP1_SCL,

SPI2_MOSI/I2S2_SD,

DFSDM1_CKIN2,

TIM12_CH2, SDIO_CK,

EVENTOUT

USART3_TX,

FSMC_D13/

FSMC_DA13,

EVENTOUT

USART3_RX,

FSMC_D14/FSMC_DA1

4, EVENTOUT

USART3_CK,

FSMC_D15/FSMC_DA1

5, EVENTOUT

I2CFMP1_SMBA,

USART3_CTS,

QUADSPI_BK1_IO0,

FSMC_A16,

EVENTOUT

TIM4_CH1,

I2CFMP1_SCL,

USART3_RTS,

QUADSPI_BK1_IO1,

FSMC_A17,

EVENTOUT

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Pinouts and pin description STM32F412xE/G

Pin Number

Table 9. STM32F412xE/G pin definition (continued)

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

60 H12 K10 82

G8 83

F8 84

PD13

VSS

VDD

I/O

61 H11 K11 85 PD14 I/O

62 H10 K12 86 PD15 I/O FT

J12

J11

J10

H12 90

PG2

PG3

PG4

PG5

H11

H10

PG6

PG7

I/O

G11 93 PG8 I/O

F10 -

VSS

VDD

C11 95 VDDUSB S

I/O

TIM4_CH2,

I2CFMP1_SDA,

QUADSPI_BK1_IO3,

FSMC_A18,

EVENTOUT

TIM4_CH3,

I2CFMP1_SCL,

FSMC_D0/FSMC_DA0,

EVENTOUT

TIM4_CH4,

I2CFMP1_SDA,

FSMC_D1/FSMC_DA1,

EVENTOUT

FSMC_A12,

EVENTOUT

FSMC_A13,

EVENTOUT

FSMC_A14,

EVENTOUT

FSMC_A15,

EVENTOUT

QUADSPI_BK1_NCS,

EVENTOUT

USART6_CK,

EVENTOUT

USART6_RTS,

EVENTOUT

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STM32F412xE/G Pinouts and pin description

Pin Number

Table 9. STM32F412xE/G pin definition (continued)

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

37 F1 63 E12 G12 96 PC6 I/O FT

38 E1 64 E11 F12 97 PC7 I/O FT

39 F3 65 E10 F11 98 PC8 I/O FT

40 E2 66 D12 E11 99 PC9 I/O FT

29 41 E3 67 D11 E12 100 PA8 I/O FT

30 42 D1 68 D10 D12 101 PA9 I/O FT

31 43 D2 69 C12 D11 102 PA10 I/O FT

TIM3_CH1, TIM8_CH1,

I2CFMP1_SCL,

I2S2_MCK,

DFSDM1_CKIN3,

USART6_TX,

FSMC_D1/FSMC_DA1,

SDIO_D6, EVENTOUT

TIM3_CH2, TIM8_CH2,

I2CFMP1_SDA,

SPI2_SCK/I2S2_CK,

I2S3_MCK,

USART6_RX,

DFSDM1_DATIN3,

SDIO_D7, EVENTOUT

TIM3_CH3, TIM8_CH3,

USART6_CK,

QUADSPI_BK1_IO2,

SDIO_D0, EVENTOUT

MCO_2, TIM3_CH4,

TIM8_CH4, I2C3_SDA,

I2S2_CKIN,

QUADSPI_BK1_IO0,

SDIO_D1, EVENTOUT

MCO_1, TIM1_CH1,

I2C3_SCL,

USART1_CK,

USB_FS_SOF,

SDIO_D1, EVENTOUT

TIM1_CH2,

I2C3_SMBA,

USART1_TX,

USB_FS_VBUS,

SDIO_D2, EVENTOUT

TIM1_CH3,

SPI5_MOSI/I2S5_SD,

USART1_RX,

USB_FS_ID,

EVENTOUT

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Pinouts and pin description STM32F412xE/G

Pin Number

Table 9. STM32F412xE/G pin definition (continued)

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

32 44 D3 70 B12 C12 103 PA11 I/O FT

33 45 C1 71 A12 B12 104 PA12 I/O FT

34 46 C2 72 A11 A12 105 PA13

73 C11 G9 106 VCAP_2

35 47 B1 74 F11 G10 107 VSS

36 48 75 G11

A1 -

F9 108

VDD

37 49 B2 76 A10 A11 109 PA14

I/O

38 50 A2 77 A9 A10 110 PA15 I/O FT

51 C3 78 B11 B11 111 PC10 I/O FT

52 B3 79 C10 B10 112 PC11 I/O FT

TIM1_CH4, SPI4_MISO,

USART1_CTS,

USART6_TX,

CAN1_RX,

USB_FS_DM,

EVENTOUT

TIM1_ETR, SPI5_MISO,

USART1_RTS,

USART6_RX,

CAN1_TX,

USB_FS_DP,

EVENTOUT

JTMS-SWDIO,

EVENTOUT

JTCK-SWCLK,

EVENTOUT

JTDI,

TIM2_CH1/TIM2_ETR,

SPI1_NSS/I2S1_WS,

SPI3_NSS/I2S3_WS,

USART1_TX,

EVENTOUT

SPI3_SCK/I2S3_CK,

USART3_TX,

QUADSPI_BK1_IO1,

SDIO_D2, EVENTOUT

I2S3ext_SD,

SPI3_MISO,

USART3_RX,

QUADSPI_BK2_NCS,

FSMC_D2/FSMC_DA2,

SDIO_D3, EVENTOUT

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STM32F412xE/G Pinouts and pin description

Pin Number

Table 9. STM32F412xE/G pin definition (continued)

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

53 A3 80 B10 C10 113 PC12 I/O FT

81 C9 E10 114

82 B9 D10 115 PD1

54 A4 83 C8 E9 116 PD2 I/O FT

84 B8 D9 117 PD3 I/O FT

85 B7 C9 118 PD4 I/O FT

B9 119

E7 120

F7 121

87 B6 A8 122

PD0

PD5

VSS

VDD

PD6

I/O

88 A5 A9 123 PD7 I/O FT

SPI3_MOSI/I2S3_SD,

USART3_CK,

FSMC_D3/FSMC_DA3,

SDIO_CK, EVENTOUT

CAN1_RX,

FSMC_D2/FSMC_DA2,

EVENTOUT

CAN1_TX,

FSMC_D3/FSMC_DA3,

EVENTOUT

TIM3_ETR,

FSMC_NWE,

SDIO_CMD,

EVENTOUT

TRACED1,

SPI2_SCK/I2S2_CK,

DFSDM1_DATIN0,

USART2_CTS,

QUADSPI_CLK,

FSMC_CLK,

EVENTOUT

DFSDM1_CKIN0,

USART2_RTS,

FSMC_NOE,

EVENTOUT

USART2_TX,

FSMC_NWE,

EVENTOUT

SPI3_MOSI/I2S3_SD,

DFSDM1_DATIN1,

USART2_RX,

FSMC_NWAIT,

EVENTOUT

DFSDM1_CKIN1,

USART2_CK,

FSMC_NE1,

EVENTOUT

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Pinouts and pin description STM32F412xE/G

Pin Number

Table 9. STM32F412xE/G pin definition (continued)

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

D7 128 PG13 I/O FT

E8 124 PG9 I/O

D8 125

C8 126

PG10

PG11

B8 127 PG12

I/O

C7 129 PG14 I/O

130

F6 131

B7 132

VSS

VDD

PG15

I/O

39 55 A5 89 A8 A7 133 PB3 I/O FT

40 56 B4 90 A7 A6 134 PB4 I/O FT

USART6_RX,

QUADSPI_BK2_IO2,

FSMC_NE2,

EVENTOUT

FSMC_NE3,

EVENTOUT

CAN2_RX, EVENTOUT

USART6_RTS,

CAN2_TX, FSMC_NE4,

EVENTOUT

TRACED2,

USART6_CTS,

FSMC_A24,

EVENTOUT

TRACED3,

USART6_TX,

QUADSPI_BK2_IO3,

FSMC_A25,

EVENTOUT

USART6_CTS,

EVENTOUT

JTDO-SWO,

TIM2_CH2,

I2CFMP1_SDA,

SPI1_SCK/I2S1_CK,

SPI3_SCK/I2S3_CK,

USART1_RX,

I2C2_SDA, EVENTOUT

JTRST, TIM3_CH1,

SPI1_MISO,

SPI3_MISO,

I2S3ext_SD, I2C3_SDA,

SDIO_D0, EVENTOUT

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STM32F412xE/G Pinouts and pin description

Pin Number

Table 9. STM32F412xE/G pin definition (continued)

Pin name

(function after reset)

(1)

Pin type

I/O structure

Notes Alternate functions

Additional functions

41 57 C4 91

42 58 B5 92

43 59 A6 93

44 60 D4 94

45 61 C5 95

46 62 B6 96

47 63 A7 99 D3 E6

48 64 A8 100 C4

135

136

137

138

139

140

141

142

PB5

PB6

PB7

BOOT0

PB8

PB9

PE0

PE1

VSS

143 PDR_ON

F5 144 VDD

I/O

TIM3_CH2,

I2C1_SMBA,

SPI1_MOSI/I2S1_SD,

SPI3_MOSI/I2S3_SD,

CAN2_RX, SDIO_D3,

EVENTOUT

TIM4_CH1, I2C1_SCL,

USART1_TX,

CAN2_TX,

QUADSPI_BK1_NCS,

SDIO_D0, EVENTOUT

TIM4_CH2, I2C1_SDA,

USART1_RX,

FSMC_NL, EVENTOUT

TIM4_CH3,

TIM10_CH1, I2C1_SCL,

SPI5_MOSI/I2S5_SD,

CAN1_RX, I2C3_SDA,

SDIO_D4, EVENTOUT

TIM4_CH4,

TIM11_CH1, I2C1_SDA,

SPI2_NSS/I2S2_WS,

CAN1_TX, I2C2_SDA,

SDIO_D5, EVENTOUT

TIM4_ETR,

FSMC_NBL0,

EVENTOUT

FSMC_NBL1,

EVENTOUT

1. Function availability depends on the chosen device.

2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These I/Os must not be used as a current source (e.g. to drive an LED).

VPP

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Pins

PF15

PG0

PG1

PE7

PE8

PE9

PE10

PA5

PC4

PC5

PF12

PF13

PF14

PF5

PC2

PC3

PA2

PA3

PA4

PE2

PE3

PE4

PE5

PE6

PF0

PF1

PF2

PF3

PF4

Pinouts and pin description STM32F412xE/G

3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F412xE/Greference manual.

4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).

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Table 10. FSMC pin definition

FSMC

64 pins

LCD/NOR/PSR

AM/SRAM

NOR/PSRAM

Mux

A10

A11

NE4

NOE

NWE

A23

A19

A20

A21

A22

DA4

DA5

DA6

DA7

NE4

NOE

NWE

DA4

DA5

DA6

A22

A23

A19

A20

A21

Yes

100 pins

Yes

DocID028087 Rev 7

144 pins

Yes

STM32F412xE/G

Pins

PC11

PC12

PD0

PD1

PD2

PD3

PD15

PG2

PG3

PG4

PG5

PC6

PD4

PD5

PD6

PD7

PG9

PG10

PG12

PD9

PD10

PD11

PD12

PD13

PD14

PE11

PE12

PE13

PE14

PE15

PB12

PB14

PD8

Table 10. FSMC pin definition

FSMC

64 pins

LCD/NOR/PSR

AM/SRAM

NOR/PSRAM

Mux

NWE

CLK

A12

A13

A14

A15

NOE

NWE

NWAIT

NE1

NE2

NE3

A24

D14

D15

A16

A17

A18

D12

D13

D10

D11

DA2

DA3

DA2

DA3

NWE

CLK

DA1

NOE

NEW

NWAIT

NE1

NE2

NE3

A24

DA14

DA15

A16

A17

A18

DA0

DA8

DA9

DA10

DA11

DA12

DA13

DA0

DA13

Yes

Pinouts and pin description

100 pins 144 pins

Yes

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Pinouts and pin description

Pins

PG14

PB7

PE0

PE1

STM32F412xE/G

Table 10. FSMC pin definition

FSMC

64 pins

LCD/NOR/PSR

AM/SRAM

NOR/PSRAM

Mux

A25

NBL0

NBL1

A25

NBL0

NBL1 -

Yes

100 pins

Yes

144 pins

Yes

66/201

DocID028087 Rev 7

Port

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8 MCO_1

PA9

PA10

PA11

AF0

SYS_AF

AF1

TIM1/

TIM2

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

PA12

PA13

PA14

PA15

JTMS-

SWDIO

JTCK-

SWCLK

JTDI

TIM1_ETR

TIM2_CH1/

TIM2_ETR

AF2

TIM3/

TIM4/

TIM5

AF3

TIM8/

TIM9/

TIM10/

TIM11

Table 11. STM32F412xE/G alternate functions

AF4 AF5 AF6 AF7 AF8

I2C1/

I2C2/

I2C3/

I2CFMP1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/I2S4

SPI2/I2S2/SPI3

/I2S3/SPI4/

I2S4/SPI5/I2S5

/DFSDM1

SPI3/I2S3/

USART1/

USART2/

USART3

AF9 AF10

DFSDM1/

USART3/

USART6/

CAN1

I2C2/I2C3/

I2CFMP1/

CAN1/CAN2

/TIM12/

TIM13/TIM14

/QUADSPI

DFSDM1/

QUADSPI/

FSMC

/OTG1_FS

AF12 AF15

FSMC /SDIO SYS_AF

TIM2_CH1/

TIM2_ETR

TIM2_CH2

TIM5_CH1

TIM5_CH2

TIM2_CH3

TIM2_CH4

TIM5_CH3

TIM5_CH4

TIM8_ETR

TIM9_CH1

TIM9_CH2

TIM2_CH1/

TIM2_ETR

TIM1_BKIN TIM3_CH1

TIM8_CH1N

TIM8_BKIN

TIM1_CH1N TIM3_CH2 TIM8_CH1N

I2C3_SCL

I2C3_

SMBA

SPI4_MOSI/I

2S4_SD

I2S2_CKIN

I2S2_MCK

SPI1_NSS/I2

S1_WS

SPI1_SCK/

I2S1_CK

SPI1_MISO

SPI1_MOSI/I

2S1_SD

SPI1_NSS/

I2S1_WS

SPI3_NSS/

I2S3_WS

I2S2_MCK

SPI5_MOSI/

I2S5_SD

SPI4_MISO

SPI5_MISO

SPI3_NSS/

I2S3_WS

USART2_CTS

USART2_RTS

USART2_TX

USART2_RX

USART2_CK

DFSDM1_

DATIN1

DFSDM1_

CKIN1

QUADSPI_

BK1_IO3

USART1_CK -

TIM13_

CH1

TIM14_

CH1

USART1_TX -

USART1_RX -

USART1_CTS

USART1_RTS

USART6_

USART1_TX -

CAN1_RX

CAN1_TX

QUADSPI_

BK2_IO0

QUADSPI_

BK2_IO1

USB_FS_

SOF

USB_FS_

VBUS

USB_FS_ID

USB_FS_DM

USB_FS_DP

FSMC_D4

FSMC_D5

EVENTOUT

FSMC_D6 EVENTOUT

FSMC_D7 EVENTOUT

SDIO_CMD EVENTOUT

SDIO_D1 EVENTOUT

SDIO_D2 EVENTOUT

EVENTOUT

Port

PB0

PB1

PB2

PB3

PB4

PB5

PB6

AF0

SYS_AF

JTDO-

SWO

JTRST

AF1

TIM1/

TIM2

TIM1_CH2N TIM3_CH3 TIM8_CH2N

TIM1_CH3N TIM3_CH4 TIM8_CH3N

TIM2_CH2

AF2

TIM3/

TIM4/

TIM5

TIM3_CH1

TIM3_CH2

Table 11. STM32F412xE/G alternate functions (continued)

AF3 AF4 AF5 AF6 AF7 AF8 AF9

TIM8/

TIM9/

TIM10/

TIM11

I2C1/

I2C2/

I2C3/

I2CFMP1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/I2S4

SPI2/I2S2/SPI3

/I2S3/SPI4/

I2S4/SPI5/I2S5

/DFSDM1

SPI3/I2S3/

USART1/

USART2/

USART3

AF10

DFSDM1/

USART3/

USART6/

CAN1

I2C2/I2C3/

I2CFMP1/

CAN1/CAN2

/TIM12/

TIM13/TIM14

/QUADSPI

DFSDM1/

QUADSPI/

FSMC

/OTG1_FS

AF12 AF15

FSMC /SDIO SYS_AF

I2CFMP1_

SDA

SPI1_SCK/I2

S1_CK

SPI1_MISO

I2C1_SMBA

SPI1_MOSI/I

2S1_SD

SPI5_SCK/

I2S5_CK

SPI5_NSS/

I2S5_WS

DFSDM1_

CKIN0

SPI3_SCK/

I2S3_CK

SPI3_MISO

SPI3_MOSI/

I2S3_SD

USART1_RX

I2S3ext_

DFSDM1_

DATIN0

QUADSPI_

CLK

QUADSPI_

CLK

I2C2_SDA

I2C3_SDA

CAN2_RX -

SDIO_D0

SDIO_D3

EVENTOUT

TIM4_CH1 I2C1_SCL USART1_TX CAN2_TX

QUADSPI_

BK1_NCS

SDIO_D0 EVENTOUT

PB7

PB8 -

FSMC_NL EVENTOUT

SDIO_D4 EVENTOUT

PB9

PB10

PB11

PB12

PB13

PB14

PB15

RTC_

50Hz

TIM2_CH3

TIM2_CH4

TIM1_BKIN

TIM1_CH1N

TIM1_CH2N

TIM1_CH3N

TIM4_CH2

TIM4_CH3

TIM4_CH4

TIM10_CH1

TIM11_CH1

I2C1_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

I2S2_CKIN

SPI5_MOSI/I2S

5_SD

USART1_RX

CAN1_RX

I2S3_MCK

USART3_TX

USART3_RX

CAN1_TX

TIM8_CH2N

TIM8_CH3N

I2C2_SMBA

SPI2_NSS/

I2S2_WS

I2CFMP1_

SMBA

I2CFMP1_

SDA

I2CFMP1_

SCL

SPI2_SCK/

I2S2_CK

SPI2_MISO

SPI2_MOSI/I

2S2_SD

SPI4_NSS/

I2S4_WS

SPI4_SCK/

I2S4_CK

I2S2ext_SD

SPI3_SCK/

I2S3_CK

USART3_

RTS

I2C3_SDA

I2C2_SDA

I2CFMP1_

SCL

USART3_

CTS

DFSDM1_

DATIN2

DFSDM1_

CKIN2

CAN2_RX

CAN2_TX

TIM12_CH1

TIM12_CH2

DFSDM1_

DATIN1

DFSDM1_

CKIN1

FSMC_D0

SDIO_D5 EVENTOUT

SDIO_D7

EVENTOUT

FSMC_D13/F

SMC_DA13

EVENTOUT

SDIO_D6 EVENTOUT

SDIO_CK EVENTOUT

PC11

PC12

PC13

PC14

PC15

PC5

PC6

PC7

PC8

PC0

PC1

PC2

PC3

PC4

PC9 MCO_2

PC10 -

AF0 AF1

Port

SYS_AF

TIM1/

TIM2

AF2

TIM3/

TIM4/

TIM5

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

Table 11. STM32F412xE/G alternate functions (continued)

AF3 AF4 AF5 AF6 AF7 AF8 AF9

TIM8/

TIM9/

TIM10/

TIM11

TIM8_CH1

TIM8_CH2

TIM8_CH3

TIM8_CH4

AF10

I2C1/

I2C2/

I2C3/

I2CFMP1

I2CFMP1_

SMBA

I2CFMP1_

SCL

I2CFMP1_

SDA

SPI2_MISO

SPI2_MOSI/I

2S2_SD

I2S1_MCK

I2S2_MCK

SPI2_SCK/

I2S2_CK

I2C3_SDA

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/I2S4

SPI2/I2S2/SPI3

/I2S3/SPI4/

I2S4/SPI5/I2S5

/DFSDM1

I2S2_CKIN

I2S3ext_SD

I2S2ext_SD

DFSDM1_

CKIN3

I2S3_MCK

SPI3_SCK/

I2S3_CK

SPI3_MISO

SPI3/I2S3/

USART1/

USART2/

USART3

USART3_TX

USART3_RX

DFSDM1/

USART3/

USART6/

CAN1

I2C2/I2C3/

I2CFMP1/

CAN1/CAN2

/TIM12/

TIM13/TIM14

/QUADSPI

DFSDM1_

CKOUT

DFSDM1/

QUADSPI/

FSMC

/OTG1_FS

USART3_RX

USART6_

QUADSPI_

BK1_IO2

QUADSPI_

BK1_IO0

QUADSPI_

BK1_IO1

QUADSPI_

BK2_NCS

QUADSPI_

BK2_IO2

QUADSPI_

BK2_IO3

FSMC_D1

DFSDM1_

DATIN3

FSMC_D2

SPI3_MOSI/

I2S3_SD

USART3_CK

FSMC_D3

AF12

FSMC /SDIO SYS_AF

FSMC_NWE EVENTOUT

FSMC_A0 EVENTOUT

FSMC_NE4 EVENTOUT

FSMC_NOE EVENTOUT

SDIO_D6

SDIO_D7

SDIO_D0

SDIO_D1

SDIO_D2

SDIO_D3

SDIO_CK

AF15

EVENTOUT

AF0 AF1

Port

SYS_AF

TIM1/

TIM2

PD10

PD11

PD12

PD13

PD14

PD15

PD4

PD5

PD6

PD7

PD0 -

PD1

PD2

PD3 TRACED1

PD8 -

PD9

AF2

TIM3/

TIM4/

TIM5

TIM3_ETR

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_CH4

Table 11. STM32F412xE/G alternate functions (continued)

AF3 AF4 AF5 AF6 AF7 AF8 AF9

TIM8/

TIM9/

TIM10/

TIM11

I2C1/

I2C2/

I2C3/

I2CFMP1

AF10 AF12 AF15

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/I2S4

SPI2/I2S2/SPI3

/I2S3/SPI4/

I2S4/SPI5/I2S5

/DFSDM1

SPI2_SCK/

I2S2_CK

SPI3_MOSI/I

2S3_SD

DFSDM1_

DATIN0

DFSDM1_

CKIN0

DFSDM1_

DATIN1

DFSDM1_

CKIN1

SPI3/I2S3/

USART1/

USART2/

USART3

USART2_

CTS

USART2_

RTS

USART2_TX

DFSDM1/

USART3/

USART6/

CAN1

I2C2/I2C3/

I2CFMP1/

CAN1/CAN2

/TIM12/

TIM13/TIM14

/QUADSPI

DFSDM1/

QUADSPI/

FSMC

/OTG1_FS

CAN1_RX

CAN1_TX

FSMC /SDIO SYS_AF

FSMC_NWE

FSMC_D2/FS

MC_DA2

EVENTOUT

FSMC_D3/FS

MC_DA3

EVENTOUT

SDIO_CMD EVENTOUT

QUADSPI_

CLK

FSMC_CLK EVENTOUT

FSMC_NOE EVENTOUT

USART2_RX

USART2_CK -

FSMC_NWE EVENTOUT

FSMC_

NWAIT

EVENTOUT

FSMC_NE1 EVENTOUT

USART3_TX -

FSMC_D13/

FSMC_DA13

EVENTOUT

I2CFMP1_

SMBA

I2CFMP1_

SCL

I2CFMP1_

SDA

I2CFMP1_

SCL

I2CFMP1_

SDA

USART3_RX

USART3_CK

USART3_

CTS

USART3_

RTS

QUADSPI_

BK1_IO0

QUADSPI_

BK1_IO1

QUADSPI_

BK1_IO3

FSMC_D14/

FSMC_DA14

EVENTOUT

FSMC_D15/

FSMC_DA15

EVENTOUT

FSMC_A16 EVENTOUT

FSMC_A17 EVENTOUT

FSMC_A18 EVENTOUT

FSMC_D0/

FSMC_DA0

FSMC_D1/

FSMC_DA1

EVENTOUT

Port

AF0

SYS_AF

PE0 -

PE1

PE2

TRACECL

PE3 TRACED0

PE4 TRACED1

PE5 TRACED2

PE6 TRACED3

PE7

PE8

PE9

PE10

PE11

PE12

PE13 -

AF1

TIM1/

TIM2

TIM1_ETR

TIM1_CH1N

TIM1_CH1

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

TIM1_CH3

AF2

TIM3/

TIM4/

TIM5

TIM4_ETR

Table 11. STM32F412xE/G alternate functions (continued)

AF3 AF4 AF5 AF6 AF7 AF8 AF9

TIM8/

TIM9/

TIM10/

TIM11

TIM9_CH1

TIM9_CH2

I2C1/

I2C2/

I2C3/

I2CFMP1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/I2S4

SPI2/I2S2/SPI3

/I2S3/SPI4/

I2S4/SPI5/I2S5

/DFSDM1

SPI3/I2S3/

USART1/

USART2/

USART3

SPI4_SCK/

I2S4_CK

SPI4_NSS/

I2S4_WS

SPI4_MISO

SPI4_MOSI/I

2S4_SD

SPI4_NSS/

I2S4_WS

SPI4_SCK/

I2S4_CK

SPI4_MISO

SPI5_SCK/

I2S5_CK

SPI5_NSS/

I2S5_WS

SPI5_MISO

SPI5_MOSI/

I2S5_SD

DFSDM1_

DATIN2

DFSDM1_

CKIN2

DFSDM1_

CKOUT

SPI5_NSS/

I2S5_WS

SPI5_SCK/

I2S5_CK

SPI5_MISO

AF10

DFSDM1/

USART3/

USART6/

CAN1

I2C2/I2C3/

I2CFMP1/

CAN1/CAN2

/TIM12/

TIM13/TIM14

/QUADSPI

QUADSPI_

BK1_IO2

DFSDM1_

DATIN3

DFSDM1_

CKIN3

DFSDM1/

QUADSPI/

FSMC

/OTG1_FS

QUADSPI_

BK2_IO0

QUADSPI_

BK2_IO1

QUADSPI_

BK2_IO2

QUADSPI_

BK2_IO3

AF12 AF15

FSMC /SDIO SYS_AF

FSMC_NBL0 EVENTOUT

FSMC_NBL1 EVENTOUT

FSMC_A23 EVENTOUT

FSMC_A19 EVENTOUT

FSMC_A20 EVENTOUT

FSMC_A21 EVENTOUT

FSMC_A22 EVENTOUT

FSMC_D4/

FSMC_DA4

FSMC_D5/

FSMC_DA5

FSMC_D6/

FSMC_DA6

FSMC_D7/

FSMC_DA7

FSMC_D8/

FSMC_DA8

FSMC_D9/

FSMC_DA9

EVENTOUT

FSMC_D10/

FSMC_DA10

EVENTOUT

PE14

PE15 -

TIM1_CH4

TIM1_BKIN -

SPI4_MOSI/I

2S4_SD

SPI5_MOSI/

I2S5_SD

FSMC_D11/

FSMC_DA11

EVENTOUT

FSMC_D12/

FSMC_DA12

EVENTOUT

Port

PF7 TRACED1

PF8

PF9

PF10

PF11

PF12

PF13

PF14

PF15

AF0

SYS_AF

PF0

PF1

PF2

PF3

PF4

PF5

PF6 TRACED0

AF1

TIM1/

TIM2

TIM1_ETR

AF2

TIM3/

TIM4/

TIM5

Table 11. STM32F412xE/G alternate functions (continued)

AF3 AF4 AF5 AF6 AF7 AF8 AF9

TIM8/

TIM9/

TIM10/

TIM11

I2C1/

I2C2/

I2C3/

I2CFMP1

TIM5_CH1

TIM5_CH2

TIM5_CH3

TIM10_CH1

I2C2_SDA

I2C2_SCL

I2C2_SMBA

TIM11_CH1

TIM5_CH4

TIM8_ETR

TIM8_BKIN

I2CFMP1_

SMBA

I2CFMP1_

SCL

I2CFMP1_

SDA

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/I2S4

SPI2/I2S2/SPI3

/I2S3/SPI4/

I2S4/SPI5/I2S5

/DFSDM1

SPI3/I2S3/

USART1/

USART2/

USART3

AF10

DFSDM1/

USART3/

USART6/

CAN1

I2C2/I2C3/

I2CFMP1/

CAN1/CAN2

/TIM12/

TIM13/TIM14

/QUADSPI

QUADSPI_

BK1_IO3

QUADSPI_

BK1_IO2

TIM13_CH1

DFSDM1/

QUADSPI/

FSMC

/OTG1_FS

TIM14_CH1

QUADSPI_

BK1_IO0

QUADSPI_

BK1_IO1

AF12

FSMC_A0

FSMC_A1

FSMC_A2

FSMC_A3

FSMC_A4

FSMC_A5

EVENTOUT

AF15

FSMC /SDIO SYS_AF

EVENTOUT

FSMC_A6

EVENTOUT

FSMC_A7 EVENTOUT

FSMC_A8 EVENTOUT

FSMC_A9 EVENTOUT

AF0 AF1

Port

SYS_AF

TIM1/

TIM2

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PG8

PG9

PG10

PG11

PG12

PG13 TRACED2

PG14 TRACED3

PG15

PH0

PH1 -

AF2

TIM3/

TIM4/

TIM5

Table 11. STM32F412xE/G alternate functions (continued)

AF3 AF4 AF5 AF6 AF7 AF8 AF9

TIM8/

TIM9/

TIM10/

TIM11

I2C1/

I2C2/

I2C3/

I2CFMP1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/I2S4

SPI2/I2S2/SPI3

/I2S3/SPI4/

I2S4/SPI5/I2S5

/DFSDM1

SPI3/I2S3/

USART1/

USART2/

USART3

AF10

DFSDM1/

USART3/

USART6/

CAN1

I2C2/I2C3/

I2CFMP1/

CAN1/CAN2

/TIM12/

TIM13/TIM14

/QUADSPI

CAN1_RX

CAN1_TX

DFSDM1/

QUADSPI/

FSMC

/OTG1_FS

AF12 AF15

FSMC /SDIO SYS_AF

FSMC_A10 EVENTOUT

FSMC_A11 EVENTOUT

FSMC_A12

FSMC_A13

FSMC_A14

FSMC_A15

EVENTOUT

QUADSPI_

BK1_NCS

EVENTOUT

USART6_

RTS

USART6_

RTS

USART6_

CTS

USART6_

CTS

QUADSPI_

BK2_IO3

QUADSPI_

BK2_IO2

CAN2_RX

CAN2_TX

FSMC_NE2 EVENTOUT

FSMC_NE3 EVENTOUT

EVENTOUT

FSMC_NE4 EVENTOUT

FSMC_A24 EVENTOUT

FSMC_A25 EVENTOUT

EVENTOUT

Memory mapping STM32F412xE/G

The memory map is shown in

Figure 18

Figure 18. Memory map

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74/201

DocID028087 Rev 7

STM32F412xE/G Memory mapping

Bus

Cortex

-M4

AHB3

AHB2

AHB1

Table 12. STM32F412xE/G register boundary addresses

Boundary address Peripheral

0xE010 0000 - 0xFFFF FFFF

0xE000 0000 - 0xE00F FFFF

0xA000 2000 - 0xDFFF FFFF

0xA000 1000 - 0xA000 1FFF

0xA000 0000 - 0xA000 0FFF

0x9000 0000 - 0x9FFF FFFF

0x7000 0000 - 0x08FFF FFFF

0x6000 0000 - 0x6FFF FFFF

0x5006 0C00 - 0x5FFF FFFF

0x5006 0800 0x5006 0BFF

0x5004 000- 0x5006 07FF

0x5000 0000 - 0x5003 FFFF

0x4002 6800 - 0x4FFF FFFF

0x4002 6400 - 0x4002 67FF

0x4002 6000 - 0x4002 63FF

0x4002 5000 - 0x4002 4FFF

0x4002 3C00 - 0x4002 3FFF

0x4002 3800 - 0x4002 3BFF

0x4002 3400 - 0x4002 37FF

0x4002 3000 - 0x4002 33FF

0x4002 2000 - 0x4002 2FFF

0x4002 1C00 - 0x4002 1FFF

0x4002 1800 - 0x4002 1BFF

0x4002 1400 - 0x4002 17FF

0x4002 1000 - 0x4002 13FF

0x4002 0C00 - 0x4002 0FFF

0x4002 0800 - 0x4002 0BFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

Reserved

Cortex-M4 internal peripherals

Reserved

QuadSPI control register

FSMC control register

QUADSPI

Reserved

FSMC

Reserved

RNG

Reserved

USB OTG FS

Reserved

DMA2

DMA1

Reserved

Flash interface register

RCC

Reserved

CRC

Reserved

GPIOH

GPIOG

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

DocID028087 Rev 7

75/201

Memory mapping STM32F412xE/G

Table 12. STM32F412xE/G register boundary addresses (continued)

Bus Boundary address Peripheral

APB2

0x4001 6400- 0x4001 FFFF

0x4001 6000 - 0x4001 63FF

0x4001 5400 - 0x4001 5FFF

0x4001 5000 - 0x4001 53FF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2400 - 0x4001 2BFF

0x4001 2000 - 0x4001 23FF

0x4001 1800 - 0x4001 1FFF

0x4001 1400 - 0x4001 17FF

0x4001 1000 - 0x4001 13FF

0x4001 0800 - 0x4001 0FFF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 7400 - 0x4000 FFFF

Reserved

DFSDM1

Reserved

SPI5/I2S5

TIM11

TIM10

TIM9

EXTI

SYSCFG

SPI4/I2S4

SPI1/I2S1

SDIO

Reserved

ADC1

Reserved

USART6

USART1

Reserved

TIM8

TIM1

Reserved

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STM32F412xE/G Memory mapping

Table 12. STM32F412xE/G register boundary addresses (continued)

Bus Boundary address Peripheral

APB1

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800- 0x4000 6BFF

0x4000 6400- 0x4000 67FF

0x4000 6000- 0x4000 63FF

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 4C00 - 0x4000 53FF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 2000 - 0x4000 23FF

0x4000 1C00 - 0x4000 1FFF

0x4000 1800 - 0x4000 1BFF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

Reserved

TIM14

TIM13

TIM12

TIM7

TIM6

TIM5

TIM4

TIM3

TIM2

PWR

Reserved

CAN2

CAN1

I2CFMP1

I2C3

I2C2

I2C1

Reserved

USART3

USART2

I2S3ext

SPI3 / I2S3

SPI2 / I2S2

I2S2ext

IWDG

WWDG

RTC & BKP Registers

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Electrical characteristics STM32F412xE/G

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3 σ ).

Unless otherwise specified, typical data are based on T

= 25 °C, V

1.7 V ≤ tested.

= 3.3 V (for the

≤ 3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 19

6.1.5 Pin input voltage

Figure 19. Pin loading conditions Figure 20. Input voltage measurement

-#5PIN

#P& 6).

-36

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STM32F412xE/G

6.1.6 Power supply scheme

Electrical characteristics

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Figure 21. Power supply scheme

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1. To connect PDR_ON pin, refer to Section: Power supply supervisor.

2. The 4.7 µF ceramic capacitor must be connected to one of the V

pin.

3. VCAP_2 pad is only available on 100-pin and 144-pin packages.

4. V

DDA

and V

SSA

5. V

DDUSB

is a dedicated independent USB power supply for the on-chip full-speed OTG PHY module and

DDUSB

value does not depend on the V last supply to be provided and the first to disappear.

and V

DDA

values, but it must be the

Caution: Each power supply pair (for example V

, V

DDA

SSA

) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.

This might cause incorrect operation of the device.

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166

Electrical characteristics STM32F412xE/G

Figure 22. Current consumption measurement scheme

,''B9%$7

9%$7

6.2

,''

9''

9''$

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 13: Voltage characteristics

Table 14: Current characteristics

, and

Table 15: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 13. Voltage characteristics

Ratings Min Max Unit

–V

| Δ V

DDx

SSX

− V

ESD(HBM)

External main supply voltage (including V

DDA

DDUSB and V

BAT

)

(1)

, V

Input voltage on FT and TC pins

(2)

Input voltage on any other pin

Input voltage for BOOT0

Variations between different V

power pins

| Variations between all the different ground pins

Electrostatic discharge voltage (human body model)

–0.3

4.0

–0.3

+4.0

–0.3

4.0

9.0

50 see

Section 6.3.14:

Absolute maximum ratings (electrical sensitivity)

1. All main power (V , V

DDA,

V ) and ground (V

, V

SSA

) pins must always be connected to the

2. V

maximum value must always be respected. Refer to

Table 14

for the values of the maximum allowed injected current.

V mV

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STM32F412xE/G Electrical characteristics

Symbol

Table 14. Current characteristics

Ratings Max.

Unit

Σ I

VDD

Σ I

VSS

Σ I

VDDUSB

VDD

VSS

Total current into sum of all V

DD_x power lines (source)

(1)

Total current out of sum of all V

SS_x ground lines (sink)

Total current into V

DDUSB power lines (source)

Maximum current into each V

DD_x

power line (source) (1)

Maximum current out of each V

SS_x ground line (sink)

Output current sunk by any I/O and control pin

160

-160

100

-100

Output current sourced by any I/O and control pin

Total output current sunk by sum of all I/O and control pins

(2)

-25

120 mA

Σ I

Total output current sunk by sum of all USB I/Os

Total output current sourced by sum of all I/Os and control pins

3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics

Injected current on FT and TC pins

(4)

-120

INJ(PIN)

(3)

–5/+0

Σ I

INJ(PIN)

Injected current on NRST and B pins

(4)

Total injected current (sum of all I/O and control pins)

(5)

±25

1. All main power (V

, V in the permitted range.

DDA,

DDUSB

) and ground (V

, V

SSA

) pins must always be connected to the external power supply,

2. This current consumption must be correctly distributed over all I/Os and control pins.

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

5. When several inputs are submitted to a current injection, the maximum negative injected currents (instantaneous values).

Σ I

INJ(PIN)

is the absolute sum of the positive and

Symbol

Table 15. Thermal characteristics

Ratings Value Unit

STG

Storage temperature range

Maximum junction temperature

–65 to +150

130

LEAD

Maximum lead temperature during soldering

(WLCSP64, LQFP64/100/144, UFQFPN48,

UFBGA100/144) see note

(1)

1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ®

7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS directive 2011/65/EU, July 2011).

°C

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Electrical characteristics STM32F412xE/G

6.3.1 General operating conditions

Symbol Parameter

Table 16. General operating conditions

Conditions Min Typ Max Unit f

HCLK

Power Scale3: Regulator ON,

VOS[1:0] bits in PWR_CR register = 0x01

Internal AHB clock frequency

Power Scale2: Regulator ON,

VOS[1:0] bits in PWR_CR register = 0x10

Power Scale1: Regulator ON,

VOS[1:0] bits in PWR_CR register = 0x11 f f

PCLK1

PCLK2

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

DDA

(2)(3)

DDUSB

Analog operating voltage

(ADC limited to 1.2 M samples)

Analog operating voltage

(ADC limited to 2.4 M samples)

Must be the same potential as V

USB supply voltage

(supply voltage for PA11 and

PA12 pins)

USB not used

USB used

(5)

(4)

BAT

0 -

1.7

(1)

2.4

1.7

3.0

3.3

100

3.6

2.4

3.6

Backup operating voltage -

VOS[1:0] bits in PWR_CR register = 0x01

Max frequency 64 MHz

1.65

1.08

(6)

3.6

1.14 1.20

(6)

Regulator ON: 1.2 V internal voltage on

VCAP_1/VCAP_2 pins

VOS[1:0] bits in PWR_CR register = 0x10

Max frequency 84 MHz

VOS[1:0] bits in PWR_CR register = 0x11

Max frequency 100 MHz

Regulator OFF: 1.2 V external voltage must be supplied on

VCAP_1/VCAP_2 pins

Max frequency 64 MHz

Max frequency 84 MHz

Max frequency 100 MHz

Input voltage on RST, FT and

TC pins

(7)

2 V ≤ V

≤ 3.6 V

≤ 2 V

Input voltage on BOOT0 pin -

1.20

(6)

1.26

1.10

1.20

1.26

-0.3

1.26 1.32

1.32

1.14

1.26

1.32

5.5

5.2

(6)

1.38

1.20

1.32

1.38

MHz

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Symbol

Table 16. General operating conditions (continued)

Parameter Conditions Min Typ Max Unit

Power dissipation at

Ambient temperature for range 6

Ambient temperature for range 7

Ambient temperature for range 3

= 85°C for range 6 or

= 105°C for range 7

= 125 °C for range 3

(8)

Junction temperature range

UFQFPN48

WLCSP64

LQFP64

LQFP100

LQFP144

UFBGA100

UFBGA144

UFQFPN48

WLCSP64

LQFP64

LQFP100

LQFP144

UFBGA100

UFBGA144

Maximum power dissipation

Low power dissipation

(9)

Maximum power dissipation

Low power dissipation

(9)

Maximum power dissipation

Low power dissipation (9)

Range 6

Range 7

Range 3

1. V

DDA

minimum value of 1.7 V with the use of an external power supply supervisor (refer to

Section 3.18.2: Internal reset OFF

2. When the ADC is used, refer to

Table 72: ADC characteristics

3. If V

REF+

pin is present, it must respect the following condition: V

DDA

-V

REF

+ < 1.2 V.

4. It is recommended to power V

DD and V

DDA from the same source. A maximum difference of 300 mV between V

DD and

DDA can be tolerated during power-up and power-down operation.

5. Only the DM (P

A11

) and DP (P

A12

) pads are supplied through V

supply of 2.7V is required.

(some application examples are shown in appendix B)

. For application where the V

BUS

) is directly

6. Guaranteed by test in production

7. To sustain a voltage higher than V

+0.3, the internal Pull-up and Pull-Down resistors must be disabled

8. If T

is lower, higher P

values are allowed as long as T

does not exceed T

Jmax

9. In low power dissipation state, T

can be extended to this range as long as T

does not exceed T

Jmax

-40

-40 -

-40

-40 -

-40

-40 -

106

116

142

104

105

125

571

351

416

156

625

392

425

465

110

130

105

125

130 mW

°C

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Electrical characteristics STM32F412xE/G

Operating power supply range

Table 17. Features depending on the operating power supply range

ADC operation

Maximum

Flash memory access frequency with no wait states

Flashmax

)

Maximum Flash memory access frequency with wait states

(1)(2)

I/O operation

Clock output frequency on

I/O pins

(3)

Possible

Flash memory operations

2.1 V

2.4 V

2.7 V

=1.7 to

3.6 V

(4)

= 2.1 to

= 2.4 to

= 2.7 to

(6)

Conversion time up to

1.2 Msps

Conversion time up to

1.2 Msps

Conversion time up to

2.4 Msps

Conversion time up to

2.4 Msps

16 MHz

(5)

18 MHz

24 MHz

30 MHz

100 MHz with 6 wait states

100 MHz with 5 wait states

100 MHz with 4 wait states

100 MHz with 3 wait states

– No I/O compensation

– No I/O compensation up to 30 MHz up to 30 MHz

– I/O compensation works up to 50 MHz

– I/O compensation works

– up to

100 MHz when V

3.0 to 3.6 V

– up to

50 MHz when V

2.7 to 3.0 V

8-bit erase and program operations only

16-bit erase and program operations

32-bit erase and program operations

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required.

2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution.

3. Refer to Table 59: I/O AC characteristics

for frequencies vs. external load.

4. V

DDA

minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.18.2: Internal reset OFF

5. Prefetch available over the complete VDD supply range.

6. The voltage range for the USB full speed embedded PHY can drop down to 2.7 V. However the electrical characteristics of

D- and D+ pins will be degraded between 2.7 and 3 V.

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6.3.3

Stabilization for the main regulator is achieved by connecting the external capacitor C

EXT the VCAP_1 and VCAP_2 pins. For packages supporting only 1 VCAP pin, the 2 CEXT

to capacitors are replaced by a single capacitor.

EXT

is specified in Table 18

Figure 23. External capacitor C

EXT

(65

/HDN

069

1. Legend: ESR is the equivalent series resistance.

Symbol

Table 18. VCAP_1/VCAP_2 operating conditions

(1)

Parameter Conditions

CEXT

ESR

CEXT

ESR

Capacitance of external capacitor with the pins

VCAP_1 and VCAP_2 available

ESR of external capacitor with the pins VCAP_1 and

VCAP_2 available

Capacitance of external capacitor with a single VCAP pin available

ESR of external capacitor with a single VCAP pin available

2.2 µF

< 2

4.7 µF

< 1

1. When bypassing the voltage regulator, the two 2.2 µF V replaced by two 100 nF decoupling capacitors.

CAP

capacitors are not required and should be

Operating conditions at power-up/power-down (regulator ON)

Subject to general operating conditions for T

Table 19. Operating conditions at power-up / power-down (regulator ON)

Symbol Parameter Min Max Unit t

VDD

rise time rate

fall time rate

∞

µs/V

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Electrical characteristics STM32F412xE/G

Note:

6.3.5

Subject to general operating conditions for T

Table 20. Operating conditions at power-up / power-down (regulator OFF)

(1)

Symbol Parameter Conditions Min Max Unit t t

VDD

VCAP

rise time rate Power-up

fall time rate Power-down

CAP_1

and V

CAP_2 rise time rate Power-up

CAP_1

and V

CAP_2

fall time rate Power-down

1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V

1.08 V.

reach below

∞

µs/V

This feature is only available for UFBGA100 and UFBGA144 packages.

Embedded reset and power control block characteristics

The parameters given in

Table 21 are derived from tests performed under ambient

temperature and V

supply voltage @ 3.3V.

Symbol

Table 21. Embedded reset and power control block characteristics

Parameter Conditions Min Typ Max Unit

PVD

PVDhyst

(2)

PVD hysteresis

POR/PDR

Programmable voltage detector level selection

Power-on/power-down reset threshold

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

PLS[2:0]=111 (falling edge)

Falling edge

Rising edge

2.09

2.14

2.19

1.98

2.04

2.08

2.23

2.30

2.37

2.13

2.19

2.25

2.39

2.45

2.51

2.29

2.35

2.39

2.54

2.60

2.65

2.44

2.51

2.56

2.70

2.76

2.82

2.59

2.66

2.71

2.86

2.93

2.99

2.65

2.84

3.02

2.96

3.03

3.10

2.85

2.93

2.99

3.07

3.14

3.21

2.95

3.03

3.09

100 -

1.60

(1) 1.68

1.76

1.64

1.72

1.80

V mV

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6.3.6

Electrical characteristics

Table 21. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

PDRhyst

(2)

PDR hysteresis mV

BOR1

BOR2

BOR3

BORhyst

(2)

Brownout level 1 threshold

Brownout level 2 threshold

Brownout level 3 threshold

BOR hysteresis

POR reset timing

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

40 -

2.13

2.19

2.24

2.23

2.29

2.33

2.44

2.50

2.56

2.53

2.59

2.63

2.75

2.83

2.88

2.85

2.92

2.97

100 -

0.5

1.5

3.0

V mV ms

RUSH

(2)

RUSH

(2)

In-Rush current on voltage regulator poweron (POR or wakeup from

Standby)

In-Rush energy on voltage regulator poweron (POR or wakeup from

Standby)

= 1.7 V, T

= 125 °C,

RUSH

= 171 mA for 31 µs

160

200

5.4

µC

1. The product behavior is guaranteed by design down to the minimum V

POR/PDR

value.

2. Guaranteed by design, not tested in production.

3. The reset timing is measured from the power-on (POR reset or wakeup from V instruction is fetched by the user application code.

BAT

) to the instant when first

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 22: Current consumption measurement scheme

All the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.

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Electrical characteristics STM32F412xE/G

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at VDD or VSS (no load).

• All peripherals are disabled except if it is explicitly mentioned.

• The Flash memory access time is adjusted to both f

HCLK

frequency and VDD ranges

(refer to

Table 17: Features depending on the operating power supply range ).

• The voltage scaling is adjusted to f

HCLK

frequency as follows:

– Scale 3 for f

HCLK

≤ 64 MHz

– Scale 2 for 64 MHz < f

HCLK

≤ 84 MHz

– Scale 1 for 84 MHz < f

HCLK

≤ 100 MHz

• The system clock is HCLK, f

PCLK1

= f

HCLK

/2, and f

PCLK2

= f

HCLK

• External clock is 4 MHz and PLL is ON except if it is explicitly mentioned.

• The maximum values are obtained for V

DD temperature (T

= 3.6 V and a maximum ambient

), and the typical values for T

= 25 °C and V

= 3.3 V unless otherwise specified.

Table 22. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - V

= 1.7 V

Typ Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) T

25 °C

85 °C

105 °C

125 °C

Unit

External clock,

PLL ON, all peripherals enabled (2)(3)

100

28.1

22.7

15.7

12.3

6.5

5.6

30.24

24.05

16.99

13.36

7.44

6.16

31.27

24.54

17.47

13.82

7.82

6.66

32.21

25.11

18.03

14.36

8.30

7.20

34.21

26.74

19.71

15.51

8.96

7.77

Supply current in

Run mode

HSI, PLL off, all peripherals

enabled

100

3.9

0.6

14.0

4.70

0.78

15.48

5.31

1.33

16.08

6.08

1.98

16.83

6.57

2.14

18.51

External clock,

PLL ON, all peripherals

11.3

7.9

6.2

3.4

2.9

12.23

8.84

7.06

4.18

3.44

12.75

9.31

7.53

4.61

3.98

13.41

10.01

8.19

5.13

4.65

16.09

11.61

9.50

5.95

5.39

HSI, PLL off, all peripherals

2.0

0.5

2.51

0.64

1. Based on characterization, not tested in production unless otherwise specified

3.13

1.21

3.89

1.90

4.51

2.21

2. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the analog part. mA

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Table 23. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - V

= 3.6 V

Typ Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) T

25 °C

85 °C

105 °C

125 °C

Unit

Supply current in Run mode

External clock,

PLL ON, all peripherals enabled

(2)

HSI, PLL OFF

(4)

, all peripherals

enabled

External clock,

PLL ON, all peripherals

HSI, PLL OFF, all peripherals

disabled (2)

100

28.4

28.80

(3)

23.0

24.09

(3)

16.0

16.83

(3)

12.6

13.46

6.8

5.8

3.9

7.63

6.31

4.65

0.6

0.78

14.3

15.09

(3)

11.6

12.28

(3)

8.2

8.75

(3)

6.5

7.21

3.6

3.2

2.0

4.22

3.65

2.48

0.5

0.65

16.22

13.36

9.68

7.69

4.68

4.18

3.12

30.84

25.20

17.77

13.98

8.14

6.74

5.33

1.34

1.26

32.39

34.40

(3)

26.57

28.30

(3)

19.12

20.90

(3)

14.68

15.85

8.61

7.43

6.11

9.30

8.03

6.60

2.00

2.16

17.90

19.72

(3)

14.99

16.80

(3)

11.21

13.00

(3)

8.47

9.74

5.29

4.94

3.94

6.08

5.68

4.54

1.94

2.24

1. Based on characterization, not tested in production unless otherwise specified

2. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the analog part.

3. Tested in production

4. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be considered

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Table 24. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator enabled except prefetch) running from Flash memory- V

= 1.7 V

Typ Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) T

25 °C

85 °C

105 °C

125 °C

Unit

Supply current in Run mode

External clock,

PLL ON,

all peripherals enabled

(2)(3)

HSI, PLL OFF, all peripherals enabled

External clock,

PLL ON

(4)

all peripherals

HSI, PLL OFF, all peripherals disabled

4. Refer to Table 45 and RM0383 for the possible PLL VCO setting

100

26.9

21.6

15.0

11.8

6.3

5.5

3.9

0.9

12.7

10.3

7.2

5.7

3.2

2.9

2.1

0.7

28.78

29.86

31.30

33.08

23.14

23.93

24.89

26.31

16.08

16.70

17.46

18.45

12.74

13.33

14.07

14.87

7.13

6.09

4.20

0.98

7.69

6.64

4.78

1.50

8.30

7.30

5.49

2.20

8.77

7.72

5.81

2.33

13.82

14.71

15.76

17.53

11.20

11.97

12.96

14.41

7.87

8.57

9.41

10.47

6.33

3.77

3.31

2.25

0.83

7.02

4.38

3.93

2.83

1.42

7.87

5.13

4.69

3.56

2.12

8.75

5.71

5.22

3.96

2.36

1. Based on characterization, not tested in production unless otherwise specified.

2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).

3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the analog part.

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Table 25. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator enabled except prefetch) running from Flash memory - V

= 3.6 V

Typ Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) T

25 °C

85 °C

105 °C

125 °C

Unit

Supply current in Run mode

External clock,

PLL ON (2) , all peripherals enabled

(3)

HSI, PLL OFF, all peripherals enabled

External clock, PLL

all peripherals disabled

100

6.6

5.7

4.0

0.8

27.2

21.9

15.2

12.1

13.0

10.5

7.5

6.0

3.5

3.1

28.70

(4)

30.14

31.98

33.80

23.60

24.31

25.37

26.82

16.45

17.03

17.87

18.89

13.12

13.67

14.46

15.29

7.59

6.51

8.12

7.07

8.77

7.77

9.27

8.21

4.32

1.14

14.06

(4)

4.88

1.67

5.69

2.38

6.01

2.51

15.34

17.27

19.20

11.21

12.16

13.47

14.98

8.29

9.01

9.88

10.99

6.73

4.18

3.72

7.32

4.73

4.25

8.27

5.57

5.10

9.20

6.19

5.67

HSI, PLL OFF, all

peripherals disabled

2. Refer to Table 45 and RM0383 for the possible PLL VCO setting

2.1

0.7

2.41

0.99

2.94

1.51

3.75

2.30

4.17

2.56

1. Based on characterization, not tested in production unless otherwise specified.

3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).

4. Tested in production.

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Electrical characteristics STM32F412xE/G

Table 26. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator disabled) running from Flash memory - V

= 3.6 V

Typ Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) T

25 °C

85 °C

105 °C

125 °C

Unit

Supply current in Run mode

External clock,

PLL ON (2) , all peripherals enabled

HSI, PLL OFF, all peripherals enabled

External clock, PLL ON all peripherals disabled

HSI, PLL OFF, all

100

36.3

31.1

22.3

18.3

10.1

8.6

6.3

1.1

22.1

19.7

14.5

12.2

7.0

6.0

4.4

0.9

38.95

41.19

42.95

45.40

33.22

34.81

36.10

38.16

23.97

25.10

26.23

27.73

19.77

20.65

21.73

22.97

11.39

12.16

13.11

13.86

9.60

10.25

11.06

11.69

6.85

1.39

6.84

4.91

1.25

7.51

1.82

7.51

5.56

1.79

8.38

2.61

8.52

6.54

2.59

8.85

2.76

23.95

25.80

27.50

30.58

20.79

22.52

24.12

26.82

15.88

17.21

18.54

20.62

13.38

14.59

15.79

17.56

8.05

8.89

10.16

11.29

9.47

7.28

2.88

1. Based on characterization, not tested in production unless otherwise specified.

2. Refer to Table 45 and RM0383 for the possible PLL VCO setting

3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).

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STM32F412xE/G Electrical characteristics

Table 27. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator disabled) running from Flash memory - V

= 1.7 V

Typ Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) T

25 °C

85 °C

105 °C

125 °C

Unit

Supply current in Run mode

External clock,

PLL ON, all peripherals enabled

(2)(3)

HSI, PLL OFF, all peripherals enabled

External clock, PLL ON

all peripherals disabled

HSI, PLL OFF, all

peripherals disabled

100

35.9

29.4

22.4

18.6

10.3

8.9

6.7

1.1

21.7

18.0

14.6

12.5

7.2

6.3

4.9

1.0

38.55

40.77

42.52

44.95

31.59

33.12

34.42

36.38

24.02

25.15

26.28

27.78

20.07

21.08

22.05

23.30

11.62

12.39

13.34

14.10

9.85

10.59

11.32

11.96

7.26

1.44

7.15

5.37

1.30

8.04

1.99

7.99

6.20

1.91

8.80

2.66

8.84

7.03

2.65

9.30

2.81

23.55

25.48

27.07

30.10

19.16

20.93

22.39

24.89

15.93

17.32

18.59

20.68

13.63

14.90

16.07

17.87

8.25

9.26

10.26

11.41

9.83

7.82

2.95

1. Based on characterization, not tested in production unless otherwise specified.

2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).

3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the analog part.

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Table 28. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator enabled with prefetch) running from Flash memory - V

= 3.6 V

Typ Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) T

25 °C

85 °C

105 °C

125 °C

Unit

Supply current in Run mode

External clock,

PLL ON, all peripherals enabled

HSI, PLL OFF, all peripherals enabled

External clock,

PLL ON

all peripherals disabled

HSI, PLL OFF, all peripherals disabled

(2)

100

38.9

32.8

23.6

18.7

10.1

8.6

6.3

1.1

24.7

21.4

15.8

12.6

7.0

6.0

4.5

0.9

41.10

42.85

44.28

46.80

34.61

35.77

36.72

38.81

24.96

25.84

26.64

28.16

19.90

20.67

21.45

22.67

11.11

11.70

12.40

13.10

9.46

10.07

10.81

11.43

6.77

1.35

6.67

4.80

1.25

7.42

1.84

7.37

5.47

1.81

8.21

2.59

8.26

6.33

2.58

8.68

2.74

26.11

27.59

28.84

32.07

22.22

23.53

24.66

27.42

16.80

17.90

18.99

21.12

13.51

14.52

15.54

17.28

7.85

8.57

9.39

10.44

9.19

7.04

2.87

1. Based on characterization, not tested in production unless otherwise specified.

2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).

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Table 29. Typical and maximum current consumption in Sleep mode - V

= 3.6 V

Typ Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) T

25 °C

85 °C

105 °C

125 °C

Unit

All peripherals enabled

(2)

External clock,

PLL ON,

Flash deep power down

100

17.7

14.3

10.0

7.9

18.48

(3)

19.83

21.70

24.00

15.39

16.31

17.48

19.34

10.71

11.35

12.13

13.41

8.53

9.13

9.89

10.94

4.4

4.0

2.7

4.99

4.42

2.83

5.46

6.11

4.95

5.64

3.47

4.21

6.75

6.23

4.66

All peripherals enabled

(2)

HSI, PLL OFF,

Flash deep power down

1 0.5

0.68

1.25

1.92

2.12

All peripherals enabled

(2)

External clock,

PLL ON Flash ON

100

18.1

14.7

10.3

8.2

19.39

15.80

11.02

8.88

20.70

16.71

11.66

9.53

22.24

17.92

12.45

10.26

24.59

19.82

13.77

11.35

Supply current in Sleep mode

All peripherals enabled

(2)

HSI, PLL OFF, Flash ON

4.7

4.2

2.7

0.8

3.2

2.6

2.0

1.7

5.30

4.67

3.10

0.93

3.42

(3)

5.82

5.18

3.72

1.50

6.53

5.90

4.50

2.18

4.98

6.88

3.63

4.44

2.81

3.46

2.54

3.12

7.23

6.53

4.98

2.41

9.70

6.26

4.87

4.39

4.08

3.92

2.71

All peripherals disabled,

External clock,

PLL ON

(2)

Flash deep power down

All peripherals disabled,

HSI, PLL OFF (2) ,

Flash deep power down

100

1.2

1.3

0.5

0.4

3.09

2.33

2.02

1.63

1.62

0.63

0.53

2.21

2.09

1.24

1.14

2.89

2.78

1.92

1.82

2.57

All peripherals disabled,

External clock,

PLL ON

(2)

, Flash ON

100

3.6

3.0

2.3

2.0

1.4

1.5

4.17

3.49

2.69

2.33

1.88

4.84

5.63

4.13

4.88

3.23

3.85

2.83

3.45

2.39

3.06

2.43

3.06

7.93

6.88

5.42

4.86

4.31

All peripherals disabled,

HSI, PLL OFF

(2)

Flash ON

0.8

0.7

1. Based on characterization, not tested in production unless otherwise specified.

0.91

0.78

1.50

1.37

2.22

2.09

3.13

2.95

2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).

3. Tested in production.

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Electrical characteristics STM32F412xE/G

Table 30. Typical and maximum current consumption in Sleep mode - V

= 1.7 V

Typ Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) T

25 °C

85 °C

105 °C

125 °C

Unit

External clock,

PLL ON,

Flash deep power down, all peripherals enabled

(2)

100

17.3

14.0

9.7

7.6

18.62

19.90

21.40

23.67

15.08

16.04

17.16

18.97

10.41

8.27

11.02

8.89

11.80

9.62

13.06

10.64

4.2

3.7

4.79

4.11

5.35

4.67

6.00

5.31

6.63

5.88

Supply current in Sleep mode

HSI, PLL OFF

Flash deep power down, all peripherals enabled

2.4

0.5

2.81

0.67

3.45

1.27

4.20

1.91

4.64

2.11

100

17.8

14.4

19.08

20.35

21.90

24.22

15.49

16.42

17.59

19.46

External clock, PLL ON

all peripherals enabled,

Flash ON

10.0

7.9

4.4

4.0

10.76

8.58

4.99

4.42

11.43

9.19

5.54

4.95

12.18

13.47

9.94

10.99

6.21

6.87

5.64

6.23

HSI, PLL OFF

Flash ON

, all peripherals enabled,

2.7

0.8

3.09

0.93

3.75

1.52

4.49

2.18

4.97

2.41

All peripherals disabled,

External clock,

PLL ON

Flash deep power down

100

2.9

2.4

1.7

1.4

3.51

2.83

2.08

1.77

4.14

3.46

2.59

2.23

4.90

4.16

3.18

2.84

5.59

4.74

3.63

3.24

1.0

1.3

1.37

1.88

2.50

2.85

Supply current in Sleep mode

All peripherals disabled,

HSI, PLL OFF (2)

Flash deep power down

0.5

0.4

3.3

2.8

2.1

0.63

0.52

3.22

2.62

1.89

1.23

1.13

3.98

3.30

2.50

1.91

1.81

4.90

4.16

3.18

2.18

2.07

5.59

4.74

3.63

All peripherals disabled,

External clock, PLL

, Flash ON

100

1.7

1.2

1.3

1.58

1.28

2.16

1.82

2.84

2.50

3.24

2.85

All peripherals disabled,

HSI, PLL OFF

Table 57: I/O static characteristics .

, Flash

0.8

0.7

1. Based on characterization, not tested in production unless otherwise specified.

0.88

0.77

1.36

1.26

1.91

1.81

2.18

2.07

2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).

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STM32F412xE/G Electrical characteristics

Symbol

Table 31. Typical and maximum current consumptions in Stop mode - V

= 1.7 V

Typ

(1)

Max

(1)

Conditions Parameter

25 °C

85 °C

105 °C

125 °C

Unit

121.1 168.0 648.7 1213.0 2970.0

DD_STOP

Flash in Stop mode, all oscillators OFF, no independent watchdog

Main regulator usage

Low power regulator usage

Flash in Deep power down mode, all oscillators OFF, no independent watchdog

Main regulator usage

Low power regulator usage

Low power low voltage regulator usage

1. Based on characterization, not tested in production.

50.8

74.8 651.3 1328.0 2730.0

79.1 122.0 609.1 1181.0 2540.0

22.4

74.7 631.9 1286.0 2680.0

18.5

40.0 548.3 1145.0 2480.0

µA

Symbol

Table 32. Typical and maximum current consumption in Stop mode - V

=3.6 V

Typ Max

(1)

Conditions Parameter

25 °C

85 °C

105 °C

125 °C

Flash in Stop mode, all oscillators OFF, no independent watchdog

Main regulator usage

Low power regulator usage

124.0 179.0

(2)

907.2 1762.0 3000.0

(2)

52.8 75.0

(2)

757.6 1559.0

2750.0

Unit

DD_STOP Flash in Deep power down mode, all oscillators OFF, no independent watchdog

Main regulator usage

Low power regulator usage

Low power low voltage regulator usage

87.6

123.0 698.5 1374.0

2550.0

26.2

74.7

737.2 1515.0

2700.0

20.1 40.0

(2)

619.1 1299.0 2500.0

(2)

µA

1. Based on characterization, not tested in production.

2. Tested in production.

Table 33. Typical and maximum current consumption in Standby mode - V

= 1.7 V

Typ

(1)

Max

(2)

Symbol Parameter Conditions

25 °C

85 °C

105 °C

125 °C

Unit

DD_STBY

Low-speed oscillator (LSE in low drive mode) and RTC ON

Supply current in

Standby mode

Low-speed oscillator (LSE in high drive mode) and RTC ON

RTC and LSE OFF

1.8

2.6

3.7

4.5

12.9

13.7

1.1

3.0

12.2

1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.

2. Based on characterization, not tested in production unless otherwise specified.

23.7

24.5

50.7

51.6

50.0

µA

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Electrical characteristics STM32F412xE/G

Table 34. Typical and maximum current consumption in Standby mode - V

= 3.6 V

Typ

(1)

Max

(2)

Symbol Parameter Conditions

25 °C

85 °C

105 °C

125 °C

Unit

DD_STBY

Low-speed oscillator (LSE in low drive mode) and RTC ON

Supply current in

Standby mode

Low-speed oscillator (LSE in high drive mode) and RTC ON

RTC and LSE OFF

3.7

4.5

5.4

6.2

17.2

18.0

31.2

32.0

62.3

63.2

2.6

4.0

16.0

30.0

61.0

(3)

1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.

2. Guaranteed by characterization, not tested in production unless otherwise specified.

3. Tested in production.

µA

Table 35. Typical and maximum current consumptions in V

BAT

mode

Typ Max

(2)

Symbol Parameter Conditions

(1)

= 25 °C

85 °C

105 °C

125 °C Unit

BAT

1.7 V

BAT

2.4 V

= V

BAT

3.3 V

BAT

3.6 V

DD_VBAT

Backup domain supply current

Low-speed oscillator (LSE in low-drive mode) and RTC ON

Low-speed oscillator (LSE in high-drive mode) and RTC ON

RTC and LSE OFF

0.74

1.52

0.87

1.70

1.04

1.97

1.11

2.09

3.0

3.8

0.04

0.05

2.0

1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a C

of 6 pF for typical values.

2. Guaranteed by characterization, not tested in production.

BAT

= 3.6 V

5.0

5.8

4.0

10.0

11.6

8.0

µA

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STM32F412xE/G Electrical characteristics

Figure 24. Typical V

BAT

current consumption (LSE and RTC ON/LSE oscillator

“low power” mode selection)

7HPSHUDWXUH&

06Y9

Figure 25. Typical V

BAT

current consumption (LSE and RTC ON/LSE oscillator

“high drive” mode selection)

7HPSHUDWXUH&

06Y9

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166

Electrical characteristics STM32F412xE/G

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 37: Peripheral current consumption ), the I/Os used by an application also contribute to the current consumption.

When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

=

×

C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

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Table 36. Switching output I/O current consumption

Symbol Parameter Conditions

(1)

I/O toggling

frequency (f

)

Typ Unit

= 3.3 V

C = C

INT

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz

C = C

INT

= 3.3 V

EXT

= 0 pF

+ C

EXT

+ C

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz

2 MHz

IDDIO

I/O switching current

C = C

EXT

INT

= 3.3 V

=10 pF

+ C

EXT

+ C

8 MHz

25 MHz

50 MHz

60 MHz

0.65

1.85

2.45

4.70

84 MHz

90 MHz

2 MHz

8 MHz

8.80

10.47

0.25

1.00

= 3.3 V

C = C

EXT

INT

= 22 pF

+ C

EXT

+ C

25 MHz

50 MHz

3.45

7.15

60 MHz

2 MHz

11.55

0.32

= 3.3 V

EXT

= 33 pF

C = C

INT

+ C

EXT

+ C

8 MHz

25 MHz

1.27

3.88

50 MHz

1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).

12.34

2.40

3.55

4.23

0.20

0.10

0.35

1.05

2.20

0.05

0.15

0.45

0.85

1.00

1.40

1.67

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Electrical characteristics STM32F412xE/G

On-chip peripheral current consumption

The MCU is placed under the following conditions:

• At startup, all I/O pins are in analog input configuration.

• All peripherals are disabled unless otherwise mentioned.

• The ART accelerator is ON.

• Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V.

• HCLK is the system clock at 100 MHz. f

PCLK1

= f

HCLK

/2, and f

PCLK2

= f

HCLK

The given value is calculated by measuring the difference of current consumption

– with all peripherals clocked off,

– with only one peripheral clocked on,

– scale 1 with f

HCLK

= 100 MHz,

– scale 2 with f

HCLK

= 84 MHz,

– scale 3 with f

HCLK

= 64 MHz.

• Ambient operating temperature is 25 °C and V

=3.3 V.

AHB1

AHB2

AHB3

Table 37. Peripheral current consumption

(Typ)

Peripheral

Scale 1 Scale 2

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOF

GPIOG

GPIOH

CRC

DMA1

(1)

DMA2

The wakeup times given in Table 38

RNG

USB_OTG_FS

FSMC

QSPI

Unit

Scale 3

1.84

1.90

1.77

1.67

1.75

1.80

1.67

1.58

1.67

1.55

1.61

1.50

1.42

1.48

1.65

0.62

1.56

0.57

1.39

0.53

0.26

0.25

0.22

1,71N+2,98 1,62N+2,87 1,45N+2,58

1,78N+2,62 1,70N+2.53 1,52N+2.26

0.77

19.68

0.74

18.73

0.66

16.78

5.36

9.99

5.11

9.51

4.56

8.53

µA/MHz

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STM32F412xE/G Electrical characteristics

APB1

Table 37. Peripheral current consumption (continued)

(Typ)

Peripheral

Scale 1 Scale 2 Scale 3

AHB-APB1 bridge

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

TIM12

TIM13

TIM14

WWDG

SPI2/I2S2

SPI3/I2S3

USART2

USART3

I2C1

I2C2

I2C3

I2CFMP1

CAN1

CAN2

PWR

6.22

4.70

4.60

1.76

4.04

4.26

4.42

4.44

1.10

13.62

10.56

10.72

13.46

2.92

2.72

4.32

4.36

5.96

6.18

5.86

1.82

5.93

4.48

4.38

1.67

3.83

4.05

4.19

4.21

1.00

12.95

10.05

10.21

12.83

2.79

2.60

4.10

4.17

4.14

5.69

5.90

5.52

1.69

5.28

3.97

3.91

1.47

3.41

3.62

3.75

0.94

11.59

8.97

9.12

11.47

2.47

2.31

3.66

3.69

5.06

5.25

4.97

1.56

Unit

µA/MHz

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Electrical characteristics STM32F412xE/G

Table 37. Peripheral current consumption (continued)

(Typ)

Peripheral

Scale 1 Scale 2 Scale 3

APB2

AHB-APB2 bridge

TIM1

TIM8

USART1

USART6

ADC1

SDIO

SPI1

SPI4

SYSCFG

TIM9

TIM10

TIM11

SPI5

DFSDM1

Bus Matrix

1. N is the number of stream enable (1...8).

1.81

1.44

4.02

3.06

1.36

1.45

0.49

2.92

1.79

0.07

6.46

6.29

3.11

3.02

3.31

3.51

1.93

1.54

4.25

3.23

1.47

1.56

0.54

3.09

1.91

0.09

6.83

6.63

3.31

3.21

3.51

3.74

1.64

1.30

3.61

2.73

1.23

1.31

0.45

2.63

1.61

0.08

5.81

5.63

2.80

2.73

2.98

3.17

Unit

µA/MHz

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STM32F412xE/G

6.3.7 Wakeup time from low-power modes

Electrical characteristics

are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:

• For Stop or Sleep modes: the wakeup event is WFE.

• WKUP (PA0/PC0/PC1) pins are used to wakeup from Standby, Stop and Sleep modes.

Figure 26. Low-power mode wakeup

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All timings are derived from tests performed under ambient temperature and V

=3.3 V.

DocID028087 Rev 7

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Electrical characteristics STM32F412xE/G

Symbol

Table 38. Low-power mode wakeup timings (1)

Parameter Conditions Min

(1)

Typ

(1)

Max

(1) Unit t t t t t t

WUSLEEP

WUSLEEPFDSM

WUSTOP

WUSTDBY

WUFLASH

Wakeup from Sleep mode

Wakeup from STOP mode

Code execution on Flash

Flash memory in Deep power down mode

Main regulator

Main regulator, Flash memory in Deep power down mode

Wakeup from Stop mode, regulator in low power mode

(2)

Regulator in low power mode, Flash memory in

Deep power down mode

Main regulator with Flash in

Stop mode or Deep power down

Wakeup from STOP mode code execution on RAM

(3) Wakeup from Stop mode, regulator in low power mode and Flash in Stop mode or

Deep power down

external clock signal has to respect the Table 57

Wakeup from Standby mode

From Flash_Stop mode

Wakeup of Flash

From Flash Deep power down mode

12.9

104.9

20.8

112.9

4.9

12.8

316.8

50.0

15.0

120.0

28.0

130.0

7.0

20.0

400.0

11.0

50.0

clk cycles

1. Guaranteed by characterization, not tested in production.

2. The specification is valid for wakeup from regulator in low power mode or low power low voltage mode, since the timing difference is negligible.

3. For the faster wakeup time for code execution on RAM, the Flash must be in STOP or DeepPower Down mode (see reference manual RM0402).

µs

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STM32F412xE/G Electrical characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The

. However, the recommended clock input

waveform is shown in Figure 27 .

The characteristics given in

Table 39 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

external clock signal has to respect the Table 57

Symbol

Table 39. High-speed external user clock characteristics

Parameter f

HSE_ext

External user clock source frequency

(1)

HSEH

HSEL t w(HSE) t w(HSE) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

(1)

OSC_IN rise or fall time

(1)

OSC_IN input capacitance

(1)

Duty cycle

OSC_IN Input leakage current

1. Guaranteed by design, not tested in production.

Conditions

≤ V

Min

0.7V

Typ

Max Unit

0.3V

±1

MHz

V ns pF

µA

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Electrical characteristics STM32F412xE/G

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The

. However, the recommended clock input

waveform is shown in Figure 28 .

The characteristics given in

Table 40 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

characterization results obtained with typical external components specified in Table 41

Symbol

Table 40. Low-speed external user clock characteristics

Parameter f

LSE_ext

LSEH

User External clock source frequency

(1)

OSC32_IN input pin high level voltage

LSEL t w(LSE) t f(LSE) t r(LSE) t f(LSE)

C in(LSE)

DuCy

(LSE)

OSC32_IN input pin low level voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

(1)

OSC32_IN input capacitance

Duty cycle

(1)

OSC32_IN Input leakage current

1. Guaranteed by design, not tested in production.

Conditions

≤ V

Min

0.7V

450

Typ

32.768

Max

1000

0.3V

±1

Unit kHz

V ns pF

µA

Figure 27. High-speed external clock source AC timing diagram

6(3%(

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TR(3%

4(3%

TF(3%

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F(3%?EXT

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T7(3% T

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STM32F412xE/G Electrical characteristics

Figure 28. Low-speed external clock source AC timing diagram

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High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 41. HSE 4-26 MHz oscillator characteristics (1)

Parameter Conditions Min Typ Max Unit f

OSC_IN

Oscillator frequency

Feedback resistor

200

26 MHz

k Ω

ACC

HSE

(2)

G t

DD m_crit_max

SU(HSE)

(3)

HSE current consumption

HSE accuracy

Maximum critical crystal g m

Startup time

=3.3 V,

ESR= 30 Ω ,

=5 pF @25 MHz

=3.3 V,

ESR= 30 Ω ,

=10 pF @25 MHz

Startup

is stabilized

-500

450

530

500

µA ppm mA/V ms

1. Guaranteed by design, not tested in production.

2. This parameter depends on the crystal used in the application. The minimum and maximum values must be respected to comply with USB standard specifications.

3. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

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Electrical characteristics

Note:

STM32F412xE/G

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (Typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 29

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 29. Typical application with an 8 MHz crystal

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1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 42

The LSE high-power mode allows to cover a wider range of possible crystals but with a cost of higher power consumption.

Symbol

ACC

LSE

(2)

Table 42. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions Min Typ Max Unit

Feedback resistor 18.4

M Ω

LSE current consumption

LSE accuracy

G m

_crit_max Maximum critical crystal g m t

SU(LSE)

(3) startup time

1. Guaranteed by design, not tested in production.

Low-power mode

(default)

High-drive mode

Startup, low-power mode

Startup, high-drive mode

is stabilized

-500

µA

500 ppm

0.56

1.50

µA/V s

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STM32F412xE/G Electrical characteristics

2. This parameter depends on the crystal used in the application. Refer to the application note AN2867.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is guaranteed by characterization and not tested in production. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

For information about the LSE high-power mode, refer to the reference manual RM0383.

Figure 30. Typical application with a 32.768 kHz crystal

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6.3.9 Internal clock source characteristics

The parameters given in

Table 43 and

Table 44 are derived from tests performed under

ambient temperature and V

supply voltage conditions summarized in

Table 16

High-speed internal (HSI) RC oscillator

Symbol f

HSI

ACC

HSI

Parameter

Table 43. HSI oscillator characteristics (1)

Conditions

Frequency -

HSI user trimming step

(2)

Accuracy of the HSI oscillator

Factory-calibrated

= -40 to 125 °C

(3)

= -40 to 105 °C

(3)

= -10 to 85 °C

(3)

= 25 °C

(4)

t su(HSI)

(2)

HSI oscillator startup time

DD(HSI)

(2)

HSI oscillator power consumption

1. V

= 3.3 V, T

= -40 to 125 °C unless otherwise specified.

2. Guaranteed by design, not tested in production

3. Based on characterization, not tested in production

4. Factory calibrated, parts not soldered.

Min Typ Max Unit

-1

-8

-4

-8

2.2

MHz

5.5

4.5

µs

60 80 µA

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Electrical characteristics

Figure 31. ACC

HSI

versus temperature

STM32F412xE/G

4! #

-IN

-AX

4YPICAL

-36

1. Guaranteed by characterization, not tested in production.

Low-speed internal (LSI) RC oscillator

Symbol

Table 44. LSI oscillator characteristics

(1)

Parameter f

LSI

(2) t su(LSI)

(3)

DD(LSI)

(3)

Frequency

LSI oscillator startup time

LSI oscillator power consumption

1. V

= 3 V, T

= -40 to 125 °C unless otherwise specified.

2. Guaranteed by characterization, not tested in production.

3. Guaranteed by design, not tested in production.

Min

Typ

0.4

Figure 32. ACC

LSI

versus temperature

Max

0.6

Unit kHz

µs

µA

MAX

AVG

MIN

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STM32F412xE/G Electrical characteristics

The parameters given in

Table 45 and

Table 46 are derived from tests performed under

temperature and V

supply voltage conditions summarized in

Symbol f

PLL_IN f

PLL_OUT f

PLL48_OUT f

VCO_OUT t

LOCK

Jitter

(3)

DD(PLL)

(4)

DDA(PLL)

(4)

Parameter

PLL input clock

(1)

Table 45. Main PLL characteristics

Conditions

Min

0.95

(2)

24 PLL multiplier output clock

48 MHz PLL multiplier output clock

PLL VCO output

PLL lock time

Cycle-to-cycle jitter

Period Jitter

Bit Time CAN jitter

PLL power consumption on VDD

PLL power consumption on

VDDA

VCO freq = 100 MHz

VCO freq = 432 MHz

RMS peak to peak

System clock

100 MHz

RMS peak to peak

Cycle to cycle at 1 MHz on 1000 samples.

VCO freq = 100 MHz

VCO freq = 432 MHz

VCO freq = 100 MHz

VCO freq = 432 MHz

100

0.15

0.45

0.30

0.55

Typ

± 150

± 200

330

Max

2.10

100

432

200

300

0.40

0.75

0.40

0.85

Unit

MHz

µs ps mA

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S.

2. Guaranteed by design, not tested in production.

3. The use of two PLLs in parallel could degraded the Jitter up to +30%.

4. Guaranteed by characterization, not tested in production.

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Electrical characteristics STM32F412xE/G

Symbol

Table 46. PLLI2S (audio PLL) characteristics

Parameter Conditions Min Typ f f f t

PLLI2S_IN

PLLI2S_OUT

VCO_OUT

LOCK

Jitter

(3)

DD(PLLI2S)

(4)

DDA(PLLI2S)

interferences (see Table 53: EMI characteristics for LQFP144

PLLI2S input clock

(1)

PLLI2S multiplier output clock

PLLI2S VCO output

PLLI2S lock time

Master I2S clock jitter

WS I2S clock jitter

PLLI2S power consumption on

DDA

VCO freq = 100 MHz

VCO freq = 432 MHz

Cycle to cycle at

12.288 MHz on

48 kHz period,

N=432, R=5

Average frequency of

12.288 MHz

N = 432, R = 5 on 1000 samples

RMS

peak to peak

Cycle to cycle at 48 KHz on 1000 samples

VCO freq = 100 MHz

VCO freq = 432 MHz

VCO freq = 100 MHz

VCO freq = 432 MHz

0.95

100

(2)

100

0.15

0.45

0.30

0.55

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design, not tested in production.

3. Value given with main PLL running.

4. Guaranteed by characterization, not tested in production.

± 280

400

0.40

0.75

0.40

0.85

Max

2.10

216

432

200

300

Unit

MHz

µs ps mA

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6.3.11 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic

). It is available only on the main PLL.

Symbol

Table 47. SSCG parameter constraints

Parameter f

Mod md

MODEPER * INCSTEP

Modulation frequency

Peak modulation depth

(Modulation period) * (Increment Step)

1. Guaranteed by design, not tested in production.

Min

0.25

Typ

Max

(1)

-1

Unit kHz

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

MODEPER = [

PLL_IN

⁄ ( 4 × f

Mod

) ] f

PLL_IN and f

Mod must be expressed in Hz.

As an example:

If f

PLL_IN

= 1 MHz, and f

MOD

= 1 kHz, the modulation depth (MODEPER) is given by equation 1:

MODEPER

= round 10

⁄ ( 4 × 10

) ] =

250

Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

INCSTEP = round [ ( ( 2

– 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ] f

VCO_OUT must be expressed in MHz.

With a modulation depth (md) = ± 2 % (4 % peak to peak), and PLLN = 240 (in MHz):

INCSTEP

= round [ ( ( 2

–

1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ]

126md(quantitazed)%

An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and

INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized

% = ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2

– 1 ) × PLLN )

As a result: md quantized

( 250 × 126 × 100 × 5 ) ⁄ ( ( 2

–

1 ) × 240 )

2.002%(peak)

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Electrical characteristics STM32F412xE/G

Figure 33

and

Figure 34 show the main PLL output clock waveforms in center spread and

down spread modes, where:

F0 is f

PLL_OUT

nominal.

T mode

is the modulation period.

md is the modulation depth.

Figure 33. PLL output clock waveforms in center spread mode

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4IME

Figure 34. PLL output clock waveforms in down spread mode

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STM32F412xE/G Electrical characteristics

Symbol

Flash memory

The characteristics are given at T

= -40 to 125 °C unless otherwise specified.

The devices are shipped to customers with the Flash memory erased.

Parameter

Supply current

Table 48. Flash memory characteristics

Conditions Min

Write / Erase 8-bit mode, V

= 1.7 V

Write / Erase 16-bit mode, V

= 2.1 V

Write / Erase 32-bit mode, V

= 3.3 V

Typ

Max

Unit mA

Symbol

Table 49. Flash memory programming

Parameter Conditions t t

ERASE16KB t prog

Word programming time

Sector (16 KB) erase time

Mass erase time

Program/erase parallelism

(PSIZE) = x 8/16/32

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32 t

ERASE64KB

Sector (64 KB) erase time

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32 t

ERASE128KB

Program/erase parallelism

(PSIZE) = x 8

Sector (128 KB) erase time

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

Min

(1)

Typ Max

(1)

Unit

16 100

(2)

400

300

250

1200 2400

700 1400

550 1100

1.3

800

600

500

2.6

µs ms ms s s

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Electrical characteristics STM32F412xE/G

Symbol

Table 49. Flash memory programming (continued)

Parameter Conditions

V prog

Programming voltage

32-bit program operation

16-bit program operation

8-bit program operation

1. Guaranteed by characterization, not tested in production.

2. The maximum programming time is measured after 100K erase operations.

Min (1)

2.7

2.1

1.7

Typ Max (1)

3.6

Unit

Symbol

Table 50. Flash memory programming with V

PP voltage

Parameter Conditions

Min

(1)

Typ Max

(1)

16 100

(2) t prog t

ERASE16KB t

ERASE64KB t

ERASE128KB t

V prog

Double word programming

Sector (16 KB) erase time

Sector (64 KB) erase time

Sector (128 KB) erase time

Mass erase time

Programming voltage

0 to +40 °C

= 3.3 V

= 8.5 V

VPP

(3)

voltage range

Minimum current sunk on the V

Cumulative time during which V

PP is applied

1. Guaranteed by design, not tested in production.

2. The maximum programming time is measured after 100K erase operations.

3. V

should only be connected during programming/erasing.

2.7

230

490

875

6.9

3.6

Unit

µs ms s

V mA hour

Symbol

Table 51. Flash memory endurance and data retention

Value

Parameter Conditions

Min

(1)

N t

END

RET

Endurance

Data retention

= -40 to +85 °C (temp. range 6)

= -40 to +105 °C (temp. range 7)

= -40 to +125 °C (temp. range 3)

1 kcycle

(2)

at T

= 85 °C

1 kcycle (2) at T

= 105 °C

1 kcycle

(2)

at T

= 125 °C

10 kcycle

(2)

at T

= 55 °C

1. Guaranteed by characterization, not tested in production.

2. Cycling performed over the whole temperature range.

Unit kcycles

Years

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Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A burst of fast transient voltage (positive and negative) is applied to V

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in

Table 53

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

Table 52. EMS characteristics for LQFP144 package

Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

= 3.3 V, LQFP144

= +25 °C, f

HCLK

= 100 MHz, conforms to IEC 61000-4-2

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

= 3.3 V, LQFP144

= +25 °C, f

HCLK

= 100 MHz, conforms to IEC 61000-4-4

When the application is exposed to a noisy environment, it is recommended to avoid pin exposition to disturbances. The pins showing a middle range robustness are: PA0, PA1,

PA2, on LQFP144 packages and PDR_ON on WLCSP49.

As a consequence, it is recommended to add a serial resistor (1 k Ω maximum) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than

50 mm on PCB).

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

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EMI

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with IEC61967-2 standard which specifies the test board and the pin loading.

Table 53. EMI characteristics for LQFP144

Symbol Parameter Conditions

Peak level

= 3.6 V, T

= 25 °C, LQFP144 package, conforming to IEC 61967-2,

EEMBC, ART ON, all peripheral clocks enabled, clock dithering disabled.

Monitored frequency band

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1 GHz

EMI Level

Max vs.

HSE

CPU

]

8/100 MHz

3.5

Unit dBµV

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6.3.14 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Symbol Ratings

Table 54. ESD absolute maximum ratings

Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage

(human body model)

= +25 °C conforming to JESD22-A114

Electrostatic discharge voltage

(charge device model)

= +25 °C conforming to ANSI/ESD STM5.3.1,

UFBGA144, UFBGA100, LQFP100, LQFP64,

UFQFPN48

= +25 °C conforming to ANSI/ESD STM5.3.1,

WLCSP64

= +25 °C conforming to ANSI/ESD STM5.3.1,

LQFP144

1. Guaranteed by characterization, not tested in production.

2000

500

400

250

Symbol

Static latchup

Two complementary static tests are required on six parts to assess the latchup performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latchup standard.

Parameter

Static latch-up class

Table 55. Electrical sensitivities

Conditions

= +125 °C conforming to JESD78A

Class

II level A

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Electrical characteristics STM32F412xE/G

Note:

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of conventional limits of induced leakage current on adjacent pins

(out of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.

The test results are given in

Table 56

Symbol

Table 56. I/O current injection susceptibility

(1)

Functional susceptibility

Description

Negative injection

Positive injection

INJ

Injected current on BOOT0 pin

Injected current on NRST pin

Injected current on PB3, PB4, PB5, PB6,

PB7, PB8, PB9, PC13, PC14, PC15, PH1,

PDR_ON, PC0, PC1,PC2, PC3, PD1,

PD5, PD6, PD7, PE0, PE2, PE3, PE4,

PE5, PE6

Injected current on any other FT pin

Injected current on any other pins

1. NA = not applicable .

–0

–5

Unit mA

It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

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General input/output characteristics

Unless otherwise specified, the parameters given in Table 57

are derived from tests

performed under the conditions summarized in Table 16

. All I/Os are CMOS and TTL compliant.

Symbol

Table 57. I/O static characteristics

Parameter

FT, TC and NRST I/O input low level voltage

Conditions

1.7 V ≤ V

≤ 3.6 V

Min

BOOT0 I/O input low level voltage

1.75 V ≤ V

≤ 3.6 V,

-40 °C ≤ T

≤ 125 °C

1.7 V ≤ V

0 °C ≤ T

≤ 3.6 V,

≤ 125 °C

FT, TC and NRST I/O input high

level voltage

(5)

1.7 V ≤ V

≤ 3.6 V 0.7V

BOOT0 I/O input high level voltage

1.75 V ≤ V

-40 °C ≤ T

≤ 3.6 V,

≤ 125 °C

1.7 V ≤ V

0 °C ≤ T

≤ 3.6 V,

≤ 125 °C

0.17V

+0.7

FT, TC and NRST I/O input hysteresis

1.7 V ≤ V

≤ 3.6 V 10% V

4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 56: I/O current injection susceptibility

HYS

I lkg

BOOT0 I/O input hysteresis

I/O input leakage current

(4)

I/O FT/TC input leakage current

(5)

1.75 V ≤ V

≤ 3.6 V,

-40 °C ≤ T

≤ 125 °C

1.7 V ≤ V

0 °C ≤ T

≤ 3.6 V,

≤ 125 °C

≤ V

= 5 V

0.1

Typ Max

0.3V

(1)

0.1V

+0.1

(2)

± 1

Weak pull-up equivalent resistor

(6)

All pins except for

PA10

(OTG_FS_ID)

PA10

(OTG_FS_ID)

Weak pull-down equivalent resistor

(7)

All pins except for

PA10

(OTG_FS_ID)

PA10

(OTG_FS_ID)

(8)

I/O pin capacitance

1. Guaranteed by test in production.

2. Guaranteed by design, not tested in production.

= V

Unit

µA k Ω pF

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Electrical characteristics STM32F412xE/G

3. With a minimum of 200 mV.

5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be

higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 56: I/O current injection susceptibility

6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order).

7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order).

8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization, not tested in production.

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements for FT and TC I/Os is shown in Figure 35

Figure 35. FT/TC I/O input characteristics

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STM32F412xE/G Electrical characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ± 8 mA, and sink or source up to ± 20 mA (with a relaxed V

) except PC13, PC14 and PC15 which can sink or source up to ± 3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

. In particular:

• The sum of the currents sourced by all the I/Os on V

DD, consumption of the MCU sourced on V

Σ I

VDD

(see

Table 14 ).

DD, plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

SS consumption of the MCU sunk on V

Σ I

VSS

(see

Table 14 ).

plus the maximum Run

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in Table 58

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 16 . All I/Os are CMOS and TTL compliant.

Symbol

Table 58. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)

(3)

(1)

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

(2)

= +8 mA

2.7 V ≤ V

≤ 3.6 V

TTL port

(2)

=+8 mA

2.7 V ≤ V

≤ 3.6 V

–0.4

2.4

0.4

(1)

(3)

(1)

(3)

(1)

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

= +20 mA

2.7 V ≤ V

= +6 mA

1.8 V ≤ V

1.7 V ≤ V

≤

3.6 V

= +4 mA

3.6 V

–1.3

–0.4

Table 14 and the sum of I

–0.4

(5)

1.3

0.4

(4)

(5)

1. The I

current sunk by the device must always respect the absolute maximum rating specified in

Table 14

. and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I

current sourced by the device must always respect the absolute maximum rating specified in

(I/O ports and control pins) must not exceed I

VDD

4. Guaranteed by characterization results, not tested in production.

5. Guaranteed by design, not tested in production.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 36 and

Table 59 , respectively.

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Electrical characteristics STM32F412xE/G

Unless otherwise specified, the parameters given in Table 59

are derived from tests performed under the ambient temperature and V

DD in

Unless otherwise specified, the parameters given in Table 60

supply voltage conditions summarized

Table 59. I/O AC characteristics (1)(2)

OSPEEDRy

[1:0] bit value

(1)

Symbol

Parameter Conditions f max(IO)out

Maximum frequency

(3)

= 50 pF, V

≥ 2.70 V

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V t f(IO)out

/ t r(IO)out

Output high to low level fall time and output low to high level rise time

= 50

3.6 V pF, V

= 1.7 V to f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out t f(IO)out

/ t r(IO)out t

EXTIpw

Output high to low level fall time and output low to high level rise time

F max(IO)out

Maximum frequency

(3)

Output high to low level fall time and output low to high level rise time

Pulse width of external signals detected by the EXTI controller

= 50 pF, V

≥ 2.70 V

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V

= 50 pF, V

≥ 2.7 V

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V

= 40 pF, V

≥ 2.70 V

= 40 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V

= 40 pF, V

≥ 2.70 V

= 40 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V

= 30 pF, V

≥ 2.70 V

= 30 pF, V

≥ 1.7 V

= 30 pF, V

≥ 2.70 V

= 30 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V

Min Typ Max Unit

10 -

100

MHz ns ns

100 (4)

(4)

100 (4)

(4)

2.5

12.5

MHz ns

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1. Guaranteed by characterization, not tested in production.

2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register.

3. The maximum frequency is defined in

Figure 36

4. For maximum frequencies above 50 MHz and V

> 2.4 V, the compensation cell should be used.

Figure 36. I/O AC characteristics definition

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DLG

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Table 57 ).

are derived from tests performed under the ambient temperature and V

supply voltage conditions summarized in

Table 16 . Refer to

Table 57: I/O static characteristics for the values of VIH and VIL for

NRST pin.

Symbol Parameter

Table 60. NRST pin characteristics

Conditions Min Typ Max

F(NRST)

(2)

NF(NRST)

Table 60 . Otherwise the reset is not taken into account by the device.

Weak pull-up equivalent resistor

(1)

NRST Input filtered pulse

NRST Input not filtered pulse

NRST_OUT

Generated reset pulse duration

= V

> 2.7 V

Internal Reset source

300

100

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order)

2. Guaranteed by design, not tested in production.

Unit k Ω ns ns

µs

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Electrical characteristics STM32F412xE/G

Figure 37. Recommended NRST pin protection

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1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

The parameters given in

Table 61 are guaranteed by design.

Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 61. TIMx characteristics

(1)(2)

Parameter Conditions

(3) Min Max Unit t res(TIM) f

EXT

Timer resolution time f

AHB/APBx prescaler=1 or 2 or 4, f

TIMxCLK

100 MHz

AHB/APBx prescaler>4,

TIMxCLK

= 100 MHz

Timer external clock frequency on CH1 to CH4 f

TIMxCLK

= 100 MHz

Timer resolution

11.9

0 f

TIMxCLK

/2 t t

TIMxCLK ns

MHz

Res

TIM

16/32 bit t

COUNTER

16-bit counter clock period when internal clock is selected f

TIMxCLK

= 100 MHz 0.0119

780 µs t

MAX_COUNT

Maximum possible count with 32-bit counter

TIMxCLK

= 100 MHz -

65536 ×

65536

51.1

TIMxCLK

1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers.

2. Guaranteed by design, not tested in production.

3. The maximum timer frequency on APB1 is 50 MHz and on APB2 is up to 100 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise

TIMxCLK >= 4x PCLKx.

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I

C interface characteristics

The I

C interface meets the requirements of the standard I

C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and V

DD disabled, but is still present.

The I

C characteristics are described in

Table 62

. Refer also to

Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA

and SCL).

The I 2 C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400 kHz). The I 2 C bus frequency can be increased up to 1 MHz. For more details about the complete solution, contact your local ST sales representative.

Symbol Parameter

Table 62. I 2 C characteristics

Standard mode

(1)(2)

Min Max

Fast mode I

(1)(2)

Unit

Min Max t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

4.7

4.0

250

3450

(3)

1000

300

1.3

0.6

100

900

(4)

300

µs ns t t t su(STA) su(STO) w(STO:STA) t

Start condition hold time

Repeated Start condition setup time

Stop condition setup time

Stop to Start condition time

(bus free)

Pulse width of the spikes that are suppressed by the analog filter for standard fast mode

4.0

4.7

4.0

4.7

0.6

0.6 -

0.6

1.3

120

(5)

µs

µs ns

C b

Capacitive load for each bus line

400 400 pF

1. Guaranteed by design, not tested in production.

2. f

PCLK1

must be at least 2 MHz to achieve standard mode I

2 achieve fast mode I clock.

C frequencies. It must be at least 4 MHz to

C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I C fast mode

3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.

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Electrical characteristics STM32F412xE/G

4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.

5. The minimum width of the spikes filtered by the analog filter is above t

(max)

Figure 38. I 2 C bus AC waveforms and measurement circuit

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1. R

= series protection resistor.

2. R

= external pull-up resistor.

3. V

DD_I2C

is the I2C bus power supply.

Table 63. SCL frequency (f

PCLK1

= 50 MHz, V

= V

DD_I2C

= 3.3 V)

(1)(2)

I2C_CCR value f

SCL

(kHz)

= 4.7 k Ω

400

300

200

100

0x8019

0x8021

0x8032

0x0096

50 0x012C

20 0x02EE

1. R

= External pull-up resistance, f

SCL

= I

C speed

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed is ±2%. These variations depend on the accuracy of the external components used to design the application.

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FMPI

C characteristics

The following table presents FMPI 2 C characteristics.

Refer also to

Section 6.3.16: I/O port characteristics

for more details on the input/output function characteristics (SDA and SCL).

Table 64. FMPI 2 C characteristics (1)

Standard mode Fast mode Fast+ mode

Parameter Unit

Min Max Min Max Min Max f

FMPI2CC

MPI2CCLK frequency 2 8 18 t w(SCLL) SCL clock low time t w(SCLH)

SCL clock high time t su(SDA) SDA setup time t

H(SDA)

SDA data hold time t v(SDA,ACK) Data, ACK valid time t r(SDA) t r(SCL)

SDA and SCL rise time

4.7

4.0

0.25

3.45

1.0

1.3

0.6

0.10

0.9

0.30

t f(SDA) t f(SCL)

SDA and SCL fall time t h(STA)

Start condition hold time t su(STA)

Repeated Start condition setup time t su(STO) Stop condition setup time

4.7

0.30

0.6

0.30

0.26

t w(STO:STA)

Stop to Start condition time

(bus free)

4.7

1.3

0.5

C b

Pulse width of the spikes that are suppressed by the analog filter for standard and fast mode

Capacitive load for each bus

Line

400

0.05

0.1

400

1. Based on characterization results, not tested in production.

2. Can be limited. Maximum supported value can be retrieved by referring to the following formulas: t

R p(min)

= 0.8473 x R

= (V

-V

OL(max) p

x C

) / I load

OL(max)

0.05

0.5

0.26

0.05

0.12

0.45

0.12

0.1

550

(2)

µs pF

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Electrical characteristics STM32F412xE/G

Figure 39. FMPI 2 C timing diagram and measurement circuit

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132/201

DocID028087 Rev 7

STM32F412xE/G Electrical characteristics t w(SCKH) t w(SCKL) t su(NSS) t h(NSS) t su(MI) t su(SI) t h(MI) t h(SI)

Symbol f

SCK

1/t c(SCK)

Duty(SCK)

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 65

for the SPI interface are derived from tests performed under the ambient temperature, f

PCLKx

frequency and V

supply voltage conditions summarized in Table 16 , with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5V

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI).

Parameter

Table 65. SPI dynamic characteristics

(1)

Conditions

Master full duplex/receiver mode,

2.7 V < V

< 3.6 V

SPI1/4/5

Master transmitter mode

1.7 V < V

< 3.6 V

SPI1/4/5

Master mode

1.7 V < V

< 3.6 V

SPI1/2/3/4/5

SPI clock frequency

Slave transmitter/full duplex mode

2.7 V < V

SPI1//4/5

< 3.6 V

Slave transmitter/full duplex mode

1.7 V < V

< 3.6 V

SPI1/4/5

Slave receiver mode,

1.7 V < V

< 3.6 V

SPI1/4/5

Slave mode,

1.7 V < V

< 3.6 V

SPI2/3

Duty cycle of SPI clock frequency

Slave mode

Min

Typ

Max

(2)

Unit

MHz

SCK high and low time Master mode, SPI presc = 2

NSS setup time

NSS hold time

Data input setup time

Data input hold time

Slave mode, SPI presc = 2

Master mode

Slave mode

Master mode

Slave mode

PCLK

− 1.5

PCLK

4.5

1.5

0.5

PCLK

+1.5

ns ns ns ns ns ns ns

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Electrical characteristics STM32F412xE/G

Symbol

Table 65. SPI dynamic characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit t a(SO

) t dis(SO)

Data output access time Slave mode

Data output disable time Slave mode

12 ns ns t t v(SO) h(SO)

Data output valid time

Slave mode (after enable edge),

2.7 V < V

< 3.6 V

Slave mode (after enable edge),

1.7 V < V

< 3.6 V

Data output hold time

Slave mode (after enable edge),

1.7 V < V

< 3.6 V

Data output valid time Master mode (after enable edge)

5.5

7.5

t t v(MO) h(MO)

Data output hold time Master mode (after enable edge)

1. Guaranteed by characterization, not tested in production.

2. Maximum frequency in Slave transmitter mode is determined by the sum of t communicates with a master having t su(MI)

= 0 while Duty(SCK) = 50% v(SO)

and t su(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI ns ns ns ns ns

Figure 40. SPI timing diagram - slave mode and CPHA = 0

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DocID028087 Rev 7

STM32F412xE/G Electrical characteristics

Figure 41. SPI timing diagram - slave mode and CPHA = 1 (1)

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Figure 42. SPI timing diagram - master mode (1)

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166

Electrical characteristics STM32F412xE/G

I

S interface characteristics

Unless otherwise specified, the parameters given in Table 66

for the I 2 S interface are derived from tests performed under the ambient temperature, f

PCLKx frequency and V

supply voltage conditions summarized in Table 16 , with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5V

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (CK, SD, WS).

Symbol Parameter

Table 66. I

S dynamic characteristics

(1)

Conditions f

MCK f

CK t v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t v(SD_MT) t h(SD_ST) t h(SD_MT)

I2S Main clock output

I2S clock frequency

Master data: 32 bits

Slave data: 32 bits

I2S clock frequency duty cycle Slave receiver

WS valid time Master mode

WS hold time

WS setup time

WS hold time

Master mode

Slave mode

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

1. Guaranteed by characterization, not tested in production.

2. The maximum value of 256xFs is 50 MHz (APB1 maximum frequency).

2.5

0.5

Min Max

256x8K 256xFs (2)

64xFs

2.5

0 -

Unit

MHz

% ns

Note: Refer to the I2S section of RM0383 reference manual for more details on the sampling frequency (F

). f

MCK

, f

, and D

values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. D

depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of

(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F

S maximum value is supported for each mode/condition.

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STM32F412xE/G

CPOL = 0

Electrical characteristics

Figure 43. I 2 S slave timing diagram (Philips protocol) (1) tc(CK)

CPOL = 1 tw(CKH) tw(CKL) th(WS)

WS input

SDtransmit tsu(WS)

LSB transmit

(2) tsu(SD_SR)

LSB receive

(2)

MSB transmit

MSB receive tv(SD_ST)

Bitn transmit th(SD_SR)

Bitn receive th(SD_ST)

LSB transmit

LSB receive SDreceive ai14881b

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 44. I 2 S master timing diagram (Philips protocol) (1) tf(CK) tr(CK) tc(CK)

CPOL = 0 tw(CKH)

CPOL = 1 tv(WS) tw(CKL) th(WS)

WS output

SDtransmit LSB transmit (2) tsu(SD_MR)

LSB receive (2)

MSB transmit

MSB receive tv(SD_MT)

Bitn transmit th(SD_MR)

Bitn receive th(SD_MT)

LSB transmit

LSB receive SDreceive ai14884b

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

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Electrical characteristics STM32F412xE/G

QSPI interface characteristics

Unless otherwise specified, the parameters given in the following tables for QSPI are derived from tests performed under the ambient temperature, f

AHB

frequency and V

supply voltage conditions summarized in Table 16 , with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C=20pF

• Measurement points are done at CMOS levels: 0.5VDD

Refer to Section 6.3.16: I/O port characteristics

for more details on the input/output alternate function characteristics.

Symbol

Table 67. QSPI dynamic characteristics in SDR mode

(1)

Parameter Conditions Min Typ f

SCK

1/t c(SCK)

QSPI clock frequency

Write mode

1.71 V ≤ V

≤ 3.6 V

C load

= 15 pF

Read mode

2.7 V<V

C load

<3.6 V

= 15 pF

1.71 V ≤ V

≤ 3.6 V

- t w(CKH) t w(CKL)

QSPI clock high and low

(CK)

/ 2)-1

(CK)

/ 2) t t s(IN) h(IN)

Data input setup time

Data input hold time

0.5

3.5

t t v(OUT) h(OUT)

Data output valid time

Data output hold time

0.5

1. Guaranteed by characterization results, not tested in production.

Max

100

(CK)

/ 2

(CK)

/ 2)+1

1.5

Unit

MHz ns

Symbol

Table 68. QSPI dynamic characteristics in DDR mode

(1)

Parameter Conditions Min Typ Max f

SCK

1/t c(SCK)

QSPI clock frequency

Write mode

1.71 V ≤ V

≤ 3.6 V

C load

= 15 pF

Read mode

2.7 V<V

C load

<3.6 V

= 15 pF

1.71 V ≤ V

≤ 3.6 V -

- -

Unit

MHz

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STM32F412xE/G Electrical characteristics

Symbol

Table 68. QSPI dynamic characteristics in DDR mode (1) (continued)

Parameter Conditions Min Typ Max t w(CKH) t w(CKL)

QSPI clock high and low

(CK)

/ 2)-1

(CK)

/ 2) t t s(IN) h(IN)

Data input setup time

Data input hold time

4 t v(OUT)

Data output valid time

2.7 V<V

<3.6 V

1.71 V<V

<3.6 V

t h(OUT)

Data output hold time

7.5

1. Guaranteed by characterization results, not tested in production.

(CK)

/ 2

(CK)

/ 2)+1

10.5

Unit ns

USB OTG full speed (FS) characteristics

This interface is present in USB OTG FS controller.

Symbol

Table 69. USB OTG FS startup time

Parameter t

STARTUP

(1) USB OTG FS transceiver startup time

1. Guaranteed by design, not tested in production.

Max

Unit

µs

Symbol

Table 70. USB OTG FS DC electrical characteristics

Parameter Conditions

Input levels

Output levels

(3)

USB OTG FS operating voltage

Differential input sensitivity

(3)

Differential common mode range

(3)

Single ended receiver threshold

Static output level low

Static output level high

PA11, PA12

(USB_FS_DM/DP)

PA9 (OTG_FS_VBUS)

I(USB_FS_DP/DM)

Includes V

DI range

of 1.5

k Ω to 3.6 V

(4)

of 15 k Ω to V

= V

PA11, PA12

(USB_FS_DM/DP)

= V

PA9 (OTG_FS_VBUS) V

= V

1. All the voltages are measured from the local ground potential.

(4)

Min.

(1)

3.0

(2)

0.2

0.8

1.3

2.8

0.65

1.1

1.5

Typ. Max.

(1)

1.8

3.6

2.5

2.0

0.3

3.6

2.0

2.1

0.25

0.37

0.55

Unit

V k Ω

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Electrical characteristics

Note:

STM32F412xE/G

2. The USB OTG FS functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V V

voltage range.

3. Guaranteed by design, not tested in production.

4. R

is the load connected on the USB OTG FS drivers.

When VBUS sensing feature is enabled, PA9 should be left at their default state (floating input), not as alternate function. A typical 200 µA current consumption of the embedded sensing block (current to voltage conversion to determine the different sessions) can be observed on PA9 when the feature is enabled.

Figure 45. USB OTG FS timings: definition of data signal rise and fall time

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Table 71. USB OTG FS electrical characteristics

(1)

Driver characteristics

Symbol Parameter Conditions Min Max Unit t r t f t rfm

CRS

Rise time

Fall time

(2)

Rise/ fall time matching

Output signal crossover voltage

= 50 pF

= 50 pF t r

/t f

1.3

110

2.0

ns ns

1. Guaranteed by design, not tested in production.

2. Measured from 10% to 90% of the data signal. For more detailed informations, refer to USB Specification -

Chapter 7 (version 2.0).

CAN (controller area network) interface

Refer to Section 6.3.16: I/O port characteristics

for more details on the input/output alternate function characteristics (CANx_TX and CANx_RX).

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STM32F412xE/G Electrical characteristics

Unless otherwise specified, the parameters given in Table 72

are derived from tests performed under the ambient temperature, f

conditions summarized in Table 16

PCLK2 frequency and V

DDA

supply voltage

Symbol Parameter

Table 72. ADC characteristics

Conditions Min Typ Max f

V f

DDA

REF+

ADC

TRIG

(2)

Power supply

Positive reference voltage

ADC clock frequency

External trigger frequency

DDA

− V

REF+

< 1.2 V

DDA

= 1.7

(1) to 2.4 V

DDA

= 2.4 to 3.6 V f

ADC

= 30 MHz,

12-bit resolution

1.7

(1)

1.7

(1)

0.6

3.6

DDA

1764

AIN

Conversion voltage range

(3)

0 (V

SSA or V

REFtied to ground)

REF+

AIN

External input impedance

ADC

(2)(4)

Sampling switch resistance

ADC

Internal sample and hold capacitor t t t t t lat

latr

STAB

CONV

See Equation 1 for details

Injection trigger conversion latency

Regular trigger conversion latency

Sampling time

Power-up time f

ADC

= 30 MHz

ADC

= 30 MHz

ADC

= 30 MHz

ADC

= 30 MHz

12-bit resolution

0.100

0.50

16.40

Total conversion time (including sampling time) f

ADC

= 30 MHz

10-bit resolution f

ADC

= 30 MHz

8-bit resolution f

ADC

= 30 MHz

6-bit resolution

0.43

0.37

0.30

16.34

16.27

16.20

9 to 492 (t

for sampling +n-bit resolution for successive approximation)

0.100

(5)

0.067

(5)

480

µs

1/f

ADC k Ω k Ω pF

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

Unit

MHz

MHz kHz

1/f

ADC

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Electrical characteristics STM32F412xE/G

Symbol Parameter

Table 72. ADC characteristics (continued)

Conditions Min Typ Max Unit f

must be added to the latency specified in Table 72 .

Sampling rate

ADC

= 30 MHz, and t

= 3 ADC cycles)

12-bit resolution

Single ADC

12-bit resolution

Interleave Dual ADC mode

12-bit resolution

Interleave Triple ADC mode

3.75

ADC V

REF

DC current consumption in conversion mode

ADC V

DDA

DC current consumption in conversion mode

300

1.6

500

1.8

1. V

DDA

minimum value of 1.7 V is possible with the use of an external power supply supervisor (refer to

Section 3.18.2:

Internal reset OFF ).

2. Guaranteed by characterization, not tested in production.

3. V

REF+

is internally connected to V

DDA

and V

REF-

is internally connected to V

SSA

4. R

ADC

maximum value is given for V

=1.7 V, and minimum value for V

=3.3 V.

5. For external triggers, a delay of 1/f

PCLK2

Msps

µA mA

Equation 1: R

AIN

max formula

AIN

=

ADC

(

C k 0.5

ADC

× ln

)

( 2

N +

)

– R

ADC

The formula above ( Equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register.

Symbol

Table 73. ADC accuracy at f

ADC

= 18 MHz (1)

Parameter Test conditions Typ Max

(2)

Unit

ET Total unadjusted error ±3 ±4

EO Offset error

EG Gain error

ED Differential linearity error

EL Integral linearity error

V f

ADC

DDA

REF

DDA

− V

=18 MHz

= 1.7 to 3.6 V

REF

< 1.2 V

±2

±1

±2

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Guaranteed by characterization, not tested in production.

±3

±2

±3

LSB

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STM32F412xE/G Electrical characteristics

Symbol

Table 74. ADC accuracy at f

ADC

= 30 MHz (1)

Parameter Test conditions Typ Max

(2)

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

ADC

AIN

REF

= 30 MHz,

< 10 k Ω ,

DDA

= 2.4 to 3.6 V,

= 1.7 to 3.6 V,

DDA

− V

REF

< 1.2 V

±2

±1.5

±1

±1.5

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Guaranteed by characterization, not tested in production.

±5

±2.5

±4

±2

±3

Symbol

Table 75. ADC accuracy at f

ADC

= 36 MHz

(1)

Parameter Test conditions Typ Max

(2)

ET Total unadjusted error ±4 ±7

Offset error

Gain error

ED Differential linearity error

EL Integral linearity error f

ADC

DDA

=36 MHz,

DDA

= 2.4 to 3.6 V,

REF

= 1.7 to 3.6 V

− V

REF

< 1.2 V

±2

±3

±2

±3

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Guaranteed by characterization, not tested in production.

±3

±6

±3

±6

Unit

LSB

Unit

LSB

Symbol

Table 76. ADC dynamic accuracy at f

ADC

= 18 MHz - limited test conditions (1)

Parameter Test conditions Min Typ Max Unit bits ENOB

SINAD

SNR

THD

Effective number of bits

Signal-to-noise and distortion ratio

Signal-to-noise ratio

Total harmonic distortion

1. Guaranteed by characterization, not tested in production.

ADC

=18 MHz

DDA

= V

REF+

= 1.7 V

Input Frequency = 20 kHz

Temperature = 25 °C

10.3

10.4

64 64.2

-72

-67

Symbol

Table 77. ADC dynamic accuracy at f

ADC

= 36 MHz - limited test conditions

(1)

Parameter Test conditions Min Typ Max Unit bits ENOB

SINAD

SNR

THD

Effective number of bits

Signal-to noise and distortion ratio

Signal-to noise ratio

Total harmonic distortion

1. Guaranteed by characterization, not tested in production.

ADC

= 36 MHz

DDA

= V

REF+

= 3.3 V

Input Frequency = 20 kHz

Temperature = 25 °C

10.6

10.8

-72

-70 dB

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166

Electrical characteristics

Note:

STM32F412xE/G

ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I

INJ(PIN)

Section 6.3.16

does not affect the ADC accuracy.

and Σ I

INJ(PIN)

Figure 46. ADC accuracy characteristics

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6$$!

1. See also Table 74 .

2. Example of an actual transfer curve.

3. Ideal transfer curve.

4. End point correlation line.

5. E

= Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

EO = Offset Error: deviation between the first actual transition and the first ideal one.

EG = Gain Error: deviation between the last ideal transition and the last actual one.

ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.

EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

AIC

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STM32F412xE/G Electrical characteristics

Figure 47. Typical connection diagram using the ADC

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1. Refer to Table 72 for the values of R

AIN

, R

ADC

and C

ADC

2. C f parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5

ADC

should be reduced.

pF). A high C parasitic

value downgrades conversion accuracy. To remedy this,

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166

Electrical characteristics STM32F412xE/G

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 48

Figure 49

, depending on whether V

REF+

is connected to V

DDA

or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 48. Power supply and reference decoupling (V

REF+ not connected to V

DDA

)

670)

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1. V

REF+

and V

REF-

REF- inputs are both available on UFBGA100. V

REF+ is also available on LQFP100. When are not available, they are internally connected to V

DDA and V

SSA

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STM32F412xE/G Electrical characteristics

Figure 49. Power supply and reference decoupling (V

REF+ connected to V

DDA

)

670)

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9 5() 9 66$

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1. V

REF+

and V

REF-

REF- inputs are both available on UFBGA100. V

REF+ is also available on LQFP100. When are not available, they are internally connected to V

DDA and V

SSA

6.3.21 Temperature sensor characteristics

Symbol

Table 78. Temperature sensor characteristics

Parameter Min Typ Max

(1)

Avg_Slope

Table 81 are derived from tests performed under ambient

START

(2)

S_temp

(2)

SENSE

linearity with temperature

Average slope

Voltage at 25 °C

Startup time

ADC sampling time when reading the temperature (1 °C accuracy)

1. Guaranteed by characterization, not tested in production.

2. Guaranteed by design, not tested in production.

± 1

2.5

0.76

± 2

Unit

°C mV/°C

µs

Symbol

Table 79. Temperature sensor calibration values

Parameter Memory address

TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, V

DDA

= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D

TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, V

DDA

= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F

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Electrical characteristics

6.3.22 V

BAT

monitoring characteristics

Symbol

Table 80. V

BAT

monitoring characteristics

Parameter Min

(1)

S_vbat

(2)(2)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q

ADC sampling time when reading the V

BAT

1 mV accuracy

1. Guaranteed by design, not tested in production.

2. Shortest sampling time can be determined in the application by multiple iterations.

–1

Typ

STM32F412xE/G

Max

Unit

K Ω

µs

The parameters given in

temperature and V

supply voltage conditions summarized in

Unless otherwise specified, the parameters given in Table 83

Symbol

Table 81. Embedded internal reference voltage

Parameter Conditions Min Typ Max Unit

REFINT

S_vrefint

(1)

Internal reference voltage

ADC sampling time when reading the internal reference voltage

- 40 °C < T

< +125 °C

RERINT_s

(2)

Internal reference voltage spread over the temperature range

= 3V ± 10mV

Coeff

(2) t

START

(2)

Temperature coefficient

Startup time -

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design, not tested in production

1.18

1.21

1.24

µs mV ppm/°C

µs

Symbol

REFIN_CAL

Table 82. Internal reference voltage calibration values

Parameter Memory address

Raw data acquired at temperature of

30 °C V

DDA

= 3.3 V

0x1FFF 7A2A - 0x1FFF 7A2B

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STM32F412xE/G Electrical characteristics

for DFSDM are derived from tests performed under the ambient temperature, f

APB2

frequency and V

conditions summarized in Table 16: General operating conditions

supply voltage

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 ₓ VDD

Refer to Section 6.3.16: I/O port characteristics

for more details on the input/output alternate function characteristics (DFSDM_CKINy, DFSDM_DATINy, DFSDM_CKOUT for DFSDM).

Symbol Parameter

Table 83. DFSDM characteristics (1)

Conditions Min Typ f

DFSDMCLK f

CKIN

(1/T

CKIN

)

DFSDM clock

Input clock frequency

SPI mode (SITP[1:0] = 01) f

CKOUT

DuCy

CKOUT

Output clock frequency

Output clock frequency duty cycle

t t wh(CKIN) wl(CKIN) t su

Input clock high and low time

Data input setup time

SPI mode (SITP[1:0] = 01),

External clock mode

(SPICKSEL[1:0] = 0)

SPI mode (SITP[1:0]=01),

External clock mode

(SPICKSEL[1:0] = 0)

T t h

Manchester

Data input hold time

Manchester data period

(recovered clock period)

SPI mode (SITP[1:0]=01),

External clock mode

(SPICKSEL[1:0] = 0)

Manchester mode (SITP[1:0]

= 10 or 11),

Internal clock mode

(SPICKSEL[1:0] ≠ 0)

1. Data based on characterization results, not tested in production.

(CKOUT

DIV+1) ₓ

DFSDMCLK

CKIN

/2-0.5

CKIN

Max f

SYSCLK

DFSDMCLK

/4)

(2 ₓ CKOUTDIV) ₓ T

DFSDMCLK

Unit

MHz

% ns

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166

Electrical characteristics STM32F412xE/G

Figure 16: DFSDM timing diagram

63,&.6(/

6,73

63,&.6(/

6,73

5HFRYHUHGFORFN

5HFRYHUHGGDWD

06Y9

150/201

Unless otherwise specified, the parameters given in Table 84

to Table 91

for the FSMC interface are derived from tests performed under the ambient temperature, f

HCLK and V

DD frequency

supply voltage conditions summarized in Table 15

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitance load C = 30 pF

• Measurement points are done at CMOS levels: 0.5.V

DocID028087 Rev 7

STM32F412xE/G Electrical characteristics

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output

characteristics.

Asynchronous waveforms and timings

Figure 50

through Figure 53 represent asynchronous waveforms and

Table 84 through

Table 91 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

• AddressSetupTime = 0x1

• AddressHoldTime = 0x1

• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)

• BusTurnAroundDuration = 0x0

In all timing tables, the T

HCLK

is the HCLK clock period.

Figure 50. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

Z1(

)60&B1(

Y12(B1( W

Z12(

K1(B12(

)60&B12(

)60&B1:(

)60&B$>@

V!?.%

V",?.%

$GGUHVV

K$B12(

K%/B12(

)60&B1%/>@

K'DWDB1(

K'DWDB12(

)60&B'>@

VX'DWDB12(

VX'DWDB1(

'DWD

Y1$'9B1(

Z1$'9

)60&B1$'9

)60&B1:$,7

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

K1(B1:$,7

VX1:$,7B1(

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166

Electrical characteristics STM32F412xE/G

Symbol

Table 84. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)(2)

Parameter Min Max t w(NE) t v(NOE_NE) t w(NOE)

FSMC_NE low time

FSMC_NEx low to FSMC_NOE low t h(NE_NOE)

FSMC_NOE low time

FSMC_NOE high to FSMC_NE high hold time t v(A_NE) t h(A_NOE) t v(BL_NE) t h(BL_NOE) t su(Data_NE) t su(Data_NOE) t h(Data_NOE) t h(Data_NE) t v(NADV_NE) t w(NADV)

FSMC_NEx low to FSMC_A valid

Address hold time after FSMC_NOE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NOE high

Data to FSMC_NEx high setup time

Data to FSMC_NOEx high setup time

Data hold time after FSMC_NOE high

Data hold time after FSMC_NEx high

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

1. C

= 30 pF.

2. Based on characterization, not tested in production.

HCLK

– 1 2 T

HCLK

+ 0.5

0 1

HCLK

- 1.5

HCLK

- 1

HCLK

- 1

1.5

0.5

HCLK

+ 0.5

Unit ns

Table 85. Asynchronous non-multiplexed SRAM/PSRAM/NOR read -

NWAIT timings

(1)(2)

Symbol Parameter Min Max Unit t w(NE)

FSMC_NE low time 7T

HCLK

- 1 7T

HCLK

+ 0.5

t t t t w(NOE) w(NWAIT) su(NWAIT_NE) h(NE_NWAIT)

FSMC_NWE low time

FSMC_NWAIT low time

FSMC_NWAIT valid before FSMC_NEx high

FSMC_NEx hold time after FSMC_NWAIT invalid

HCLK

– 1.5

HCLK

– 0.5

HCLK

-1

+ 1

1. C

= 30 pF.

2. Based on characterization, not tested in production.

HCLK

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STM32F412xE/G Electrical characteristics

Figure 51. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

Z1(

)60&B1([

)60&B12(

)60&B1:(

Y1:(B1(

Z1:(

K1(B1:(

)60&B$>@

)60&B1%/>@

)60&B'>@

)60&B1$'9

V!?.%

V",?.%

Y'DWDB1(

Y1$'9B1(

Z1$'9

K$B1:(

$GGUHVV

K%/B1:(

1%/

K'DWDB1:(

'DWD

)60&B1:$,7

K1(B1:$,7

VX1:$,7B1(

06Y9

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

(1)(2)

Symbol

t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NE) t h(Data_NWE) t v(NADV_NE) t w(NADV)

Parameter Min Max

FSMC_NE low time

FSMC_NEx low to FSMC_NWE low

3 T

HCLK

- 1 3 T

HCLK

+0.5

HCLK

+ 0.5

HCLK

+ 0.5

FSMC_NWE low time

FSMC_NWE high to FSMC_NE high hold time

HCLK

– 1.5

HCLK

+ 1

HCLK

- 1 -

FSMC_NEx low to FSMC_A valid 0.5

Address hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NWE high

Data to FSMC_NEx low to Data valid

Data hold time after FSMC_NWE high

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

HCLK

- 0.5

HCLK

- 1

HCLK

+ 0.5

HCLK

+ 2

HCLK

+ 0.5

Unit

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Electrical characteristics STM32F412xE/G

1. C

= 30 pF.

2. Based on characterization, not tested in production.

Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR write -

NWAIT timings (1)(2)

Symbol Parameter Min Max Unit t w(NE)

FSMC_NE low time 8T

HCLK

- 1 8T

HCLK

+ 0.5

t t t w(NWE) su(NWAIT_NE) h(NE_NWAIT)

FSMC_NWE low time 6T

HCLK

+ 0.5

HCLK

+ 1

FSMC_NWAIT valid before FSMC_NEx high 6T

HCLK

+ 0.5

FSMC_NEx hold time after FSMC_NWAIT invalid

HCLK

+ 1 -

1. C

= 30 pF.

2. Based on characterization, not tested in production.

Figure 52. Asynchronous multiplexed PSRAM/NOR read waveforms

Z1(

)60&B1(

Y12(B1(

K1(B12(

)60&B12(

Z12(

)60&B1:(

V!?.%

K$B12(

)60&B$>@

$GGUHVV

V",?.%

K%/B12(

)60&B1%/>@ 1%/

K'DWDB1(

Y$B1(

$GGUHVV

VX'DWDB1(

VX'DWDB12(

'DWD

K'DWDB12(

)60&B$'>@

Y1$'9B1( T

H!$?.!$6

Z1$'9

)60&B1$'9

)60&B1:$,7

K1(B1:$,7

VX1:$,7B1(

06Y9

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STM32F412xE/G Electrical characteristics

Table 88. Asynchronous multiplexed PSRAM/NOR read timings (1)(2)

Symbol Parameter Min Max t w(NE) t v(NOE_NE) t tw(NOE)

FSMC_NE low time

FSMC_NEx low to FSMC_NOE low t h(NE_NOE)

FSMC_NOE low time

FSMC_NOE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid t v(A_NE) t v(NADV_NE) t w(NADV)

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time t h(AD_NADV)

FSMC_AD(address) valid hold time after

FSMC_NADV high) t h(A_NOE) t h(BL_NOE) t v(BL_NE) t su(Data_NE) t su(Data_NOE) t h(Data_NE) t h(Data_NOE)

Address hold time after FSMC_NOE high

FSMC_BL time after FSMC_NOE high

FSMC_NEx low to FSMC_BL valid

Data to FSMC_NEx high setup time

Data to FSMC_NOE high setup time

Data hold time after FSMC_NEx high

Data hold time after FSMC_NOE high

1. C

= 30 pF.

2. Based on characterization, not tested in production.

HCLK

– 1 3T

HCLK

+ 0.5

HCLK

+ 1

HCLK

– 1.5

HCLK

0.5

0 1

HCLK

– 0.5

HCLK

+ 0.5

HCLK

– 0.5

HCLK

- 2

HCLK

- 2

0.5

Unit ns

Table 89. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings

(1)(2)

Symbol Parameter Min Max Unit t w(NE)

FSMC_NE low time t t t w(NOE) su(NWAIT_NE) h(NE_NWAIT)

FSMC_NWE low time

FSMC_NWAIT valid before FSMC_NEx high

FSMC_NEx hold time after

FSMC_NWAIT invalid

1. C

= 30 pF.

2. Based on characterization, not tested in production.

HCLK

- 1 8T

HCLK

+ 0.5

HCLK

- 1

HCLK

+ 0.5

HCLK

+ 1 ns

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Electrical characteristics STM32F412xE/G

Figure 53. Asynchronous multiplexed PSRAM/NOR write waveforms

Z1(

)60&B1([

)60&B12(

)60&B1:(

)60&B$>@

)60&B1%/>@

)60&B$'>@

W Y1$'9B1(

Y1:(B1(

V!?.%

V",?.%

Y$B1(

$GGUHVV

Z1$'9

Z1:(

K$B1:(

$GGUHVV

1%/

Y'DWDB1$'9

K%/B1:(

'DWD

H!$?.!$6

K1(B1:(

K'DWDB1:(

)60&B1$'9

)60&B1:$,7

K1(B1:$,7

VX1:$,7B1(

06Y9

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STM32F412xE/G Electrical characteristics

Table 90. Asynchronous multiplexed PSRAM/NOR write timings (1)(2)

Symbol Parameter Min Max t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t v(NADV_NE) t w(NADV)

FSMC_NE low time

FSMC_NEx low to FSMC_NWE low

FSMC_NWE low time 2T

HCLK

- 1 2T

HCLK

+ 0.5

FSMC_NWE high to FSMC_NE high hold time T

HCLK

FSMC_NEx low to FSMC_A valid -

- 1.5

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time t h(AD_NADV)

FSMC_AD(adress) valid hold time after

FSMC_NADV high) t h(A_NWE) t h(BL_NWE) t v(BL_NE) t v(Data_NADV) t h(Data_NWE)

Address hold time after FSMC_NWE high

FSMC_BL hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

FSMC_NADV high to Data valid

Data hold time after FSMC_NWE high

1. C

= 30 pF.

2. Based on characterization, not tested in production.

HCLK

- 1 4T

HCLK

+0.5

HCLK

+ 1

HCLK

- 1.5

HCLK

– 0.5

HCLK

+ 0.5

1.5

HCLK

+ 2

+ 0.5

Unit ns

Table 91. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings (1)(2)

Symbol Parameter Min Max Unit t w(NE)

FSMC_NE low time 9T

HCLK

- 1 9T

HCLK

+ 0.5

t t t w(NWE) su(NWAIT_NE) h(NE_NWAIT)

FSMC_NWE low time

FSMC_NWAIT valid before FSMC_NEx high

HCLK

- 1 7T

HCLK

+ 0.5

HCLK

-1 -

FSMC_NEx hold time after FSMC_NWAIT invalid

HCLK

+ 1 -

1. C

= 30 pF.

2. Based on characterization, not tested in production.

Synchronous waveforms and timings

Figure 54

through Figure 57

represent synchronous waveforms and Table 92

through

Table 95 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

• BurstAccessMode = FSMC_BurstAccessMode_Enable;

• MemoryType = FSMC_MemoryType_CRAM;

• WriteBurst = FSMC_WriteBurst_Enable;

• CLKDivision = 1; (0 is not supported, see the STM32F446 reference manual: RM0390)

• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

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Electrical characteristics STM32F412xE/G

In all timing tables, the T

HCLK

FSMC_CLK = 90 MHz).

is the HCLK clock period (with maximum

Figure 54. Synchronous multiplexed NOR/PSRAM read timings

Z&/.

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)60&B&/.

G&/./1([/

'DWDODWHQF\

G&/.+1([+

)60&B1([

G&/./1$'9/

G&/./1$'9+

)60&B1$'9

G&/./$9

G&/.+$,9

)60&B$>@

G&/./12(/

G&/.+12(+

)60&B12(

G&/./$',9

G&/./$'9

)60&B$'>@

VX$'9&/.+

)60&B1:$,7

:$,7&)* E:$,732/E

$'>@

VX1:$,79&/.+

K&/.+$'9

VX$'9&/.+

K&/.+1:$,79

K&/.+$'9

K&/.+1:$,79

)60&B1:$,7

:$,7&)* E:$,732/E

VX1:$,79&/.+

K&/.+1:$,79

06Y9

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STM32F412xE/G Electrical characteristics

Table 92. Synchronous multiplexed NOR/PSRAM read timings (1)(2)

Symbol Parameter Min Max t t t t t w(CLK) d(CLKH_NExH) d(CLKL-NADVL) d(CLKL-NADVH) t d(CLKL-NExL) t d(CLKL-AV) d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t d(CLKL-ADV) t d(CLKL-ADIV)

FSMC_CLK period

FSMC_CLK low to FSMC_NEx low (x=0..2)

HCLK

- 0.5

FSMC_CLK high to FSMC_NEx high (x= 0…2) T

HCLK

+ 0.5

FSMC_CLK low to FSMC_NADV low -

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x=16…25)

FSMC_CLK high to FSMC_Ax invalid

(x=16…25)

HCLK

FSMC_CLK low to FSMC_NOE low

FSMC_CLK high to FSMC_NOE high

FSMC_CLK low to FSMC_AD[15:0] valid t su(ADV-CLKH)

FSMC_CLK low to FSMC_AD[15:0] invalid

FSMC_A/D[15:0] valid data before FSMC_CLK high t h(CLKH-ADV)

FSMC_A/D[15:0] valid data after FSMC_CLK high t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

1. C

= 30 pF.

2. Based on characterization, not tested in production.

HCLK

2 -

1.5

2.5

Unit ns

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Electrical characteristics STM32F412xE/G

Figure 55. Synchronous multiplexed PSRAM write timings

Z&/.

%867851

)60&B&/.

G&/./1([/

'DWDODWHQF\

)60&B1([

G&/./1$'9/

)60&B1$'9

G&/./1$'9+

G&/./$9

)60&B$>@

G&/./1:(/

)60&B1:(

G&/./$'9

)60&B$'>@

)60&B1:$,7

:$,7&)* E:$,732/E

G&/./$',9

G&/./'DWD

$'>@

VX1:$,79&/.+

G&/./'DWD

G&/.+1([+

G&/.+$,9

G&/.+1:(+

K&/.+1:$,79

G&/.+1%/+

)60&B1%/

06Y9

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STM32F412xE/G Electrical characteristics

Symbol

Table 93. Synchronous multiplexed PSRAM write timings (1)(2)

Parameter Min Max t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t

(CLKH-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-DATA) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FSMC_CLK period, V

range= 2.7 to 3.6 V

FSMC_CLK low to FSMC_NEx low (x= 0...2)

FSMC_CLK high to FSMC_NEx high (x= 0…2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x=16…25)

FSMC_CLK high to FSMC_Ax invalid (x=16…25)

FSMC_CLK low to FSMC_NWE low

FSMC_CLK high to FSMC_NWE high

FSMC_CLK low to FSMC_AD[15:0] valid

FSMC_CLK low to FSMC_AD[15:0] invalid

FSMC_A/D[15:0] valid data after FSMC_CLK low

FSMC_CLK low to FSMC_NBL low

FSMC_CLK high to FSMC_NBL high

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

1. C

= 30 pF.

2. Based on characterization, not tested in production.

HCLK

- 0.5

HCLK

+ 0.5

HCLK

+ 0.5

HCLK

2.5

1.5

Unit ns

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Electrical characteristics STM32F412xE/G

Figure 56. Synchronous non-multiplexed NOR/PSRAM read timings

WZ&/.

)60&B&/.

G&/./1([/

'DWDODWHQF\

G&/.+1([+

)60&B1([

G&/./1$'9/

G&/./1$'9+

)60&B1$'9

G&/./$9

G&/.+$,9

)60&B$>@

G&/./12(/

G&/.+12(+

)60&B12(

)60&B'>@

VX'9&/.+

VX1:$,79&/.+

K&/.+'9

VX'9&/.+

K&/.+1:$,79

K&/.+'9

)60&B1:$,7

:$,7&)* E

:$,732/E

)60&B1:$,7

:$,7&)* E

:$,732/E

VX1:$,79&/.+

K&/.+1:$,79

VX1:$,79&/.+

K&/.+1:$,79

06Y9

Table 94. Synchronous non-multiplexed NOR/PSRAM read timings (1)(2)

Symbol Parameter Min Max t w(CLK) t

(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH)

FSMC_CLK period

FSMC_CLK low to FSMC_NEx low (x=0..2)

FSMC_CLK high to FSMC_NEx high (x= 0…2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x=16…25)

FSMC_CLK high to FSMC_Ax invalid (x=16…25)

FSMC_CLK low to FSMC_NOE low t su(DV-CLKH)

FSMC_CLK high to FSMC_NOE high

FSMC_D[15:0] valid data before FSMC_CLK high

FSMC_D[15:0] valid data after FSMC_CLK high t h(CLKH-DV) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

HCLK

– 0.5

HCLK

+0.5

HCLK

2 -

1.5

Unit ns

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1. C

= 30 pF.

2. Based on characterization, not tested in production.

Figure 57. Synchronous non-multiplexed PSRAM write timings

Z&/.

)60&B&/.

G&/./1([/

)60&B1([

G&/./1$'9/

)60&B1$'9

'DWDODWHQF\

G&/./1$'9+

G&/.+1([+

G&/./$9

G&/.+$,9

)60&B$>@

G&/./1:(/

G&/.+1:(+

)60&B1:(

)60&B'>@

G&/./'DWD

)60&B1:$,7

:$,7&)* E

:$,732/E

)60&B1%/

VX1:$,79&/.+

G&/.+1%/+

K&/.+1:$,79

06Y9

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Electrical characteristics STM32F412xE/G

Table 95. Synchronous non-multiplexed PSRAM write timings (1)(2)

Symbol Parameter Min Max t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t d(CLKH-NWEH) t d(CLKL-Data) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-

CLKH) t h(CLKH-NWAIT)

FSMC_CLK period

FSMC_CLK low to FSMC_NEx low (x=0..2)

FSMC_CLK high to FSMC_NEx high (x= 0…2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x=16…25)

FSMC_CLK high to FSMC_Ax invalid (x=16…25)

FSMC_CLK low to FSMC_NWE low

FSMC_CLK high to FSMC_NWE high

FSMC_D[15:0] valid data after FSMC_CLK low

FSMC_CLK low to FSMC_NBL low

FSMC_CLK high to FSMC_NBL high

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

1. C

= 30 pF.

2. Based on characterization, not tested in production.

HCLK

– 0.5

HCLK

+ 0.5

HCLK

+ 0.5

HCLK

1.5

Unit ns

6.3.26 SD/SDIO MMC/eMMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 96

for the SDIO are derived from tests performed under the ambient temperature, f

PCLK2 frequency and V

supply voltage

conditions summarized in Table 16

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5V

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output

characteristics.

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Figure 58. SDIO high-speed mode

Electrical characteristics

Figure 59. SD default mode

Symbol

Table 96. Dynamic characteristics: SD / MMC characteristics (1)(2)

Parameter Conditions f

W(CKL) t

W(CKH)

Clock frequency in data transfer mode

SDIO_CK/fPCLK2 frequency ratio

Clock low time

Clock high time

fpp =50MHz fpp =50MHz

CMD, D inputs (referenced to CK) in MMC and SD HS mode

Min

9.5

8.5

Typ

10.5

9.5

ISU t

Input setup time HS

Input hold time HS fpp =50MHz fpp =50MHz

CMD, D outputs (referenced to CK) in MMC and SD HS mode t

OV t

Output valid time HS

Output hold time HS fpp =50MHz fpp =50MHz

2.5

Max

8/3

13.5

Unit

MHz

ns ns ns

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166

Electrical characteristics STM32F412xE/G

Symbol

Table 96. Dynamic characteristics: SD / MMC characteristics (1)(2) (continued)

Parameter Conditions Min Typ Max

CMD, D inputs (referenced to CK) in SD default mode t

ISUD

Input setup time SD fpp =25MHz t

IHD

Input hold time SD fpp =25MHz

CMD, D outputs (referenced to CK) in SD default mode t

OVD

Output valid default time SD fpp =25 MHz t

OHD

Output hold default time SD fpp =25 MHz

1. Guaranteed by characterization results, not tested in production.

2. V

= 2.7 to 3.6 V.

2.5

0.5

1.5

Unit ns ns

Table 97. Dynamic characteristics: eMMC characteristics V

= 1.7 V to 1.9 V

(1)(2)

Symbol Parameter Conditions Min Typ Max f

W(CKL) t

W(CKH)

Clock frequency in data transfer mode

SDIO_CK/fPCLK2 frequency ratio

Clock low time

Clock high time

CMD, D inputs (referenced to CK) in eMMC mode

fpp =50MHz fpp =50MHz

9.5

8.5

10.5

9.5

8/3

ISU t

Input setup time HS

Input hold time HS

CMD, D outputs (referenced to CK) in eMMC mode fpp =50MHz fpp =50MHz t

OV t

Output valid time HS

Output hold time HS fpp =50MHz fpp =50MHz

1. Guaranteed by characterization results, not tested in production.

2. C

LOAD

= 20 pF.

3.5

13.5

Unit

MHz

ns ns ns

Symbol

Table 98. RTC characteristics

Parameter Conditions f

PCLK1

/RTCCLK frequency ratio

Any read/write operation from/to an RTC register

Min

Max

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STM32F412xE/G Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com.

ECOPACK ® is an ST trademark.

Figure 60. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale package outline

EEE =

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1. Drawing is not to scale.

DocID028087 Rev 7

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196

Package information STM32F412xE/G

Table 99. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches

(1)

Symbol millimeters

Min Typ Max Min Typ Max

G aaa e e1 e2

A3 (2) b

(3)

E bbb ccc ddd eee

0.525

0.220

3.588

3.616

0.555

0.170

0.380

0.025

0.250

3.623

3.651

0.400

2.800

0.4115

0.4255

0.585

0.280

3.658

3.686

0.100

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Back side coating.

3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

0.0207

0.0087

0.1413

0.1424

0.0162

0.0168

0.0219

0.0067

0.0150

0.0010

0.0098

0.1426

0.1437

0.0157

0.1102

0.0039

0.0020

0.0230

0.0110

0.1440

0.1451

Figure 61. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale recommended footprint

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STM32F412xE/G Package information

Pitch

Dpad

Dsm

Table 100. WLCSP64 recommended PCB design rules (0.4 mm pitch)

Dimension Recommended values

Stencil opening

Stencil thickness

0.4 mm

0.225 mm

0.290 mm typ. (depends on the soldermask registration tolerance)

0.250 mm

0.100 mm

Device marking for WLCSP64

The following figure gives an example of topside marking and pin 1 position identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 62. WLCSP64 marking example (package top view)

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1. Parts marked as “ES” or “E” or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

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Package information

7.2 UFQFPN48 package information

STM32F412xE/G

Figure 63. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline

3LQLGHQWLILHU

ODVHUPDUNLQJDUHD

( (

H E

'HWDLO<

GGG

6HDWLQJ

SODQH

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DUHD

SLQFRUQHU

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1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground.

Table 101. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

0.500

0.000

6.900

5.500

0.550

0.020

7.000

5.600

0.600

0.050

7.100

5.700

0.0197

0.0000

0.2717

0.2165

0.0217

0.0008

0.2756

0.2205

0.0236

0.0020

0.2795

0.2244

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Table 101. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

T b e ddd

5.500

0.300

0.200

5.600

0.400

0.152

0.250

0.500

5.700

0.500

0.300

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.2165

0.0118

0.0079

0.2205

0.0157

0.0060

0.0098

0.0197

0.2244

0.0197

0.0118

0.0031

Figure 64. UFQFPN48 recommended footprint

!"?&0?6

1. Dimensions are in millimeters.

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Package information STM32F412xE/G

Device marking for UFQFPN48

The following figure gives an example of topside marking and pin 1 position identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 65. UFQFPN48 marking example (package top view)

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7.3 LQFP64 package information

Package information

Figure 66. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

6($7,1*3/$1(

*$8*(3/$1(

FFF &

' /

3,1

,'(17,),&$7,21

1. Drawing is not to scale.

:B0(B9

DocID028087 Rev 7

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Package information

Table 102. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

L1 ccc

D1 b c

0°

0.450

0.050

1.350

1.400

0.170

0.090

0.220

- 12.000

10.000

7.500

12.000

10.000

7.500

0.500

3.5°

0.600

1.000

1. Values in inches are converted from mm and rounded to 4 decimal digits.

7°

0.750

0.080

1.600

0.150

1.450

0.270

0.200

Min.

0°

0.0177

0.0020

0.0531

0.0067

0.0035

Typ.

0.2953

0.4724

0.3937

0.2953

0.0197

3.5°

0.0236

0.0394

0.0551

0.0087

0.4724

0.3937

STM32F412xE/G

Max.

7°

0.0295

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

174/201

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Figure 67. LQFP64 recommended footprint

Package information

AIC

1. Dimensions are in millimeters.

DocID028087 Rev 7

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196

Package information STM32F412xE/G

Device marking for LQFP64

The following figure gives an example of topside marking and pin 1 position identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 68. LQFP64 marking example (package top view)

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7.4 LQFP100 package information

Package information

Figure 69. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline

3%!4).'0,!.%

'!5'%0,!.%

CCC #

, +

0).

)$%.4)&)#!4)/.

,?-%?6

1. Drawing is not to scale. Dimensions are in millimeters.

Table 103. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max c

A2 b

0.050

1.350

0.170

0.090

15.800

13.800

1.400

0.220

16.000

14.000

1.600

0.150

1.450

0.270

0.200

16.200

14.200

0.0020

0.0531

0.0067

0.0035

0.6220

0.5433

0.0551

0.0087

0.6299

0.5512

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

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Package information STM32F412xE/G

Table 103. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max

E3 e

E1 k ccc

15.800

13.800

0.450

0.0°

12.000

16.000

14.000

12.000

0.500

0.600

1.000

3.5°

16.200

14.200

0.750

7.0°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.6220

0.5433

0.0177

0.0°

0.4724

0.6299

0.5512

0.4724

0.0197

0.0236

0.0394

3.5°

0.6378

0.5591

0.0295

7.0°

0.0031

Figure 70. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint

178/201

1. Dimensions are in millimeters.

DocID028087 Rev 7

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STM32F412xE/G Package information

Device marking for LQFP100

The following figure gives an example of topside marking and pin 1 position identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 71. LQFP100 marking example (package top view)

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(6)

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DocID028087 Rev 7

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196

Package information

7.5 LQFP144 package information

STM32F412xE/G

Figure 72. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline

3%!4).'

0,!.%

CCC #

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, +

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

!?-%?6

180/201

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STM32F412xE/G Package information

Table 104. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max e

E3 k ccc

D1 b c

0.050

1.350

0.170

0.090

21.800

19.800

21.800

19.800

0.450

0°

1.400

0.220

22.000

20.000

17.500

22.000

20.000

17.500

0.500

0.600

1.000

3.5°

1.600

0.150

1.450

0.270

0.200

22.200

20.200

22.200

20.200

0.750

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.8583

0.7795

0.0177

0°

0.0020

0.0531

0.0067

0.0035

0.8583

0.7795

0.6890

0.8661

0.7874

0.6890

0.0197

0.0236

0.0394

3.5°

0.0551

0.0087

0.8661

0.7874

0.8740

0.7953

0.0295

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.8740

0.7953

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Package information STM32F412xE/G

Figure 73. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint

1. Dimensions are expressed in millimeters.

DLH

182/201

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STM32F412xE/G Package information

Device marking for LQFP144

The following figure gives an example of topside marking and pin 1 position identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 74. LQFP144 marking example (package top view)

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196

Package information

7.6 UFBGA100 package information

STM32F412xE/G

Figure 75. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline

= 6HDWLQJSODQH

$ $

(

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1. Drawing is not to scale.

Table 105. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043

A2 0.400 0.450 0.500 0.0157 0.0177 0.0197

A3 0.130 -

A4 0.270 0.320 0.370 0.0106 0.0126 0.0146

D1 5.450 5.500 5.550 0.2146 0.2165 0.2185

E1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e - -

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Table 105. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

ddd eee fff -

0.100

0.150

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0039

0.0059

0.0020

Figure 76. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint

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Pitch

Dpad

Dsm

Table 106. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)

Dimension Recommended values

Stencil opening

Stencil thickness

0.5

0.280 mm

0.370 mm typ. (depends on the soldermask registration tolerance)

0.280 mm

Between 0.100 mm and 0.125 mm

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Package information STM32F412xE/G

Device marking for

UFBGA100

The following figure gives an example of topside marking and ball 1 position identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 77. UFBGA100 marking example (package top view)

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7.7 UFBGA144 package information

Package information

Figure 78. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package outline

& 6HDWLQJSODQH

$ $

(

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GGG =

$ $

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III 0 &

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1. Drawing is not to scale.

Table 107. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043

A2 0.400 0.450 0.500 0.0157 0.0177 0.0197

A3 -

A4 -

0.130

0.320 -

D1 8.750 8.800 8.850

0.3917

0.3445

0.0157 0.0173

0.3937 0.3957

0.3465

0.3484

0.0295

0.3465

0.0315

0.3484

0.0335

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Package information STM32F412xE/G

Table 107. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

ddd eee -

fff -

0.080

0.150

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0236 0.0256

0.0031

0.0059

0.0031

Figure 79. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array recommended footprint

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Note:

ϬϮzͺ&Wͺsϭ

Pitch

Dpad

Dsm

Table 108. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA)

Dimension Recommended values

0.80 mm

0.400 mm

0.550 mm typ. (depends on the soldermask registration tolerance)

Non solder mask defined (NSMD) pads are recommended.

4 to 6 mils solder paste screen printing process.

Stencil opening is 0.400 mm.

Stencil thickness is between 0.100 mm and 0.125 mm.

Pad trace width is 0.120 mm.

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Device marking for UFBGA144

The following figure gives an example of topside marking and ball A1 position identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 80. UFBGA144 marking example (package top view)

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196

Package information STM32F412xE/G

The maximum chip junction temperature (T

J max) must never exceed the values given in

Table 16: General operating conditions on page 82 .

The maximum chip-junction temperature, T

J using the following equation:

max., in degrees Celsius, may be calculated

max = T

max + (PD max x Θ

)

Where:

• T

max is the maximum ambient temperature in °C,

• Θ

is the package junction-to-ambient thermal resistance, in ° C/W,

• PD max is the sum of P

INT

max and P

I/O max (PD max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Symbol

Table 109. Package thermal characteristics

Parameter Value

Thermal resistance junction-ambient

LQFP144 - 20 x 20 mm

Thermal resistance junction-ambient

LQFP100 - 14 x 14 mm

Thermal resistance junction-ambient

LQFP64 - 10 x 10 mm

Thermal resistance junction-ambient

UFBGA144 - 10 x 10 mm / 0.8 mm pitch

Thermal resistance junction-ambient

UFBGA100 - 7 x 7 mm

Thermal resistance junction-ambient

WLCSP64 - 3.623 x 3.651 mm

Thermal resistance junction-ambient

UFQFPN48 - 7 x 7 mm

Unit

°C/W

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

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Table 110. Ordering information scheme

Example: STM32 F 412 C E T 6 P TR

Device family

STM32 = Arm

-based 32-bit microcontroller

Product type

F = General-purpose

Device subfamily

412 = 412 line

Pin count

C = 48 pins

R = 64 pins

V = 100 pins

Z = 144 pins

Flash memory size

E = 512 Kbytes of Flash memory

G = 1024 Kbytes of Flash memory

Package

H = UFBGA 7 x 7 mm

J = UFBGA 10 x 10 mm

T = LQFP

U = UFQFPN

Y = WLCSP

Temperature range

6 = Industrial temperature range, -40 to 85 °C

7 = Industrial temperature range, -40 to 105 °C

3 = Industrial temperature range, -40 to 125°C

Option

Blank = Standard production

P = Internal regulator disabled

Packing

TR = tape and reel

No character = tray or tube

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Recommendations when using the internal reset OFF STM32F412xE/G

Appendix A Recommendations when using the internal reset OFF

When the internal reset is OFF, the following integrated features are no longer supported:

• The integrated power-on-reset (POR)/power-down reset (PDR) circuitry is disabled.

• The brownout reset (BOR) circuitry must be disabled. By default BOR is OFF.

• The embedded programmable voltage detector (PVD) is disabled.

• V

BAT

functionality is no more available and VBAT pin should be connected to V

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Appendix B Application block diagrams

Application block diagrams

B.1 USB OTG full speed (FS) interface solutions

Figure 81. USB controller configured as peripheral-only and used in Full speed mode

9'' 9''86%

9WR9''86%

9ROWDJHUHJXODWRU

670)[[

SLQVSDFNDJHV

26&B,1

26&B287

9%86

966

06Y9

1. External voltage regulator only needed when building a V

BUS

powered device.

Figure 82. USB peripheral-only Full speed mode with direct connection for VBUS sense

9''!9

9''86%

670)[[

SLQVSDFNDJHV

26&B,1

26&B287

1. External voltage regulator only needed when building a V

BUS

powered device.

DocID028087 Rev 7

9%86

966

06Y9

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Application block diagrams STM32F412xE/G

Figure 83. USB peripheral-only Full speed mode, VBUS detection using GPIO

99''9 9''86%

670)[[

SLQVSDFNDJHV

26&B,1

26&B287

*3,2

9%86

966

06Y9

1. External voltage regulator only needed when building a V

BUS

powered device.

Figure 84. USB controller configured as host-only and used in full speed mode

670)[[

*3,2

*3,2,54

9''

2YHUFXUUHQW

&XUUHQWOLPLWHU

SRZHUVZLWFK

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06Y9

1. The current limiter is required only if the application has to support a V switch can be used if 5 V are available on the application board.

BUS

powered device. A basic power

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Figure 85. USB controller configured in dual mode and used in full speed mode

9''

9WR9''

9ROWDJH

UHJXODWRU

9''

670)[[

*3,2

2YHUFXUUHQW

*3,2,54

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B.2

06Y9

1. External voltage regulator only needed when building a V

BUS

powered device.

2. The current limiter is required only if the application has to support a V switch can be used if 5 V are available on the application board.

BUS

powered device. A basic power

3. The ID pin is required in dual role only.

Sensor Hub application example

Figure 86. Sensor Hub application example

670)

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196

Application block diagrams

B.3 Display application example

Figure 87. Display application example

STM32F412xE/G

670)

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%227

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Note: 16 bit displays interfaces can be addressed with 100 and 144 pins packages.

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Revision history

Revision history

Date

10-Nov-2015

01-Feb-2016

25-Mar-2016

Revision

Table 111. Document revision history

Changes

Initial release.

Added:

–

Table 3: Embedded bootloader interfaces

–

Figure 3: Compatible board design for LQFP144 package

–

Figure 62: WLCSP64 marking example (package top view)

–

Figure 77: UFBGA100 marking example (package top view)

Updated:

–

Section 3.17: Power supply schemes

–

Section 3.23: Timers and watchdogs

–

Section 3.32: Universal serial bus on-the-go full-speed (USB_OTG_FS)

–

Figure 1: Compatible board design for LQFP100 package

–

Figure 2: Compatible board design for LQFP64 package

–

Figure 14: STM32F412xE/G LQFP100 pinout

–

Figure 16: STM32F412xE/G UFBGA100 pinout

–

Figure 17: STM32F412xE/G UFBGA144 pinout

–

Figure 20: Input voltage measurement

–

Figure 80: UFBGA144 marking example (package top view)

–

Table 2: STM32F412xE/G features and peripheral counts

–

Table 9: STM32F412xE/G pin definition

–

Table 13: Voltage characteristics

–

Table 14: Current characteristics

–

Table 16: General operating conditions

–

Table 37: Peripheral current consumption

–

Table 52: EMS characteristics for LQFP144 package

–

Table 64: FMPI

C characteristics

Added:

–

Figure 82: USB peripheral-only Full speed mode with direct connection for VBUS sense

–

Figure 83: USB peripheral-only Full speed mode, VBUS detection using GPIO

Updated:

–

Figure 15: STM32F412xE/G LQFP144 pinout

–

Section 6.3.6: Supply current characteristics

–

Table 9: STM32F412xE/G pin definition

–

Table 11: STM32F412xE/G alternate functions

–

Table 12: STM32F412xE/G register boundary addresses

–

Table 16: General operating conditions

–

Table 37: Peripheral current consumption

–

Table 97: Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V

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Revision history STM32F412xE/G

Date

27-May-2016

Revision

Table 111. Document revision history

Changes

Updated:

–

Section 3.23.2: General-purpose timers (TIMx)

–

Table 22: Typical and maximum current consumption, code with data processing

Table 23: Typical and maximum current consumption, code with data processing

–

Table 24: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- V

–

Table 25: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - V

–

Table 26: Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - V

–

Table 27: Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - V

–

Table 28: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory -

–

Table 29: Typical and maximum current consumption in Sleep mode - V

–

Table 30: Typical and maximum current consumption in Sleep mode - V

–

Table 38: Low-power mode wakeup timings

–

(1)

–

Figure 38: I

C bus AC waveforms and measurement circuit

–

Figure 39: FMPI

C timing diagram and measurement circuit

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Date

23-May-2017

Revision

Table 111. Document revision history

Changes

Updated:

–

Section 2: Description

–

Table 2: STM32F412xE/G features and peripheral counts

–

Section 3.19.1: Regulator ON

–

Section 3.19.2: Regulator OFF

–

Table 4: Regulator ON/OFF and internal power supply supervisor availability

–

Table 15: Thermal characteristics

–

Table 16: General operating conditions

–

Table 21: Embedded reset and power control block characteristics

– Table from:

Table 22: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - V

Table 35: Typical and maximum current consumptions in V

BAT

= 1.7 V to

mode

–

Figure 24: Typical V

BAT

current consumption (LSE and RTC ON/LSE oscillator

“low power” mode selection)

–

Figure 25: Typical V

BAT

current consumption (LSE and RTC ON/LSE oscillator

“high drive” mode selection)

–

Table 43: HSI oscillator characteristics

–

Table 44: LSI oscillator characteristics

–

Table 51: Flash memory endurance and data retention

–

Table 55: Electrical sensitivities

–

Table 57: I/O static characteristics

–

Table 88: Asynchronous multiplexed PSRAM/NOR read timings

– Note

in Figure 62: WLCSP64 marking example (package top view)

– Note

in Figure 65: UFQFPN48 marking example (package top view)

– Note

in Figure 68: LQFP64 marking example (package top view)

– Note

in Figure 71: LQFP100 marking example (package top view)

– Note

in Figure 74: LQFP144 marking example (package top view)

– Note

in Figure 77: UFBGA100 marking example (package top view)

– Note

in Figure 80: UFBGA144 marking example (package top view)

–

Table 110: Ordering information scheme

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Revision history STM32F412xE/G

Date

13-Jul-2017

19-Dec-2017

Revision

Table 111. Document revision history

Changes

Updated:

–

Table 2: STM32F412xE/G features and peripheral counts

–

Table 7: USART feature comparison

–

Table 9: STM32F412xE/G pin definition

–

Section 3.29: Digital filter for sigma-delta modulators (DFSDM)

–

Table 107: UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data

Added:

–

Section 4.1: WLSCP64 pinout description

–

Section 4.2: UFQFPN48 pinout description

–

Section 4.3: LQFP64 pinout description

–

Section 4.4: LQFP100 pinout description

–

Section 4.5: LQFP144 pinout description

–

Section 4.6: UFBGA100 pinout description

–

Section 4.7: UFBGA144 pinout description

–

Section 4.8: Pin definition

–

Table 10: FSMC pin definition

Updated:

–

Table 23: Typical and maximum current consumption, code with data processing

Table 23: Typical and maximum current consumption, code with data processing

–