(16 Kbit) are Electrically Erasable PROgrammable Memory (EEPROM) devices accessed through the MICROWIRE™ bus protocol. The memory array can be configured either in bytes (x8b) or in words (x16b).

The M93Cx6-DRE devices operate within a voltage supply range from 1.7 V to 5.5 V

The M93Cx6-DRE devices are guaranteed over the -40 °C/+105 °C temperature range and are compliant with the level of reliability defined by the AEC-Q100 grade 2.

Device

M93C86

M93C76

M93C66

M93C56

M93C46

Table 2. Memory size versus organization

Number of bits Number of 8-bit bytes Number of 16-bit words

16384

8192

4096

2048

1024

2048

1024

512

256

128

1024

512

256

128

Figure 1. Logic diagram

6##

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633

ORG

Signal name

Table 3. Signal names

Function

Chip Select

Serial Data input

Serial Data output

Serial Clock

Organization Select

Supply voltage

Ground

Input

Output

Input

Direction

6/32 DocID028496 Rev 2

M93Cx6-DRE Description

The M93Cx6-DRE is accessed by a set of instructions, as summarized in Table 4 , and in

more detail in

Table 5: Instruction set for the M93C46 to

Table 7: Instruction set for the

M93C76 and M93C86 ).

Instruction

READ

WRITE

WEN

WDS

ERASE

ERAL

WRAL

Table 4. Instruction set for the M93Cx6-DRE

Description

Read Data from Memory

Write Data to Memory

Write Enable

Write Disable

Erase Byte or Word

Erase All Memory

Write All Memory with same Data

Data

Byte or Word

A Read Data from Memory (READ) instruction loads the address of the first byte or word to be read in an internal address register. The data at this address is then clocked out serially.

The address register is automatically incremented after the data is output and, if Chip Select

Input (S) is held High, the M93Cx6-DRE can output a sequential stream of data bytes or words. In this way, the memory can be read as a data stream from eight to 16384 bits long

(in the case of the M93C86), or continuously (the address counter automatically rolls over to

00h when the highest address is reached).

Programming is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle) and does not require an Erase cycle prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the byte or word locations of the M93Cx6-DRE. After the start of the programming cycle, a

Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is driven High. An internal Power-on Data Protection mechanism in the M93Cx6-DRE inhibits the device when the supply is too low.

Figure 2. 8-pin package connections (top view)

-#X

6##

/2'

633

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See

Section 12: Package information for package dimensions, and how to identify pin-1.

DU = Don't Use. The DU (do not use) pin does not contribute to the normal operation of the device. It is reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be connected to V

or V

DocID028496 Rev 2 7/32

Connecting to the serial bus

2 Connecting to the serial bus

M93Cx6-DRE

Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus.

Only one device is selected at a time, so only one device drives the Serial Data output (Q) line at a time, the other devices are high impedance.

The pull-down resistor R (represented in

Figure 3 ) ensures that no device is selected if the

bus master leaves the S line in the high impedance state.

In applications where the bus master may be in a state where all inputs/outputs are high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pull-down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled low): this ensures that C does not become high at the same time as S goes low, and so, that the t

SLCH

requirement is met. The typical value of R is 100 k Ω .

Figure 3. Bus master and memory devices on the serial bus

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8/32 DocID028496 Rev 2

M93Cx6-DRE Operating features

3.1

3.1.1

Supply voltage (V

CC

)

Operating supply voltage (V

)

Prior to selecting the memory and issuing instructions to it, a valid and stable V

voltage within the specified [V

(min), V

(max)] range must be applied. In order to secure a stable

DC supply voltage, it is recommended to decouple the V

line with a suitable capacitor

(usually of the order of 10 nF to 100 nF) close to the V

package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t

When the power supply is turned on, V

rises from V

to V

. During this time, the Chip

Select (S) line is not allowed to float and should be driven to V

, it is therefore recommended to connect the S line to V

via a suitable pull-down resistor. The V

CC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in

Table 13 .

3.1.3 Power-up and device reset

In order to prevent inadvertent Write operations during power-up, a power on reset (POR) circuit is included. At power-up (continuous rise of V

), the device does not respond to any instruction until V

has reached the power on reset threshold voltage (this threshold is lower than the minimum V

operating voltage defined in Operating conditions, in

Section 11: DC and AC parameters ).

When V

passes the POR threshold, the device is reset and is in the following state:

• Standby Power mode

• deselected (assuming that there is a pull-down resistor on the S line)

As soon as the V

voltage has reached a stable value within [V the device is ready for operation.

(min), V

(max)] range,

In a similar way, during power-down (continuous decrease in V

), the device must not be accessed when V

drops below V

(min).

3.1.4 Power-down

At power down, the power-on-reset (POR) circuit resets and locks the device as soon as the

reached the internal threshold voltage.

At power-down (continuous decrease in V

), as soon as V

drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it.

During power-down, the device must be deselected and in the Standby Power mode (that is, there should be no internal Write cycle in progress).

DocID028496 Rev 2 9/32

Memory organization M93Cx6-DRE

The M93Cx6-DRE memory is organized either as bytes (x8) or as words (x16). If

Organization Select (ORG) is left unconnected (or connected to V

) the x16 organization is selected; when Organization Select (ORG) is connected to Ground (V

) the x8 organization is selected. When the M93Cx6-DRE is in Standby mode, Organization Select

(ORG) should be set either to V

or V

to reach the device minimum power consumption

(as any voltage between V

and V

applied to ORG input may increase the device

Standby current).

Figure 4. M93Cx6-DRE ORG input connection

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10/32 DocID028496 Rev 2

M93Cx6-DRE

5 Instructions

Instructions

Instruction

The instruction set of the M93Cx6-DRE devices contains seven instructions, as summarized in

Table 5

to Table 7 . Each instruction consists of the following parts, as shown in

Figure 5:

READ, WRITE, WEN, WDS sequences :

• Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock

• A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of

Serial Clock (C).

• Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock

(C). (Some instructions also use the first two bits of the address to define the op-code).

• The address bits of the byte or word that is to be accessed. For the M93C46, the address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization

(see Table 5 ). For the M93C56 and M93C66, the address is made up of 8 bits for the

x16 organization or 9 bits for the x8 organization (see Table 6 ). For the M93C76 and

M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8

organization (see Table 7 ).

The M93Cx6-DRE devices are fabricated in CMOS technology and are therefore able to run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in “AC characteristics” tables, in

Section 11: DC and AC parameters .

Description

Table 5. Instruction set for the M93C46 x8 origination (ORG = 0)

Start bit

Opcode Address

(1)

Data x16 origination (ORG = 1)

Required clock cycles

Address

(1)

Data

Required clock cycles

READ

WRITE

WEN

Read Data from

Memory

Write Data to

Memory

Write Enable

A6-A0 Q7-Q0

A6-A0 D7-D0

A5-A0 Q15-Q0

A5-A0 D15-D0

11 XXXX -

WDS Write Disable 1

00 11X XXXX

00X

XXXX

10 00 XXXX 9

ERASE

Erase Byte or

Word

1 11 A6-A0 10 A5-A0 9

ERAL Erase All Memory

WRAL

Write All Memory with same Data

X = Don't Care bit.

10X

XXXX

01X

XXXX

D7-D0

10 XXXX -

01 XXXX D15-D0

DocID028496 Rev 2 11/32

Instructions M93Cx6-DRE

Instruction

READ

WRITE

Table 6. Instruction set for the M93C56 and M93C66

Description x8 origination (ORG = 0)

Start bit

Opcode Address

(1) (2)

Data

Required clock cycles x16 origination (ORG = 1)

Address

(1) (3)

Data

Required clock cycles

Read Data from Memory 1

Write Data to Memory 1

A8-A0

Q7-

D7-

A7-A0

Q15-

A7-A0 D15-D0

WEN

WDS

ERASE

ERAL

Write Enable

Write Disable

Erase Byte or Word

Erase All Memory

1 1XXX

XXXX

0 0XXX

XXXX

A8-A0

1 0XXX

XXXX

0 1XXX

XXXX

D7-

11XX

XXXX

00XX

XXXX

A7-A0

10XX

XXXX

01XX

XXXX

D15-D0

27 WRAL

Write All Memory with same Data

X = Don't Care bit.

Address bit A8 is not decoded by the M93C56.

Address bit A7 is not decoded by the M93C56.

Instruction

Table 7. Instruction set for the M93C76 and M93C86 x8 Origination (ORG = 0) x16 Origination (ORG = 1)

Description

Start bit

Opcode Address

(1)(2)

Data

Required clock cycles

Address

(1) (3)

Data

Required clock cycles

READ

WRITE

Read Data from

Memory

Write Data to

Memory

A10-A0

Q7-Q0

D7-D0

A9-A0 Q15-Q0

A9-A0 D15-D0

WEN

WDS

ERASE

ERAL

Write Enable

Write Disable

Erase Byte or Word 1

Erase All Memory

WRAL

Write All Memory with same Data

1 00

X = Don't Care bit.

Address bit A10 is not decoded by the M93C76.

Address bit A9 is not decoded by the M93C76.

11X XXXX

XXXX

00X XXXX

XXXX

A10-A0

10X XXXX

XXXX

01X XXXX

XXXX

D7-D0

11 XXXX

XXXX

00 XXXX

XXXX

A9-A0

10 XXXX

XXXX

01 XXXX

XXXX

D15-D0

12/32 DocID028496 Rev 2

M93Cx6-DRE

5.1

Instructions

Read Data from Memory

The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q).

When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Cx6-DRE automatically increments the internal address register and clocks out the next byte (or word) as long as the Chip

Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read

(the address counter automatically rolls over to 00h when the highest address is reached).

5.2 Erase and Write data

5.2.1 Write Enable and Write Disable

The Write Enable (WEN) instruction enables the future execution of erase or write instructions, and the Write Disable (WDS) instruction disables it. When power is first applied, the M93Cx6-DRE initializes itself so that erase and write instructions are disabled.

After a Write Enable (WEN) instruction has been executed, erasing and writing remains enabled until a Write Disable (WDS) instruction is executed, or until V

falls below the power-on reset threshold voltage. To protect the memory contents from accidental corruption, it is advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable

(WEN) or Write Disable (WDS) instructions.

5.2.2 Write

For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and address bits. These form the byte or word that is to be written. As with the other bits, Serial

Data Input (D) is sampled on the rising edge of Serial Clock (C).

After the last data bit has been sampled, the Chip Select Input (S) must be taken low before the next rising edge of Serial Clock (C).

If Chip Select Input (S) is brought low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. The completion of the cycle can be detected by monitoring the READY/BUSY line, as described later in this document.

Once the Write cycle has been started, it is internally self-timed (the external clock signal on

Serial Clock (C) may be stopped or left running after the start of a Write cycle). The Write cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an explicit erase instruction before a Write Data to Memory (WRITE) instruction.

DocID028496 Rev 2 13/32

Instructions M93Cx6-DRE

Figure 5. READ, WRITE, WEN, WDS sequences

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Table 6 and Table 7 .

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14/32 DocID028496 Rev 2

M93Cx6-DRE Instructions

As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with same Data (WRAL) instruction requires that a dummy address be provided. As with the

Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same

Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided.

This value is written to all the addresses of the memory device. The completion of the cycle can be detected by monitoring the READY/BUSY line, as described next.

Figure 6. WRAL sequence

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Table 5 ,

Table 6 and Table 7

ECC (Error Correction Code) and Write cycling

The devices identified with the Process letter “K” embed an Error Correction Code (ECC) internal logic function which is transparent for the Microwire communication protocol.

The ECC logic is implemented on each byte.

DocID028496 Rev 2 15/32

Instructions

5.2.5

M93Cx6-DRE

Erase Byte or Word

The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or word) to 1. Once the address has been correctly decoded, the falling edge of the Chip

Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be

detected by monitoring the READY/BUSY line, as described in Section 6: READY/BUSY status .

Figure 7. ERASE, ERAL sequences

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The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set to 1). The format of the instruction requires that a dummy address be provided. The Erase cycle is conducted in the same way as the Erase instruction (ERASE). The completion of the cycle can be detected by monitoring the READY/BUSY line, as described in

Section 6:

READY/BUSY status .

16/32 DocID028496 Rev 2

M93Cx6-DRE

6 READY/BUSY status

READY/BUSY status

While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.

(Please note, though, that there is an initial delay, of t

SLSH

, before this status information becomes available). In this state, the M93Cx6-DRE ignores any data on the bus. When the

Write cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1) indicates that the M93Cx6-DRE is ready to receive the next instruction. Serial Data Output

(Q) remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is decoded.

7

8 Initial delivery state

The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).

Common I/O operation

Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a current limiting resistor, to form a common, single-wire data bus. Some precautions must be taken when operating the memory in this way, mostly to prevent a short circuit current from flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output

(Q). Please see the application note AN394 for details.

DocID028496 Rev 2 17/32

Clock pulse counter

9 Clock pulse counter

M93Cx6-DRE

In a noisy environment, the number of pulses received on Serial Clock (C) may be greater than the number delivered by the master (the microcontroller). This can lead to a misalignment of the instruction of one or more bits (as shown in

Figure 8 ) and may lead to

the writing of erroneous data at an erroneous address.

To avoid this problem, the M93Cx6-DRE has an on-chip counter that counts the clock pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL instruction is aborted, and the contents of the memory are not modified.

The number of clock cycles expected for each instruction, and for each member of the

M93Cx6-DRE family, are summarized in Table 5: Instruction set for the M93C46

Table 7:

Instruction set for the M93C76 and M93C86

. For example, a Write Data to Memory (WRITE) instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization) from the start bit to the falling edge of Chip Select Input (S). That is:

1 Start bit

+ 2 Op-code bits

+ 9 Address bits

+ 8 Data bits

Figure 8. Write sequence with one clock glitch

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18/32 DocID028496 Rev 2

M93Cx6-DRE Maximum ratings

Stressing the device outside the ratings listed in the Absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 8. Absolute maximum ratings

Parameter Min.

Max.

Unit

Ambient operating temperature –40 130 °C

STG

LEAD

OUT

ESD

Storage temperature

Lead temperature during soldering

Output range (Q = V

Input range

Supply voltage

or Hi-Z)

Electrostatic discharge voltage (human body model)

(2)

–65

–0.50

See note

150

(1)

+0.5

6.5

4000

°C

Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb free assembly), the ST

ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances

(RoHS directive 2011/65/EU of July 2011).

Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with

ANSI/ESDA/JEDEC JS-001-2012), C1 = 100 pF, R1 = 1500

, R2 = 500

DocID028496 Rev 2 19/32

DC and AC parameters

11 DC and AC parameters

M93Cx6-DRE

This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device.

Table 9. Operating conditions (voltage range R, temperature range 8)

Symbol Parameter Min.

Max.

Unit

Supply voltage

Ambient operating temperature

1.7

- 40

5.5

105

°C

Symbol

Table 10. AC measurement conditions

Parameter

Load capacitance

Input rise and fall times

Input voltage levels

Input timing reference voltages

Output timing reference voltages

Min.

Max.

100

0.2 V

to 0.8 V

0.3 V

to 0.7 V

0.3 V

to 0.7 V

Figure 9. AC testing input output waveforms

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Table 11. Input and output capacitance

Parameter Test condition

(1)

Min Symbol

OUT

Output capacitance

Input capacitance

OUT

= 0V

Sampled only, not 100% tested, at T

= 25 °C and a frequency of 1 MHz.

Max

Unit pF pF

Table 12. Cycling performance by byte

Symbol Parameter Test condition Min.

Max.

Unit

Ncycle

Write cycle endurance

≤

< 5.5 V

TA = 85 °C, 1.7 V < V

< 5.5 V

TA = 105 °C, 1.7 V < V

< 5.5 V -

4,000,000

1,200,000

900,000

Write cycle

A Write cycle is executed when either a Write, a Write All, an Erase or an Erase All instruction is decoded.

(1)

Unit pF ns

20/32 DocID028496 Rev 2

M93Cx6-DRE DC and AC parameters

Symbol

CC0

(1)

CC1

Parameter

Input leakage current

Output leakage current

Supply current (Read)

Supply current (Write)

Input low voltage (D, C, S)

Input high voltage (D, C, S)

Output low voltage

Output high voltage

RES

Internal reset threshold voltage

Average value during the Write cycle (t

)

Table 13. DC characteristics

Test conditions

(in addition to conditions specified in

Table 9 )

Supply current (Standby mode)

= V

or V

S = V

, V

OUT

= V

or V

= 1.7 V, C = 0.1 V

/0.9 V

Q = open, f

= 2 MHz

= 2.5 V, C = 0.1 V

/0.9 V

Q = open, f

= 2 MHz

= 5.5 V, f

= 2 MHz

C = 0.1 V

/0.9 V

, Q = open

1.7 V ≤

< 5.5 V during t

S = V

CC t° = 25 °C, V

= 1.7V,

S = V

CC,

= V

or V

CC t° = 25 °C, V

= 2.5 V,

S = V

CC,

= V

or V

CC t° = 25 °C, V

= 5.5 V,

S = V

CC,

= V

or V

CC t° = 105 °C, V

= 1.7V,

S = V

CC,

= V

or V

CC t° = 105 °C, V

= 2.5 V,

S = V

CC,

= V

or V

CC t° = 105 °C, V

= 5.5 V,

S = V

CC,

= V

or V

1.7V

≤

< 2.5 V

2.5 V ≤

< 5.5 V

1.7V ≤

< 2.5 V

2.5 V ≤

< 5.5 V

= 1.7 V, I

= 1 mA

≥ 2.5 V, I

= 2.1 mA

= 1.7 V, I

= 1 mA

≥ 2.5 V, I

= -2.1 mA

Min.

–0.45

0.75 V

0.7 V

0.8 V

0.5

Max.

1.5

0.25 V

0.3 V

0.3

0.4

1.5

Unit

µA mA mA

µA

DocID028496 Rev 2 21/32

DC and AC parameters M93Cx6-DRE

Table 14. AC characteristics

Test conditions specified in

Table 9 and Table 10

Symbol Alt.

Parameter Min.

Max.

Unit f

C t

SLCH t

SHCH t

SLSH

(1) t

CHCL

(2) t

CLCH

(2) t

DVCH t

CHDX t

CLSH t

CLSL t

SHQV f

SK t

DIS t

DIH t

SKS t

CSH t

SV t

CSS t

CS t

SKH t

SKL

Clock frequency

Chip Select low to Clock high

Chip Select set-up time

Chip Select low to Chip Select high

Clock high time

Clock low time

Data in set-up time

Data in hold time

Clock set-up time (relative to S)

Chip Select hold time

Chip Select to READY/BUSY status

D.C.

200

MHz ns ns ns ns ns ns ns ns ns ns t

SLQZ

(3) t

Chip Select low to output Hi-Z (V

>2.5 V)

Chip Select low to output Hi-Z (V

<2.5 V)

Delay to output low

100

200 ns ns t t

CHQL

CHQV t

PD0 t

PD1 t

Delay to output valid -

200

200 ns ns t

Erase or Write cycle time 4 ms

Chip Select Input (S) must be brought low for a minimum of t

SLSH

between consecutive instruction cycles.

CHCL

+ t

CLCH

≥

1 / f

Value defined from characterization, not tested in production.

22/32 DocID028496 Rev 2

M93Cx6-DRE

DC and AC parameters

Figure 10. Synchronous timing (Start and op-code input)

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Package information M93Cx6-DRE

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

ECOPACK

is an ST trademark.

12.1 SO8N package information

Figure 13. SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline

CCC

*$8*(3/$1(

K c

A2 b k

L e h

% %

62$B9

Drawing is not to scale.

Symbol

Table 15. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data millimeters inches

(1)

Min.

Typ.

Max.

Min.

Typ.

Max.

0.100

1.250

0.280

0.170

4.800

5.800

3.800

0.250

0°

0.400

4.900

6.000

3.900

1.270

1.750

0.250

0.480

0.230

5.000

6.200

4.000

0.500

8°

1.270

0.0039

0.0492

0.0110

0.0067

0.1890

0.2283

0.1496

0.0098

0°

0.0157

0.1929

0.2362

0.1535

0.0500

0.0689

0.0098

0.0189

0.0091

0.1969

0.2441

0.1575

0.0197

8°

0.0500

24/32 DocID028496 Rev 2

M93Cx6-DRE Package information

Symbol

Table 15. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data (continued) millimeters inches

(1)

Min.

Typ.

Max.

Min.

Typ.

Max.

L1 ccc

1.040

0.100

Values in inches are converted from mm and rounded to four decimal digits.

0.0409

0.0039

Figure 14. SO8N – 8-lead plastic small outline, 150 mils body width, package recommended footprint

[

2B621B)3B9

Dimensions are expressed in millimeters.

DocID028496 Rev 2 25/32

Package information M93Cx6-DRE

Figure 15.TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch, package outline

ϴ ϱ

Đ ϭ ϭ ϰ ɲ

Ϯ ϭ

>ϭ

W ď Ğ

76623$0B9

Drawing is not to scale.

Table 16. TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch, package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

D e

A2 b

0.050

0.800

0.190

0.090

2.900

1.000

3.000

0.650

1.200

0.150

1.050

0.300

0.200

0.100

3.100

6.200

4.300

6.400

4.400

6.600

4.500

0.2441

0.1693

L 0.450

0.600

0.750

0.0177

0°

1.000

8°

0°

Values in inches are converted from mm and rounded to four decimal digits.

0.0020

0.0315

0.0075

0.0035

0.1142

0.0394

0.1181

0.0256

0.2520

0.1732

0.0236

0.0394

0.0472

0.0059

0.0413

0.0118

0.0079

0.0039

0.1220

0.2598

0.1772

0.0295

8°

26/32 DocID028496 Rev 2

M93Cx6-DRE Package information

Figure 16. WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package outline

3LQ,'PDUNLQJ

$ %

'DWXP<

3LQ

(

6HH=

'HWDLO

[

DDD #

7RSYLHZ

1'[H

%RWWRPYLHZ

1;E EEE

GGG

$ %

'DWXP<

FFF #

HHH #

6HDWLQJSODQH

/ /

7HUPLQDOWLS

6LGHYLHZ

'HWDLO³=´

$<B0(B9

Drawing is not to scale.

The central pad (the area E2 by D2 in the above illustration) must be either connected to Vss or left floating

(not connected) in the end application.

DocID028496 Rev 2 27/32

Package information M93Cx6-DRE

Table 17. WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

(2)

(3) aaa bbb ccc ddd eee

(4)

E e

A1 b

0.700

0.025

0.200

1.900

2.900

0.300

1.050

0.400

0.300

0.750

0.045

0.250

2.000

3.000

0.500

0.800

0.065

0.300

2.100

3.100

0.150

1.650

1.450

0.500

0.0276

0.0010

0.0079

0.0748

0.1142

0.0118

0.0413

0.0157

0.0118

0.0295

0.0018

0.0098

0.0787

0.1181

0.0197

0.150

0.100

0.050

0.080

Values in inches are converted from mm and rounded to four decimal digits.

NX is the number of terminals.

ND is the number of terminals on “D” sides.

Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring.

0.0059

0.0039

0.0020

0.0031

0.0315

0.0026

0.0118

0.0827

0.1220

0.0059

0.0650

0.0571

0.0197

28/32 DocID028496 Rev 2

M93Cx6-DRE Part numbering

Table 18. Ordering information scheme

Example:

Device type

M93 = MICROWIRE serial EEPROM

Device function

M93C 86 R MN 8 T P /K

86 = 16 Kbit (2048 x 8)

76 = 8 Kbit (1024 x 8)

66 = 4 Kbit (512 x 8)

56 = 2 Kbit (256 x 8)

46 = 1 Kbit (128 x 8)

Operating voltage

R = V

= 1.7 to 5.5 V

Package

(1)

MN = SO8 (150 mils width)

DW = TSSOP8 (169 mils width)

MF = WFDFPN8 (2 x 3 mm)

Device grade

8 = - 40 to 105 °C

Packing

T = tape and reel packing blank = tube packing

Plating technology

P or G = ECOPACK2

Process

/K = Manufacturing technology code

All packages are ECOPACK2 flame retardants).

(RoHS compliant and free of brominated, chlorinated and antimony-oxide

DocID028496 Rev 2 29/32

Part numbering M93Cx6-DRE

Engineering samples

Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.

30/32 DocID028496 Rev 2

M93Cx6-DRE Revision history

Date

09-Nov-2015

23-Feb-2017

Revision

Table 19. Document revision history

Changes

Initial release.

Updated:

–

Features

–

Section 1: Description

–

Section 3.1.4: Power-down

–

Table 9: Operating conditions (voltage range R, temperature range 8)

–

Table 12: Cycling performance by byte

–

Table 13: DC characteristics

–

Table 18: Ordering information scheme

DocID028496 Rev 2 31/32

M93Cx6-DRE

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

32/32 DocID028496 Rev 2

Reklaam

16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit (8-bit or 16-bit wide)

MICROWIRE™ serial EEPROM 105 °C operation

Features

Contents

List of tables

List of figures

1 Description

2 Connecting to the serial bus

3.1

Supply voltage (V

CC

)

5 Instructions

5.1

Read Data from Memory

5.2 Erase and Write data

6 READY/BUSY status

7

8

Initial delivery state

Common I/O operation

9 Clock pulse counter

11 DC and AC parameters

12.1 SO8N package information

7RSYLHZ

%RWWRPYLHZ

6LGHYLHZ

'HWDLO³=´

Engineering samples

Seotud

STMicroelectronics M93C56-A125 Datasheet

STMicroelectronics M93C66-R Datasheet

STMicroelectronics M93C86-125 Datasheet

STMicroelectronics M95040-DRE Datasheet

STMicroelectronics M95256-DRE Datasheet

STMicroelectronics M95128-DRE Datasheet

STMicroelectronics M95320-DRE Datasheet

STMicroelectronics M24C04-DRE Datasheet

STMicroelectronics M24C08-DRE Datasheet

STMicroelectronics M24C02-DRE Datasheet

STMicroelectronics M24256-DRE Datasheet

STMicroelectronics M24C32-DRE Datasheet