PROgrammable Memory). The M95256-DRE is a byte-alterable memory (32768 × 8 bits) organized as 512 pages of 64 bytes in which the data integrity is significantly improved with an embedded Error Correction Code logic.

The M95256-DRE offers an additional Identification Page (64 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode.

Figure 1. Logic diagram

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6/42 DocID027468 Rev 2

M95256-DRE

Figure 2. 8-pin package connections

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6##

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1. See

Package information

section for package dimensions and how to identify pin-1.

Signal name

HOLD

Table 1. Signal names

Description

Serial Clock

Serial data input

Serial data output

Chip Select

Write Protect

Hold

Supply voltage

Ground

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Description

DocID027468 Rev 2 7/42

Signal description M95256-DRE

2.1

2.2

2.3

2.4

All input signals must be held high or low (according to voltages of V

Table 12 ). These signals are described below.

or V

, as specified in

Serial Data output (Q)

This output signal is used to transfer data serially out of the device during a Read operation.

Data is shifted out on the falling edge of Serial Clock (C), most significant bit (MSB) first. In all other cases, the Serial Data output is in high impedance.

Serial Data input (D)

This input signal is used to transfer data serially into the device. D input receives instructions, addresses, and the data to be written. Values are latched on the rising edge of

Serial Clock (C), most significant bit (MSB) first.

Serial Clock (C)

This input signal allows to synchronize the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial

Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

Chip Select (S)

Driving Chip Select (S) low selects the device in order to start communication. Driving Chip

Select (S) high deselects the device and Serial Data output (Q) enters the high impedance state.

The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.

This pin is used to write-protect the Status Register.

2.7 V

SS

ground

is the reference for all signals, including the V

supply voltage.

8/42 DocID027468 Rev 2

M95256-DRE Signal description

2.8 V

CC

supply voltage

is the supply voltage pin. Refer to

Section 3.1: Active power and Standby power modes

and to

Section 5.1: Supply voltage (VCC)

DocID027468 Rev 2 9/42

Operating features M95256-DRE

3.1 Active power and Standby power modes

When Chip Select (S) is low, the device is selected and in the Active power mode.

When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in progress, the device then goes in to the Standby power mode, and the device consumption drops to I

CC1

, as specified in

Table 12 .

The device can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

• CPOL=0, CPHA=0

• CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in

Figure 3

, is the clock polarity when the bus master is in Stand-by mode and not transferring data:

• C remains at 0 for (CPOL=0, CPHA=0)

• C remains at 1 for (CPOL=1, CPHA=1)

Figure 3. SPI modes supported

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10/42 DocID027468 Rev 2

M95256-DRE Operating features

3.4

The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence.

The Hold mode starts when the Hold (HOLD) signal is driven low and the Serial Clock (C) is low (as shown in

Figure 4 ). During the Hold mode, the Serial Data output (Q) is high

impedance, and the signals present on Serial Data input (D) and Serial Clock (C) are not decoded. The Hold mode ends when the Hold (HOLD) signal is driven high and the Serial

Clock (C) is or becomes low.

Figure 4. Hold mode activation

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Deselecting the device while it is in Hold mode resets the paused communication.

-36

Protocol control and data protection

The Chip Select (S) input offers a built-in safety feature, as the S input is edge-sensitive as well as level-sensitive: after power-up, the device is not selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been high prior to going low, in order to start the first operation.

For Write commands (WRITE, WRSR, WRID, LID) to be accepted and executed:

• the Write Enable Latch (WEL) bit must be set by a Write Enable (WREN) instruction

• a falling edge and a low state on Chip Select (S) during the whole command must be decoded

• instruction, address and input data must be sent as multiple of eight bits

• the command must include at least one data byte

• Chip Select (S) must be driven high exactly after a data byte boundary

Write command can be discarded at any time by a rising edge on Chip Select (S) outside of a byte boundary.

To execute Read commands (READ, RDSR, RDID, RDLS), the device must decode:

• a falling edge and a low level on Chip Select (S) during the whole command

• instruction and address as multiples of eight bits (bytes)

From this step, data bits are shifted out until the rising edge on Chip Select (S).

DocID027468 Rev 2 11/42

Operating features

3.4.2 Status Register and data protection

M95256-DRE

The Status Register format is shown in

Table 2

and the status and control bits of the Status

SRWD

Table 2. Status Register format b5 b4 b3 b2 b1 b0

Note:

Status Register Write Protect

Block Protect bits

Write Enable Latch bit

Write In Progress bit

Bits b6, b5, b4 are always read as 0.

WIP bit

The WIP bit (Write In Progress) is a read-only flag that indicates the Ready/Busy state of the device. When a Write command (WRITE, WRSR, WRID, LID) has been decoded and a

Write cycle (t

) is in progress, the device is busy and the WIP bit is set to 1. When WIP=0, the device is ready to decode a new command.

During a Write cycle, reading continuously the WIP bit allows to detect when the device becomes ready (WIP=0) to decode a new command.

WEL bit

The WEL bit (Write Enable Latch) bit is a flag that indicates the status of the internal Write

Enable Latch. When WEL is set to 1, the Write instructions (WRITE, WRSR, WRID, LID) are executed; when WEL is set to 0, any decoded Write instruction is not executed.

The WEL bit is set to 1 with the WREN instruction. The WEL bit is reset to 0 after the following events:

• Write Disable (WRDI) instruction completion

• Write instructions (WRITE, WRSR, WRID, LID) completion including the write cycle time t

• Power-up

BP1, BP0 bits

The Block Protect bits (BP1, BP0) are non-volatile. BP1,BP0 bits define the size of the

memory block to be protected against write instructions, as defined in Table 2 . These bits

are written with the Write Status Register (WRSR) instruction, provided that the Status

Register is not protected (refer to “ SRWD bit and W input signal ”, on page 13

12/42 DocID027468 Rev 2

M95256-DRE Operating features

Status Register bits

BP1

BP0

Table 3. Write-protected block size

Protected block Protected array addresses

None

Upper quarter

Upper half

Whole memory

None

6000h-7FFFh

4000h-7FFFh

0000h - 7FFFh plus Identification page

SRWD bit and W input signal

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect pin (W) signal. When the SRWD bit is written to 0, it is possible to write the Status

When the SRWD bit is written to 1, two cases have to be considered, depending on the state of the W input pin:

• Case 1: if pin W is driven high, it is possible to write the Status Register.

• Case 2: if pin W is driven low, it is not possible to write the Status Register (WRSR is discarded) and therefore SRWD,BP1,BP0 bits cannot be changed (the size of the protected memory block defined by BP1,BP0 bits is frozen).

Case 2 can be entered in either sequence:

• Writing SRWD bit to 1 after driving pin W low, or

• Driving pin W low after writing SRWD bit to 1.

The only way to exit Case 2 is to pull pin W high.

Note: if pin W is permanently tied high, the Status Register cannot be write-protected.

The protection features of the device are summarized in

Table 4 .

SRWD bit W signal

Table 4. Protection modes

Status Register is writable.

Status

Status Register is write-protected.

The M95256-DRE offers an Identification page (64 bytes) in addition to the 256 Kbit memory. The Identification page contains two fields:

• Device identification: the three first bytes are programmed by STMicroelectronics with the Device identification code, as shown in

Table 5

• Application parameters: the bytes after the Device identification code are available for application specific data.

DocID027468 Rev 2 13/42

Operating features

Note:

M95256-DRE

If the end application does not need to read the Device identification code, this field can be overwritten and used to store application-specific data. Once the application-specific data are written in the Identification page, the whole Identification page should be permanently locked in Read-only mode.

The Read, Write, Lock Identification Page instructions are detailed in

Section 4: Instructions .

Table 5. Device identification bytes

Content Value

Address in

Identification page

00h

01h

02h

ST Manufacturer code

SPI Family code

Memory Density code

20h

00h

0Fh (256 Kbit)

14/42 DocID027468 Rev 2

M95256-DRE

4 Instructions

Instructions

Each command is composed of bytes (MSBit transmitted first), initiated with the instruction

byte, as summarized in Table 6 .

If an invalid instruction is sent (one not contained in Table 6 ), the device automatically enters

a Wait state until deselected.

Instruction

Table 6. Instruction set

Description

WREN

WRDI

RDSR

WRSR

READ

WRITE

RDID

WRID

RDLS

LID

Write Enable

Write Disable

Read Status Register

Write Status Register

Read from Memory Array

Write to Memory Array

Read Identification Page

Write Identification Page

Reads the Identification Page lock status.

Locks the Identification page in read-only mode.

Instruction format

0000 0110

0000 0100

0000 0101

0000 0001

0000 0011

0000 0010

1000 0011

1000 0010

1000 0011

1000 0010

For read and write commands to memory array and Identification Page, the address is

defined by two bytes as explained in Table 7 .

Table 7. Significant bits within the two address bytes

(1)(2)

MSB Address byte LSB Address byte

Instructions b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

READ or

WRITE

RDID or

WRID

RDLS or

LID x

A14 A13 A12 A11 A10

1. A: Significant address bit.

2. x: bit is Don’t Care.

DocID027468 Rev 2 15/42

Instructions M95256-DRE

The WREN instruction must be decoded by the device before a write instruction (WRITE,

WRSR, WRID or LID).

As shown in Figure 5

, to send this instruction to the device, Chip Select (S) is driven low, the bits of the instruction byte are shifted in (MSB first) on Serial Data Input (D) after what the

Chip Select (S) input is driven high and the WEL bit is set (Status Register bit).

Figure 5. Write Enable (WREN) sequence

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One way of resetting the WEL bit (in the Status Register) is to send a Write Disable instruction to the device.

As shown in

Figure 6 , to send this instruction to the device, Chip Select (S) is driven low,

and the bits of the instruction byte are shifted in (MSB first), on Serial Data Input (D), after what the Chip Select (S) input is driven high and the WEL bit is reset (Status Register bit).

If a Write cycle is currently in progress, the WRDI instruction is decoded and executed and the WEL bit is reset to 0 with no effect on the ongoing Write cycle.

Figure 6. Write Disable (WRDI) sequence

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16/42 DocID027468 Rev 2

M95256-DRE

4.3

Instructions

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction is used to read the content of the Status

As shown in

Figure 7 , to send this instruction to the device, Chip Select (S) is first driven

low. The bits of the instruction byte are shifted in (MSB first) on Serial Data Input (D), the

Status Register content is then shifted out (MSB first) on Serial Data Output (Q).

If Chip Select (S) continues to be driven low, the Status Register content is continuously shifted out.

The Status Register can always be read, even if a Write cycle (t

) is in progress. The Status

Section 3.4.2: Status Register and data protection .

Figure 7. Read Status Register (RDSR) sequence

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DocID027468 Rev 2 17/42

Instructions

4.4

M95256-DRE

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

The Write Status Register (WRSR) instruction is entered (MSB first) by driving Chip Select

(S) low, sending the instruction code followed by the data byte on Serial Data input (D), and driving the Chip Select (S) signal high.

The contents of the SRWD and BP1, BP0 bits are updated after the completion of the

WRSR instruction, including the Write cycle (t

The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0 bits in the Status Register (see

Table 2: Status Register format

The Status Register functionality is detailed in Section 3.4.2: Status Register and data protection .

The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

Figure 8. Write Status Register (WRSR) sequence

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18/42 DocID027468 Rev 2

M95256-DRE

4.5

Instructions

Read from Memory Array (READ)

The READ instruction is used to read the content of the memory.

As shown in

Figure 9 , to send this instruction to the device, Chip Select (S) is first driven

low.

The bits of the instruction byte and address bytes are shifted in (MSB first) on Serial Data

Input (D) and the addressed data byte is then shifted out (MSB first) on Serial Data Output

(Q). The first addressed byte can be any byte within any page.

If Chip Select (S) continues to be driven low, the internal address register is automatically incremented, and the next byte of data is shifted out. The whole memory can therefore be read with a single READ instruction.

When the highest address is reached, the address counter rolls over to zero, allowing the

Read cycle to be continued indefinitely.

The Read cycle is terminated by driving Chip Select (S) high at any time when the data bits are shifted out on Serial Data Output (Q).

The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

Figure 9. Read from Memory Array (READ) sequence

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1. Depending on the memory size, as shown in Table 7 , the most significant address bits are Don’t Care.

DocID027468 Rev 2 19/42

Instructions

4.6

M95256-DRE

Write to Memory Array (WRITE)

The WRITE instruction is used to write new data in the memory.

As shown in

Figure 10

, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in (MSB first), on Serial Data Input (D). The instruction is terminated by driving Chip

Select (S) high at a data byte boundary.

Figure 10

shows a single byte write.

Figure 10. Byte Write (WRITE) sequence

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1. Depending on the memory size, as shown in

Table 7

, the most significant address bits are Don’t Care.

A Page write is used to write several bytes inside a page, with a single internal Write cycle.

For a Page write, Chip Select (S) has to remain low, as shown in Figure 11 , so that the next

data bytes are shifted in. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the address counter exceeds the page boundary (the page size is 64 bytes), the internal address pointer rolls over to the beginning of the same page where next data bytes will be written. If more than 64 bytes are received, only the last 64 bytes are written.

Note:

For both Byte write and Page write, the self-timed Write cycle starts from the rising edge of

Chip Select (S), and continues for a period t

(as specified in Table 13

The instruction is discarded, and is not executed, under the following conditions:

• if a Write cycle is already in progress

• if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits

•

if one of the conditions defined in Section 3.4.1

is not satisfied

The self-timed Write cycle t

is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as “1”.

20/42 DocID027468 Rev 2

M95256-DRE Instructions

Figure 11. Page Write (WRITE) sequence

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DocID027468 Rev 2 21/42

Instructions

4.7

M95256-DRE

Read Identification Page (RDID)

The Read Identification Page instruction is used to read the Identification Page (additional page of 64 bytes which can be written and later permanently locked in Read-only mode).

The Chip Select (S) signal is first driven low, the bits of the instruction byte and address bytes are then shifted in (MSB first) on Serial Data input (D). Address bit A10 must be 0 and the other upper address bits are Don't Care (it might be easier to define these bits as 0, as

shown in Table 7 ). The data byte pointed to by the lower address bits [A5:A0] is shifted out

(MSB first) on Serial Data output (Q).

The first byte addressed can be any byte within the identification page.

If Chip Select (S) continues to be driven low, the internal address register is automatically incremented and the byte of data at the new address is shifted out.

Note that there is no roll over feature in the Identification Page. The address of bytes to read must not exceed the page boundary.

The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip

Select (S) signal can occur at any time when the data bits are shifted out.

The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

Figure 12. Read Identification Page sequence

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The first three bytes of the Identification page offer information about the device itself.

Please refer to

Section 3.5: Identification page

for more information.

22/42 DocID027468 Rev 2

M95256-DRE

4.8

Instructions

Write Identification Page (WRID)

The Write Identification Page instruction is used to write the Identification Page (additional page of 64 bytes which can also be permanently locked in Read-only mode).

The Chip Select signal (S) is first driven low, and then the bits of the instruction byte, address bytes, and at least one data byte are shifted in (MSB first) on Serial Data input (D).

Address bit A10 must be 0 and the other upper address bits are Don't Care (it might be

easier to define these bits as 0, as shown in Table 7

). The lower address bits [A5:A0] define the byte address inside the identification page.

The self-timed Write cycle starts from the rising edge of Chip Select (S), and continues for a period t

(as specified in

Table 13 ).

Figure 13. Write Identification Page sequence

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The first three bytes of the Identification page offer the Device Identification code (Please refer to

Section 3.5: Identification page

for more information). Using the WRID command on these first three bytes overwrites the Device Identification code.

The instruction is discarded, and is not executed, under the following conditions:

• If a Write cycle is already in progress

• If the Block Protect bits (BP1,BP0) = (1,1)

•

If one of the conditions defined in Section 3.4.1: Protocol control

is not satisfied.

Read Lock Status (RDLS)

The Read Lock Status instruction is used to read the lock status.

To send this instruction to the device, Chip Select (S) first has to be driven low. The bits of the instruction byte and address bytes are then shifted in (MSB first) on Serial Data input

(D). Address bit A10 must be 1; all other address bits are Don't Care (it might be easier to define these bits as 0, as shown in

Table 7 ). The Lock bit is the LSB (Least Significant Bit) of

the byte read on Serial Data output (Q). It is at ‘1’ when the lock is active and at ‘0’ when the lock is not active. If Chip Select (S) continues to be driven low, the same data byte is shifted out.

The read cycle is terminated by driving Chip Select (S) high. The instruction sequence is

shown in Figure 14 .

DocID027468 Rev 2 23/42

Instructions M95256-DRE

The Read Lock Status instruction is not accepted and not executed if a Write cycle is currently in progress.

Figure 14. Read Lock Status sequence

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The Lock Identification Page (LID) command is used to permanently lock the Identification

Page in Read-only mode.

The LID instruction is issued by driving Chip Select (S) low, sending (MSB first) the instruction code, the address and a data byte on Serial Data input (D), and driving Chip

Select (S) high. In the address sent, A10 must be equal to 1. All other address bits are Don't

Care (it might be easier to define these bits as 0, as shown in

Table 7

). The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care. The LID instruction is terminated by driving Chip Select (S) high at a data byte boundary, otherwise, the instruction is not executed.

Figure 15. Lock ID sequence

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Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed Write cycle which duration is t

Figure 15

(specified in

Table 13 ). The instruction sequence is shown in

DocID027468 Rev 2

M95256-DRE Instructions

The instruction is discarded, and is not executed, under the following conditions:

• If a Write cycle is already in progress

• If the Block Protect bits (BP1,BP0) = (1,1)

•

If one of the conditions defined in Section 3.4.1: Protocol control

is not satisfied.

DocID027468 Rev 2 25/42

Application design recommendations

5 Application design recommendations

5.1

5.1.1

M95256-DRE

Supply voltage (V

CC

)

Operating supply voltage (V

)

Prior to selecting the memory and issuing instructions to it, a valid and stable V

CC within the specified [V

CC(min)

, V

CC(max)

voltage

] range must be applied (see

Table 10 and Table 11

This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal Write cycle (t

W secure a stable DC supply voltage, it is recommended to decouple the V

CC suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V

CC pins.

line with a

). In order to

package

When the power supply is turned on, V

continuously rises from V therefore recommended to connect the S line to V

Figure 16

to V

CC time, the Chip Select (S) line is not allowed to float but should follow the V

. During this

voltage. It is

via a suitable pull-up resistor (see

The V

voltage has to rise continuously from 0 V up to the minimum V

defined in Table 12

operating voltage

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included.

At power-up, the device does not respond to any instruction until V

reaches the internal threshold voltage (this threshold is defined in the DC characteristics

Table 12

as VRES).

When V

passes over the POR threshold, the device is reset and in the following state:

• in the Standby power mode

• deselected

• Status register values:

– Write Enable Latch (WEL) bit is reset to 0.

– Write In Progress (WIP) bit is reset to 0.

– SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).

• not in the Hold condition

As soon as the V

voltage has reached a stable value within [V the device is ready for operation.

(min), V

(max)] range,

26/42 DocID027468 Rev 2

M95256-DRE Application design recommendations

5.1.3 Power-down

At power down, the power-on-reset (POR) circuit resets and locks the device as soon as the

reached the internal threshold voltage

During power-down (continuous decrease in the V

supply voltage below the minimum

operating voltage defined in

Table 12 ), the device must be:

• deselected (Chip Select (S) should be allowed to follow the voltage applied on V

• in Standby power mode (there should not be any internal Write cycle in progress).

Figure 16

shows an example of three devices, connected to the SPI bus master. Only one device is selected at a time, so that only the selected device drives the Serial Data output

(Q) line. All the other devices outputs are then in high impedance.

Figure 16. Bus master and memory devices on the SPI bus

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1. The Write Protect (W) and Hold (HOLD) signals must be driven high or low as appropriate.

A pull-up resistor connected on each /S input (represented in Figure 16 ) ensures that each

device is not selected if the bus master leaves the /S line in the high impedance state.

DocID027468 Rev 2 27/42

Application design recommendations

5.3 Cycling with Error Correction Code (ECC)

M95256-DRE

The Error Correction Code (ECC) is an internal logic function which is transparent for the

SPI communication protocol.

The ECC logic is implemented on each group of four EEPROM bytes

(a)

. Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved.

Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group

(a)

. As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in

Table 9: Cycling performance by groups of 4 bytes .

Example1: maximum cycling limit reached with 1 million cycles per byte

Each byte of a group can be equally cycled 1 million times (at 25 °C) so that the group cycling budget is 4 million cycles.

Example2: maximum cycling limit reached with unequal byte cycling

Inside a group, byte0 can be cycled 2 million times, byte1 can be cycled 1 million times, byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 million cycles.

28/42 a. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.

DocID027468 Rev 2

M95256-DRE Delivery state

7

The device is delivered with:

• the memory array set to all 1s (each byte = FFh),

• Status register: bit SRWD =0, BP1 =0 and BP0 =0,

• Identification page: the first three bytes define the Device identification code (value

defined in Table 5 ). The content of the following bytes is Don’t Care.

Absolute maximum ratings

Stressing the device outside the ratings listed in

Table 8

may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 8. Absolute maximum ratings

Parameter Min.

Max.

Unit

STG

AMR

LEAD

Storage temperature

Ambient operating temperature

Lead temperature during soldering

Voltage on Q pin

Input voltage

- 65

- 40

See note

- 0.50

150

(1)

+0.6

6.5

°C

DC output current (Q = 0)

DC output current (Q = 1) -

5 mA mA

Supply voltage - 0.50

6.5

ESD

Electrostatic pulse (Human Body Model)

(2)

4000 V

1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK ®

7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS directive 2011/65/EU of July 2011).

2. Positive and negative pulses applied on pin pairs, in accordance with AEC-Q100-002 (compliant with

ANSI/ESDA/JEDEC JS-001-2012, C1=100 pF, R1=1500 Ω , R2=500 Ω )

DocID027468 Rev 2 29/42

DC and AC parameters

8 DC and AC parameters

M95256-DRE

This section summarizes the operating conditions and the DC/AC characteristics of the device.

Symbol

Table 9. Cycling performance by groups of 4 bytes

Parameter Test condition Min.

Max.

Unit

Ncycle Write cycle endurance

(1)

≤ 25 °C, 1.7 V < V

< 5.5 V

= 85 °C, 1.7 V < V

< 5.5 V

= 105 °C, 1.7 V < V

< 5.5 V -

4,000,000

1,200,000

900,000

Write cycle

1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where

N is an integer, or for the status register byte (refer also to

Section 5.3: Cycling with Error Correction Code (ECC) ). The

Write cycle endurance is defined by characterization and qualification.

2. A Write cycle is executed when either a Page Write, a Byte Write, a WRSR, a WRID or an LID instruction is decoded.

When using the Byte Write, the Page Write or the WRID, refer also to Section 5.3: Cycling with Error Correction Code

(ECC)

(2)

Symbol

A f

Table 10. Operating conditions (voltage range R, temperature range 8)

Parameter Conditions

Supply voltage -

Ambient operating temperature

Operating clock frequency

≥ 2.5 V, capacitive load on Q pin ≤ 100pF

≥ 1.7 V, capacitive load on Q pin ≤ 100pF

Min.

Max.

1.7

- 40

5.5

105

Unit

°C

MHz

Table 11. Operating conditions (voltage range R, temperature range 8) for high-speed communications

Parameter Conditions Min.

Max.

Unit Symbol

A f

Supply voltage

Ambient operating temperature

Operating clock frequency

≥ 4 .5 V, capacitive load on Q pin ≤ 60 pF

4.5

- 40

5.5

°C

MHz

30/42 DocID027468 Rev 2

M95256-DRE DC and AC parameters

Symbol

OUT

(1)

CC0

(3)

CC1

Table 12. DC characteristics (voltage range R, temperature range 8)

Parameter

Test conditions

(in addition to conditions specified

in Table 10 )

Min.

Output capacitance (Q)

Input capacitance

Input leakage current

Output leakage current

Supply current (Read)

Supply current (Write)

Supply current (Standby mode)

Input low voltage

Input high voltage

Output low voltage

Output high voltage

RES

(1) Internal reset threshold voltage

1. Characterized only, not 100% tested.

2. When –40 °C < t° < 85 °C.

3. Average value during the Write cycle (t

OUT

= 0 V

= V

or V

S = V

, V

OUT

= V

or V

= 1.7 V, C = 0.1 V

/0.9 V

Q = open, f

= 5 MHz

= 2.5 V, C = 0.1 V

/0.9 V

Q = open, f

= 10 MHz

= 5.5 V, f

= 20 MHz

(2)

C = 0.1 V

/0.9 V

, Q = open

1.7 V ≤

< 5.5 V during t

S = V

CC t° = 25 °C, V

S = V

CC,

= 1.7 V,

= V

or V

CC t° = 25 °C, V

S = V

CC,

= 2.5 V,

= V

or V

CC t° = 25 °C, V

S = V

CC,

= 5.5 V,

= V

or V

CC t° = 105 °C, V

S = V

CC,

= 1.7 V,

= V

or V

CC t° = 105 °C, V

S = V

CC,

= 2.5 V,

= V

or V

CC t° = 105 °C, V

S = V

CC,

= 5.5 V,

= V

or V

1.7 V ≤

< 2.5 V

2.5 V ≤

< 5.5 V

1.7 V ≤ V

< 2.5 V

2.5 V ≤

< 5.5 V

= 1.7 V, I

= 1 mA

≥ 2.5 V, I

= 2 mA

= 1.7 V, I

= 1 mA

≥ 2.5 V, I

= -2 mA

- 0.45

0.75 V

0.7 V

0.8 V

0.5

Max.

(1)

2.5

0.25 V

0.3 V

+ 1

0.3

0.4

1.5

Unit pF

µA mA mA

µA

DocID027468 Rev 2 31/42

DC and AC parameters M95256-DRE

Table 13. AC characteristics

Min. Max. Min. Max. Min. Max.

Symbol Alt.

Parameter

Test conditions specified in

Table 10

Test conditions specified in

Table 10

Test conditions specified in

Table 11

Unit f

C t

SLCH t

SHCH t

SHSL t

CHSH t

CHSL t

(1) t

CLCH

(2) t

CHCL

(2) t

DVCH t

CHDX t

HHCH t

HLCH t

CLHL t t t t t f t

CSS1

CSS2 t t t

SCK

CSH t

CLH

CLL

DSU

Clock frequency

S active setup time

S not active setup time

S deselect time

S active hold time

S not active hold time

Clock high time

Clock low time

Clock rise time

Clock fall time

Data in setup time

Data in hold time

Clock low hold time after HOLD not active

Clock low hold time after HOLD active

Clock low set-up time before HOLD active

MHz ns

µs t

CLHH

Clock low set-up time before HOLD not active

0 0 0 t

SHQZ

(2) t

CLQV

(3) t

CLQX t

QLQH

(2) t

QHQL

(2) t

HHQV t

HLQZ

(2) t

W t t

DIS t

V t

HO t

RO t

FO t

LZ t

Output disable time

Clock low to output valid

Output hold time

Output rise time

Output fall time

HOLD high to output valid

HOLD low to output high-Z

Write time

4 ns ms

1. t

+ t

must never be lower than the shortest possible clock period, 1/f

(max).

2. Value guaranteed by characterization, not 100% tested in production.

3. t

CLQV

must be compatible with t

(or greater than) t

CLQV

(clock low time): if t

is the Read setup time of the SPI bus master, t

must be equal to

32/42 DocID027468 Rev 2

M95256-DRE

&+6/

'9&+

DC and AC parameters

Figure 17. AC measurement I/O waveform

,QSXW/HYHOV

,QSXWDQG2XWSXW

7LPLQJ5HIHUHQFH/HYHOV

ೌ9

$,&

Figure 18. Serial input timing

6+6/

6/&+

06%,1

&+&/

&+';

&+6+

/6%,1

&/&+

6+&+

+LJKLPSHGDQFH

$,G

Figure 19. Hold timing

+/&+

&/+/

++&+

+/4=

&/++

++49

+2/'

$,F

DocID027468 Rev 2 33/42

DC and AC parameters

T#,16

T#,18

!$$2

,3").

T#,#(

Figure 20. Serial output timing

T#(

T#(#, T#,

T1,1(

T1(1,

T3(3,

M95256-DRE

T3(1:

!)F

34/42 DocID027468 Rev 2

M95256-DRE Package information

9.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

SO8N package information

Figure 21. SO8N – 8-lead plastic small outline, 150 mils body width, package outline

CCC

*$8*(3/$1(

% %

62$B9

1. Drawing is not to scale.

Table 14. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data millimeters inches

(1)

Symbol

Typ.

Min.

Max.

Typ.

Min.

Max.

b c ccc

A2 e h

E1 k

4.90

6.00

3.90

1.27

0.10

1.25

0.28

0.17

4.80

5.80

3.80

0.25

0°

1.75

0.25

0.48

0.23

0.10

5.00

6.20

4.00

0.50

8°

0.1929

0.2362

0.1535

0.05

0.0039

0.0492

0.011

0.0067

0.189

0.2283

0.1496

0.0098

0°

0.0689

0.0098

0.0189

0.0091

0.0039

0.1969

0.2441

0.1575

0.0197

8°

DocID027468 Rev 2 35/42

Package information M95256-DRE

Table 14. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data (continued) millimeters inches (1)

Symbol

Typ.

Min.

Max.

Typ.

Min.

Max.

1.04

0.40

1.27

0.0409

1. Values in inches are converted from mm and rounded to four decimal digits.

0.0157

0.05

Figure 22. TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package outline

36/42

ϴ ϱ

Đ ϭ ϭ ϰ ɲ

Ϯ ϭ

>ϭ

W ď Ğ

76623$0B9

1. Drawing is not to scale.

Table 15. TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

b c

D e

0.050

0.800

0.190

0.090

2.900

1.000

3.000

0.650

1.200

0.150

1.050

0.300

0.200

0.100

3.100

0.0020

0.0315

0.0075

0.0035

0.1142

0.0394

0.1181

0.0256

0.0472

0.0059

0.0413

0.0118

0.0079

0.0039

0.1220

DocID027468 Rev 2

M95256-DRE Package information

Table 15. TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package mechanical data (continued) millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

6.200

4.300

0.450

6.400

4.400

0.600

6.600

4.500

0.750

0.2441

0.1693

0.0177

L1 1.000

α 0° 8° 0°

1. Values in inches are converted from mm and rounded to four decimal digits.

0.2520

0.1732

0.0236

0.0394

0.2598

0.1772

0.0295

8°

Figure 23. WFDFPN8 (MLP8) – 8-lead very thin fine pitch dual flat package no lead

2 x 3 mm, 0.5 mm, package outline

3LQ,'PDUNLQJ

$ %

'DWXP<

3LQ

(

6HH=

'HWDLO

[

DDD #

7RSYLHZ

1'[H

%RWWRPYLHZ

1;E EEE

GGG

$ %

'DWXP<

FFF #

HHH #

6HDWLQJSODQH

/ /

'HWDLO³=´

7HUPLQDOWLS

6LGHYLHZ

$<B0(B9

1. Drawing is not to scale.

2. The central pad (the area E2 by D2 in the above illustration) must be either connected to Vss or left floating

(not connected) in the end application.

DocID027468 Rev 2 37/42

Package information M95256-DRE

Table 16. WFDFPN8 (MLP8) – 8-lead very thin fine pitch dual flat package no lead

2 x 3 mm, 0.5 mm pitch, mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

aaa bbb ccc ddd eee (4)

NX (2)

(3)

E e

A1 b

0.700

0.025

0.200

1.900

2.900

0.300

1.050

0.400

0.300

0.750

0.045

0.250

2.000

3.000

0.500

0.800

0.065

0.300

2.100

3.100

0.150

1.650

1.450

0.500

0.0276

0.0010

0.0079

0.0748

0.1142

0.0118

0.0413

0.0157

0.0118

0.0295

0.0018

0.0098

0.0787

0.1181

0.0197

0.150

0.100

0.050

0.080

0.0059

0.0039

0.0020

0.0031

1. Values in inches are converted from mm and rounded to four decimal digits.

2. NX is the number of terminals.

3. ND is the number of terminals on “D” sides.

4. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring.

0.0315

0.0026

0.0118

0.0827

0.1220

0.0059

0.0650

0.0571

0.0197

38/42 DocID027468 Rev 2

M95256-DRE Ordering information

Table 17. Ordering information scheme

Example:

Device type

M95 = SPI serial access EEPROM

M95 256-D R DW 8 T P /K

Device function

256-D = 256 Kbit (32 Kbytes) plus Identification Page

Operating voltage

R = V

= 1.7 to 5.5 V

Package

(1)

MN = SO8 (150 mils width)

DW = TSSOP8 (169 mils width)

MF = WFDFPN8 (2 x 3 mm)

Device grade

8 = – 40 to 105 °C.

Option blank = Tube packing

T = Tape and reel packing

Plating technology

P or G = ECOPACK2

Process letter

/K = Manufacturing technology code

1. All packages are ECOPACK2 flame retardants).

(RoHS compliant and free of brominated, chlorinated and antimony-oxide

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.

DocID027468 Rev 2 39/42

Ordering information M95256-DRE

Engineering samples

Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

40/42 DocID027468 Rev 2

M95256-DRE Revision history

Date

09-Feb-2015

15-Feb-2017

Revision

Table 18. Document revision history

Changes

Initial release.

Updated:

–

Features

–

Section 5.1.3: Power-down

–

Table 9: Cycling performance by groups of 4 bytes

–

Table 10: Operating conditions (voltage range R, temperature range 8)

–

Table 12: DC characteristics (voltage range R, temperature range 8)

–

Table 15: TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package mechanical data

–

Figure 22: TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package outline

–

Section 10: Ordering information

DocID027468 Rev 2 41/42

M95256-DRE

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

42/42 DocID027468 Rev 2

256-Kbit serial SPI bus EEPROM - 105 °C operation

Features

Contents

List of tables

List of figures

1 Description

2.1

2.2

2.3

2.4

Serial Data output (Q)

Serial Data input (D)

Serial Clock (C)

Chip Select (S)

2.7 V

SS

ground

2.8 V

CC

supply voltage

3.1 Active power and Standby power modes

3.4

Protocol control and data protection

WIP bit

WEL bit

BP1, BP0 bits

SRWD bit and W input signal

4 Instructions

4.3

Read Status Register (RDSR)

4.4

Write Status Register (WRSR)

4.5

Read from Memory Array (READ)

4.6

Write to Memory Array (WRITE)

4.7

Read Identification Page (RDID)

4.8

Write Identification Page (WRID)

4.9

Read Lock Status (RDLS)

5 Application design recommendations

5.1

Supply voltage (V

CC

)

5.3 Cycling with Error Correction Code (ECC)

Example1: maximum cycling limit reached with 1 million cycles per byte

Example2: maximum cycling limit reached with unequal byte cycling

7

Absolute maximum ratings

8 DC and AC parameters

9.1

SO8N package information

7RSYLHZ

%RWWRPYLHZ

'HWDLO³=´

6LGHYLHZ

Engineering samples

Terkait

STMicroelectronics M95256-DF Datasheet

STMicroelectronics M95M04-DR Datasheet

STMicroelectronics M95256-125 Datasheet

STMicroelectronics M95256-A145 Datasheet

STMicroelectronics M95640-DRE Datasheet

STMicroelectronics M95M04-A145 Datasheet

STMicroelectronics M95160-DRE Datasheet

STMicroelectronics M95080-DRE Datasheet

STMicroelectronics M95128-DRE Datasheet

STMicroelectronics M95320-DRE Datasheet

STMicroelectronics M95128-A145 Datasheet

STMicroelectronics M95040-DRE Datasheet