STMicroelectronics STM32L452CE Datasheet

Maximum current into each V

power pin (source)

Maximum current out of each V

ground pin (sink)

Total output current sourced by sum of all I/Os and control pins

Output current sunk by any I/O and control pin except FT_f

Max

140

100

Unit

100

20 I

IO(PIN)

∑I

IO(PIN)

Output current sunk by any FT_f pin

Output current sourced by any I/O and control pin

Total output current sunk by sum of all I/Os and control pins

(3)

Table 20: Voltage characteristics

100

100 mA

INJ(PIN)

(4)

Injected current on FT_xxx, TT_xx, RST and B pins, except PA4,

PA5

-5/+0

(5)

∑|I

INJ(PIN)

Injected current on PA4, PA5

Total injected current (sum of all I/Os and control pins)

(6)

-5/0

1. All main power (V

, V

DDA

, V

DDUSB

, V

BAT

) and ground (V

, V

SSA

) pins must always be connected to the external power

2. Valid also for V

DD12

on SMPS packages.

3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

4. Positive injection (when V specified maximum value.

> V

DDIOx

) is not possible on these I/Os and does not occur for input voltages lower than the

5. A negative injection is induced by V

< V

. I

INJ(PIN)

must never be exceeded. Refer also to

for the maximum allowed input voltage values.

6. When several inputs are submitted to a current injection, the maximum ∑|I injected currents (instantaneous values).

INJ(PIN)

| is the absolute sum of the negative

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Electrical characteristics

Symbol

STG

Table 22. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

STM32L452xx

Unit

°C

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6.3 Operating conditions

6.3.1 General operating conditions

Table 23. General operating conditions

Symbol f

HCLK f

PCLK1 f

PCLK2

Parameter

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Conditions

Min

Standard operating voltage -

1.71

(1)

DD12

Standard operating voltage

DDA

BAT

Analog supply voltage

Backup operating voltage

DDUSB

USB supply voltage

Full frequency range

Up to 26 MHz

ADC or COMP used

DAC or OPAMP used

VREFBUF used

ADC, DAC, OPAMP, COMP,

VREFBUF not used

USB used

USB not used

TT_xx I/O

1.55

3.0

-0.3

1.08

1.05

1.62

1.8

2.4

I/O input voltage

All I/O except TT_xx -0.3

Power dissipation at

= 85 °C for suffix 6

Power dissipation at

= 125 °C for suffix 3

(4)

LQFP100

UFBGA100

LQFP64

UFBGA64

WLCSP64

LQFP48

UFQFPN48

LQFP100

UFBGA100

LQFP64

UFBGA64

WLCSP64

LQFP48

UFQFPN48

Max

3.6

1.32

3.6

Unit

MHz

3.6

DDIOx

+0.3

Min(Min(V

DDUSB

, V

DDA

5.5 V)

)+3.6 V,

(2)(3)

357

267

345

308

377

346

690

172

V mW mW

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Electrical characteristics STM32L452xx

Symbol

Table 23. General operating conditions (continued)

Parameter Conditions Min Max Unit

Ambient temperature for the suffix 6 version

Ambient temperature for the suffix 3 version

Junction temperature range

Maximum power dissipation

Low-power dissipation (5)

Maximum power dissipation

Low-power dissipation

(5)

Suffix 6 version

Suffix 3 version

–40

105

125

130

105

130

1. When RESET is released functionality is guaranteed down to V

BOR0

Min.

2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.

Maximum I/O input voltage is the smallest value between Min(V

, V

DDA

, V

DDUSB

)+3.6 V and 5.5V.

3. For operation with voltage higher than Min (V be disabled.

, V

DDA

, V

DDUSB

) +0.3 V, the internal Pull-up and Pull-Down resistors must

4. If T

is lower, higher P

values are allowed as long as T

does not exceed T

Jmax

(see Section 7.8: Thermal characteristics

5. In low-power dissipation state, T

Thermal characteristics

can be extended to this range as long as T

does not exceed T

Jmax

(see Section 7.8:

°C

6.3.2

6.3.3 Operating conditions at power-up / power-down

The parameters given in

Table 24 are derived from tests performed under the ambient

temperature condition summarized in

Table 23 .

Symbol t

VDD t

VDDA t

VDDUSB

Table 24. Operating conditions at power-up / power-down

Parameter Conditions Min Max

rise time rate

fall time rate

DDA

rise time rate

DDA

fall time rate

DDUSB

rise time rate

DDUSB

fall time rate

∞

Unit

µs/V

The requirements for power-up/down sequence specified in Section 3.9.1: Power supply schemes must be respected.

Embedded reset and power control block characteristics

The parameters given in

Table 25 are derived from tests performed under the ambient

temperature conditions summarized in Table 23: General operating conditions

Table 25. Embedded reset and power control block characteristics

Symbol Parameter Conditions

(1)

Min Typ Max t

RSTTEMPO

(2)

Reset temporization after

BOR0 is detected

DD rising 250 400

Unit

μs

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STM32L452xx Electrical characteristics

Table 25. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions (1) Min Typ Max Unit

BOR0

(2)

BOR1

BOR2

BOR3

BOR4

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6 hyst_BORH0

Brown-out reset threshold 0

Brown-out reset threshold 1

Brown-out reset threshold 2

Brown-out reset threshold 3

Brown-out reset threshold 4

Programmable voltage detector threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Hysteresis voltage of BORH0

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Hysteresis in continuous mode

Hysteresis in other mode

V hyst_BOR_PVD

(BOR_PVD)

(2)

PVM1

Hysteresis voltage of BORH

(except BORH0) and PVD

BOR (3) (except BOR0) and

PVD consumption from V

DDUSB

peripheral voltage monitoring

PVM3

DDA

peripheral voltage monitoring

Rising edge

Falling edge

2.85

2.76

2.1

2.26

2.15

2.41

2.31

2.56

2.47

2.26

2.16

2.56

2.47

1.62

1.6

2.06

1.96

2.69

2.59

2.85

2.75

2.92

2.84

1.18

1.61

1.6

2.90

2.81

2.15

2.05

2.31

2.20

2.46

2.36

2.61

2.52

2.31

2.20

2.61

2.52

1.66

1.64

2.1

2.74

2.64

2.91

2.81

2.98

2.90

100

1.1

1.22

1.65

1.64

2.95

2.86

2.19

2.1

2.36

2.25

2.51

2.41

2.66

2.57

2.35

2.24

2.66

2.57

1.7

1.69

2.14

2.04

2.79

2.69

2.96

2.86

3.04

2.96

1.6

1.26

1.69

1.68

V mV mV

µA

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Electrical characteristics STM32L452xx

Table 25. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions (1) Min Typ Max Unit

PVM4

V hyst_PVM3

V hyst_PVM4

(PVM1)

(2)

DDA

peripheral voltage monitoring

PVM3 hysteresis

PVM4 hysteresis

PVM1 consumption from V

Rising edge

Falling edge

1.78

1.77

1.82

1.81

0.2

1.86

1.85

V mV mV

µA

(PVM3/PVM4)

(2)

PVM3 and PVM4 consumption from V

2 µA

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

2. Guaranteed by design.

3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables.

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6.3.4 Embedded voltage reference

The parameters given in

Table 26 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 23: General operating conditions

Symbol

Table 26. Embedded internal voltage reference

Parameter Conditions Min Typ Max

REFINT

Internal reference voltage t t

S_vrefint

(1) start_vrefint

ADC sampling time when reading the internal reference voltage

Start time of reference voltage buffer when ADC is enable

REFINTBUF

)

REFINT

buffer consumption from V

ADC

when converted by

–40 °C < T

< +130 °C

∆V

REFINT

Internal reference voltage spread over the temperature range

= 3 V

Coeff

DDCoeff

REFINT_DIV1

REFINT_DIV2

REFINT_DIV3

Temperature coefficient

Long term stability

Voltage coefficient

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage

–40°C < T

< +130°C

1000 hours, T = 25°C

3.0 V < V

< 3.6 V

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

1.182

1.212

1.232

(2)

12.5

7.5

(2)

30 50

(2)

300 1000

(2)

250 1200

(2)

Unit

µs

µA mV ppm/°C ppm ppm/V

REFINT

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Electrical characteristics STM32L452xx

1.235

1.23

1.225

1.22

1.215

1.21

1.205

1.2

1.195

1.19

1.185

-40 -20

Figure 20. V

REFINT

versus temperature

0 20

Mean

Min

Max

80 100 120 °C

MSv40169V1

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STM32L452xx

6.3.5

Electrical characteristics

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 19: Current consumption measurement scheme with and without external SMPS power supply .

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted with the minimum wait states number, depending on the f

HCLK

frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0394 reference manual).

• When the peripherals are enabled f

PCLK

= f

HCLK

The parameters given in

Table 27 to

Table 50 are derived from tests performed under

ambient temperature and supply voltage conditions summarized in

Table 23: General operating conditions

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192

Symbol Parameter

DD_ALL

(Run)

DD_ALL

(LPRun)

Table 27. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF)

Conditions TYP MAX

(1)

Voltage scaling f

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

26 MHz 2.35

2.40

2.50

16 MHz 1.50

1.55

1.65

2.65

1.80

3.00

2.15

2.65

2.75

1.70

1.75

2.90

1.95

3.20

2.20

3.75

2.80

Supply current in

Run mode f

HCLK

= f

HSE

up to

48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Range 2

8 MHz 0.815 0.845 0.940

1.10

1.45

4 MHz 0.465 0.495 0.595

0.760

1.10

0.95

1.00

0.55

0.60

2 MHz 0.295 0.320 0.420

0.580

0.910

0.35

0.40

1 MHz 0.205 0.235 0.330

0.495

0.825

0.25

0.30

100 kHz 0.130 0.155 0.250

0.415

0.745

0.15

0.25

80 MHz 8.45

8.50

8.65

8.90

9.25

9.45

9.50

72 MHz 7.65

7.70

7.85

64 MHz 6.80

6.85

7.00

8.05

7.20

8.45

7.60

8.50

7.60

8.60

7.70

Supply current in

Low-power run mode f

HCLK

= f

MSI all peripherals disable

Range 1 48 MHz 5.10

5.15

5.25

32 MHz 3.45

3.50

3.60

24 MHz 2.60

2.65

2.80

16 MHz 1.80

1.85

1.95

2 MHz 225

1 MHz 130

260

160

365

270

400 kHz 73.0

99.5

205

100 kHz 38.0

71.0

175

5.45

3.80

2.95

2.15

550

450

385

355

5.85

4.20

3.35

2.50

900

800

735

705

5.70

3.85

2.95

2.00

275

170

105

5.80

3.95

3.05

2.10

335

225

165

140

470

375

325

315

6.00

4.15

3.20

2.30

1.15

0.75

0.55

0.45

1.45

1.05

0.85

0.75

2.00

1.60

1.40

1.30

0.40

0.65

1.25

9.75

10.10

10.75

8.80

7.90

9.15

8.25

9.85

8.90

6.35

4.50

3.55

2.60

770

670

600

565

7.00

5.15

4.20

3.25

1400

1300

1250

1200 mA

µA

1. Guaranteed by characterization results, unless otherwise specified.

Symbol

DD_ALL

(Run)

Table 28. Current consumption in Run modes, code with data processing running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

DD12

= 1.10 V)

Conditions

(1)

Parameter

TYP

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C

Unit

Supply current in Run mode f

HCLK

= f

HSE

up to 48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

80 MHz 3.04

3.06

72 MHz 2.75

2.77

64 MHz 2.44

2.46

48 MHz 1.83

1.85

32 MHz 1.24

1.26

24 MHz 0.93

0.95

16 MHz 0.65

0.67

8 MHz 0.35

0.36

4 MHz 0.20

0.21

2 MHz 0.13

0.14

1 MHz 0.09

0.10

100 kHz 0.06

0.07

1.29

1.01

0.70

0.41

3.11

2.82

2.52

1.89

0.26

0.18

0.14

0.11

1.37

1.06

0.77

0.47

3.20

2.89

2.59

1.96

0.33

0.25

0.21

0.18

1.51

1.20

0.90

0.63

3.33

3.04

2.73

2.10

0.47

0.39

0.36

0.32

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,

DD12

= 1.10 V

Symbol Parameter

Table 29. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART disable

Conditions TYP MAX

(1)

Voltage scaling f

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Supply current in

Low-power run f

HCLK

= f

MSI all peripherals disable

Range 2

Range 1

26 MHz 2.75

2.80

2.90

16 MHz 1.95

2.00

2.10

8 MHz 1.10

1.15

1.25

3.10

2.25

1.40

3.40

2.60

1.75

3.15

2.25

1.25

4 MHz 0.640 0.670 0.765

0.935

1.25

0.75

2 MHz 0.380 0.405 0.505

0.670

1.00

0.45

1 MHz 0.250 0.275 0.375

0.540

0.865

0.30

100 kHz 0.135 0.160 0.255

0.420

0.750

0.15

80 MHz 8.85

8.90

9.05

72 MHz 8.00

8.05

8.20

64 MHz 7.90

7.95

8.10

48 MHz 6.60

6.65

6.80

32 MHz 4.75

4.80

4.95

24 MHz 3.60

3.65

3.80

16 MHz 2.60

2.65

2.75

2 MHz 340 360 470

9.30

8.40

8.35

7.05

5.15

4.00

2.95

650

9.70

8.85

8.75

7.45

5.55

4.35

3.35

10.0

9.05

8.95

7.55

5.40

4.10

3.00

1000 400

1 MHz 175 215 320 500 855 225

400 kHz 89.5

120

100 kHz 42.5

75.5

225

180

405

360

760

715

130

1. Guaranteed by characterization results, unless otherwise specified.

10.5

9.35

7.90

5.75

4.40

3.25

575

3.40

2.50

1.50

0.95

0.65

0.50

0.40

420

340

320

10.5

9.15

9.10

7.65

5.50

4.20

3.05

455

3.25

2.30

1.35

0.80

0.50

0.35

0.25

285

185

145

3.70

2.75

1.75

1.25

0.95

0.80

0.65

11.0

9.70

8.30

6.10

4.75

3.60

11.5

10.5

9.00

6.80

5.40

4.25

880 1550

4.30

3.35

2.35

1.80

1.50

1.35

1.25

720 1350

620 1250

575 1200 mA

µA

Symbol

DD_ALL

(Run)

Table 30. Current consumption in Run modes, code with data processing running from Flash,

ART disable and power supplied by external SMPS (V

DD12

= 1.10 V)

Conditions

(1)

Parameter

TYP

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C

Uni t

Supply current in Run mode f

HCLK

= f

HSE

up to 48MHz included, bypass mode

PLL ON above 48 MHz all peripherals disable

80 MHz 3.18

3.20

72 MHz 2.88

2.89

64 MHz 2.84

2.86

48 MHz 2.37

2.39

32 MHz 1.71

1.73

24 MHz 1.29

1.31

16 MHz 0.93

0.95

8 MHz 0.47

0.50

4 MHz 0.28

0.29

2 MHz 0.16

0.17

1 MHz 0.11

0.12

100 kHz 0.06

0.07

3.25

3.34

2.95

3.02

2.91

3.00

2.44

2.53

1.78

1.85

1.37

1.44

0.99

1.06

0.54

0.60

0.33

0.40

0.22

0.29

0.16

0.23

0.11

0.18

2.00

1.56

1.20

0.75

3.49

3.18

3.15

2.68

0.54

0.43

0.37

0.32

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,

DD12

= 1.10 V

Table 31. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1

Conditions TYP MAX

(1)

Symbol Parameter

Voltage scaling f

HCLK

25 °C 55 °C 85 °C

105

°C

125

°C

25 °C 55 °C 85 °C

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode

Supply current in low-power run mode f

HCLK

48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable f

HCLK

= f

HSE

= f

MSI

up to

Range 2

Range 1 all peripherals disable

FLASH in power-down

26 MHz 2.40

2.40

2.55

2.70

3.05

2.70

2.75

2.90

3.20

3.80

16 MHz 1.50

1.55

1.65

1.80

2.15

1.70

1.80

1.95

2.25

2.80

8 MHz 0.820

0.850

0.950

1.10

1.45

0.95

1.00

1.15

1.45

2.00

4 MHz 0.470

0.500

0.600

0.765

1.10

0.55

0.60

0.75

1.05

1.60

2 MHz 0.295

0.325

0.420

0.585

0.915

0.35

0.40

0.55

0.85

1.40

1 MHz 0.210

0.235

0.330

0.495

0.825

0.25

0.30

0.45

0.75

1.30

100 kHz 0.130

0.155

0.250

0.415

0.750

0.15

0.25

0.35

0.65

1.25

80 MHz 8.55

8.60

8.75

8.95

9.35

9.55

9.65

9.85

10.5

11.0

72 MHz 7.70

7.80

7.90

8.15

8.50

8.60

8.70

8.90

9.25

9.95

64 MHz 6.90

6.95

7.10

7.30

7.70

7.75

7.95

8.35

9.00

48 MHz 5.15

5.20

5.30

5.55

5.90

5.75

5.85

6.05

6.40

7.05

32 MHz 3.45

3.50

3.65

3.85

4.25

3.90

4.00

4.20

4.50

5.15

24 MHz 2.65

2.70

2.80

3.00

3.40

3.00

3.05

3.25

3.55

4.20

16 MHz 1.80

1.85

1.95

2.15

2.55

2.05

2.10

2.30

2.60

3.25

2 MHz 220 255 360 540 895 270 330 460 760 1400

1 MHz 120 155 260 440 795 165 215 370 660 1300

400 kHz 60.0

92.0

100 kHz 36.0

62.5

195

165

375

345

730 100

695 63.0

160

130

330

305

585 1250

555 1200

1. Guaranteed by characterization results, unless otherwise specified.

105

°C

125

°C

Unit mA

µA

Symbol

Table 32. Current consumption in Run, code with data processing running from

SRAM1 and power supplied by external SMPS (V

DD12

= 1.10 V)

Conditions

(1)

Parameter

HCLK

TYP

25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(Run) Supply current in Run mode f

HCLK

= f

HSE

up to 48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

80 MHz 3.10

3.12

3.14

72 MHz 2.80

2.81

2.84

64 MHz 2.50

2.51

2.53

48 MHz 1.87

1.88

1.90

32 MHz 1.26

1.27

1.29

24 MHz 0.96

0.96

0.98

16 MHz 0.65

0.66

0.68

8 MHz 0.35

0.36

0.38

4 MHz 0.20

0.21

0.22

2 MHz 0.13

0.13

0.15

1 MHz 0.09

0.09

0.11

100 kHz 0.05

0.06

0.07

1.32

1.02

0.71

0.41

3.18

2.87

2.57

1.93

0.25

0.18

0.14

0.10

1.38

1.07

0.77

0.47

3.24

2.94

2.63

2.00

0.31

0.24

0.20

0.16

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,

DD12

= 1.10 V

Electrical characteristics STM32L452xx

Table 33. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF)

Conditions TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

Reduced code

(1)

Coremark

2.35

2.65

102 mA µA/MHz

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode f

HCLK

= f

HSE

up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable

Supply current in

Low-power run f

HCLK

= f

MSI

= 2 MHz all peripherals disable

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

Coremark

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

1. Reduced code used for characterization results provided in Table 27 ,

Coremark

Dhrystone 2.1

Fibonacci

While(1)

9.45

9.85

9.25

8.45

2.75

2.60

2.35

8.45

225

260

270

245

285 mA

µA

118

123

116

106

100

106

113

130

135

123

143

µA/MHz

Table 34. Typical current consumption in Run, with different codes running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

DD12

= 1.10 V)

Conditions

(1)

TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode PLL

ON above

48 MHz all peripherals disable

Reduced code

(2)

1.01

Coremark 1.14

Dhrystone 2.1

Fibonacci

1.19

1.12

While(1) 1.01

Reduced code

(2)

3.04

Coremark

Dhrystone 2.1

Fibonacci

While(1)

3.40

3.54

3.33

3.04

µA/MHz

110/221

DS11912 Rev 7

STM32L452xx Electrical characteristics

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:

SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.10 V

2. Reduced code used for characterization results provided in

Table 27 ,

Table 35. Typical current consumption in Run, with different codes running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

DD12

= 1.05 V)

Conditions

(1)

TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode PLL

ON above

48 MHz all peripherals disable

Reduced code

(2)

0.92

Coremark 1.04

Dhrystone 2.1

Fibonacci

1.08

1.02

While(1) 0.92

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:

SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.05 V

2. Reduced code used for characterization results provided in

DS11912 Rev 7

192

Electrical characteristics STM32L452xx

Table 36. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable

TYP Conditions TYP

Symbol Parameter

Voltage scaling

Code 25 °C

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode

Supply current in

Low-power run f f

HCLK

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

HCLK

= f

HSE

MSI

up to

= 2 MHz all peripherals disable

Reduced code

Coremark

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

Coremark

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

1. Reduced code used for characterization results provided in Table 27 ,

Coremark

Dhrystone 2.1

Fibonacci

While(1)

(1)

8.85

8.15

7.55

7.95

340

380

355

405

2.75

2.50

2.30

2.20

2. Reduced code used for characterization results provided in Table 27 ,

Unit mA mA

µA

25 °C

Unit

µA/MHz

170

190

178

111

102

178

203

106

84.6

Table 37. Typical current consumption in Run modes, with different codes running from

Flash, ART disable and power supplied by external SMPS (V

DD12

= 1.10 V)

Conditions

(1)

TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Reduced code

(2)

1.19

Coremark

Dhrystone 2.1

Fibonacci

1.08

0.99

While(1) 0.95

Reduced code

(2)

3.18

Coremark

Dhrystone 2.1

2.93

Fibonacci

While(1)

2.71

2.86

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.10 V

2. Reduced code used for characterization results provided in Table 27 ,

112/221

DS11912 Rev 7

STM32L452xx Electrical characteristics

Table 38. Typical current consumption in Run modes, with different codesrunning from

Flash, ART disable and power supplied by external SMPS (V

DD12

= 1.05 V)

Conditions (1) TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals

Reduced code

(2)

1.08

Coremark 0.98

Dhrystone 2.1

Fibonacci

While(1)

0.98

0.90

0.86

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.05 V

Table 39. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1

TYP Conditions TYP

Symbol Parameter

Voltage scaling

Code 25 °C

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode

Supply current in

Low-power run f f

HCLK

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

HCLK

= f

HSE

up to

= f

MSI

= 2 MHz all peripherals disable

Reduced code

(1)

Coremark

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

Coremark

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

1. Reduced code used for characterization results provided in Table 27 ,

Coremark

Dhrystone 2.1

Fibonacci

While(1)

2. Reduced code used for characterization results provided in Table 27 ,

7.80

8.75

220

190

215

200

210

2.40

2.20

2.35

2.20

2.30

8.55

7.75

8.45

Unit mA mA

µA

25 °C

Unit

µA/MHz

109

110

108

100

105

107

106

DS11912 Rev 7

113/221

192

Electrical characteristics STM32L452xx

Symbol

Table 40. Typical current consumption in Run, with different codesrunning from

SRAM1 and power supplied by external SMPS (V

DD12

= 1.10 V)

Conditions (1) TYP TYP

Parameter Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Reduced code

(2)

1.04

Coremark 0.95

Dhrystone 2.1

Fibonacci

1.01

0.95

While(1) 0.99

Reduced code

(2)

3.07

Coremark 2.79

Dhrystone 2.1

Fibonacci

While(1)

3.04

2.80

3.15

Unit

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.10 V

2. Reduced code used for characterization results provided in Table 27 ,

Symbol

Table 41. Typical current consumption in Run, with different codesrunning from

SRAM1 and power supplied by external SMPS (V

DD12

= 1.05 V)

Conditions

(1)

TYP TYP

Parameter Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Reduced code

(2)

0.94

Coremark

Dhrystone 2.1

Fibonacci

0.86

0.92

0.86

While(1) 0.90

Unit

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.05 V

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings .

114/221

DS11912 Rev 7

Symbol Parameter

Table 42. Current consumption in Sleep and Low-power sleep modes, Flash ON

Conditions

Voltage scaling f

HCLK

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(Sleep)

DD_ALL

(LPSleep)

Supply current in sleep mode, f

HCLK

= f

HSE

up to 48 MHz included, bypass mode pll ON above

48 MHz all peripherals disable

Range 2

Range 1

Supply current in low-power sleep mode f

HCLK

= f

MSI all peripherals disable

26 MHz 0.700 0.730 0.830

1.00

1.35

16 MHz 0.475 0.505 0.605

0.775

1.10

0.80

0.55

8 MHz 0.300 0.325 0.425

0.590

0.920

0.35

4 MHz 0.210 0.235 0.335

0.500

0.830

0.25

2 MHz 0.165 0.190 0.290

0.455

0.785

0.20

1 MHz 0.145 0.170 0.265

0.430

0.760

0.15

100 kHz 0.125 0.150 0.245

0.410

0.740

0.15

80 MHz 2.30

2.35

2.45

2.65

3.05

2.55

72 MHz 2.10

2.15

2.25

64 MHz 1.90

1.90

2.05

2.45

2.25

2.80

2.60

2.35

2.10

48 MHz 1.40

1.40

1.55

32 MHz 0.970

1.00

1.15

1.75

1.30

2.15

1.70

24 MHz 0.765 0.800 0.920

1.10

1.50

16 MHz 0.555 0.590 0.705

0.895

1.25

2 MHz 76.0

110 215 395 745

1.60

1.10

0.90

0.65

120

1 MHz 54.0

86.5

195 370 725 88.5

400 kHz 39.0

70.5

100 kHz 35.5

75.0

175

195

355

345

710

715

68.5

66.0

1. Guaranteed by characterization results, unless otherwise specified.

1.20

3.80

3.55

3.35

2.80

2.35

2.10

1.85

1250

1.90

1.65

1.45

1.35

1.25

1250

1200

0.65

3.15

2.90

2.70

2.15

1.70

1.45

1.20

610

1.30

1.05

0.85

0.75

0.70

0.65

585

570

560

0.35

2.85

2.60

2.35

1.85

1.40

1.15

0.90

355

1.05

0.80

0.60

0.45

0.40

335

320

305

0.20

2.65

2.40

2.20

1.65

1.20

0.95

0.75

185

0.90

0.65

0.45

0.30

0.25

160

140

130 mA

µA

Symbol

Table 43. Current consumption in Sleep, Flash ON and power supplied by external SMPS

DD12

= 1.10 V)

Conditions

(1)

Parameter

TYP

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C

DD_ALL

(Sleep) Supply current in sleep mode, f

HCLK

= f

HSE

up to 48 MHz included, bypass mode pll ON above

48 MHz all peripherals disable

80 MHz 0.83

0.84

72 MHz 0.75

0.77

64 MHz 0.68

0.68

48 MHz 0.50

0.50

32 MHz

24 MHz

16 MHz

0.35

0.28

0.20

0.36

0.29

0.21

0.88

0.81

0.74

0.56

0.41

0.33

0.25

0.95

0.88

0.81

0.63

0.47

0.40

0.32

8 MHz

4 MHz

2 MHz

1 MHz

0.13

0.14

0.09

0.10

0.07

0.08

0.06

0.07

0.18

0.14

0.13

0.11

0.25

0.22

0.20

0.19

0.40

0.36

0.34

0.33

100 kHz 0.05

0.06

0.11

0.18

0.32

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,

DD12

= 1.10 V

1.10

1.01

0.93

0.77

0.61

0.54

0.45

Unit mA

Symbol Parameter

Table 44. Current consumption in Low-power sleep modes, Flash in power-down

Conditions TYP MAX

(1)

Voltage scaling f

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(LPSleep)

Supply current in low-power sleep mode f

HCLK

= f

MSI all peripherals disable

2 MHz 76.5

105 220

1 MHz 54.0

81.0

195

400 kHz 28.0

64.5

175

100 kHz 21.5

55.0

170

1. Guaranteed by characterization results, unless otherwise specified.

410

385

370

360

740

715

695

690

110

81.5

60.5

58.5

175

155

130

120

350

325

305

300

600

570

555

550

1250

1200

µA

Symbol

DD_ALL

(Stop 2)

DD_ALL

(Stop 2 with

RTC)

Parameter

Supply current in

Stop 2 mode,

RTC disabled

Table 45. Current consumption in Stop 2 mode

Conditions

RTC clocked by LSI

Supply current in

Stop 2 mode,

RTC enabled

RTC clocked by LSE bypassed at 32768 Hz

RTC clocked by LSE quartz

(2) in low drive mode

TYP MAX

(1)

25 °C 55 °C 85 °C

1.8 V 2.05

5.40

19.0

2.4 V 2.10

5.45

19.0

3 V 2.05

5.55

19.5

3.6 V 2.05

5.65

20.0

1.8 V 2.30

5.65

19.0

2.4 V 2.35

5.80

19.5

3 V 2.50

5.90

20.0

3.6 V 2.60

6.15

20.5

1.8 V 2.60

6.05

21.0

2.4 V 2.55

6.20

21.0

3 V 2.80

6.35

21.5

3.6 V 2.85

6.60

22.5

1.8 V 2.40

5.70

19.0

2.4 V 2.50

5.85

19.5

3 V 2.60

6.00

20.0

3.6 V 2.65

6.25

20.5

105 °C 125 °C 25 °C

44.0

44.5

45.0

46.5

44.0

44.5

45.5

47.0

48.0

49.0

49.5

51.5

44.5

45.0

46.0

47.0

97.0

98.5

100

105

97.0

99.0

100

105

97.0

98.5

100

105

98.0

99.5

100

105

4.00

4.05

4.10

4.20

4.50

4.65

4.90

5.20

55 °C

11.5

12.0

12.5

13.0

85 °C 105 °C 125 °C

41.5

42.0

43.0

44.0

42.0

42.5

43.5

44.5

105

100

105

100

105

235

220

225

230

235

220

225

230

DD_ALL

(wakeup from

Stop 2)

Supply current during wakeup from Stop 2 mode

Wakeup clock is

MSI = 48 MHz, voltage Range 1.

See

(3)

Wakeup clock is

MSI = 4 MHz, voltage Range 2.

See

(3)

Wakeup clock is

HSI16 = 16 MHz, voltage Range 1.

See

(3)

3 V 1.85

3 V 1.50

3 V 1.55

Unit

µA

µA mA

1. Guaranteed based on test during characterization, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

Symbol

DD_ALL

(Stop 1)

DD_ALL

(Stop 1 with

RTC)

Parameter

Supply current in

Stop 1 mode,

RTC disabled

Supply current in stop

1 mode,

RTC enabled

RTC clocked by LSI

Table 46. Current consumption in Stop 1 mode

Conditions

RTC clocked by LSE bypassed, at 32768 Hz

RTC clocked by LSE quartz

(2) in low drive mode

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

1.8 V 9.85

29.0

100

2.4 V 9.85

29.5

100

3 V 9.90

29.5

100

3.6 V 10.0

28.0

105

1.8 V 10.5

29.5

100

2.4 V 10.5

29.5

100

3 V 10.5

30.0

105

3.6 V 10.5

30.0

105

1.8 V 10.0

29.5

100

2.4 V 10.0

29.5

100

3 V 10.5

30.0

105

3.6 V 11.0

30.5

105 230

1.8 V 10.0

29.0

99.5

220

2.4 V 10.0

29.0

99.5

220

3 V 10.0

29.0

100 220

3.6 V 10.5

29.5

100

230

225

230

225

430

435

410

430

435

440

435

440

435

440

17.0

17.5

17.0

17.5

55 °C

49.5

50.0

50.5

50.0

50.5

51.5

85 °C 105 °C 125 °C

185

190

185

190

405

395

400

405

395

400

860

850

860

840

845

855

Unit

µA

DD_ALL

(wakeup from Stop1)

Supply current during wakeup from

Stop 1

Wakeup clock MSI = 48 MHz, voltage Range 1.

See

(3)

Wakeup clock MSI = 4 MHz, voltage Range 2.

See

(3)

Wakeup clock HSI16 =

16 MHz, voltage Range 1.

See

(3)

3 V 1.15

3 V 1.20

1. Guaranteed based on test during characterization, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings .

Symbol

DD_ALL

(Stop 0)

Parameter

Supply current in

Stop 0 mode,

RTC disabled

Conditions

Table 47. Current consumption in Stop 0

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

1.8 V

2.4 V

3 V

3.6 V

125 150

125 155

240

245

390

395

400

645

650

655

145

150

155

190

195

200

350

355

360

365

600

605

1150

610 1150

615 1150

(2)

µA

1. Guaranteed by characterization results, unless otherwise specified.

2. Guaranteed by test in production.

Symbol

DD_ALL

(Standby)

DD_ALL

(Standby with RTC)

Parameter

Supply current in Standby mode (backup registers retained),

RTC disabled

Supply current in Standby mode (backup registers retained),

RTC enabled

with independent watchdog

Table 48. Current consumption in Standby mode

Conditions no independent watchdog

RTC clocked by LSI, no independent watchdog

RTC clocked by LSI, with independent watchdog

RTC clocked by LSE bypassed at 32768Hz

RTC clocked by LSE quartz

(2)

in low drive mode

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

1.8 V 100 270 1200 3300 8650 205

2.4 V 110 305 1400 3850 10000 225

55 °C

650

750

85 °C 105 °C 125 °C

3250

3750

9250 25000

11000 29000

3 V 125

3.6 V 160

1.8 V 265

2.4 V 335

360 1650 4550 12000 290

445 2000 5500 14500 355 1150 5250 15000 38500

435 1350 3450 8700

540 1650 4100 10500 -

950

4450 13000 33500

3 V 420

3.6 V 580

1.8 V 345

2.4 V 420

3 V 510

3.6 V 635

1.8 V 375

2.4 V 490

655 1950 4850 12500

895 2450 5950 14500

505 1400 3450 8600

720 1150 3750 9550 25000

620 1650 4050 10000 875 1450 4400 11500 29000

745 2000 4750 12000 1070 1700 5100 13500 34000

915 2450 5900 14500 1320 2100 6000 15500 39000

540 1450 3550 8800

690 1800 4250 10500

3 V 620 860 2150 5100 12500

3.6 V 845 1150 2700 6200 15000

1.8 V 395

2.4 V 500

3 V 625

3.6 V 795

1.8 V 375

2.4 V 460

550

665

1500

1750

3550

4250

8800

10500

3 V 565 810 2100 5050 12500

3.6 V 720 1000 2600 5900 15000

Unit nA nA nA

Symbol

DD_ALL

(SRAM2)

(3)

DD_ALL

(wakeup from

Standby)

Parameter

Supply current to be added in

Standby mode when SRAM2 is retained

Supply current during wakeup from Standby mode

See

(4)

Table 48. Current consumption in Standby mode (continued)

Conditions

MSI = 4 MHz.

Wakeup clock is

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

1.8 V 250

2.4 V 250

3 V 255

3.6 V 255

55 °C 85 °C 105 °C 125 °C

730 2700 6350 13850 575 1800 6350 14500 32000

740 2700 6150 14000 620 1800 6450 14500 32000

740

755

2700

2800

6450

6500

13500

645

790

1850

1950

6500

15000 32500

15000 33000

Unit nA

3 V 2.00

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. The supply current in Standby with SRAM2 mode is: I

+ RTC) + I

DD_ALL

(SRAM2).

DD_ALL

(Standby) + I

DD_ALL

(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: I

DD_ALL

(Standby

4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings .

Symbol

DD_ALL

(Shutdown)

Parameter

Supply current in Shutdown mode

(backup registers retained) RTC disabled

Table 49. Current consumption in Shutdown mode

Conditions TYP MAX

(1)

25 °C 55 °C 85 °C

1.8 V 19.0

120 720

105 °C 125 °C 25 °C

2200 6400 38.0

55 °C

350

85 °C 105 °C 125 °C

2050 6350 19500

2.4 V 26.0

145 855 2600 7450 62.0

3 V 37.0

185 1050 3100 8700 105

400

500

2400 7450 22500

2850 8750 26000

Unit nA

3.6 V 67.0

260 1350 3950 11000 160 650 3500 10500 30000

Symbol

DD_ALL

(Shutdown with RTC)

Parameter

Supply current in Shutdown mode

(backup registers retained) RTC enabled

Table 49. Current consumption in Shutdown mode (continued)

Conditions

RTC clocked by LSE bypassed at 32768 Hz

RTC clocked by LSE quartz

(2)

in low drive mode

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

1.8 V 165 275 950 2600 6550

2.4 V 235 370 1150 3100 7650

55 °C

85 °C 105 °C 125 °C

3 V 325 485 1450 3750 9050

3.6 V 445 655 1900 4800 11500

1.8 V 290 410 1050 2550 6700

2.4 V 375 515 1250 3050 7800

3 V 480 645 1550 3700 8800

3.6 V 625 840 1950 4950 11500

Unit nA

DD_ALL

(wakeup from

Shutdown)

Supply current during wakeup from Shutdown mode

Wakeup clock is

MSI = 4 MHz.

See

(3)

3 V 1.00

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings .

Symbol

DD_VBAT

(VBAT)

Parameter

Backup domain supply current

Table 50. Current consumption in VBAT mode

Conditions TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

RTC disabled

RTC enabled and clocked by LSE bypassed at 32768 Hz

BAT

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

3.00

4.00

5.00

11.0

145 165

205 235

285 315

375 430

285

370

470

715

550

670

820

1350

1. Guaranteed by characterization results, unless otherwise specified.

Electrical characteristics STM32L452xx

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 71: I/O static characteristics

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 51: Peripheral current consumption ), the I/Os used by an application also contribute

to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load

(internal or external) connected to the pin:

= V

DDIOx

×

C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

DDIOx

is the I/O supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

+ C

is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

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STM32L452xx Electrical characteristics

AHB

APB1

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 51 . The MCU is placed

under the following conditions:

• All I/O pins are in Analog mode

• The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

•

Ambient operating temperature and supply voltage conditions summarized in Table 20:

Voltage characteristics

• The power consumption of the digital part of the on-chip peripherals is given in

Table 51 . The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

Table 51. Peripheral current consumption

Range 1 Range 2 Peripheral

Bus Matrix

(1)

ADC independent clock domain

ADC clock domain

CRC

DMA1

DMA2

FLASH

GPIOA

(2)

GPIOB (2) )

GPIOC

(2)

GPIOD

(2)

GPIOE

(2)

GPIOH

(2)

QSPI

RNG independent clock domain

RNG clock domain

SRAM1

SRAM2

TSC

All AHB Peripherals

AHB to APB1 bridge (3)

CAN1

DAC1

1.7

1.6

1.7

1.8

1.7

0.6

3.2

0.4

2.1

0.4

1.4

1.5

6.2

7.0

2.2

0.5

0.8

1.0

1.6

25.2

0.9

4.1

2.4

1.4

1.3

1.5

1.6

0.6

2.9

0.1

1.9

0.2

1.3

5.2

5.8

N/A

0.9

0.8

1.3

21.7

0.7

3.2

1.8

Low-power run and sleep

1.6

1.7

1.6

0.5

3.1

0.2

1.9

0.3

1.4

5.8

7.3

N/A

0.7

0.8

1.3

23.6

0.9

3.9

2.2

Unit

µA/MHz

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192

Electrical characteristics

APB1

STM32L452xx

Table 51. Peripheral current consumption (continued)

Peripheral Range 1 Range 2

Low-power run and sleep

RTCA

CRS

USB FS independent clock domain

USB FS clock domain

I2C1 independent clock domain

I2C1 clock domain

I2C2 independent clock domain

I2C2 clock domain

I2C3 independent clock domain

I2C3 clock domain

LPUART1 independent clock domain

LPUART1 clock domain

LPTIM1 independent clock domain

LPTIM1 clock domain

LPTIM2 independent clock domain

LPTIM2 clock domain

OPAMP

PWR

SPI2

SPI3

TIM2

TIM6

USART2 independent clock domain

USART2 clock domain

USART3 independent clock domain

USART3 clock domain

WWDG

All APB1 on

1.7

0.3

2.9

3.5

1.1

2.9

0.9

2.3

3.5

1.1

1.9

0.6

2.9

0.8

3.1

0.8

0.4

1.8

1.7

6.2

1.0

4.1

1.3

4.3

1.5

0.5

51.5

1.1

0.3

N/A

1.6

0.6

2.4

0.4

2.7

0.7

0.2

0.1

1.6

1.3

5.0

0.6

N/A

2.8

0.9

3.0

0.7

2.3

0.4

3.6

0.9

3.5

1.1

0.5

35.5

2.1

0.6

N/A

0.8

0.4

1.6

5.9

0.9

N/A

3.4

1.0

3.4

0.9

2.5

0.8

1.8

0.6

2.8

0.7

3.9

3.8

1.1

4.2

1.3

0.5

48.6

Unit

µA/MHz

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APB2

Table 51. Peripheral current consumption (continued)

Peripheral Range 1 Range 2

Low-power run and sleep

AHB to APB2 (4)

SAI1 independent clock domain

SAI1 clock domain

SDMMC1 independent clock domain

SDMMC1 clock domain

SPI1

SYSCFG/VREFBUF/COMP

TIM1

TIM15

TIM16

USART1 independent clock domain

USART1 clock domain

All APB2 on

ALL

1.0

0.2

2.3

2.1

4.7

8.1

3.7

2.7

2.5

1.8

0.6

4.8

1.5

24.2

100.9

3.9

6.5

3.0

2.1

1.9

1.6

0.5

0.9

0.2

1.8

4.2

1.3

19.9

77.1

7.6

3.4

2.6

1.9

1.7

0.6

0.9

0.2

1.9

2.0

3.9

4.6

1.7

22.6

94.8

Unit

µA/MHz

1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).

2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).

3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1.

4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2.

6.3.6

Symbol

Wakeup time from low-power modes and voltage scaling transition times

The wakeup times given in Table 52 are the latency between the event and the execution of

the first user instruction.

The device goes in low-power mode after the WFE (Wait For Event) instruction.

Table 52. Low-power mode wakeup timings

(1)

Parameter Conditions Typ Max Unit t

WUSLEEP

Wakeup time from Sleep mode to Run mode

WULPSLEEP

Wakeup time from Lowpower sleep mode to Lowpower run mode

Wakeup in Flash with Flash in power-down during low-power sleep mode (SLEEP_PD=1 in FLASH_ACR) and with clock MSI = 2 MHz

Nb of

CPU cycles

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Electrical characteristics STM32L452xx

Symbol t

WUSTOP0 t

WUSTOP1

Table 52. Low-power mode wakeup timings (1) (continued)

Parameter

Wake up time from Stop 0 mode to Run mode in

Flash

Wake up time from Stop 0 mode to Run mode in

SRAM1

Wake up time from Stop 1 mode to Run in Flash

Wake up time from Stop 1 mode to Run mode in

SRAM1

Range 1

Range 2

Range 1

Range 2

Range 1

Range 2

Range 1

Range 2

Conditions Typ

Wakeup clock MSI = 48 MHz 3.34

Wakeup clock HSI16 = 16 MHz 3.7

Wakeup clock MSI = 24 MHz 3.8

Wakeup clock HSI16 = 16 MHz 3.7

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 48 MHz

9.3

1.85

Wakeup clock HSI16 = 16 MHz 2.68

Wakeup clock MSI = 24 MHz 2.47

Wakeup clock HSI16 = 16 MHz 2.68

Wakeup clock MSI = 4 MHz 9.67

12.5

Wakeup clock MSI = 48 MHz 6.75

Wakeup clock HSI16 = 16 MHz 7.14

7.6

Wakeup clock MSI = 24 MHz 7

Wakeup clock HSI16 = 16 MHz 7.14

Wakeup clock MSI = 4 MHz

7.82

7.9

10.44

11.9

Wakeup clock MSI = 48 MHz 5.21

Wakeup clock HSI16 = 16 MHz 6.23

Wakeup clock MSI = 24 MHz 5.73

5.9

6.9

6.4

Wakeup clock HSI16 = 16 MHz 6.23

Wakeup clock MSI = 4 MHz 10.9

6.9

12.3

7.1

2.7

3.4

4.3

6.5

7.1

6.5

Wake up time from Stop 1 mode to Low-power run mode in Flash

Wake up time from Stop 1 mode to Low-power run mode in SRAM1

Regulator in low-power mode (LPR=1 in PWR_CR1)

Wakeup clock MSI = 2 MHz

16.05

17.06

Max Unit

19.2

20.3

µs

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STM32L452xx Electrical characteristics

Symbol t

WUSTOP2 t

WUSTBY

Table 52. Low-power mode wakeup timings (1) (continued)

Parameter

Range 1

Wake up time from Stop 2 mode to Run mode in

Flash

Range 2

Range 1

Wake up time from Stop 2 mode to Run mode in

SRAM1

Range 2

Wakeup time from Standby mode to Run mode

Range 1

Conditions Typ Max Unit

Wakeup clock MSI = 48 MHz 7.93

Wakeup clock HSI16 = 16 MHz 7.32

Wakeup clock MSI = 24 MHz 8.25

Wakeup clock HSI16 = 16 MHz 7.32

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 48 MHz

11.43

13.3

5.23

Wakeup clock HSI16 = 16 MHz 6.33

Wakeup clock MSI = 24 MHz 5.78

7.1

6.5

9.1

8.5

9.4

8.4

Wakeup clock HSI16 = 16 MHz 6.33

Wakeup clock MSI = 4 MHz 11.37

7.1

12.9

Wakeup clock MSI = 8 MHz

Wakeup clock MSI = 4 MHz

16.13

24.06

18.2

26.6

Wakeup clock MSI = 8 MHz

Wakeup clock MSI = 4 MHz

16.09

18.2

24 26.6

µs

µs t

WUSTBY

SRAM2

Wakeup time from Standby with SRAM2 to Run mode t

WUSHDN

Wakeup time from

Shutdown mode to Run mode

1. Guaranteed by characterization results.

Range 1

Range 1 Wakeup clock MSI = 4 MHz 255.38 316.41

µs

Symbol

Table 53. Regulator modes transition times (1)

Parameter Conditions t

WULPRUN t

VOST

Wakeup time from Low-power run mode to

Run mode

(2)

Code run with MSI 2 MHz

Regulator transition time from Range 2 to

Range 1 or Range 1 to Range 2 (3)

Code run with MSI 24 MHz

1. Guaranteed by characterization results.

2. Time until REGLPF flag is cleared in PWR_SR2.

3. Time until VOSF flag is cleared in PWR_SR2.

Symbol

Table 54. Wakeup time using USART/LPUART

(1)

Parameter t t

WUUSART

WULPUART

Wakeup time needed to calculate the maximum USART/LPUART baudrate permitting to wakeup up from stop mode when USART/LPUART clock source is

HSI16

1. Guaranteed by design.

Conditions

Stop 0 mode

Stop 1 mode and Stop 2 mode

Typ

Max

1.7

8.5

Unit

µs

Unit

µs

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Electrical characteristics STM32L452xx

6.3.7 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14

. However,

Symbol f

HSE_ext

User external clock source frequency

HSEH

HSEL

Table 55. High-speed external user clock characteristics (1)

Parameter Conditions Min Typ

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage t w(HSEH) t w(HSEL)

OSC_IN high or low time

Voltage scaling

Range 1

Voltage scaling

Range 2

Voltage scaling

Range 1

Voltage scaling

Range 2

0.7 V

DDIOx

1. Guaranteed by design.

Max

DDIOx

0.3 V

DDIOx

Unit

MHz

V ns

Figure 21. High-speed external clock source AC timing diagram tw(HSEH)

VHSEH

VHSEL

90%

10% tr(HSE)

THSE tf(HSE) tw(HSEL) t

MS19214V2

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STM32L452xx Electrical characteristics

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14

. However,

Symbol

Table 56. Low-speed external user clock characteristics (1)

Parameter f

LSE_ext

LSEH

LSEL t w(LSEH) t w(LSEL)

User external clock source frequency

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

OSC32_IN high or low time

1. Guaranteed by design.

Conditions

Min

0.7 V

DDIOx

250

Typ

32.768

Max

1000

DDIOx

0.3 V

DDIOx

Unit kHz

V ns

Figure 22. Low-speed external clock source AC timing diagram tw(LSEH)

VLSEH

VLSEL

90%

10% tr(LSE)

TLSE tf(LSE) tw(LSEL) t

MS19215V2

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Electrical characteristics STM32L452xx

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 57 . In the

application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Symbol

Table 57. HSE oscillator characteristics (1)

Parameter Conditions

(2)

Min Typ Max Unit

I f

OSC_IN

DD(HSE)

Oscillator frequency

Feedback resistor

HSE current consumption

During startup

(3)

= 3 V,

Rm = 30 Ω,

CL = 10 pF@8 MHz

= 3 V,

Rm = 45 Ω,

CL = 10 pF@8 MHz

= 3 V,

Rm = 30 Ω,

CL = 5 pF@48 MHz

= 3 V,

Rm = 30 Ω,

CL = 10 pF@48 MHz

200

0.44

0.45

0.68

0.94

5.5

MHz kΩ mA

= 3 V,

Rm = 30 Ω,

CL = 20 pF@48 MHz

1.77

G m

Maximum critical crystal transconductance

Startup 1.5

mA/V t

SU(HSE)

(4)

Startup time V

is stabilized 2 ms

1. Guaranteed by design.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. This consumption level occurs during the first 2/3 of the t

SU(HSE) startup time

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 23

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

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STM32L452xx

Note:

Electrical characteristics

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 23. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

OSC_IN f

HSE

8 MHz resonator

EXT

(1) OSC_OUT

Bias controlled gain

MS19876V1

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 58 . In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 58. LSE oscillator characteristics (f

LSE

= 32.768 kHz)

(1)

Parameter Conditions

(2)

DD(LSE)

Gm critmax t

SU(LSE)

(3)

LSE current consumption

Maximum critical crystal gm

Startup time

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

is stabilized

Min Typ Max Unit

250

315

500

630

0.5

0.75

1.7

2.7

µA/V s

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192

Electrical characteristics STM32L452xx

1. Guaranteed by design.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 24. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

OSC32_IN f

LSE

32.768 kHz resonator

Drive programmable amplifier

OSC32_OUT

Note:

MS30253V2

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

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STM32L452xx Electrical characteristics

6.3.8 Internal clock source characteristics

The parameters given in

Table 59 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 23: General operating conditions

. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Symbol

Table 59. HSI16 oscillator characteristics (1)

Parameter Conditions

DuCy(HSI16)

(2)

∆

∆ t

Temp

VDD su t stab

DD f

HSI16

TRIM

(HSI16)

HSI16 Frequency

HSI16 user trimming step

=3.0 V, T

=30 °C

Trimming code is not a multiple of 64

Trimming code is a multiple of 64

Duty Cycle

HSI16 oscillator frequency drift over temperature

= 0 to 85 °C

= -40 to 125 °C

HSI16 oscillator frequency drift over V

HSI16 oscillator start-up time

=1.62 V to 3.6 V

HSI16 oscillator stabilization time

HSI16 oscillator power consumption

1. Guaranteed by characterization results.

2. Guaranteed by design.

Min

15.88

0.2

-4

-1

-2

-0.1

Typ

0.3

-6

0.8

155

Max Unit

16.08

MHz

0.4

-8

1.5

0.05

1.2

190

μs

μA

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Electrical characteristics STM32L452xx

MHz

16.4

16.3

16.2

16.1

15.9

15.8

15.7

15.6

-40 -20

Figure 25. HSI16 frequency versus temperature

+2%

+1.5%

+1%

0 min

-1%

-1.5%

-2%

40 mean

60 80 max

100 120 °C

MSv39299V1

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STM32L452xx Electrical characteristics

Symbol f

MSI

Multi-speed internal (MSI) RC oscillator

∆

TEMP

(MSI)

(2)

Table 60. MSI oscillator characteristics

(1)

Parameter Conditions Min

MSI frequency after factory calibration, done at V

=3 V and

=30 °C

MSI oscillator frequency drift over temperature

MSI mode

PLL mode

XTAL=

32.768 kHz

MSI mode

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

= -0 to 85 °C

= -40 to 125 °C

-3.5

7.896

15.79

23.69

31.58

47.38

98.7

197.4

394.8

789.6

0.987

1.974

3.948

-8

Typ

196.608

393.216

786.432

1.016

1.999

3.998

7.995

15.991

23.986

32.014

48.005

98.304

100

200

400

800

Max Unit

101.3

202.6

405.2

810.4

1.013

2.026

4.052

kHz

8.104

MHz

16.21

24.31

32.42

48.62

kHz

MHz

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Electrical characteristics

Symbol

Table 60. MSI oscillator characteristics (1) (continued)

Parameter Conditions

VDD

∆F

(MSI)

P_USB

(2)

MT_USB

CC jitter(MSI)

(6)

P jitter(MSI) t

∆

Jitter(MSI)

Jitter(MSI) t

(MSI)

STAB

(MSI)

MSI oscillator frequency drift over V

(reference is 3 V)

MSI mode

Range 0 to 3

Range 4 to 7

=1.62 V to 3.6 V

=2.4 V to 3.6 V

=1.62 V to 3.6 V

=2.4 V to 3.6 V

Range 8 to 11

=1.62 V to 3.6 V

=2.4 V to 3.6 V

Frequency variation in sampling mode

(3)

MSI mode

= -40 to 85 °C

= -40 to 125 °C

Period jitter for

USB clock

(4)

PLL mode

Range 11 for next transition for paired transition for next transition

Medium term jitter for USB clock

(5)

PLL mode

Range 11 for paired transition

RMS cycle-tocycle jitter

PLL mode Range 11

RMS Period jitter PLL mode Range 11

MSI oscillator start-up time

MSI oscillator stabilization time

Range 0

Range 1

Range 2

Range 3

Range 4 to 7

Range 8 to 11

PLL mode

Range 11

10 % of final frequency

5 % of final frequency

1 % of final frequency

Min

-1.2

-0.5

-2.5

-0.8

-5

-1.6

Typ

2.5

0.25

0.5

STM32L452xx

Max Unit

0.5

0.7

1.2

3.458

3.916

1 ns

0.5

ps ps us

1.25

2.5

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Symbol

Table 60. MSI oscillator characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit

(MSI)

MSI oscillator power consumption

MSI and

PLL mode

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

0.6

0.8

1.2

1.9

4.7

6.5

18.5

110

155

µA

1. Guaranteed by characterization results.

2. This is a deviation for an individual part once the initial frequency has been measured.

3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.

4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter of MSI @48 MHz clock.

5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles.

For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28 cycles.

For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over

56 cycles.

6. Guaranteed by design.

1.2

1.7

2.5

110

130

190

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Electrical characteristics STM32L452xx

Figure 26. Typical current consumption versus MSI frequency

High-speed internal 48 MHz (HSI48) RC oscillator

Symbol

Table 61. HSI48 oscillator characteristics

(1)

Parameter Conditions f

HSI48

TRIM

HSI48 Frequency

HSI48 user trimming step

USER TRIM

COVERAGE

HSI48 user trimming coverage

DuCy(HSI48) Duty Cycle

ACC

HSI48_REL

Accuracy of the HSI48 oscillator over temperature (factory calibrated)

VDD

(HSI48)

HSI48 oscillator frequency drift with V

I t su

(HSI48) HSI48 oscillator start-up time

(HSI48)

HSI48 oscillator power consumption

=3.0V, T

±32 steps

=30°C

= 3.0 V to 3.6 V,

= –15 to 85 °C

= 1.65 V to 3.6 V,

= –40 to 125 °C

= 3 V to 3.6 V

= 1.65 V to 3.6 V

Min

±3

(3)

Typ

0.11

(2)

±3.5

(3)

0.025

(3)

0.05

(3)

2.5

340

±4.5

(3)

0.05

(3)

0.1

(3)

380

Max Unit

0.18

MHz

±3

(3)

μs

μA

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Symbol

Table 61. HSI48 oscillator characteristics (1) (continued)

Parameter Conditions Min

jitter

Next transition jitter

Accumulated jitter on 28 cycles (4)

Paired transition jitter

Accumulated jitter on 56 cycles

(4)

1. V

= 3 V, T

= –40 to 125°C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Jitter measurement are performed without clock source activated in parallel.

Typ

+/-0.15

+/-0.25

Table 63 are derived from tests performed under temperature and

Max Unit

Figure 27. HSI48 frequency versus temperature

-2

-4

-6

-50 -30 -10

Avg

10 30 min

50 70 90 max

110 130

°C

MSv40989V1

Low-speed internal (LSI) RC oscillator

Symbol Parameter

Table 62. LSI oscillator characteristics (1)

Conditions Min f

LSI

LSI Frequency

= 3.0 V, T

= 30 °C

= 1.62 to 3.6 V, T

= -40 to 125 °C t t

STAB

(LSI)

(2)

LSI oscillator startup time

LSI oscillator stabilization time

LSI oscillator power consumption

1. Guaranteed by characterization results.

2. Guaranteed by design.

5% of final frequency

31.04

29.5

Typ

125

110

Max Unit

32.96

34 kHz

130 μs

180 μs

180 nA

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Electrical characteristics STM32L452xx

6.3.9 PLL characteristics

The parameters given in

supply voltage conditions summarized in

Table 23: General operating conditions .

Symbol f

PLL_IN f

PLL_P_OUT

PLL multiplier output clock P f

PLL_Q_OUT

PLL multiplier output clock Q f

PLL_R_OUT

PLL multiplier output clock R f

VCO_OUT t

LOCK

Jitter

(PLL)

Table 63. PLL, PLLSAI1 characteristics

(1)

Parameter

PLL input clock

(2)

Conditions

PLL input clock duty cycle

PLL VCO output

PLL lock time

RMS cycle-to-cycle jitter

RMS period jitter

PLL power consumption on

The test results are given in Table 66

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

System clock 80 MHz

VCO freq = 96 MHz

VCO freq = 192 MHz

VCO freq = 344 MHz

Min

3.0968

Typ Max Unit

40 -

30 -

200 260

300 380

520 650

16 MHz

MHz

344

MHz

128

40 μs

±ps

μA

1. Guaranteed by design.

2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the 2 PLLs.

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6.3.10 Flash memory characteristics

t t

Symbol t prog prog_row prog_page

Table 64. Flash memory characteristics (1)

Parameter

64-bit programming time one row (32 double word) programming time one page (2 Kbyte) programming time t

ERASE

Page (2 KB) erase time t prog_bank t

ME one bank (512 Kbyte) programming time

Mass erase time

(one or two banks)

Conditions

normal programming fast programming normal programming fast programming

normal programming fast programming

Average consumption from V

Maximum current (peak)

Write mode

Erase mode

Write mode

Erase mode

Typ

22.13

3.4

7 (for 2 μs)

7 (for 41 μs)

81.69

2.61

1.91

20.91

15.29

22.02

5.35

3.91

1. Guaranteed by design.

Symbol

Table 65. Flash memory endurance and data retention

Parameter Conditions

N t

END

RET

Endurance

Data retention

= –40 to +105 °C

1 kcycle

(2)

at T

= 85 °C

1 kcycle (2) at T

= 105 °C

1 kcycle

(2)

at T

= 125 °C

10 kcycles

(2)

at T

= 55 °C

10 kcycles

(2)

at T

= 85 °C

10 kcycles (2) at T

= 105 °C

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

Min

(1)

Unit kcycles

Years

Max Unit

90.76

µs

2.90

2.12

23.24

16.98

24.47

5.95

4.35

24.59

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Electrical characteristics STM32L452xx

6.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

and

A device reset allows normal operations to be resumed.

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

Table 66. EMS characteristics

Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

SS f

= 3.3 V, T

HCLK

= +25 °C,

= 80 MHz, conforming to IEC 61000-4-2 f

= 3.3 V, T

HCLK

= +25 °C,

= 80 MHz, conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

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Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 67. EMI characteristics

Symbol Parameter

EMI

Conditions

Monitored frequency band

Peak level

0.1 MHz to 30 MHz

= 3.6 V, T

= 25 °C,

LQFP100 package compliant with IEC

61967-2

30 MHz to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

EMI Level

Max vs.

HSE

HCLK

]

8 MHz/ 80 MHz

-8

2.5

Unit dBµV

6.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Symbol

Table 68. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value (1)

Unit

ESD(HBM)

Electrostatic discharge voltage (human body model)

ESD(CDM)

Electrostatic discharge voltage (charge device model)

= +25 °C, conforming to ANSI/ESDA/JEDEC

JS-001

= +25 °C, conforming to ANSI/ESD

STM5.3.1

1. Guaranteed by characterization results.

2000

250

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Electrical characteristics STM32L452xx

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.

• A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol

Parameter

Table 69. Electrical sensitivities

Conditions

Static latch-up class T

= +105 °C conforming to JESD78A

Class

6.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

DDIOx product operation. However, in order to give an indication of the robustness of the

(for standard, 3.3 V-capable I/O pins) should be avoided during normal microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

The characterization results are given in

Table 70 .

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

Symbol

Table 70. I/O current injection susceptibility (1)

Functional susceptibility

Description

Negative injection

Positive injection

Unit

INJ

Injected current on all pins except PA4, PA5, PE8, PE9,

PE10, PE11, PE12

Injected current on PE8, PE9, PE10, PE11, PE12

Injected current on PA4, PA5 pins

1. Guaranteed by characterization results.

2. Injection is not possible.

-5

-0

-5

N/A

(2)

N/A

Table 71 are derived from tests

0 mA

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6.3.14 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in

performed under the conditions summarized in Table 23: General operating conditions

. All

I/Os are designed as CMOS- and TTL-compliant.

Symbol

(1)

V hys

(3)

I lkg

Parameter

Table 71. I/O static characteristics

Conditions Min

I/O input low level voltage

I/O input high level voltage

1.62 V<V

1.08 V<V

1.62 V<V

DDIOx

<3.6 V

<1.62 V

<3.6 V 0.7xV

DDIOx

1. Refer to Figure 28: I/O input characteristics .

I/O input high level voltage

1.62 V<V

DDIOx

<3.6 V 0.49xV

DDIOX

+0.26

(3)

I/O input high level voltage

TT_xx, FT_xxx and

NRST I/O input hysteresis

1.08 V<V

1.62 V<V

DDIOx

<1.62 V 0.61xV

DDIOX

<3.6 V

FT_xx input leakage current

(3)(4)

≤

Max(V

DDXXX

)

(5)(6)

Max(V

DDXXX

Max(V

DDXXX

) ≤ V

)+1 V

≤

Max(V

≤ 5.5 V

)+1 V <

≤ Max(V

DDXXX

)

+0.05

(3)

Typ

200

Max

0.3xV

0.39xV

0.43xV

DDIOx

(2)

DDIOx

650

±100

200

(7)

±150

-0.06

-0.1

(3)(7)

(3)

Unit

V mV nA

FT_u and PC3 I/O

TT_xx input leakage current

Max(V

DDXXX

Max(V

DDXXX

) ≤ V

)+1 V

≤

Max(V

≤ 5.5 V

)+1 V <

≤ Max(V

DDXXX

) (7)

Max(V

3.6 V

) ≤ V

Weak pull-up equivalent resistor

(8)

= V

Weak pull-down equivalent resistor (8)

I/O pin capacitance

= V

DDIOx

2500

(3)

250

±150

2000

(3)

kΩ kΩ pF

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Electrical characteristics STM32L452xx

2. Tested in production.

3. Guaranteed by design.

4. All FT_xx IO except FT_u and PC3 I/O.

5. Max(V

DDXXX

) is the maximum value of all the I/O supplies.

6. To sustain a voltage higher than Min(V disabled.

, V

DDA

, V

DDUSB

) +0.3 V, the internal Pull-up and Pull-Down resistors must be

7. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:

Total_Ileak_max

= 10 µA + [number of IOs where V

is applied on the pad] ₓ I lkg

(Max).

8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 28 for standard I/Os, and in Figure 28

for

5 V tolerant I/Os.

Figure 28. I/O input characteristics

148/221

TTL requirement Vih min = 2V

min = 0

.7xV

DDIO x

DDIOx

+0.2

6 for V

DDIOx

>1.6

DDIOx

<1.62 or

0.49xV

Teste d in production CMOS requirement Vih on Vi h min = 0.

lation V il max

61xV

DDIOx

=0.43xV

DDIOx

+0.05

for 1.08<V

-0.1 for 1.08

<V DDIOx

<1.62 or 0.39xV

ax = 0.3xVdd

DDIOx

-0.06 for

DDIO x

>1.62

TTL requirement Vil max = 0.8V

Based on simu ction CMOS req uirement Vil m

Tested in produ

MSv37613V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed V

GPIOs PC13, PC14 and PC15 are supplied through the power switch, limiting source capability up to 3 mA only.

DS11912 Rev 7

STM32L452xx Electrical characteristics

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

• The sum of the currents sourced by all the I/Os on V

DDIOx, consumption of the MCU sourced on V

DD,

ΣI

VDD

(see Table 20: Voltage characteristics ).

plus the maximum cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

, plus the maximum consumption of the MCU sunk on V

, cannot exceed the absolute maximum rating ΣI

Table 20: Voltage characteristics

VSS

(see

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 23: General operating conditions . All I/Os are CMOS- and TTL-compliant (FT or TT

unless otherwise specified).

Symbol

Table 72. Output voltage characteristics (1)

Parameter Conditions Min Max Unit

(4)

Output low level voltage for an I/O pin CMOS port

Output high level voltage for an I/O pin

| = 8 mA

DDIOx

(2)

(3)

≥ 2.7 V

Output low level voltage for an I/O pin TTL port

Output high level voltage for an I/O pin

DDIOx

(2)

= 8 mA

(5)

≥ 2.7 V

Output low level voltage for an I/O pin PC13, PC14 and PC15

Output high level voltage for an I/O pin

| = 3 mA

DDIOx

≥ 2.7 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

= 20 mA

DDIOx

(5)

≥ 2.7 V

DDIOx

2.4

DDIOx

-0.4

-0.35

0.4

0.07

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

DDIOx

= 4 mA

Voltage characteristics

≥ 1.62 V

= 2 mA

1.62 V ≥ V

DDIOx

≥ 1.08 V

DDIOx

-1.3

-0.45

0.65ₓV

DDIOx

1.3

0.45

0.35ₓV

DDIOx

Output low level voltage for an FT I/O pin in FM+ mode (FT I/O with "f" option)

| = 20 mA

DDIOx

≥ 2.7 V

| = 10 mA

DDIOx

≥ 1.62 V

| = 2 mA

1.62 V ≥ V

DDIOx

≥ 1.08 V

0.4

1. The I

current sourced or sunk by the device must always respect the absolute maximum rating specified in

Table 20:

, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ΣI

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. PC13, PC14 and PC15 are tested/characterized at their maximum current of 3 mA.

4. Guaranteed by design.

5. Not applicable to PC13, PC14 and PC15.

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Electrical characteristics STM32L452xx

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 29

and

Table 73 , respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 23: General operating conditions

Speed Symbol

Table 73. I/O AC characteristics (1)(2)

Parameter Conditions

Fmax Maximum frequency

Tr/Tf Output rise and fall time

Fmax Maximum frequency

Tr/Tf Output rise and fall time

C=50 pF, 2.7 V≤V

DDIOx

≤3.6 V

C=50 pF, 1.62 V≤V

DDIOx

≤2.7 V

C=50 pF, 1.08 V≤V

DDIOx

≤1.62 V

C=10 pF, 2.7 V≤V

DDIOx

≤3.6 V

C=10 pF, 1.62 V≤V

DDIOx

≤2.7 V

C=10 pF, 1.08 V≤V

DDIOx

≤1.62 V

C=50 pF, 2.7 V≤V

DDIOx

≤3.6 V

C=50 pF, 1.62 V≤V

DDIOx

≤2.7 V

C=50 pF, 1.08 V≤V

DDIOx

≤1.62 V

C=10 pF, 2.7 V≤V

DDIOx

≤3.6 V

C=10 pF, 1.62 V≤V

DDIOx

≤2.7 V

C=10 pF, 1.08 V≤V

DDIOx

≤1.62 V

C=50 pF, 2.7 V≤V

DDIOx

≤3.6 V

C=50 pF, 1.62 V≤V

DDIOx

≤2.7 V

C=50 pF, 1.08 V≤V

DDIOx

≤1.62 V

C=10 pF, 2.7 V≤V

DDIOx

≤3.6 V

C=10 pF, 1.62 V≤V

DDIOx

≤2.7 V

C=10 pF, 1.08 V≤V

DDIOx

≤1.62 V

C=50 pF, 2.7 V≤V

DDIOx

≤3.6 V

C=50 pF, 1.62 V≤V

DDIOx

≤2.7 V

C=50 pF, 1.08 V≤V

DDIOx

≤1.62 V

C=10 pF, 2.7 V≤V

DDIOx

≤3.6 V

C=10 pF, 1.62 V≤V

DDIOx

≤2.7 V

C=10 pF, 1.08 V≤V

DDIOx

≤1.62 V

Unit

MHz ns

Min

Max

140

110

0.1

1.5

0.1

4.5

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Speed Symbol

Table 73. I/O AC characteristics (1)(2) (continued)

Parameter Conditions Min Max Unit

Fmax

Tr/Tf

Fmax

Tr/Tf

Maximum frequency

Output rise and fall time

Maximum frequency

Output rise and fall time

C=50 pF, 2.7 V≤V

C=10 pF, 2.7 V≤V

C=50 pF, 2.7 V≤V

C=10 pF, 2.7 V≤V

C=30 pF, 2.7 V≤V

C=10 pF, 2.7 V≤V

C=30 pF, 2.7 V≤V

DDIOx

C=50 pF, 1.62 V≤V

C=50 pF, 1.08 V≤V

DDIOx

C=10 pF, 1.62 V≤V

C=10 pF, 1.08 V≤V

DDIOx

C=50 pF, 1.62 V≤V

C=50 pF, 1.08 V≤V

DDIOx

C=10 pF, 1.62 V≤V

C=10 pF, 1.08 V≤V

DDIOx

C=30 pF, 1.62 V≤V

C=30 pF, 1.08 V≤V

DDIOx

C=10 pF, 1.62 V≤V

C=10 pF, 1.08 V≤V

DDIOx

C=30 pF, 1.62 V≤V

C=30 pF, 1.08 V≤V

≤3.6 V

DDIOx

≤3.6 V

DDIOx

≤3.6 V

DDIOx

≤3.6 V

DDIOx

≤3.6 V

DDIOx

≤3.6 V

DDIOx

≤3.6 V

DDIOx

≤2.7 V

≤1.62 V

≤2.7 V

≤1.62 V

≤2.7 V

≤1.62 V

≤2.7 V

≤1.62 V

≤2.7 V

≤1.62 V

≤2.7 V

≤1.62 V

≤2.7 V

≤1.62 V

100

(3)

37.5

5.8

2.5

3.3

MHz ns

Fm+

Fmax Maximum frequency

Tf Output fall time

(4)

C=50 pF, 1.6 V≤V

DDIOx

≤3.6 V

MHz ns

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.

Refer to the RM0394 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.

4. The fall time is defined between 70% and 30% of the output waveform accordingly to I 2 C specification.

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Electrical characteristics

Figure 29. I/O AC characteristics definition

(1)

90% 10%

50% 50%

10% 90% t r(IO)out t f(IO)out

STM32L452xx when loaded by the specified capacitance.

MS32132V2

1. Refer to Table 73: I/O AC characteristics .

6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, R

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 23: General operating conditions .

Symbol Parameter

Table 74. NRST pin characteristics (1)

Conditions Min Typ Max Unit

IL(NRST)

IH(NRST)

V hys(NRST)

F(NRST)

NF(NRST)

NRST input low level voltage

NRST input high level voltage

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

= V

NRST input filtered pulse

NRST input not filtered pulse

1.71 V ≤ V

≤ 3.6 V

0.7ₓV

DDIOx

350

200

0.3ₓV

DDIOx

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order)

V mV kΩ ns ns

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Figure 30. Recommended NRST pin protection

External reset circuit

(1)

0.1 μF

NRST

(2)

Filter

Internal reset

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

Table 74: NRST pin characteristics

. Otherwise the reset is not taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

6.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is detected by the event controller.

Symbol

Table 75. EXTI Input Characteristics (1)

Parameter

PLEC

Pulse length to event controller

1. Guaranteed by design.

Conditions

Min

Typ

Max

Unit ns

6.3.17 Analog switches booster

Symbol

Table 76. Analog switches booster characteristics (1)

Parameter

DD t

SU(BOOST)

Supply voltage

Booster startup time

DD(BOOST)

Booster consumption for

1.62 V ≤ V

≤ 2.0 V

Booster consumption for

2.0 V ≤ V

≤ 2.7 V

Booster consumption for

2.7 V ≤ V

≤ 3 .6 V

1. Guaranteed by design.

Min

1.62

Typ

Max

3.6

240

250

500

900

Unit

µs

µA

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Electrical characteristics STM32L452xx

6.3.18 Analog-to-Digital converter characteristics

Note:

Unless otherwise specified, the parameters given in Table 77

are preliminary values derived from tests performed under ambient temperature, f

PCLK frequency and V

conditions summarized in Table 23: General operating conditions

DDA

supply voltage

It is recommended to perform a calibration after each power-up.

Symbol

DDA

REF+

REFf

ADC f s f

TRIG

CMIN

AIN

(3)

AIN

ADC

Parameter

Table 77. ADC characteristics

(1) (2)

Conditions Min

Analog supply voltage

Positive reference voltage

DDA

≥ 2 V

DDA

< 2 V

Negative reference voltage

Range 1

ADC clock frequency

Sampling rate for FAST channels

Range 2

Resolution = 12 bits

Resolution = 10 bits

Resolution = 8 bits

Resolution = 6 bits

Resolution = 12 bits

Resolution = 10 bits

Sampling rate for SLOW channels

Resolution = 8 bits

Resolution = 6 bits

External trigger frequency f

ADC

= 80 MHz

Resolution = 12 bits

1.62

Input common mode Differential mode

0.14

Typ

DDA

SSA

Max

3.6

DDA

7.27

8.88

4.21

4.71

5.33

6.15

5.33

6.15

5.33

REF+

REF-

- 0.18

)/2

REF+

REF-

)/2

REF+

REF-

+ 0.18

)/2

Conversion voltage range(2)

External input impedance

Internal sample and hold capacitor

REF+

Unit

MHz

Msps

MHz

1/f

ADC

V kΩ pF t

STAB t

CAL

Power-up time

Calibration time

ADC

= 80 MHz

1.45

116 conversion cycle

µs

1/f

ADC

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Symbol

Table 77. ADC characteristics (1) (2) (continued)

Parameter Conditions Min Typ Max Unit t t t

LATR

LATRINJ t s

ADCVREG_STUP

Trigger conversion latency Regular and injected channels without conversion abort

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

Trigger conversion latency Injected channels aborting a regular conversion

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

Sampling time f

ADC

= 80 MHz

ADC voltage regulator start-up time

ADC

= 80 MHz

Resolution = 12 bits

Total conversion time

(including sampling time)

Resolution = 12 bits

1.5

2.5

0.03125

2.5

0.1875

2.5

2.0

2.25

2.125

3.5

3.0

3.25

3.125

8.00625

640.5

8.1625

1/f

ADC

µs

ADC

µs

I t

CONV

DDA

(ADC)

DDV_S

DDV_D

(ADC)

ADC consumption from the V

DDA

supply

ADC consumption from the V

REF+ mode

ADC consumption from the V

REF+ mode

single ended

differential fs = 5 Msps fs = 1 Msps fs = 10 ksps fs = 5 Msps fs = 1 Msps fs = 10 ksps fs = 5 Msps fs = 1 Msps fs = 10 ksps ts + 12.5 cycles for successive approximation

= 15 to 653

730 830

160

130

0.6

260

1.3

220

160

310

1/f

ADC

µA

1. Guaranteed by design

2. The I/O analog switch voltage booster is enable when V

DDA

< 2.4V). It is disable when V

DDA

≥ 2.4 V.

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

REF+

can be internally connected to V

DDA

and V

Section 4: Pinouts and pin description

REF-

can be internally connected to V

for further details.

SSA

, depending on the package.

The maximum value of R

AIN

can be found in Table 78: Maximum ADC RAIN .

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Electrical characteristics

Resolution

12 bits

10 bits

8 bits

6 bits

1. Guaranteed by design.

STM32L452xx

8006.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

8006.75

31.25

81.25

156.25

8006.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

306.25

593.75

1156.25

3093.75

8006.75

Table 78. Maximum ADC R

AIN

(1)(2)

Sampling cycle

@80 MHz

Sampling time [ns]

@80 MHz

AIN

max (Ω)

Fast channels

(3)

Slow channels

(4)

92.5

247.5

640.5

2.5

6.5

12.5

640.5

2.5

6.5

12.5

24.5

47.5

24.5

47.5

92.5

247.5

640.5

2.5

6.5

12.5

24.5

47.5

92.5

247.5

2.5

6.5

12.5

24.5

47.5

92.5

247.5

6800

15000

50000

220

560

1200

47000

180

470

1000

1800

2700

39000

120

390

820

1500

2200

5600

12000

100

330

680

1500

2200

4700

12000

2700

3900

8200

18000

50000

5600

12000

50000

N/A

330

1000

39000

N/A

270

680

1500

2200

33000

N/A

180

560

1200

1800

4700

10000

N/A

100

470

1200

1800

3900

10000

2200

3300

6800

15000

50000

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2. The I/O analog switch voltage booster is enable when V

DDA

< 2.4V). It is disable when V

DDA

≥ 2.4 V.

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

3. Fast channels are: PC0, PC1, PC2, PC3, PA0, PA1.

4. Slow channels are: all ADC inputs except the fast channels.

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Table 79. ADC accuracy - limited test conditions 1 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

Integral linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

DDA

= VREF+ = 3 V,

TA = 25 °C

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

1.5

2.5

1.5

2.5

1 2

Slow channel (max speed) 1 2

Fast channel (max speed) 10.4 10.5

Slow channel (max speed) 10.4 10.5

Fast channel (max speed) 10.8 10.9

Slow channel (max speed) 10.8 10.9

Fast channel (max speed) 64.4 65 -

Slow channel (max speed) 64.4 65

Fast channel (max speed) 66.8 67.4

Slow channel (max speed) 66.8 67.4

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 67 68

Slow channel (max speed) 67 68

4 5

3.5

4.5

3.5

4.5

1 2.5

1.5

2.5

1.5

2.5

4.5

2.5

4.5

2.5

3.5

2.5

3.5

1 1.5

LSB bits dB

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Table 79. ADC accuracy - limited test conditions 1 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

DDA

= V

REF+

= 3 V,

TA = 25 °C

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-74 -73

-79 -76

-79 -76 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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Electrical characteristics STM32L452xx

Table 80. ADC accuracy - limited test conditions 2 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ V

DDA Integral linearity error

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

1.5

3.5

1.5

3.5

1 3

Slow channel (max speed) 1 2.5

Fast channel (max speed) 10 10.5

Slow channel (max speed) 10 10.5

Fast channel (max speed) 10.7 10.9

Slow channel (max speed) 10.7 10.9

Fast channel (max speed) 62 65 -

Slow channel (max speed) 62 65

Fast channel (max speed) 66 67.4

Slow channel (max speed) 66 67.4

Fast channel (max speed) 64 66

Slow channel (max speed) 64 66

Fast channel (max speed) 66.5 68

Slow channel (max speed) 66.5 68

4 6.5

3.5

5.5

3.5

5.5

1 4.5

1 5

1.5

2.5

3.5

2.5

3.5

1 1.5

LSB bits dB

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Table 80. ADC accuracy - limited test conditions 2 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ V

DDA

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-74 -65

-74 -67

-79 -70

-79 -71 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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Electrical characteristics STM32L452xx

Table 81. ADC accuracy - limited test conditions 3 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

Integral linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ V

DDA

3.6 V,

= V

REF+

≤

Voltage scaling Range 1

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1.2

1.5

1 1.2

3 3.5

2.5

3.5

2 2.5

Slow channel (max speed) 2 2.5

Fast channel (max speed) 10 10.4

Slow channel (max speed) 10 10.4

Fast channel (max speed) 10.6 10.7

Slow channel (max speed) 10.6 10.7

Fast channel (max speed) 62 64 -

Slow channel (max speed) 62 64

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 63 65

Slow channel (max speed) 63 65

Fast channel (max speed) 66 67

Slow channel (max speed) 66 67

5.5

7.5

4.5

6.5

4.5

7.5

4.5

5.5

2 5

2.5

2 3.5

2.5

4.5

3.5

1.2

1.5

LSB bits dB

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Table 81. ADC accuracy - limited test conditions 3 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ V

DDA

3.6 V,

= V

REF+

≤

Voltage scaling Range 1

Single ended

Differential

Fast channel (max speed)

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-69 -67

-71 -67

-72 -71

-72 -71 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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Electrical characteristics STM32L452xx

Table 82. ADC accuracy - limited test conditions 4 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

ADC clock frequency ≤

26 MHz,

1.65 V ≤ V

DDA

3.6 V,

= VREF+ ≤

Voltage scaling Range 2

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

2.5

2 2.5

Slow channel (max speed) 2 2.5

Fast channel (max speed) 10.2 10.5

Slow channel (max speed) 10.2 10.5

Fast channel (max speed) 10.6 10.7

Slow channel (max speed) 10.6 10.7

Fast channel (max speed) 63 65 -

Slow channel (max speed) 63 65

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 64 65

Slow channel (max speed) 64 65

Fast channel (max speed) 66 67

Slow channel (max speed) 66 67

5 5.4

3.5

4.5

2 4

2 3.5

4 4.5

1 1.5

LSB bits dB

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Table 82. ADC accuracy - limited test conditions 4 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

26 MHz,

1.65 V ≤ V

DDA

3.6 V,

= VREF+ ≤

Voltage scaling Range 2

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-71 -69

-73 -72

-73 -72 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

Figure 31. ADC accuracy characteristics

SSA

4095

4094

4093

1 LSB

IDEAL

1 2 3 4 5 6

(2)

(3)

(1)

4093 4094 4095 4096

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

= total unajusted error : maximum deviation

between the actual and ideal transfer curves.

= offset error : maximum deviation

between the first actual transition and

the first ideal one.

= gain error : deviation between the last

ideal transition and the last actual one.

= differential linearity error : maximum

deviation between actual steps and the ideal ones.

= integral linearity error : maximum deviation

between any actual transition and the end point

correlation line.

DDA

MS19880V2

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Electrical characteristics STM32L452xx

Figure 32. Typical connection diagram using the ADC

DDA

AINx

C parasitic

(2)

I lkg

(3)

Sample and hold ADC converter

ADC

12-bit converter

ADC

AIN

(1)

MS33900V5

1. Refer to Table 77: ADC characteristics

for the values of R

AIN

and C

ADC

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

Table 71: I/O static characteristics for the value of the pad capacitance). A high

C parasitic

value downgrades conversion accuracy. To remedy this, f

ADC

should be reduced.

3. Refer to Table 71: I/O static characteristics for the values of Ilkg.

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 18: Power supply scheme

. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

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6.3.19 Digital-to-Analog converter characteristics

Symbol

DDA

REF+

REF-

BON

BOFF

Parameter

Table 83. DAC characteristics (1)

Conditions

Analog supply voltage for

DAC ON

DAC output buffer OFF (no resistive load on DAC1_OUT1 pin or internal connection)

Other modes

Min

1.71

1.80

Positive reference voltage

DAC output buffer OFF (no resistive load on DAC1_OUT1 pin or internal connection)

Other modes

1.71

1.80

Negative reference voltage

Resistive load

Output Impedance

Capacitive load

DAC output buffer ON connected to V

SSA connected to V

DDA

DAC output buffer OFF

Output impedance sample and hold mode, output buffer ON

= 2.7 V

= 2.0 V

Output impedance sample and hold mode, output buffer OFF

= 2.7 V

= 2.0 V

DAC output buffer ON

Sample and hold mode

9.6

DAC_OUT t

SETTLING t

WAKEUP

(2)

PSRR

Voltage on DAC1_OUT1 output

DAC output buffer ON

DAC output buffer OFF

Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when DAC1_OUT1 reaches final value

±0.5LSB, ±1 LSB, ±2 LSB,

±4 LSB, ±8 LSB)

Normal mode

DAC output buffer ON

CL ≤ 50 pF,

RL ≥ 5 kΩ

±0.5 LSB

±1 LSB

±2 LSB

±4 LSB

±8 LSB

Normal mode DAC output buffer

OFF, ±1LSB, CL = 10 pF

Wakeup time from off state

(setting the ENx bit in the

DAC Control register) until final value ±1 LSB

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

Normal mode DAC output buffer

OFF, CL ≤ 10 pF

DDA

supply rejection ratio

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL = 5 kΩ, DC

0.2

Electrical characteristics

Typ Max Unit

3.6

DDA

13.8

3.5

16.5

18.0

REF+

– 0.2

REF+

2.9

2.85

2.8

2.75

2.5

kΩ kΩ kΩ kΩ pF

µF

µs

1.7

1.6

1.55

1.48

1.4

SSA

11.7

0.1

4.2

-80

7.5

-28

µs dB

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Electrical characteristics STM32L452xx

Symbol

W_to_W t

SAMP

I leak

CI int t

TRIM

V offset

DDA

(DAC)

Table 83. DAC characteristics (1) (continued)

Parameter Conditions Min

Minimal time between two consecutive writes into the

DAC_DORx register to guarantee a correct

DAC1_OUT1 for a small variation of the input code

(1 LSB)

DAC_MCR:MODEx[2:0] =

000 or 001

DAC_MCR:MODEx[2:0] =

010 or 011

CL ≤ 50 pF, RL ≥ 5 kΩ

CL ≤ 10 pF

Sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when

DAC1_OUT1 reaches final value ±1LSB)

DAC1_OUT1 pin connected

DAC1_OUT1 pin not connected

(internal connection only)

Output leakage current

DAC output buffer

ON, C

DAC output buffer

OFF, C

= 100 nF

DAC output buffer

OFF

Sample and hold mode,

DAC1_OUT1 pin connected

Internal sample and hold capacitor

Middle code offset trim time

DAC output buffer ON

Middle code offset for 1 trim code step

REF+

= 3.6 V

REF+

= 1.8 V

DAC consumption from

DDA

DAC output buffer ON

DAC output buffer OFF

No load, middle code (0x800)

No load, worst code

(0xF1C)

No load, middle code (0x800)

1.4

5.2

Sample and hold mode, C

100 nF

Typ

0.7

10.5

1500

750

315

450

Max

3.5

(3)

8.8

500

670

Unit

µs ms

µs nA pF

µs

µV

0.2

315 ₓ

Ton/(Ton

+Toff)

(4)

670 ₓ

Ton/(Ton

+Toff)

µA

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STM32L452xx Electrical characteristics

Symbol

DDV

(DAC)

Table 83. DAC characteristics (1) (continued)

Parameter Conditions Min

DAC output buffer ON

DAC output buffer OFF

No load, middle code (0x800)

No load, worst code

(0xF1C)

No load, middle code (0x800)

DAC consumption from

REF+

Sample and hold mode, buffer ON,

= 100 nF, worst case

Typ

185

340

155

Max

240

400

205

Unit

185 ₓ

Ton/(Ton

+Toff)

400 ₓ

Ton/(Ton

+Toff)

µA

Sample and hold mode, buffer OFF,

= 100 nF, worst case

155 ₓ

Ton/(Ton

+Toff)

205 ₓ

Ton/(Ton

+Toff)

3. Refer to Table 71: I/O static characteristics .

1. Guaranteed by design.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0394 reference manual for more details.

Figure 33. 12-bit buffered / non-buffered DAC

Buffered/non-buffered DAC

Buffer

(1)

LOAD

12-bit digital to analog converter

DACx_OUT

LOAD ai17157d

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

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192

Electrical characteristics

Symbol

DNL

INL

Parameter

Table 84. DAC accuracy (1)

Conditions

Differential non linearity

(2) monotonicity

Integral non linearity

(3)

DAC output buffer ON

DAC output buffer OFF

10 bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

DAC output buffer OFF

CL ≤ 50 pF, no RL

Offset

Offset1

Offset error at code 0x800

(3)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

Offset error at code 0x001

(4)

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer OFF

CL ≤ 50 pF, no RL

REF+

= 3.6 V

= 1.8 V

OffsetCal

Gain

TUE

TUECal

SNR

THD

Offset Error at code 0x800 after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

REF+

= 3.6 V

REF+

= 1.8 V

Gain error

Total unadjusted error

(5)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

DAC output buffer OFF

CL ≤ 50 pF, no RL

Total unadjusted error after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

Signal-to-noise ratio

Total harmonic distortion

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

1 kHz, BW 500 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

BW 500 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

STM32L452xx

Min

Typ

guaranteed

Max

±2

±4

±5

±7

±0.5

±30

±12

±25

±8

±5

Unit

LSB

71.2

71.6

-78

-79

±23 LSB

dB dB

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Symbol Parameter

Table 84. DAC accuracy (1) (continued)

Conditions Min Typ Max Unit

SINAD

ENOB

Signal-to-noise and distortion ratio

Effective number of bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

70.4

11.4

11.5

dB bits

1. Guaranteed by design.

2. Difference between two consecutive codes - 1 LSB.

3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

4. Difference between the value measured at Code (0x001) and the ideal value.

5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (V

REF+

– 0.2) V when buffer is ON.

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Electrical characteristics STM32L452xx

6.3.20 Voltage reference buffer characteristics

Symbol

DDA

REFBUF_

OUT

TRIM

CL esr

I load

I line_reg

I load_reg

Parameter

Table 85. VREFBUF characteristics (1)

Conditions

Analog supply voltage

Voltage reference output

Normal mode

Degraded mode

(2)

Normal mode

Degraded mode

(2)

= 0

= 1

= 0

= 1

= 0

= 1

= 0

= 1

Trim step resolution

Load capacitor

Equivalent

Serial Resistor of Cload

Static load current

Line regulation 2.8 V ≤ V

DDA

≤ 3.6 V

I load

= 500 µA

I load

= 4 mA

Load regulation

500 μA ≤ I load

≤4 mA Normal mode

Min

0.5

2.4

2.8

1.65

2.046

(3)

2.498

(3)

DDA

-150 mV

DDA

-150 mV

200

100

Typ Max

3.6

2.4

2.8

2.048

2.049

(3)

2.5

2.502

(3)

DDA

±0.05

±0.1

1 1.5

Coeff

PSRR t

START

INRUSH

Temperature coefficient

-40 °C < T

< +125 °C

0 °C < T

< +50 °C

Power supply rejection

Start-up time

100 kHz

CL = 0.5 µF

(4)

CL = 1.1 µF

(4)

CL = 1.5 µF

(4)

Control of maximum DC current drive on VREFBUF_

OUT during start-up phase

(5)

300

500

650

µF

4 mA

1000

500

500 ppm/V ppm/mA

T coeff_ vrefint +

T coeff_ vrefint

350

650

800 ppm/ °C dB

µs

Unit

Ω mA

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Symbol Parameter

Table 85. VREFBUF characteristics (1) (continued)

Conditions Min Typ Max Unit

DDA

(VREF

BUF)

VREFBUF consumption from V

DDA

I load

= 0 µA

I load

= 500 µA

I load

= 4 mA -

µA

1. Guaranteed by design, unless otherwise specified.

2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which follows (V voltage).

DDA

- drop

3. Guaranteed by test in production.

4. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.

5. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the V the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for V

= 0 and V

= 1.

DDA

voltage should be in

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192

Electrical characteristics

6.3.21 Comparator characteristics

Symbol Parameter

Table 86. COMP characteristics (1)

Conditions

DDA

Analog supply voltage

Comparator input voltage range

Scaler input voltage

(2)

Scaler offset voltage

BRG_EN=0 (bridge disable)

DDA

(SCALER)

Scaler static consumption from V

DDA t

START_SCALER

Scaler startup time t

START t

(3)

BRG_EN=1 (bridge enable)

Comparator startup time to reach propagation delay specification

High-speed mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Medium mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Ultra-low-power mode

Propagation delay with

100 mV overdrive

High-speed mode

Medium mode

DDA

≥ 2.7 V

DDA

< 2.7 V

V offset

V hys

Comparator offset error

Comparator hysteresis

Ultra-low-power mode

Full common mode range

No hysteresis

Low hysteresis

Medium hysteresis

High hysteresis

STM32L452xx

Min Typ Max Unit

1.62

3.6

0 V

DDA

0.55

0.8

100

REFINT

±5

200

±10

300

200

100

0.9

µs ns

µs mV nA

µA

µs

±5

±20

mV mV

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STM32L452xx Electrical characteristics

Symbol

DDA

(COMP)

Table 86. COMP characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit

400 600

Ultra-lowpower mode

Comparator consumption from V

DDA

Medium mode

High-speed mode

Static

With 50 kHz

±100 mV overdrive square signal

Static

With 50 kHz

±100 mV overdrive square signal

Static

With 50 kHz

±100 mV overdrive square signal

1200

100 nA

µA

I bias

Comparator input bias current

1. Guaranteed by design, unless otherwise specified.

2. Refer to Table 26: Embedded internal voltage reference

3. Guaranteed by characterization results.

4. Mostly I/O leakage when used in analog mode. Refer to I lkg

parameter in Table 71: I/O static characteristics .

(4) nA

6.3.22 Operational amplifiers characteristics

Symbol

DDA

CMIR

OFFSET

∆VI

OFFSET

Parameter

Table 87. OPAMP characteristics (1)

Conditions

Analog supply voltage

(2)

Common mode input range

Input offset voltage

Input offset voltage drift

25 °C, No Load on output.

All voltage/Temp.

Normal mode

Low-power mode

TRIMOFFSETP

TRIMLPOFFSETP

TRIMOFFSETN

TRIMLPOFFSETN

Offset trim step at low common input voltage

(0.1 ₓ V

DDA

)

Offset trim step at high common input voltage

(0.9 ₓ V

DDA

)

Min

1.8

Typ

±5

±10

DDA

±1.5

±3

V mV

μV/°C

0.8

Max

3.6

1.1

1.35

Unit

V mV

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192

Electrical characteristics

Symbol

LOAD

LOAD_PGA

LOAD

LOAD_PGA

LOAD

CMRR

PSRR

GBW

(3)

OHSAT

OLSAT

φ m

STM32L452xx

Table 87. OPAMP characteristics (1) (continued)

Parameter Conditions Min

Drive current

Drive current in

PGA mode

Normal mode

Low-power mode

Normal mode

Low-power mode

DDA

≥ 2 V

DDA

≥ 2 V

Resistive load

(connected to

VSSA or to

VDDA)

Normal mode

Low-power mode

DDA

< 2 V

Typ

Max

500

100

450

Unit

µA

Resistive load in PGA mode

(connected to

VSSA or to

DDA

)

Capacitive load

Power supply rejection ratio

Low saturation voltage

Phase margin

Normal mode

Low-power mode

Common mode rejection ratio

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Gain Bandwidth

Product

Low-power mode

Normal mode

Low-power mode

Slew rate

(from 10 and

90% of output voltage)

Open loop gain

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

High saturation voltage

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

DDA

< 2 V

4.5

40 -

-85

-90

LOAD

≤ 50 pf,

≥ 4 kΩ DC

LOAD

≤ 50 pf,

≥ 20 kΩ DC

DDA

≥ 2.4 V

(OPA_RANGE = 1)

DDA

< 2.4 V

(OPA_RANGE = 0)

≥ 2.4 V

< 2.4 V

I load

= max or R load min Input at V

DDA

100

DDA

load

= max or R load min Input at 0.

90 -

550 1600 2200

100 420 600

250

700

180

950

280

700

180

300

80 -

110

110 -

100

kΩ pF dB dB kHz

V/ms dB mV

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Symbol

GM t

WAKEUP

I bias

PGA gain

Table 87. OPAMP characteristics (1) (continued)

Parameter Conditions Min

Gain margin

Normal mode

Low-power mode -

Wake up time from OFF state.

Normal mode

Low-power mode

LOAD

≤ 50 pf,

≥ 4 kΩ follower configuration

LOAD

≤ 50 pf,

≥ 20 kΩ follower configuration

OPAMP input bias current

General purpose input -

Non inverting gain value

PGA Gain = 2

R network

R2/R1 internal resistance values in PGA mode

(5)

PGA Gain = 4

PGA Gain = 8

PGA Gain = 16

Delta R

Resistance variation (R1 or

R2)

PGA gain error PGA gain error

Gain = 2

-15

-1

PGA BW

PGA bandwidth for different non inverting gain

Gain = 4

Gain = 8

Gain = 16 -

Typ

GBW/

80/80

120/

140/

150/

Max

(4)

Unit dB

µs nA

kΩ/kΩ

MHz

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Electrical characteristics STM32L452xx

Symbol

Table 87. OPAMP characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit en

Voltage noise density

Normal mode

Low-power mode

Normal mode

Low-power mode at 1 kHz, Output loaded with 4 kΩ at 1 kHz, Output loaded with 20 kΩ at 10 kHz, Output loaded with 4 kΩ at 10 kHz, Output loaded with 20 kΩ

500

600

180

290 -

nV/√Hz

DDA

(OPAMP)

Table 71: I/O static characteristics

OPAMP consumption from V

DDA

Normal mode

Low-power mode no Load, quiescent mode

120

260

100

1. Guaranteed by design, unless otherwise specified.

2. The temperature range is limited to 0 °C-125 °C when V

DDA

is below 2 V

3. Guaranteed by characterization results.

4. Mostly I/O leakage, when used in analog mode. Refer to I lkg

parameter in

5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between

OPAMP inverting input and ground. The PGA gain =1+R2/R1

µA

6.3.23 Temperature sensor characteristics

Symbol

(1)

Avg_Slope (2)

30 t

START

(TS_BUF)

START

Table 88. TS characteristics

Parameter

linearity with temperature

Average slope

Voltage at 30°C (±5 °C)

(3)

Sensor Buffer Start-up time in continuous mode

Start-up time when entering in continuous mode

(4)

Min

2.3

0.742

Typ

±1

2.5

0.76

Max

±2

2.7

0.785

120

Unit

°C mV/°C

µs

µs t

S_temp