This datasheet provides the ordering information and mechanical device characteristics of the STM32F101x4 and STM32F101x6 low-density access line microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family, please refer to

Section 2.2:

Full compatibility throughout the family .

The Low-density STM32F101xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com

For information on the Cortex ® -M3 core please refer to the Cortex ® -M3 Technical Reference

Manual, available from the www.arm.com website.

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Description

2 Description

STM32F101x4, STM32F101x6

The STM32F101x4 and STM32F101x6 Low-density access line family incorporates the high-performance ARM Cortex ® -M3 32-bit RISC core operating at a 36 MHz frequency, high-speed embedded memories (Flash memory of 16 to 32 Kbytes and SRAM of 4 to 6

Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (one I 2 C, one SPI, and two

USARTs), one 12-bit ADC and up to two general-purpose 16-bit timers.

The STM32F101xx Low-density access line family operates in the –40 to +85 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F101xx Low-density access line family includes devices in three different packages ranging from 36 pins to 64 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

These features make the STM32F101xx Low-density access line microcontroller family suitable for a wide range of applications such as application control and user interface, medical and handheld equipment, PC peripherals, gaming and GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, Video intercoms, and

HVACs.

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DocID15058 Rev 6

STM32F101x4, STM32F101x6 Description

Figure 1 shows the general block diagram of the device family.

Table 2. Low-density STM32F101xx device features and peripheral counts

Peripheral STM32F101Tx STM32F101Cx STM32F101Rx

Flash - Kbytes 16 32 16 32 16 32

SRAM - Kbytes 4 6 4 6 4 6

General-purpose 2 2 2 2 2 2

SPI

USART

2 2 2 2 2 2

12-bit synchronized ADC number of channels

GPIOs

CPU frequency

Operating voltage

Operating temperatures

Packages

10 channels

36 MHz

16 channels

2.0 to 3.6 V

Ambient temperature: –40 to +85 °C (see Table 8 )

Junction temperature: –40 to +105 °C (see Table 8

)

VFQFPN36 LQFP48 LQFP64

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Description STM32F101x4, STM32F101x6

Figure 1. STM32F101xx Low-density access line block diagram

TRACECLK

TRACED[0: 3 ] as A S

NJTR S T

JTDI

JTCK/ S WCLK

JTM S / S WDIO

JTDO as AF

NR S T

VDDA

V SS A

8 0AF

PA[ 15:0]

PB[ 15:0]

PC[15:0]

PD[ 3 :0]

MO S I,MI S O,

S CK,N SS as AF

RX,TX, CT S , RT S ,

S m a rtc a rd as AF

16AF

TPIU

S W/JTAG

S WD

Cortex M 3 CPU

F m a x

NVIC

6 M Hz

NVIC pbu s

Dbu s

S y s t em

Ibu s

GP DMA

7 ch a nnel s

@VDDA

S UPPLY

S UPERVI S ION

POR / PDR

PVD

R s t

Int

EXTI

WAKEUP

GPIOA

GPIOB

GPIOC

GPIOD

S PI

Tr a ce controller

Fl as h 3 2 KB

64 bit

POWER

VOLT. REG.

3 .

3 V TO 1.

8 V

@VDD

AHB2

APB2

S RAM

6 KB

@VDD

PCLK1

PCLK 2

HCLK

FCLK

RC 8 MHz

PLL &

CLOCK

MANAGT

RC 42 kHz

@VDDA

AHB2

APB 1

XTAL O S

4-16 MHz

IWDG

S t a nd by

in terf a ce

@VBAT

XTAL 3 2 kHz

RTC

AWU

B a ck up reg

B a cku p i nterf a ce

TIM2

TIM 3

U S ART2

I2C

W W D G

U S ART1

@VDDA

12bit ADC IF

Temp s en s o r

= 2 to 3 .6 V

O S C_IN

O S C_OUT

BAT

O S C 3 2_IN

O S C 3 2_OUT

TAMPER-RTC

4 Ch a nn el s

RX,TX, CT S , RT S ,

CK, S m a rtC a rd as AF

S CL, S DA, S MBA as AF a i1517 3 c

1. AF = alternate function on I/O port pin.

2. T

= –40 °C to +85 °C (junction temperature up to 105 °C).

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DocID15058 Rev 6

STM32F101x4, STM32F101x6 Description

Figure 2. Clock tree

8 MHz

HSI RC HSI

PLLSRC

PLLMUL

..., x16 x2, x3, x4

PLL

HSI

PLLCLK

HSE

SYSCLK

36 MHz max

AHB

Prescaler

/1, 2..512

PLLXTPRE

CSS

36 MHz max

APB1

Prescaler

/1, 2, 4, 8, 16

HCLK to AHB bu s, core, memory and DMA

Clock

Ena b le (3 b its) to Cortex System timer

FCLK Cortex free r u nning clock

36 MHz max

Peripheral Clock

Ena b le (13 b its)

PCLK1 to APB1 peripherals

TIM2, TIM3

If (APB1 prescaler =1) x1 else x2 to TIM2, TIM3

TIMXCLK

Peripheral Clock

Ena b le (3 b its)

APB2

Prescaler

/1, 2, 4, 8, 16

36 MHz max

Peripheral Clock

Ena b le (11 b its)

PCLK2 to APB2 peripherals

OSC_OUT

OSC_IN

4-16 MHz

HSE OSC

OSC32_IN

OSC32_OUT

LSE OSC

32.768 kHz

LSI RC

40 kHz

/128

LSE

RTCCLK to RTC

RTCSEL[1:0]

LSI to Independent Watchdog (IWDG)

IWDGCLK

ADC

Prescaler

/2, 4, 6, 8 to ADC

ADCCLK

MCO

Main

Clock O u tp u t

MCO

/2 PLLCLK

HSI

HSE

SYSCLK

Legend:

HSE = high-speed external clock signal

HSI = high-speed internal clock signal

LSI = low-speed internal clock signal

LSE = low-speed external clock signal ai15174

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is

36 MHz.

2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.

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Description STM32F101x4, STM32F101x6

The STM32F101xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are referred to as low-density devices, the STM32F101x8 and STM32F101xB are referred to as medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are referred to as high-density devices.

Low- and high-density devices are an extension of the STM32F101x8/B devices, they are specified in the STM32F101x4/6 and STM32F101xC/D/E datasheets, respectively. Lowdensity devices feature lower Flash memory and RAM capacities and a timer less. Highdensity devices have higher Flash memory and RAM capacities, and additional peripherals like FSMC and DAC, while remaining fully compatible with the other members of the

STM32F101xx family.

The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD and STM32F101xE are a drop-in replacement for the STM32F101x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle.

Moreover, the STM32F101xx performance line family is fully compatible with all existing

STM32F101xx access line and STM32F102xx USB access line devices.

Table 3. STM32F101xx family

Memory size

Low-density devices Medium-density devices High-density devices

Pinout 16 KB

Flash

32 KB

Flash

(1)

64 KB

Flash

128 KB

Flash

256 KB

Flash

384 KB

Flash

512 KB

Flash

4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM

32 KB

RAM

48 KB

RAM

48 KB

RAM

144

100 -

64 2 × USARTs

2 × 16-bit timers

1 × SPI, 1 × I

1 × ADC

3 × USARTs

3 × 16-bit timers

2 × SPIs, 2 × I2Cs,

1 × ADC

5 × USARTs

4 × 16-bit timers, 2 × basic timers

3 × SPIs, 2 × I

Cs, 1 × ADC,

2 × DACs, FSMC (100 and 144 pins)

1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices.

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STM32F101x4, STM32F101x6 Description

2.3 Overview

2.3.1 ARM

Cortex

-M3 core with embedded Flash and SRAM

The ARM ® Cortex ® -M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM ® Cortex ® -M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The STM32F101xx Low-density access line family having an embedded ARM core, is therefore compatible with all ARM tools and software.

2.3.3

16 or 32 Kbytes of embedded Flash is available for storing programs and data.

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

2.3.5

Up to 6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

Nested vectored interrupt controller (NVIC)

The STM32F101xx Low-density access line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of

Cortex ® -M3) and 16 priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

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Description STM32F101x4, STM32F101x6

2.3.7

The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines.

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 36 MHz. See

Figure 2 for details on the clock tree.

2.3.9

At startup, boot pins are used to select one of three boot options:

• Boot from User Flash

• Boot from System Memory

• Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606.

Power supply schemes

• V

= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.

Provided externally through V

pins.

• V

SSA

, V

DDA

and V

= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to V

DDA

SSA must be connected to V

DD and V is 2.4 V when the ADC is used).

, respectively.

• V

BAT

= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

is not present.

For more details on how to connect power pins, refer to

Figure 10: Power supply scheme .

2.3.10 Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when V

DD external reset circuit.

is below a specified threshold, V

POR/PDR

, without the need for an

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be generated when V

DDA

drops below the V

PVD

threshold and/or when V

DDA

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DocID15058 Rev 6

STM32F101x4, STM32F101x6 Description higher than the V

PVD

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

Refer to

Table 10: Embedded reset and power control block characteristics

for the values of

POR/PDR

and V

PVD

The regulator has three operation modes: main (MR), low power (LPR) and power down.

• MR is used in the nominal regulation mode (Run)

• LPR is used in the Stop mode

• Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output.

Note:

The STM32F101xx Low-density access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.

2.3.13 DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer.

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Description STM32F101x4, STM32F101x6

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I 2 C, USART, general purpose timers

TIMx and ADC.

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V

BAT

pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when V

power is not present.

The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

This timer is dedicated for OS, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

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There areup to two synchronizable general-purpose timers embedded in the STM32F101xx

Low-density access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture,

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Description output compare, PWM or one pulse mode output. This gives up to 12 input captures / output compares / PWMs on the largest packages.

The general-purpose timers can work together via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

2.3.19 I

C bus

The I²C bus interface can operate in multimaster and slave modes. It can support standard and fast modes.

It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.

A hardware CRC generation/verification is embedded.

The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.

The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability.

The USART interfaces can be served by the DMA controller.

2.3.21 Serial peripheral interface (SPI)

The SPI interface is able to communicate up to 18 Mbit/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

The SPI interface can be served by the DMA controller.

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

The 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

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Description STM32F101x4, STM32F101x6

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < V

DDA

< 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

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STM32F101x4, STM32F101x6

3 Pinouts and pin description

Pinouts and pin description

Figure 3. STM32F101xx Low-density access line LQFP64 pinout

9%$7

3&$17,B7$03

3&26&B,1

3&26&B287

3'26&B,1

3'26&B287

1567

966$

9''$

3$:.83

/4)3

9''B

966B

Figure 4. STM32F101xx Low-density access line LQFP48 pinout

DLE

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1-OSC_OUT

NRST

VSSA

VDDA

PA0-WKUP

PA1

PA2

48 47 46 45 44 43 42 41 40 39 38 37

LQFP48

13 14 15 16 17 18 19 20 21 22 23 24

VDD_2

VSS_2

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12 ai14378d

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Pinouts and pin description STM32F101x4, STM32F101x6

Figure 5. STM32F101xx Low-density access line UFQPFN48 pinout

6"!4

0#4!-0%224#

0#/3#?).

0#/3#?/54

0$/3#?).

0$/3#?/54

.234

633!

6$$!

0!7+50

1&0.

6$$?

633?

Figure 6. STM32F101xx Low-density access line VFQPFN36 pinout

-36

DD_3

OSC_IN/PD0

OSC_OUT/PD1

NRST

SSA

DDA

PA0-WKUP

PA1

PA2

36 35 34 33 32 31 30 29 28

2 26

QFN36

5 23

20 8

9 19

10 11 12 13 14 15 16 17 18

DD_2

SS_2

PA13

PA12

PA11

PA10

PA9

PA8

DD_1 ai14654

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STM32F101x4, STM32F101x6

Pins

Pinouts and pin description

Table 4. Low-density STM32F101xx pin definitions

Alternate functions

(3)(4)

Pin name

Main function

(3)

(after reset) Default Remap

13 17 10

3 -

BAT

PC13-TAMPER-

RTC

(5)

PC14-OSC32_IN

(5)

4 PC15-OSC32_OUT

(5)

5 2 OSC_IN

6 3 OSC_OUT

8 12 5

9 13 6

NRST

PC0

PC1

PC2

PC3

SSA

DDA

I/O

10 14 7 PA0-WKUP I/O

14 20 11

15 21 12

16 22 13

PA1

PA2

PA3

SS_4

DD_4

PA4

PA5

PA6

I/O

PA3

SS_4

DD_4

PA4

PA5

PA6

BAT

PC13

(6)

PC14

(6)

PC15

(6)

OSC_IN

OSC_OUT

NRST

PC0

PC1

PC2

PC3

SSA

DDA

PA0

PA1

PA2

TAMPER-RTC

OSC32_IN

OSC32_OUT

ADC_IN10 -

ADC_IN11 -

ADC_IN12 -

ADC_IN13 -

WKUP/USART2_CTS/

ADC_IN0/

TIM2_CH1_ETR

(7)

USART2_RTS/

ADC_IN1/TIM2_CH2

(7)

USART2_TX/

ADC_IN2/TIM2_CH3

(7)

USART2_RX/

ADC_IN3/TIM2_CH4

(7)

SPI_NSS

(7)

/ADC_IN4

USART2_CK

SPI_SCK

(7)

/ADC_IN5 -

SPI_MISO

(7)

/ADC_IN6/

TIM3_CH1 (7)

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Pinouts and pin description

Pins

STM32F101x4, STM32F101x6

Table 4. Low-density STM32F101xx pin definitions (continued)

Alternate functions (3)(4)

Pin name

Main function

(3)

(after reset) Default Remap

17 23 14

18 26 15

19 27 16

20 28 17

21 29 -

22 30 -

23 31 18

24 32 19

25 33 -

26 34 -

27 35 -

28 36 -

37 -

38 -

29 41 20

30 42 21

31 43 22

32 44 23

33 45 24

34 46 25

35 47 26

36 48 27

PA7 I/O PA7

PB15

PC6

PC7

PC8

PC9

PA8

PA9

PA10

PA11

PA12

PC4

PC5

I/O

PB0 I/O

PB1

PB2

PB10

PB11

SS_1

DD_1

PB12

PB13

PB14

PC4

PC5

PB0

I/O PB1

I/O FT PB2/BOOT1

I/O FT PB10

I/O

PB11

SS_1

DD_1

PB12

PB13

PB14

I/O FT

PA13

SS_2

DD_2

I/O

PA9

PA10

PA11

PA12

JTMS-

SWDIO

SS_2

DD_2

PB15

PC6

PC7

PC8

PC9

PA8

SPI_MOSI

(7)

/ADC_IN7/

TIM3_CH2

(7)

ADC_IN14 -

ADC_IN15 -

ADC_IN8/TIM3_CH3

(7)

ADC_IN9/TIM3_CH4

(7)

TIM2_CH3

TIM2_CH4

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

USART1_CK/MCO -

USART1_TX

(7)

USART1_RX (7) -

USART1_CTS -

USART1_RTS -

PA13

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STM32F101x4, STM32F101x6

Pins

Pinouts and pin description

Table 4. Low-density STM32F101xx pin definitions (continued)

Alternate functions (3)(4)

Pin name

Main function

(3)

(after reset) Default Remap

37 49 28 PA14 I/O FT

JTCK/SWCL

PA14

50 29

51 -

52 -

53 -

5 2

6 3

54 -

PA15

PC10

PC11

PC12

PD0

PD1

PD2

I/O FT JTDI

I/O FT PC10

I/O FT PC11

I/O FT

PC12

OSC_IN

(8)

I/O FT OSC_OUT

(8)

I/O FT PD2

TIM3_ETR

TIM2_CH1_ETR/

PA15 / SPI_NSS

55 30

56 31

57 32

42 58 33

43 59 34

44 60 35

PB3

PB4

PB5

I/O

PB6

PB7

BOOT0 I

I/O FT

JTDO

NJTRST

PB5

PB6

PB7

BOOT0

I2C_SMBA

I2C_SCL

(7)

I2C_SDA

(7)

TIM2_CH2 / PB3

TRACESWO

SPI_SCK

TIM3_CH1 / PB4

SPI_MISO

TIM3_CH2 /

SPI_MOSI

USART1_TX

USART1_RX

45 61 -

46 62 -

PB8

PB9

I/O

PB8

PB9

I2C_SCL

I2C_SDA

63 36

64 1

SS_3

DD_3

S -

SS_3

DD_3

1. I = input, O = output, S = supply.

2. FT= 5 V tolerant.

3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be

called SPI, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

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Pinouts and pin description STM32F101x4, STM32F101x6

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the

Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the

STMicroelectronics website: www.st.com.

7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.

8. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as

OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.

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DocID15058 Rev 6

STM32F101x4, STM32F101x6 Memory mapping

The memory map is shown in

Figure 7 .

Figure 7. Memory map

0xFFFF FFFF

0xE010 0000

0xE000 0000

Cortex-M3 internal peripherals

0xC000 0000

0xA000 0000

0x8000 0000

0x6000 0000

0x4000 0000

Peripherals

0x2000 0000

SRAM

0x0000 0000

Reserved

0x1FFF FFFF

0x1FFF F80F

0x1FFF F800 reserved

Option Bytes

System memory

0x1FFF F000 reserved

0x0801 FFFF

Flash memory

0x0800 0000

0x0000 0000

Aliased to Flash or system memory depending on

BOOT pins

APB memory space

0xFFFF FFFF

0xE010 0000 reserved reserved

0x6000 0000 reserved

0x4002 3400

CRC

0x4002 3000 reserved

0x4002 2400

0x4002 2000

Flash interface

0x4002 1400 reserved

0x4002 1000

RCC

0x4002 0400 reserved

0x4002 0000

DMA reserved

0x4001 3C00

USART1

0x4001 3800 reserved

0x4001 3400

SPI

0x4001 3000 reserved

0x4001 2C00 reserved

0x4001 2800

ADC

0x4001 2400 reserved

0x4001 1800

0x4001 1400

Port D

0x4001 1000

Port C

0x4001 0C00

Port B

0x4001 0800

Port A

0x4001 0400

EXTI

0x4001 0000

AFIO reserved

0x4000 7400

PWR

0x4000 7000

BKP

0x4000 6C00 reserved

0x4000 6800 reserved

0x4000 6400 reserved

0x4000 6000

0x4000 5800 reserved

0x4000 5400

0x4000 4800

0x4000 4400

I2C reserved

USART2 reserved

0x4000 3400

0x4000 3000

IWDG

0x4000 2C00

WWDG

RTC

0x4000 2800

0x4000 0800 reserved

0x4000 0400

TIM3

0x4000 0000

TIM2 ai15175 b

DocID15058 Rev 6

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Electrical characteristics STM32F101x4, STM32F101x6

5.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3

σ

Unless otherwise specified, typical data are based on T

= 25 °C, V

2 V ≤ V tested.

= 3.3 V (for the

≤ 3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2

σ

)

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 8 .

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9

28/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6

Figure 8. Pin loading conditions

Electrical characteristics

Figure 9. Pin input voltage

STM32F10xxx pin STM32F10xxx pin

C = 50 pF

VIN ai14124 b ai14123 b

5.1.6 Power supply scheme

Figure 10. Power supply scheme

VBAT

1.8-3.6V

Po wer swi tch

Back u p circ u itry

(OSC32K,RTC,

Wake u p logic

Back u p registers)

OUT

Logic

GP I/O s

5 × 100 nF

+ 1 × 4.7 µF

VDD

1/2/3/4/5

VSS

1/2/3/4/5

VDD

10 nF

+ 1 µF

10 nF

+ 1 µF

VREF

VDDA

VREF+

VSSA

Reg u lator

ADC

VREF-

Analog:

RCs, PLL,

...

Kernel logic

(CPU,

Digital

& Memories) ai15496

Caution: In

Figure 10 , the 4.7 µF capacitor must be connected to V

DD3

DocID15058 Rev 6

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Electrical characteristics STM32F101x4, STM32F101x6

Figure 11. Current consumption measurement scheme

IDD_VBAT

VBAT

IDD

VDD

VDDA ai14126

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 5: Voltage characteristics ,

Table 6: Current characteristics , and Table 7: Thermal characteristics

may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 5. Voltage characteristics

Ratings Min Max Unit

(2)

− V

DDx

SSX

− V

ESD(HBM)

External main supply voltage (including

DDA and V

)

(1)

Input voltage on five volt tolerant pin

Input voltage on any other pin

Variations between different V

DD power pins

Variations between all the different ground pins

–0.3

−

0.3

4.0

+ 4.0

4.0

Electrostatic discharge voltage (human body model)

see Section 5.3.11: Absolute maximum ratings (electrical sensitivity)

V mV

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

2. V

maximum must always be respected. Refer to Table 6: Current characteristics for the maximum

allowed injected current values.

30/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

Symbol

Table 6. Current characteristics

Ratings Max.

Unit

VDD

VSS

Total current into V

DDA power lines (source)

(1)

Total current out of V

SS ground lines (sink)

(1)

Output current sunk by any I/O and control pin

150

INJ(PIN)

(2)

Output current source by any I/Os and control pin

Injected current on five volt tolerant pins

(3)

Injected current on any other pin

(4)

Total injected current (sum of all I/O and control pins)

(5)

−

-5/+0

± 5 mA

Σ I

INJ(PIN)

± 25

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

2. Negative injection disturbs the analog performance of the device. See note in

Section 5.3.17: 12-bit ADC characteristics

3. Positive injection is not possible on these I/Os. A negative injection is induced by V values.

. I

INJ(PIN)

must

never be exceeded. Refer to Table 5: Voltage characteristics

for the maximum allowed input voltage

4. A positive injection is induced by V

never be exceeded. Refer to

values.

while a negative injection is induced by V

Table 5: Voltage characteristics

. I

for the maximum allowed input voltage

must

5. When several inputs are submitted to a current injection, the maximum Σ I positive and negative injected currents (instantaneous values).

INJ(PIN)

is the absolute sum of the

Symbol

STG

Table 7. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

5.3.1 General operating conditions

Symbol f

HCLK f

PCLK1 f

PCLK2

DDA

(1)

BAT

Table 8. General operating conditions

Parameter Conditions

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

Analog operating voltage

(ADC not used)

Analog operating voltage

(ADC used)

Backup operating voltage

Must be the same potential as V

(2)

Min

2.4

1.8

Max

3.6

Unit

MHz

DocID15058 Rev 6

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Electrical characteristics STM32F101x4, STM32F101x6

Symbol

Table 8. General operating conditions (continued)

Parameter Conditions Min Max Unit

Power dissipation at T

85 °C

(3)

Ambient temperature

LQFP64

LQFP48 -

444

363

VFQFPN36 1000

Maximum power dissipation –40

Low power dissipation

(4)

–40 105

–40 105 mW

°C

Junction temperature range

1. When the ADC is used, refer to

Table 41: ADC characteristics .

2. It is recommended to power V between V

and V

DDA

and V

DDA

from the same source. A maximum difference of 300 mV

can be tolerated during power-up and operation.

3. If T is lower, higher P

values are allowed as long as T

characteristics on page 82

does not exceed T

max (see Table 6.5: Thermal

4. In low power dissipation state, T can be extended to this range as long as T

Table 6.5: Thermal characteristics on page 82

does not exceed T

J max (see

5.3.3

Subject to general operating conditions for T

Symbol t

VDD

Table 9. Operating conditions at power-up / power-down

Parameter Conditions Min Max

rise time rate

fall time rate

∞

Unit

µs/V

Embedded reset and power control block characteristics

The parameters given in

Table 10 are derived from tests performed under the ambient

temperature and V

supply voltage conditions summarized in

Table 8

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DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

Symbol

Table 10. Embedded reset and power control block characteristics

Parameter Conditions Min Typ Max Unit

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

2.1

2.18

2.26

2 2.08

2.16

2.19

2.28

2.37

2.09

2.18

2.27

2.28

2.38

2.48

2.18

2.28

2.38

2.48

2.58

2.28

2.38

2.48

PVD

Programmable voltage detector level selection

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

2.47

2.58

2.69

2.37

2.48

2.59

2.57

2.68

2.79

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

2.47

2.66

2.56

2.58

2.78

2.68

2.69

2.9

2.8

PLS[2:0]=111 (rising edge) 2.76

2.88

PLS[2:0]=111 (falling edge) 2.66

2.78

2.9

PVDhyst

(2)

POR/PDR

PVD hysteresis

Power on/power down reset threshold

Falling edge

Rising edge

1.8

(1)

100

1.88

1.96

1.84

1.92

2.0

PDRhyst

(2) t

RSTTEMPO

(2)

PDR hysteresis

Reset temporization -

1.5

1. The product behavior is guaranteed by design down to the minimum V

POR/PDR

value.

2. Guaranteed by design, not tested in production.

2.5

4.5

V mV

V mV ms

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Electrical characteristics STM32F101x4, STM32F101x6

5.3.5

The parameters given in

Table 11

are derived from tests performed under the ambient temperature and V

supply voltage conditions summarized in

Table 8

Symbol

Table 11. Embedded internal reference voltage

Parameter Conditions Min Typ Max Unit

REFINT

Internal reference voltage

S_vrefint

(1)

ADC sampling time when reading the internal reference voltage

–40 °C < T

< +85 °C 1.16 1.20

1.24

5.1

17.1

(2)

RERINT

(2)

Internal reference voltage spread over the temperature range

= 3 V ±10 mV 10

µs mV

Coeff

(2)

Temperature coefficient 100 ppm/

°C

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design, not tested in production.

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 11: Current consumption measurement scheme

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

or V

(no load)

• All peripherals are disabled except if it is explicitly mentioned

• The Flash access time is adjusted to f

HCLK wait state from 24 to 36 MHz)

frequency (0 wait state from 0 to 24 MHz, 1

• Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)

• When the peripherals are enabled f

PCLK1

= f

HCLK/2

, f

PCLK2

= f

HCLK

The parameters given in

Table 12 are derived from tests performed under the ambient

temperature and V

supply voltage conditions summarized in

Table 8

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STM32F101x4, STM32F101x6 Electrical characteristics

Table 12. Maximum current consumption in Run mode, code with data processing running from Flash

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

= 85 °C

36 MHz 26

Supply current in Run mode

External clock

(2)

, all peripherals enabled

External clock

(2)

, all peripherals Disabled

24 MHz

16 MHz

8 MHz

36 MHz

24 MHz

16 MHz

8 MHz

19 mA

1. Based on characterization, not tested in production.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

Table 13. Maximum current consumption in Run mode, code with data processing running from RAM

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

= 85 °C

Supply current in

Run mode

External clock

(2)

, all peripherals enabled

External clock

(2)

all peripherals disabled

36 MHz

24 MHz

16 MHz

8 MHz

36 MHz

24 MHz

16 MHz

8 MHz

5 mA

1. Based on characterization, tested in production at V

DD max, f

HCLK

max.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

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Electrical characteristics STM32F101x4, STM32F101x6

Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled

36 MHz

16 MHz

8 MHz

– 45°C 25 °C 70 °C

Temperat u re (°C)

85 °C

Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled

36 MHz

16 MHz

8 MHz

– 45°C 25 °C 70 °C

Temperat u re (°C)

85 °C

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DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

Table 14. Maximum current consumption in Sleep mode, code running from Flash or RAM

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

= 85 °C

36 MHz 14

Supply current in

Sleep mode

External clock

(2)

all peripherals enabled

External clock

(2)

, all peripherals disabled

24 MHz

16 MHz

8 MHz

36 MHz

24 MHz

16 MHz

8 MHz

4.5

7 mA

1. Based on characterization, tested in production at V

DD max and f

HCLK

max with peripherals enabled.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

Table 15. Typical and maximum current consumptions in Stop and Standby modes

Typ

(1)

Max

Symbol Parameter Conditions

BAT

= 2.0 V

/ V

BAT

= 2.4 V

BAT

= 3.3 V

85 °C

(2)

Unit

Supply current in

Stop mode

Regulator in Run mode,

Low-speed and high-speed internal

RC oscillators and high-speed oscillator OFF (no independent watchdog)

Regulator in Low Power mode,

Low-speed and high-speed internal

RC oscillators and high-speed oscillator OFF (no independent watchdog)

Supply current in

Standby mode

Low-speed internal RC oscillator and independent watchdog ON

Low-speed internal RC oscillator

ON, independent watchdog OFF

DD_VBAT

Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF

Backup domain supply current

Low-speed oscillator and RTC ON

1. Typical values are measured at T

= 25 °C.

2. Based on characterization, not rested in production.

0.9

21.3

11.3

2.6

2.4

1.7

1.1

21.7

11.7

3.4

3.2

1.4

160

145

3.2

1.9

µA

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Electrical characteristics STM32F101x4, STM32F101x6

Figure 14. Typical current consumption on V

BAT different

with RTC on versus temperature at

BAT

values

2.5

1.5

0.5

2 V

2.4 V

3 V

3 .6 V

–40 °C 25 °C 70 °C

Temper a ture (°C)

8 5 °C 105 °C a i17 3 51

Figure 15. Typical current consumption in Stop mode with regulator in Run mode versus temperature at V

= 3.3 V and 3.6 V

3.3 V

3.6 V

–45 °C 25 °C

Temperat u re (°C)

85 °C

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DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

Figure 16. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at V

= 3.3 V and 3.6 V

3.3 V

3.6 V

–45 °C 25 °C

Temperat u re (°C)

85 °C

2.5

1.5

Figure 17. Typical current consumption in Standby mode versus temperature at V

3.3 V and

3.6 V

3.5

3.3 V

3.6 V

0.5

–45 °C 25 °C

Temperat u re (°C)

85 °C

DocID15058 Rev 6

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Electrical characteristics STM32F101x4, STM32F101x6

Typical current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

or V

(no load)

• All peripherals are disabled except if it is explicitly mentioned

• The Flash access time is adjusted to f

HCLK wait state from 24 to 36 MHz)

frequency (0 wait state from 0 to 24 MHz, 1

• Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)

• When the peripherals are enabled f

PCLK1 f

PCLK2

= f

HCLK/4

, f

PCLK2

= f

HCLK/2

, f

ADCCLK

The parameters given in

Table 16 are derived from tests performed under the ambient

temperature and V

supply voltage conditions summarized in

Table 8

Table 16. Typical current consumption in Run mode, code with data processing running from Flash

Typ

(1)

Typ

(1)

Symbol Parameter Conditions f

HCLK All peripherals enabled

(2)

All peripherals disabled

Unit

36 MHz 17.2

13.8

Supply current in

Run mode

External clock

(3)

Running on high speed internal RC

(HSI), AHB prescaler used to reduce the frequency

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

1.5

1.2

1.05

16.5

10.5

11.2

8.1

1.5

0.7

0.5

7.4

4.3

2.4

1.8

1.4

1.2

13.1

8.2

8.9

6.6

4.2

2.6

5.9

3.6

1.3

0.9

0.65

0.45

1. Typical values are measures at T

= 25 °C, V

= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

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DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

Table 17. Typical current consumption in Sleep mode, code running from Flash or

RAM

Typ (1) Typ (1)

Symbol Parameter Conditions f

HCLK All peripherals enabled

(2)

All peripherals disabled

Unit

External clock

(3)

Supply current in

Sleep mode

125 kHz

36 MHz

24 MHz

Running on High

Speed Internal RC

(HSI), AHB prescaler used to reduce the frequency

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

6.7

4.8

3.4

1.5

1.25

1.1

1.05

6.1

4.2

2.8

1.4

0.9

0.7

0.55

1.1

0.98

0.96

3.1

2.3

1.8

1.2

500 kHz

125 kHz

0.48

0.4

0.38

1. Typical values are measures at T

= 25 °C, V

= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

0.95

2.5

1.7

1.2

0.55

0.5

0.45

0.42

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

Table 18 . The MCU is placed

under the following conditions:

• all I/O pins are in input mode with a static value at V

or V

(no load)

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

• ambient operating temperature and V

Table 5

supply voltage conditions summarized in

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Electrical characteristics STM32F101x4, STM32F101x6

Table 18. Peripheral current consumption

Peripheral Typical consumption at 25 °C Unit

AHB (up to 36 MHz)

APB1 (up to 18 MHz)

DMA1

CRC

BusMatrix

(1)

APB1-Bridge

TIM2

TIM3

USART2

I2C1

WWDG

PWR

BKP

IWDG

APB2-Bridge

GPIO A

15.97

1.67

8.33

7.22

33.33

33.61

12.78

10.83

3.33

1.94

2.78

1.39

3.33

7.50

μ A/MHz

APB2 (up to 36 MHz)

GPIO B

GPIO C

GPIO D

6.81

7.22

6.94

SPI1

USART1

ADC1

(2)

4.86

12.78

15.54

1. The BusMatrix is automatically active when at least one master is ON. (CPU, DMA1) .

2. Specific conditions for measuring ADC current consumption: f f

ADCCLK

= f part equal to 0.7 mA must be added.

HCLK

= 28 MHz, f

APB1

= f

HCLK

, f

APB2

= f

HCLK

APB2

/ 2. When ADON bit in the ADC_CR2 register is set to 1, a current consumption of analog

High-speed external user clock generated from an external source

The characteristics given in

Table 19 result from tests performed using an high-speed

external clock source, and under the ambient temperature and supply voltage conditions summarized in

Table 8

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DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

Symbol

Table 19. High-speed external user clock characteristics

Parameter f

HSE_ext

User external clock source frequency

(1)

HSEH

HSEL t w(HSE) t w(HSE) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

(1)

OSC_IN input capacitance

Duty cycle

(1)

OSC_IN Input leakage current

1. Guaranteed by design, not tested in production.

Conditions

≤ V

Min

0.7V

Typ Max Unit

0.3V

±1

MHz

V ns pF

µA

Low-speed external user clock generated from an external source

The characteristics given in

Table 20 result from tests performed using an low-speed

external clock source, and under the ambient temperature and supply voltage conditions summarized in

Table 8

Symbol

Table 20. Low-speed external user clock characteristics

Parameter Conditions f

LSE_ext

LSEH

User external clock source frequency

(1)

OSC32_IN input pin high level voltage

LSEL

OSC32_IN input pin low level voltage

t w(LSE) t w(LSE) t r(LSE) t f(LSE)

C in(LSE)

DuCy

(LSE)

OSC32_IN high or low time

OSC32_IN rise or fall time

(1)

OSC32_IN input capacitance

Duty cycle

(1)

OSC32_IN Input leakage current V

≤ V

1. Guaranteed by design, not tested in production.

Min

0.7V

450

Typ Max

32.768

1000

0.3V

±1

Unit kHz

V ns pF

µA

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Electrical characteristics STM32F101x4, STM32F101x6

Figure 18. High-speed external clock source AC timing diagram

VHSEH

VHSEL

90%

10% tr(HSE)

THSE tf(HSE) tW(HSE) tW(HSE) t

External clock so u rce fHSE_ext

OSC _IN

STM32F10xxx

Figure 19. Low-speed external clock source AC timing diagram ai14127 b

VLSEH

VLSEL

90%

10% tr(LSE)

TLSE tf(LSE) tW(LSE) tW(LSE) t

External clock so u rce fLSE_ext

OSC32_IN

STM32F10xxx ai14140c

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 21

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

44/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

Symbol

Table 21. HSE 4-16 MHz oscillator characteristics (1)(2)

Parameter Conditions Min Typ Max Unit f

OSC_IN

Oscillator frequency

Feedback resistor

200

MHz k Ω i

Recommended load capacitance versus equivalent serial resistance of the crystal (R

)

(3)

= 30 Ω

HSE driving current

= 3.3 V, V

IN with 30 pF load

= V

1 pF mA g m t

SU(HSE)

(4)

Oscillator transconductance

Startup time

Startup

is stabilized

2 -

mA/V ms

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization, not tested in production.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 20

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 20. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

CL1

OSC_IN fHSE

8 MH z resonator

Bias controlled gain

REXT(1)

OSC_OU T STM32F10xxx

CL2 ai14128 b

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 22

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization

DocID15058 Rev 6

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Electrical characteristics STM32F101x4, STM32F101x6 time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 22. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1) (2)

Parameter Conditions Min Typ Max Unit

Feedback resistor 5 M Ω

Recommended load capacitance versus equivalent serial resistance of the crystal (R

)

= 30 K Ω 15 pF

LSE driving current

= 3.3 V

= V

1.4

µA g m

Oscillator transconductance 5 µA/V t

SU(LSE)

(3)

Startup time

is stabilized

= 50 °C

= 25 °C

= 10 °C

= 0 °C

= -10 °C

= -20 °C

= -30 °C

= -40 °C -

1.5

2.5

60 -

1. Based on characterization, not tested in production.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer s

Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to

15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.

Load capacitance CL has the following formula: CL = CL1 x CL2 / ( CL1 + CL2 ) + C where C stray is between 2 pF and 7 pF.

stray

is the pin capacitance and board or trace PCB-related capacitance. Typically, it

Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL ≤ capacitance of 12.5 pF.

Example: if resonator with a load capacitance of CL = 6 pF, and C stray

= 2 pF is chosen, then CL1 = CL2 = 8 pF.

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STM32F101x4, STM32F101x6 Electrical characteristics

Figure 21. Typical application with a 32.768 kHz crystal

5.3.7

Resonator with integrated capacitors

CL1

32.768 KH z resonator

OSC32_IN

Bias controlled gain

OSC32_OU T

CL2 fLSE

STM32F10xxx ai14129 b

Internal clock source characteristics

The parameters given in

Table 23 are derived from tests performed under the ambient

temperature and V

supply voltage conditions summarized in

Table 8

High-speed internal (HSI) RC oscillator

Symbol

Table 23. HSI oscillator characteristics

(1)

Parameter Conditions Min Typ Max Unit

DuCy

I t f

HSI

ACC

(HSI)

HSI su(HSI)

(4)

DD(HSI)

(4)

Frequency

Duty cycle -

Accuracy of the HSI oscillator

User-trimmed with the RCC_CR register

(2)

Factorycalibrated

(4) (5)

= –40 to 105 °C

= –10 to 85 °C

= 0 to 70 °C

= 25 °C

HSI oscillator startup time

HSI oscillator power consumption

–2

–1.5

–1.3

–1.1

(3)

2.5

2.2

1.8

100

MHz

µA

1. V

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com

3. Guaranteed by design, not tested in production.

4. Based on characterization, not tested in production.

5. The actual frequency of HSI oscillator may be impacted by a reflow, but does not drift out of the specified range.

µs

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Electrical characteristics STM32F101x4, STM32F101x6

Low-speed internal (LSI) RC oscillator

Table 24. LSI oscillator characteristics

(1)

Symbol Parameter f

LSI

(2) t su(LSI)

(3)

DD(LSI)

(3)

Frequency

LSI oscillator startup time

LSI oscillator power consumption

1. V

= 3 V, T

= –40 to 85 °C unless otherwise specified.

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production.

Min

Typ

0.65

Max

1.2

Unit kHz

µs

µA

Wakeup time from low-power mode

The wakeup times given in

Table 25 are measured on a wakeup phase with an 8-MHz HSI

RC oscillator. The clock source used to wake up the device depends from the current operating mode:

• Stop or Standby mode: the clock source is the RC oscillator

• Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under the ambient temperature and V

DD voltage conditions summarized in

Table 8

supply

Table 25. Low-power mode wakeup timings

Symbol Parameter Typ Unit t

WUSLEEP

(1)

Wakeup from Sleep mode 1.8

µs t

WUSTOP

(1)

Wakeup from Stop mode (regulator in run mode) 3.6

µs

Wakeup from Stop mode (regulator in low-power mode) 5.4

WUSTDBY

(1)

Wakeup from Standby mode 50 µs

1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction.

The parameters given in

Table 26 are derived from tests performed under the ambient

temperature and V

supply voltage conditions summarized in

Table 8

Table 26. PLL characteristics

Symbol f

PLL_IN f

PLL_OUT

Parameter

PLL input clock

(2)

PLL input clock duty cycle

PLL multiplier output clock

Min (1)

Value

Typ

8.0

Max (1)

Unit

MHz

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STM32F101x4, STM32F101x6 Electrical characteristics

Symbol

Table 26. PLL characteristics (continued)

Value

Parameter

Min

(1)

Typ

Unit

Max

(1) t

LOCK

Jitter

PLL lock time

Cycle-to-cycle jitter

200

300

µs ps

1. Based on device characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

Flash memory

The characteristics are given at T

= –40 to 85 °C unless otherwise specified.

Table 27. Flash memory characteristics

Symbol Parameter Conditions Min

(1)

Typ Max

(1) t

I prog t

ERASE t

16-bit programming time

Page (1 KB) erase time

Mass erase time

Supply current

= –40 to +85 °C

= –40 to +85 °C f

Read mode

HCLK

= 36 MHz with 1 wait state, V

= 3.3 V f

Write / Erase modes

HCLK

= 36 MHz, V

= 3.3 V

Power-down mode / Halt,

= 3.0 to 3.6 V

V prog

Programming voltage

1. Guaranteed by design, not tested in production.

52.5

3.6

Unit

µs ms ms mA mA

µA

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (Electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

SS compliant with the IEC 61000-4-4 standard.

and

through a 100 pF capacitor, until a functional disturbance occurs. This test is

A device reset allows normal operations to be resumed.

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Electrical characteristics STM32F101x4, STM32F101x6

The test results are given in

Table 28

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

FESD

EFTB

Table 28. EMS characteristics

Parameter Conditions

Voltage limits to be applied on any I/O pin to induce a functional disturbance f

= 3.3 V, T

= +25 °C,

HCLK

= 36 MHz conforms to IEC 61000-4-2

Fast transient voltage burst limits to be applied through 100 pF on V

and V to induce a functional disturbance

SS pins f

= 3.3 V, T

= +25 °C,

HCLK

= 36 MHz conforms to IEC 61000-4-4

Level/Class

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC61967-2 standard which specifies the test board and the pin loading.

Table 29. EMI characteristics

Symbol Parameter

EMI

Conditions

Monitored frequency band

Peak level

0.1 MHz to 30 MHz

= 3.3 V, T

= 25 °C, compliant with

IEC 61967-2

30 MHz to 130 MHz

130 MHz to 1GHz

EMI Level

Max vs. [f

HSE

HCLK

]

8/36 MHz

3.5

Unit dBµV

50/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

5.3.11 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Symbol

Table 30. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage (human body model)

Electrostatic discharge voltage (charge device model)

= +25 °C conforming to JESD22-A114

= +25 °C conforming to

ANSI/ESD STM5.3.1

1. Based on characterization results, not tested in production.

2000

500

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78 IC latch-up standard.

Symbol

Parameter

Table 31. Electrical sensitivities

Conditions

Static latch-up class T

= +85 °C conforming to JESD78A

Class

II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

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Electrical characteristics STM32F101x4, STM32F101x6

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation).

The test results are given in

Table 32

Symbol

INJ

Table 32. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

Injected current on OSC_IN32,

OSC_OUT32, PA4, PA5, PC13

Injected current on all FT pins

Injected current on any other pin

-0

-5

Unit mA

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STM32F101x4, STM32F101x6 Electrical characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 33

are derived from tests

performed under the conditions summarized in Table 8 . All I/Os are CMOS and TTL

compliant.

Symbol Parameter

Table 33. I/O static characteristics

Conditions Min Typ Max Unit

Standard IO input low level voltage

IO FT

(2)

input low level voltage

Standard IO input high level voltage

-0.3

0.41*(V

-2 V)+1.3 V

(1)

0.28*(V

-2 V)+0.8 V

(1)

0.32*(V

-2 V)+0.75 V

(1)

+0.3

IO FT (2) input high level voltage

> 2 V

≤ 2 V

0.42*(V

-2 V)+1 V

(1)

5.5

5.2

V hys

Standard IO Schmitt trigger voltage hysteresis

(3)

IO FT Schmitt trigger voltage hysteresis

(3)

200

5% V

(4)

I lkg

Input leakage current

(5)

≤ V

Standard I/Os

= 5 V

I/O FT

± 1

µA

Weak pull-up equivalent resistor

(6)

Weak pull-down equivalent resistor

(6)

= V

50 k Ω

I/O pin capacitance 5 -

1. Data based on design simulation.

2. FT = Five-volt tolerant. In order to sustain a voltage higher than V disabled.

+0.3 the internal pull-up/pull-down resistors must be

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

4. With a minimum of 100 mV.

5. Leakage could be higher than max. if negative current is injected on adjacent pins.

6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimum (~10% order)

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Electrical characteristics STM32F101x4, STM32F101x6

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in

Figure 22

and

Figure 23 for standard I/Os, and

Figure 24 and Figure 25 for 5 V tolerant I/Os.

Figure 22. Standard I/O input characteristics - CMOS port

6)(6),6

)(MIN

),MAX

4ESTEDINPRODUCTION

!REANOT

DETERMINED

6 )(6

#-/3STANDARDREQUIREMENT

6)(6$$

ULATIONS

"ASEDONDESIGNSIM

#-/3STANDARDREQUIREMENT

6),6$$

6 $$

ULATIONS

"ASEDONDESIGNSIM

4ESTEDINPRODUCTION

6$$6

AIC

Figure 23. Standard I/O input characteristics - TTL port

)(MIN

6)(6),6

44,REQUIREMENTS 6)(6

!REANOT

DETERMINED

6)(6$$ ULATIONS

"ASEDONDESIGNSIM

6),6$$

"ASEDONDESIGNSIM

ULATIONS

),MAX

44,REQUIREMENTS 6),6

6$$6

AIB

54/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

6)(6),6

4ESTEDINPRODUCTION

Figure 24. 5 V tolerant I/O input characteristics - CMOS port

!REANOT

DETERMINED

#-/3STANDARDREQUIREMENTS

6 )(6

6)(6$$

"ASEDONDESIGNSIM

ULATIONS

6),6$$

"ASEDONDESIGNSIM

ULATIONS

#-/3STANDARDREQUIR

MENT6 ), 6$$

4ESTEDINPRODUCTION

6$$

6$$6

AIC

Figure 25. 5 V tolerant I/O input characteristics - TTL port

6)(6),6

44,REQUIREMENT6)(6

!REANOT

DETERMINED

6)(6$$

"ASEDONDESIGNSIM

ULATIONS

6),6$$ ULATIONS

"ASEDONDESIGNSIM

)(MIN

),MAX

44,REQUIREMENTS6),6

6$$6

AIB

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Electrical characteristics STM32F101x4, STM32F101x6

Output driving current

The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed V

) except PC13, PC14 and PC15 which can sink or source up to +/-3mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 5.2

• The sum of the currents sourced by all the I/Os on V

DD,

I consumption of the MCU sourced on V

DD,

VDD

(see

Table 6

plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

I consumption of the MCU sunk on V

VSS

(see

Table 6

plus the maximum Run

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in Table 34

are derived from tests performed under the ambient temperature and V

DD in

Table 8

. All I/Os are CMOS and TTL compliant.

supply voltage conditions summarized

Symbol

Table 34. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)

(3)

(1)

(3)

(1)

(3)

(1)

(3)

Output Low level voltage for an I/O pin when 8 pins are sunk at the same time

Output High level voltage for an I/O pin when 8 pins are sourced at the same time

Output low level voltage for an I/O pin when 8 pins are sunk at the same time

Output high level voltage for an I/O pin when 8 pins are sourced at the same time

Output low level voltage for an I/O pin when 8 pins are sunk at the same time

Output high level voltage for an I/O pin when 8 pins are sourced at the same time

Output low level voltage for an I/O pin when 8 pins are sunk at the same time

Output high level voltage for an I/O pin when 8 pins are sourced at the same time

CMOS port

(2)

= +8 mA,

2.7 V < V

< 3.6 V

TTL port

(2)

= +8 mA

2.7 V < V

< 3.6 V

= +20 mA

(4)

2.7 V < V

< 3.6 V

= +6 mA

2 V < V

(4)

< 2.7 V

–0.4

2.4

–1.3

–0.4

0.4

1.3

0.4

1. The I

current sunk by the device must always respect the absolute maximum rating specified in

Table 6

and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I

Table 6

current sourced by the device must always respect the absolute maximum rating specified in

and the sum of I

(I/O ports and control pins) must not exceed I

VDD

4. Based on characterization data, not tested in production.

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STM32F101x4, STM32F101x6 Electrical characteristics

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 26 and

Table 35 , respectively.

Unless otherwise specified, the parameters given in Table 35

are derived from tests performed under the ambient temperature and V

DD in

Table 8

supply voltage conditions summarized

Table 35. I/O AC characteristics (1)

MODEx

[1:0] bit value (1)

Symbol Parameter Conditions Max Unit

f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out

Maximum frequency

(2)

Output high to low level fall time

Output low to high level rise time

Maximum frequency

(2)

= 50 pF, V

= 2 V to 3.6 V

= 50 pF, V

= 2 V to 3.6 V

Output high to low level fall time

Output low to high level rise time

= 50 pF, V

= 2 V to 3.6 V

125

(3)

125

(3)

F max(IO)out

Maximum Frequency

(2) t f(IO)out t r(IO)out

Output high to low level fall time

Output low to high level rise time

= 30 pF, V

= 2.7 V to 3.6 V 50

= 50 pF, V

= 2.7 V to 3.6 V 30

= 50 pF, V

= 2 V to 2.7 V 20

= 30 pF, V

= 2.7 V to 3.6 V 5 (3)

= 50 pF, V

= 2.7 V to 3.6 V 8

(3)

= 50 pF, V

= 2 V to 2.7 V 12

(3)

= 30 pF, V

= 2.7 V to 3.6

(3)

= 50 pF, V

= 2.7 V to 3.6 V 8

(3)

= 50 pF, V

= 2 V to 2.7 V 12 (3) t

EXTIpw

Pulse width of external signals detected by the

EXTI controller

MHz ns

MHz

MHz ns ns

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register.

2. The maximum frequency is defined in

Figure 26

3. Guaranteed by design, not tested in production.

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Electrical characteristics STM32F101x4, STM32F101x6

Figure 26. I/O AC characteristics definition

%84%2.!,

/54054

/.P&

TR)/ OUT

4 TF)/ OUT

-AXIMUMFREQUENCYISACHIEVEDIFTRTF

4ANDIFTHEDUTYCYCLEIS

WHENLOADEDBYP&

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Table 33 ).

Unless otherwise specified, the parameters given in Table 36

are derived from tests performed under the ambient temperature and V

DD in

Table 8

supply voltage conditions summarized

Symbol

Table 36. NRST pin characteristics

Parameter Conditions Min Typ Max Unit

IL(NRST)

(1)

IH(NRST)

(1)

NRST Input low level voltage

NRST Input high level voltage -

–0.5

2 -

0.8

+0.5

V hys(NRST)

F(NRST)

(1)

NF(NRST)

(1)

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST Input filtered pulse

NRST Input not filtered pulse

= V

300

200

100

mV k Ω ns ns

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution the series resistance must be minimum (~10% order)

58/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

Figure 27. Recommended NRST pin protection

Extern a l re s et circuit

(1)

NR S T

(2)

VDD

RPU

0.1 µ F

Filter

Intern a l Re s et

S TM 3 2F10xxx a i141 3 2d

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 36 . Otherwise the reset will not be taken into account by the device.

max level specified in

DocID15058 Rev 6

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Electrical characteristics STM32F101x4, STM32F101x6

The parameters given in

Table 37 are guaranteed by design.

Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output

alternate function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 37. TIMx

(1)

characteristics

Parameter Conditions Min

1 t res(TIM)

Timer resolution time f

EXT

Res

TIM

Timer external clock frequency on CH1 to CH4

Timer resolution

TIMxCLK

= 36 MHz 27.8

0 f

TIMxCLK

= 36 MHz

COUNTER

16-bit counter clock period when internal clock is selected

TIMxCLK

= 36 MHz 0.0278

MAX_COUNT

Maximum possible count

TIMxCLK

= 36 MHz -

1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.

Max

TIMxCLK

65536

Unit t

TIMxCLK ns

MHz

MHz bit t

TIMxCLK

µs 1820

65536 × 65536 t

TIMxCLK

119.2

I

C interface characteristics

The STM32F101xx Low-density access line I 2 C interface meets the requirements of the standard I 2 C communication protocol with the following restrictions: the I/O pins SDA and

SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DD is disabled, but is still present.

The I 2 C characteristics are described in

Table 38

. Refer also to

Section 5.3.12: I/O current injection characteristics

for more details on the input/output alternate function characteristics

(SDA and SCL).

60/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

Symbol

Table 38. I 2 C characteristics

Standard mode I

(1)

Parameter

Min Max

Fast mode I

(1) (2)

Min Max

Unit t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

4.7

4.0

250

1000

300

1.3

0.6

100

(3)

20+0.1C

900

(4)

300

µs ns t su(STA)

Start condition hold time

Repeated Start condition setup time

4.0

4.7

0.6

0.6 -

µs t su(STO)

Stop condition setup time t w(STO:STA)

Stop to Start condition time (bus free)

4.0

4.7

0.6

1.3

µs

C b

Capacitive load for each bus line 400 400

1. Guaranteed by design, not tested in production.

2. f

PCLK1

must be at least 2 MHz to achieve standard mode I

2 achieve fast mode I fast mode clock.

C frequencies. It must be at least 4 MHz to

C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C

3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.

4. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal.

DocID15058 Rev 6

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Electrical characteristics STM32F101x4, STM32F101x6

Figure 28. I 2 C bus AC waveforms and measurement circuit (1)

6$$?)# 6$$?)#

)£#BUS

5S 5S

34-&X

3$!

3#,

3TARTREPEATED

3TART

TSU34!

3$!

TF3$!

TH34!

TR3$!

TW3#,,

TSU3$!

TH3$!

3TOP

TSU34/34!

3#,

TW3#,( TR3#, TF3#, TSU34/

AIE

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

2. Rs = Series protection resistors, Rp = Pull-up resistors, V

DD_I2C

= I2C bus supply.

Table 39. SCL frequency (f

PCLK1

= MHz, V

DD_I2C

= 3.3 V)

(1)(2)

I2C_CCR value f

SCL

(kHz)

= 4.7 k Ω

400 0x801E

300

200

100

0x8028

0x803C

0x00B4

0x0168

20 0x0384

1. R

= External pull-up resistance, f

SCL

= I

C speed,

2. For speeds around 200 kHz, the tolerance on the achieved speed is of tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application.

± 5%. For other speed ranges, the

62/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 40

are derived from tests performed under the ambient temperature, f

conditions summarized in Table 8 .

PCLKx frequency and V

supply voltage

Refer to Section 5.3.12: I/O current injection characteristics for more details on the

input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol Parameter

Table 40. SPI characteristics

Conditions Min Max Unit f

SCK

1/t c(SCK) t r(SCK) t f(SCK) t su(NSS)

(1) t h(NSS)

(1) t t w(SCKH)

(1) w(SCKL)

(1) t su(MI)

(1) t su(SI)

(1) t h(MI)

(1) t h(SI)

(1) t a(SO)

(1)(2) t dis(SO)

(1)(3) t v(SO)

(1) t v(MO)

(1) t h(SO)

(1) t h(MO)

(1)

SPI clock frequency

Master mode

Slave mode

SPI clock rise and fall time

NSS setup time

NSS hold time

SCK high and low time

Capacitive load: C = 30 pF

Slave mode

Master mode, f

PCLK presc = 4

= 36 MHz,

Data input setup time

Master mode

Data input setup time

Slave mode

Data input hold time

Master mode

Data input hold time

Slave mode

SPI

Slave mode, f

PCLK presc = 4

= 36 MHz,

Data output access time

Slave mode, f

PCLK

= 24 MHz

Data output disable time Slave mode

Data output valid time

Slave mode (after enable edge)

Master mode (after enable edge)

Data output hold time

Slave mode (after enable edge)

Master mode (after enable edge)

4 t

PCLK

4 t

PCLK

MHz ns

1. Based on characterization, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

DocID15058 Rev 6

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Electrical characteristics STM32F101x4, STM32F101x6

Figure 29. SPI timing diagram - slave mode and CPHA = 0

NSS inp u t tc(SCK) tSU(NSS)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tw(SCKH) tw(SCKL) ta(SO)

MISO

OUT P UT ts u (SI)

MOSI

I NPUT tv(SO)

MS B O UT

M SB IN th(SI) th(SO)

BI T6 OUT

B I T1 IN th(NSS) tr(SCK) tf(SCK)

LSB OUT tdis(SO)

LSB IN

Figure 30. SPI timing diagram - slave mode and CPHA = 1 (1) ai14134c

NSS inp u t tSU(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 tw(SCKH) tw(SCKL)

MISO

OUT P UT ta(SO) ts u (SI)

MOSI

I NPUT tc(SCK) tv(SO)

MS B O UT th(SI)

M SB IN B I T1 IN th(SO)

BI T6 OUT th(NSS) tr(SCK) tf(SCK) tdis(SO)

LSB OUT

LSB IN

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

ai14135

64/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

Figure 31. SPI timing diagram - master mode (1)

High

NSS inp u t tc(SCK)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTUT ts u (MI) tw(SCKH) tw(SCKL)

MS BIN th(MI)

M SB OUT tv(MO)

BI T6 IN

B I T1 OUT th(MO)

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136

DocID15058 Rev 6

65/87

Electrical characteristics STM32F101x4, STM32F101x6

Note:

Unless otherwise specified, the parameters given in Table 41

are derived from tests performed under the ambient temperature, f

conditions summarized in Table 8 .

PCLK2 frequency and V

DDA

supply voltage

It is recommended to perform a calibration after each power-up.

Symbol Parameter

Table 41. ADC characteristics

Conditions Min Typ Max f

DDA f

ADC f

(1)

TRIG

(1)

AIN

Power supply

ADC clock frequency

Sampling rate

External trigger frequency

Conversion voltage range

(2)

ADC

= 14 MHz

2.4

0.6

0.043

0 (V

SSA or V

REFtied to ground)

3.6

823

REF+

AIN

(1)

ADC

(1)

ADC

(1)

External input impedance

Sampling switch resistance

Internal sample and hold capacitor

See Equation 1 and

Table 42 for details

8 t t t t

CAL

(1) t t lat

(1) latr

(1)

STAB

(1)

CONV

(1)

Calibration time

Injection trigger conversion latency

Regular trigger conversion latency

Sampling time

Stabilization time

Total conversion time

(including sampling time) f f f

ADC f

ADC

ADC f

ADC

= 14 MHz

5.9

0.214

(3)

0.143

(3)

0.107

1.5

17.1

239.5

1 18

14 to 252 (t

for sampling +12.5 for successive approximation)

1. Guaranteed by design, not tested in production.

2. V

REF+

is internally connected to V

DDA

and V

REF-

is be internally connected to V

SSA

3. For external triggers, a delay of 1/f

PCLK2

must be added to the latency specified in

Table 41 .

κΩ

κΩ pF

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

1/f

ADC

µs

Unit

MHz

MHz kHz

1/f

ADC

1/f

ADC

66/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

Equation 1: R

AIN

max formula:

AIN

< f

ADC

----------------------------------------------------------------

× C

ADC

× ln ( 2 )

– R

ADC

The form u la a b ove ( Equation 1 ) is u sed to determine the maxim u m external impedance allowed for an error b elow 1/4 of LSB. Here N = 12 (from 12b it resol u tion).

1.5

7.5

13.5

28.5

41.5

55.5

71.5

239.5

T s

(cycles)

Table 42. R

AIN

max for f

ADC

= 14 MHz

(1) t

(µs)

0.11

0.54

0.96

2.04

2.96

3.96

5.11

17.1

1. Guaranteed by design, not tested in production.

0.4

5.9

11.4

25.2

37.2

AIN

max (k Ω )

Symbol

Table 43. ADC accuracy - limited test conditions (1) (2)

Parameter Test conditions Typ Max

(3)

Unit

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

PCLK2 f

ADC

= 28 MHz,

= 14 MHz, R

DDA

= 25 °C

ADC calibration

AIN

< 10 k Ω ,

= 3 V to 3.6 V

Measurements made after

±1.3

±1

±0.5

±0.7

±0.8

±2

±1.5

±1

±1.5

LSB

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I affect the ADC accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

in Section 5.3.12

does not

3. Based on characterization, not tested in production.

DocID15058 Rev 6

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Electrical characteristics STM32F101x4, STM32F101x6

Symbol Parameter

Table 44. ADC accuracy (1) (2) (3)

Test conditions Typ Max

(4)

Unit

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

PCLK2 f

ADC

= 28 MHz,

= 14 MHz, R

ADC calibration

AIN

< 10 k Ω ,

DDA

= 2.4 V to 3.6 V

Measurements made after

±2

±1.5

±1

±1.5

±5

±2.5

±3

±2

±3

LSB

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V

, frequency and temperature ranges.

3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I affect the ADC accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

in Section 5.3.12

does not

4. Based on characterization, not tested in production.

Figure 32. ADC accuracy characteristics

[1LSB

IDEAL

DDA

4096

4095

4094

4093

SSA

2 3

1 LSB

IDEAL

4 5 6 7

(2)

(3)

(1)

4093 4094 4095 4096

DDA

(1) Example of an act u al transfer c u rve

(2) The ideal transfer c u rve

(3) End point correlation line

=Total u nadj u sted er ror: maxim u m deviation b etween the act u al and the ideal transfer c u rves.

=Offset e rror: deviation b etween the first act transition and the first ideal one.

u al

=Gain er ror: deviation b etween the last ideal transition and the last act u al one.

=Differential linearity error: maxim u m deviation b etween act u al steps and the ideal one.

=Integral linearity error: maxim u m deviation b etween any act u al transition and the end point correlation line.

ai15497

68/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Electrical characteristics

Figure 33. Typical connection diagram using the ADC

VAIN

RAIN(1)

AINx

Cparasitic

VDD

0.6 V

IL±1 µA

STM32F10xxx

Sample and hold ADC converter

RADC(1)

12b it converter

CADC(1) ai14139d

1. Refer to Table 41 for the values of R

AIN

, R

ADC

and C

ADC

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 this, f

ADC pF). A high C

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 34

. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 34. Power supply and reference decoupling

STM32F10xx4/6

DDA

1 µF // 10 nF

SSA ai15498

DocID15058 Rev 6

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Electrical characteristics STM32F101x4, STM32F101x6

5.3.18 Temperature sensor characteristics

Symbol

(1)

Avg_Slope

(1) t

START

(2)

(1)

S_temp

(3)(2)

Table 45. TS characteristics

Parameter

SENSE

linearity with temperature

Average slope

Voltage at 25°C

Startup time

ADC sampling time when reading the temperature

Min

4.0

1.34

Typ

± 1

4.3

1.43

1. Guaranteed by characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. Shortest sampling time can be determined in the application by multiple iterations.

Max

± 2

4.6

1.52

17.1

Unit

°C mV/°C

µs

70/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Package characteristics

6.1 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

ECOPACK

is an ST trademark.

Figure 35. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package outline

6HDWLQJSODQH

GGG &

$ $

(

3LQ,'

1. Drawing is not to scale.

(

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DocID15058 Rev 6

71/87

Package characteristics STM32F101x4, STM32F101x6

Table 46. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max e

K ddd

A3 b

0.800

0.180

5.875

1.750

5.875

1.750

0.450

0.350

0.250

0.900

0.020

0.650

0.200

0.230

6.000

3.700

6.000

3.700

0.500

0.550

1.000

0.050

1.000

0.300

6.125

4.250

6.125

4.250

0.550

0.750

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.2313

0.0689

0.0177

0.0138

0.0098

0.0315

0.0071

0.2313

0.0689

0.2362

0.1457

0.0197

0.0217

0.0354

0.0008

0.0256

0.0079

0.0091

0.2362

0.1457

0.2411

0.1673

0.0217

0.0295

0.0031

0.0394

0.0020

0.0394

0.0118

0.2411

0.1673

72/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Package characteristics

Figure 36. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package recommended footprint

1. Dimensions are expressed in millimeters.

:2?&0?6

DocID15058 Rev 6

73/87

Package characteristics STM32F101x4, STM32F101x6

Device Marking for VFQFPN36

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Figure 37. VFQFPN36 marking example (package top view)

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1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

Samples to run qualification activity.

74/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6

6.3 LQFP64 package information

Package characteristics

Figure 38. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

6($7,1*3/$1(

*$8*(3/$1(

FFF &

' /

3,1

,'(17,),&$7,21

:B0(B9

D1 b c

1. Drawing is not to scale.

Table 47. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min

0.050

1.350

0.170

0.090

Typ

1.400

0.220

12.000

10.000

7.500

12.000

10.000

Max

1.600

0.150

1.450

0.270

0.200

Min

0.0020

0.0531

0.0067

0.0035

Typ

0.0551

0.0087

0.4724

0.3937

0.2953

0.4724

0.3937

Max

0.0630

0.0059

0.0571

0.0106

0.0079

DocID15058 Rev 6

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Package characteristics STM32F101x4, STM32F101x6

Table 47. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

L1 ccc

E3 e

0°

0.450

7.500

0.500

3.5°

0.600

1.000

7°

0.750

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0°

0.0177

Typ

0.2953

0.0197

3.5°

0.0236

0.0394

Max

7°

0.0295

0.0031

Figure 39. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint

76/87

1. Dimensions are expressed in millimeters.

DocID15058 Rev 6

AIC

STM32F101x4, STM32F101x6 Package characteristics

Device Marking for LQFP64

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Figure 40. LQFP64 marking example (package top view)

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DocID15058 Rev 6

77/87

Package characteristics

6.4 LQFP48 package information

STM32F101x4, STM32F101x6

Figure 41. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

3%!4).'

0,!.%

CCC #

'!5'%0,!.%

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

"?-%?6

78/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Package characteristics

Symbol

Table 48. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max e

E3 k ccc b c

0.050

1.350

0.170

0.090

8.800

6.800

8.800

6.800

0.450

0°

1.400

0.220

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

1.600

0.150

1.450

0.270

0.200

9.200

7.200

9.200

7.200

0.750

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.3465

0.2677

0.0177

0°

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

0.0551

0.0087

0.3543

0.2756

0.3622

0.2835

0.0295

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

DocID15058 Rev 6

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Package characteristics STM32F101x4, STM32F101x6

Figure 42. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint

1. Dimensions are expressed in millimeters.

AID

80/87

DocID15058 Rev 6

STM32F101x4, STM32F101x6 Package characteristics

Device Marking for LQFP48

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Figure 43. LQFP48 marking example (package top view)

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670)

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DocID15058 Rev 6

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Package characteristics STM32F101x4, STM32F101x6

The maximum chip junction temperature (T

J max) must never exceed the values given in

Table 8: General operating conditions on page 31 .

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

max = T

max + (P

max x Θ

)

Where:

• T

max is the maximum ambient temperature in ° C,

• Θ

is the package junction-to-ambient thermal resistance, in ° C/W,

• P

max is the sum of P

INT

max and P

I/O max (P

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Symbol

Table 49. Package thermal characteristics

Parameter Value

Thermal resistance junction-ambient

LQFP 64 - 10 x 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP 48 - 7 x 7 mm / 0.5 mm pitch

Thermal resistance junction-ambient

UFQFPN 48 - 6 x 6 mm / 0.5 mm pitch

Thermal resistance junction-ambient

VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch

Unit

°C/W

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

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STM32F101x4, STM32F101x6

6.5.2

Package characteristics

Evaluating the maximum junction temperature for an application

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Table 50: Ordering information scheme .

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. Here, only temperature range 6 is available (–40 to 85 °C).

The following example shows how to calculate the temperature range needed for a given application, making it possible to check whether the required temperature range is compatible with the STM32F101xx junction temperature range.

Example: high-performance application

Assuming the following application conditions:

Maximum ambient temperature T

Amax

DDmax

= 50 mA, V

= 82 °C (measured according to JESD51-2),

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V and maximum 8 I/Os used at the same time in output mode at low level with I

= 20 mA, V

= 1.3 V

INTmax =

50 mA × 3.5 V= 175 mW

IOmax = 20

× 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

This gives: P

INTmax

= 175 mW and P

IOmax

= 272 mW

Dmax =

175

272 = 447 mW

Thus: P

Dmax

= 447 mW

Using the values obtained in Table 49

Jmax

is calculated as follows:

– For LQFP64, 45 °C/W

Jmax

= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C

This is within the junction temperature range of the STM32F101xx (–40 < T

< 105 °C).

Figure 44. LQFP64 P

max vs. T

700

600

500

400

300

200

100

65 75 85 95

(°C)

105 115

S u ffix 6

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Ordering information scheme

7 Ordering information scheme

STM32F101x4, STM32F101x6

Table 50. Ordering information scheme

Example: STM32 F 101 C 4 T 6 A xxx

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

101 = access line

Pin count

T = 36 pins

C = 48 pins

R = 64 pins

Flash memory size

4 = 16 Kbytes of Flash memory

6 = 32 Kbytes of Flash memory

Package

T = LQFP

U = VFQFPN

Temperature range

6 = Industrial temperature range, –40 to 85 °C.

Internal code

“A” or blank

(1)

Options xxx = programmed parts

TR = tape and real

1. For STM32F101x6 devices with a blank internal code, please refer to the STM32F103x6/8/B datasheet available from the ST website: www.st.com.

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the nearest ST sales office.

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STM32F101x4, STM32F101x6 Revision history

Date

23-Sep-2008

Revision

07-Apr-2009

24-Sep-2009

20-May-2010

Table 51. Document revision history

Changes

Initial release.

I/O information clarified on page 1 .

Figure 7: Memory map modified.

Table 4: Low-density STM32F101xx pin definitions

: PB4, PB13, PB14,

PB15, PB3/TRACESWO moved from Default column to Remap column.

REF-

is not available in the offered packages:

Figure 1: STM32F101xx

Low-density access line block diagram ,

Figure 10: Power supply scheme

and

Figure 34: Power supply and reference decoupling

updated,

Figure 30: Power supply and reference decoupling (VREF+ not connected to VDDA) removed.

Note modified in

Table 12: Maximum current consumption in Run mode, code with data processing running from Flash

and Table 14: Maximum current consumption in Sleep mode, code running from Flash or RAM

Figure 15 ,

Figure 16 and Figure 17

show typical curves.

ACC

HSI

max values modified in

Table 23: HSI oscillator characteristics .

Small text changes.

Note 5 updated and Note 4

added in Table 4: Low-density STM32F101xx pin definitions

RERINT

and T

Coeff

added to

Table 11: Embedded internal reference voltage

. Typical I

DD_VBAT

value added in Table 15: Typical and maximum current consumptions in Stop and Standby modes .

Figure 14: Typical current consumption on VBAT with RTC on versus temperature at different VBAT values

added.

HSE_ext

min modified in Table 19: High-speed external user clock characteristics .

and C

replaced by C in Table 21: HSE 4-16 MHz oscillator characteristics and

Table 22: LSE oscillator characteristics (fLSE =

32.768 kHz)

, notes modified and moved below the tables.

Note 1 modified below

Figure 20: Typical application with an 8 MHz crystal .

Table 23: HSI oscillator characteristics

modified. Conditions removed from

Table 25: Low-power mode wakeup timings .

Figure 27: Recommended NRST pin protection modified.

IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to

IEC 61967-2 in Section 5.3.10: EMC characteristics on page 49 .

Jitter added to Table 26: PLL characteristics

ADC

AIN

and R

AIN

parameters modified in Table 41: ADC characteristics

max values modified in Table 42: RAIN max for fADC = 14 MHz

Small text changes.

Added VFQFPN48 package.

Updated note 2 below

Table 38: I2C characteristics

Updated Figure 28: I2C bus AC waveforms and measurement circuit(1)

Updated Figure 27: Recommended NRST pin protection

Updated Section 5.3.12: I/O current injection characteristics

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Revision history STM32F101x4, STM32F101x6

Date

19-Apr-2011

25-Sep-2015

Table 51. Document revision history (continued)

Revision Changes

Updated footnotes below Table 5: Voltage characteristics on page 30

and

Table 6: Current characteristics on page 31

Updated tw min in Table 19: High-speed external user clock characteristics on page 43

Updated startup time in

Table 22: LSE oscillator characteristics (fLSE =

32.768 kHz) on page 46

Added

Section 5.3.12: I/O current injection characteristics

Updated Section 5.3.13: I/O port characteristics

Updated:

– All GPIOs are high current...’ in Section 2.3.22: GPIOs (generalpurpose inputs/outputs)

– first sentence in Output driving current

–

Table 2: Low-density STM32F101xx device features and peripheral counts

Table 4: Low-density STM32F101xx pin definitions

–

Table 6: Current characteristics

–

Table 8: General operating conditions

–

Table 18: Peripheral current consumption

– notes in Table 38: I2C characteristics

– note 2.

Table 44: ADC accuracy

– title of Table 39: SCL frequency (fPCLK1= MHz, VDD_I2C = 3.3 V)

– reference for ‘V

ESD(CDM)

’ in Table 30: ESD absolute maximum ratings

–

Table 50: Ordering information scheme

–

Table 49: Package thermal characteristics

–

Figure 28: I2C bus AC waveforms and measurement circuit(1)

Added

– note 5.

Table 23: HSI oscillator characteristics

–

Figure 37: VFQFPN36 marking example (package top view)

–

Figure 40: LQFP64 marking example (package top view)

–

Figure 43: LQFP48 marking example (package top view)

Corrected

– Corrected ‘tf(IO)out’ in

Figure 26: I/O AC characteristics definition

– Sigma letter in Section 5.1.1: Minimum and maximum values

Removed

– UFDFPN48 package

– First sentence in Section 5.3.16: Communications interfaces

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STM32F101x4, STM32F101x6

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