STMicroelectronics STM32F102C6 Datasheet

STM32F102x4

STM32F102x6

Low-density USB access line, Arm

®

-based 32-bit MCU with

16/32 KB Flash, USB FS, 5 timers, ADC and 5 com. interfaces

Datasheet

-

production data

Features

• Core: Arm ® 32-bit Cortex ® -M3 CPU

– 48 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 WS memory access

– Single-cycle multiplication and hardware division

• Memories

– 16 or 32 Kbytes of Flash memory

– 4 or 6 Kbytes of SRAM

• Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR and programmable voltage detector (PVD)

– 4 to 16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration

• Low power

– Sleep, Stop and Standby modes

– V

BAT

supply for RTC and backup registers

• Debug mode

– Serial wire debug (SWD) and JTAG interfaces

• DMA

– 7-channel DMA controller

– Peripherals supported: timers, ADC, SPIs,

I

2

Cs and USARTs

• 1 × 12-bit, 1.2 µs A/D converter (up to 16 channels)

– Conversion range: 0 to 3.6 V

– Temperature sensor

• Up to 51 fast I/O ports

– 37/51 I/Os all mappable on 16 external interrupt vectors and almost all 5 V-tolerant

LQFP48

7 × 7 mm

LQFP64

10 × 10 mm

• Up to five timers

– Two 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

– 2 watchdog timers (Independent and

Window)

– SysTick timer: 24-bit downcounter

• Up to five communication interfaces

– One I 2 C interface (SMBus/PMBus)

– Two USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– One SPI (12 Mbit/s)

– One USB 2.0 full speed interface

• CRC calculation unit, 96-bit unique ID

• ECOPACK packages

Table 1. Device summary

Reference Part number

STM32F102x4 STM32F102C4, STM32F102R4

STM32F102x6 STM32F102C6, STM32F102R6

August 2019

This is information on a product in full production.

DS5934 Rev 6

1/79

www.st.com

1

2

Contents

Contents

3

STM32F102x4, STM32F102x6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2

Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3.1

Arm

®

Cortex

®

-M3 core with embedded Flash memory and SRAM . . . . 13

2.3.2

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.3

2.3.4

2.3.5

2.3.6

CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14

External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.7

2.3.8

Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.9

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.10

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.11

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.12

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.13

DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.14

RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16

2.3.15

Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.16

Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.17

SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.18

General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.19

I

²

C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.20

Universal synchronous/asynchronous receiver transmitter (USART) . . 18

2.3.21

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.22

Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.23

GPIOs (general-purpose inputs / outputs) . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.24

ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.25

Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.26

Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 19

Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/79

DS5934 Rev 6

STM32F102x4, STM32F102x6

4

5

6

Contents

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 29

Embedded reset and power control block characteristics . . . . . . . . . . . 30

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.3.9

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.3.10

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.3.11

Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 48

5.3.12

I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.3.13

I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.3.14

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3.15

TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3.16

Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3.17

12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.3.18

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.1

LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.2

LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.3

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

DS5934 Rev 6

3/79

4

7

8

Contents STM32F102x4, STM32F102x6

6.4

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.4.1

Evaluating the maximum junction temperature for an application . . . . . 75

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4/79

DS5934 Rev 6

STM32F102x4, STM32F102x6

List of tables

List of tables

Table 1.

Table 2.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM32F102x4 and STM32F102x6 low-density USB access line features

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

STM32F102xx USB access line family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Low-density STM32F102xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 10.

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 11.

Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 12.

Maximum current consumption in Run mode, code with data processing running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 13.

Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 14.

Max. current consumption in Sleep mode, code running from Flash memory or RAM. . . . 34

Table 15.

Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 34

Table 16.

Typical current consumption in Run mode, code with data processing running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 17.

Typical current consumption in Sleep mode, code running from Flash memory or RAM . . 38

Table 18.

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 19.

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 20.

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 21.

HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 22.

LSE oscillator characteristics (f

LSE

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 23.

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 24.

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 25.

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 26.

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 27.

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 28.

Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 29.

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 30.

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 31.

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 32.

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 33.

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 34.

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 35.

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 36.

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 37.

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 38.

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 39.

I

2

C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 40.

SCL frequency (f

PCLK1

= 36 MHz, V

DD_I2C

= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 41.

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 42.

USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 43.

USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 44.

USB: Full speed electrical characteristics of the driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

DS5934 Rev 6

5/79

6

List of tables STM32F102x4, STM32F102x6

Table 45.

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 46.

R

AIN

max for f

ADC

= 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 47.

ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 48.

ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 49.

TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 50.

LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 51.

LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 52.

Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 53.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6/79

DS5934 Rev 6

STM32F102x4, STM32F102x6

List of figures

List of figures

Figure 1.

STM32F102T8 medium-density USB access line block diagram . . . . . . . . . . . . . . . . . . . . 11

Figure 2.

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 3.

STM32F102xx medium-density USB access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . 20

Figure 4.

STM32F102xx medium-density USB access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . 20

Figure 5.

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 6.

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 8.

Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 9.

Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 10.

Typical current consumption in Run mode versus temperature (at 3.6 V), code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 33

Figure 11.

Typical current consumption in Run mode versus temperature (at 3.6 V), code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 33

Figure 12.

Typical current consumption on V

BAT for different V

BAT

with RTC on versus temperature

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 13.

Typical current consumption in Stop mode with regulator in Run mode versus temperature, V

DD

= 3.3 / 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14.

Typical current consumption in Stop mode with regulator in Low-power mode versus temperature, V

DD

= 3.3 / 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 15.

Typical current consumption in Standby mode versus temperature, V

DD

= 3.3 / 3.6 V . . . 36

Figure 16.

High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 17.

Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 18.

Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 19.

Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 20.

Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 21.

Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 22.

5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 23.

5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 24.

I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 25.

Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 26.

I

2

C bus AC waveforms and measurement circuit

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 27.

SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 28.

SPI timing diagram - slave mode and CPHA=1

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 29.

SPI timing diagram - master mode

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 30.

USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 31.

ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 32.

Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 33.

Power supply and reference decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 34.

LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 68

Figure 35.

LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 36.

LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 37.

LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 71

Figure 38.

LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 39.

LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 40.

LQFP64 P

D

max vs. T

A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DS5934 Rev 6

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7

Introduction

1 Introduction

STM32F102x4, STM32F102x6

This datasheet provides the ordering information and mechanical device characteristics of

STM32F102x4 and STM32F102x6 low-density USB access line microcontrollers. For more details on the whole STMicroelectronics STM32F102xx family refer to

Section 2.2: Full compatibility throughout the family .

The medium-density STM32F102xx datasheet must be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory refer to STM32F10xxx Flash memory microcontrollers (PM0075) .

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com

.

For information on the Arm ® Cortex ® -M3 core

Reference Manual, available from the Arm ®

(a) refer to the Cortex

website.

® -M3 Technical

8/79

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS5934 Rev 6

STM32F102x4, STM32F102x6

2 Description

Description

The STM32F102xx medium-density USB access line incorporates the high-performance

Arm ® Cortex ® -M3 32-bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (Flash memory of 16 or 32 Kbytes and SRAM of 4 or 6 Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (one I 2 C, one SPI, one USB and two

USARTs), one 12-bit ADC and two general-purpose 16-bit timers.

The STM32F102xx family operates in the –40 to +85 °C temperature range, from a 2.0 to

3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F102xx medium-density USB access line is delivered in the LQFP48 7 × 7 mm and LQFP64 10 × 10 mm packages.

The STM32F102xx medium-density USB access line microcontrollers are suitable for a wide range of applications.

• Application control and user interface

• Medical and handheld equipment

• PC peripherals, gaming and GPS platforms

• Industrial applications: PLC, inverters, printers, and scanners

• Alarm systems, Video intercom, and HVAC

Figure 1 shows the general block diagram of the device family.

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67

Description STM32F102x4, STM32F102x6

Table 2. STM32F102x4 and STM32F102x6 low-density USB access line features and peripheral counts

Peripheral STM32F102Cx STM32F102Rx

Flash memory - Kbytes

SRAM - Kbytes

Timers

Communication interfaces

General purpose

SPI

I 2 C

USART

USB

12-bit synchronized ADC number of channels

GPIOs

CPU frequency

Operating voltage

Operating temperature

Packages

2

1

1

1

16

4

2

2

1

1

1

32

6

2

2

1

1

1

16

4

2

1

10 channels

1

16 channels

37 51

48 MHz

2.0 to 3.6 V

Ambient temperature: –40 to +85 °C (see

Table 8

)

Junction temperature: –40 to +105 °C (see

Table 8 )

LQFP48 LQFP64

2

1

1

1

32

6

2

10/79

DS5934 Rev 6

STM32F102x4, STM32F102x6 Description

Figure 1. STM32F102T8 medium-density USB access line block diagram

TRACECLK

TRACED[0:3] as AS

JNTRST

JTDI

JTCK/SWCLK

JTMS/SWDIO

JTDO as AF

NRST

VDDA

VSSA

51AF

PA[ 15:1]

PB[ 15:0]

PC[15:0]

PD[2:0]

MOSI,MISO,

SCK,NSS as AF

RX,TX, CTS, RTS,

Smart Card as AF

TPIU

SW/JTAG

Cortex M3 CPU

F max

: 48 MHz

NVIC

NVIC pbus

Dbus

Syst em

Ibus

GP DMA

7 channels

@VDDA

SUPPLY

SUPERVISION

POR / PDR

PVD

Rst

Int

EXTI

WAKEUP

GPIOA

GPIOB

GPIOC

GPIOD

SPI

USART1

Trace

Flash 32 KB

64 bit

POWER

VOLT. REG.

3.3 V to 1.8 V

@VDD

AHB2

APB2

SRAM

6 KB

@VDD

PCLK1

PCLK 2

HCLK

FCLK

RC 8 MHz

RC 40 kHz

@VDDA

PLL &

CLOCK

MANAGT

AHB2

APB 1

XTAL OSC

4-16 MHz

IWDG

Stand by

in terface

@VBAT

XTAL 32 kHz

RTC

AWU

Backup reg

Backup interface

TIM2

TIM3

USART2

I2C

USB 2.0 FS

W W D G

V

DD

= 2 to 3.6 V

V

SS

OSC_IN

OSC_OUT

V

BAT

OSC32_IN

OSC32_OUT

TAMPER-RTC

4 Chann els

4 Chann els

RX,TX, CTS, RTS,

CK, SmartCard as AF

SCL,SDA,SMBA L as AF

USBDP, USBDM as AF

16AF

@VDDA

12bit ADC1 IF

Temp sen so r ai15452b

1. AF = alternate function on I/O port pin.

2. T

A

= –40 °C to +85 °C (junction temperature up to 105 °C).

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67

Description STM32F102x4, STM32F102x6

OSC_OUT

OSC_IN

OSC32_IN

OSC32_OUT

MCO

Figure 2. Clock tree

To Flash prog. if FLITFCLK

8 MHz

HSI RC

PLLSRC

4-16 MHz

HSE OSC

HSI

PLLMUL

..., x16 x2, x3, x4

PLL

/2

PLLXTPRE

HSI

PLLCLK

HSE

SW

SYSCLK

48 MHz

max

USB

Prescaler

/1, 1.5

AHB

Prescaler

/1, 2..512

48 MHz

USBCLK to USB interface

48 MHz max

/8

APB1

Prescaler

/1, 2, 4, 8, 16

HCLK to AHB bus, core, memory and DMA

Clock

Enable (3 bits) to Cortex System timer

FCLK Cortex free running clock

24 MHz max

Peripheral Clock

Enable (13 bits)

PCLK1 to APB1 peripherals

CSS

TIM2, TIM3

If (APB1 prescaler =1) x1 else x2 to TIM2, TIM3

TIMXCLK

Peripheral Clock

Enable (2 bits)

APB2

Prescaler

/1, 2, 4, 8, 16

48 MHz max

Peripheral Clock

Enable (11 bits)

PCLK2 to APB2 peripherals

/2

LSE OSC

32.768 kHz

/128

LSE

RTCCLK to RTC

ADC

Prescaler

/2, 4, 6, 8 to ADC

ADCCLK

LSI RC

40 kHz

RTCSEL[1:0]

LSI to Independent Watchdog (IWDG)

IWDGCLK

Legend:

HSE = high-speed external clock signal

HSI = high-speed internal clock signal

LSI = low-speed internal clock signal

LSE = low-speed external clock signal

Main

Clock Output

MCO

/2 PLLCLK

HSI

HSE

SYSCLK ai15455b

1. For the USB function to be available, both HSE and PLL must be enabled, with the USB clock output

(USBCLK) at 48 MHz.

2. To have an ADC conversion time of 1.2 µs, APB2 must be at 12 MHz, 24 MHz or 48 MHz.

3. The Flash memory programming interface clock (FLITFCLK) is always the HSI clock.

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Description

The STM32F102xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F102x4 and STM32F102x6 are referred to as low-density devices and the STM32F102x8 and STM32F102xB are referred to as medium-density devices.

Low-density devices are an extension of the STM32F102x8/B devices, they are specified in the STM32F102x4/6 datasheet. Low-density devices feature lower Flash memory and RAM capacities, a timer and a few communication interfaces less.

The STM32F102x4 and STM32F102x6 are a drop-in replacement for the STM32F102x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle.

Moreover the STM32F102xx family is fully compatible with all existing STM32F101xx access line and STM32F103xx performance line devices.

Pins

Table 3. STM32F102xx USB access line family

Low-density STM32F102xx devices Medium-density STM32F102xx devices

16 KB

Flash memory

32 KB

Flash memory

(1)

64 KB

Flash memory

128 KB

Flash memory

4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM

64

48

2 × USARTs, 2 × 16-bit timers

1 × SPI, 1 × I

2

C, 1 × ADC, 1 × USB

3 × USARTs, 3 × 16-bit timers

2 × SPIs, 2 × I2Cs, 1 × ADC, 1 × USB

36 -

2 × USARTs,

3 × 16-bit timers

1 × SPI, 1 × I2C,

1 × ADC, 1 × USB

-

1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the reference datasheet for electrical characteristics is the one of the STM32F102x8/B medium-density devices.

2.3 Overview

2.3.1 Arm

®

Cortex

®

-M3 core with embedded Flash memory and SRAM

The Arm ® Cortex ® -M3 processor is the latest generation of Arm ® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The Arm ® Cortex ® -M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an Arm ® core in the memory size usually associated with 8- and 16-bit devices.

The STM32F102xx medium-density USB access line having an embedded Arm ® core is therefore compatible with all Arm ® tools and software.

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67

Description STM32F102x4, STM32F102x6

2.3.3

16 or 32 Kbytes of embedded Flash is available for storing programs and data.

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity, In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

2.3.5

4 or 6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

Nested vectored interrupt controller (NVIC)

The STM32F102xx medium-density USB access line embeds a nested vectored interrupt controller able to handle up to 36 maskable interrupt channels (not including the 16 interrupt lines of Cortex ® -M3) and 16 priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Makes possible early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

2.3.7

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The external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect external line with pulse width lower than the Internal APB2 clock period. Up to 51 GPIOs are connected to the 16 external interrupt lines.

Clocks and startup

System clock selection is performed on startup. however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

DS5934 Rev 6

STM32F102x4, STM32F102x6 Description interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the High Speed APB

(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 48 MHz. See

Figure 2 for details on the clock tree.

2.3.9

At startup, boot pins are used to select one of five boot options:

• Boot from User Flash

• Boot from System Memory

• Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details refer to AN2606, available on www.st.com

.

Power supply schemes

• V

DD

= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.

Provided externally through V

DD

pins.

• V

SSA

, V

DDA

= 2.0 to 3.6 V: External analog power supplies for ADC. Reset blocks, RCs and PLL (minimum voltage to be applied to V

DDA

V

DDA

and V

SSA must be connected to V

DD and V is 2.4 V when the ADC is used).

SS

, respectively.

• V

BAT

= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

DD

is not present.

For more details on how to connect power pins, refer to

Figure 8: Power supply scheme .

2.3.10 Power supply supervisor

The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in Reset mode when V

DD external reset circuit.

is below a specified threshold, V

POR/PDR

, without the need for an

The device features an embedded programmable voltage detector (PVD) that monitors the

V

DD

/ V

DDA

power supply and compares it to the V generated when V

DD higher than the V

PVD

/V

DDA

drops below the V

PVD

threshold. An interrupt can be

PVD

threshold and/or when V

DD

/ V message and/or put the MCU into a safe state. The PVD is enabled by software.

DDA

is

threshold. The interrupt service routine can then generate a warning

Refer to

Table 10: Embedded reset and power control block characteristics

for the values of

V

POR/PDR

and V

PVD

.

The regulator has three operation modes: main (MR), low power (LPR) and power down.

• MR is used in the nominal regulation mode (Run)

• LPR is used in the Stop mode

• Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

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67

Description STM32F102x4, STM32F102x6

This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output.

Note:

The STM32F102xx medium-density USB access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

The Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in Low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and registers content are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.

2.3.13 DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I 2 C, USART, general purpose timers

TIMx and ADC.

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

V

DD

supply when present or through the V

BAT

pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when V

DD

power is not present.

The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Description periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock. it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

This timer is dedicated for OS, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

There are two synchronizable general-purpose timers embedded in the STM32F102xx medium-density USB access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature four independent channels each for input capture, output compare, PWM or one-pulse mode output. This gives up to twelve input captures / output compares / PWMs on the LQFP48 and LQFP64 packages.

The general-purpose timers can work together via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode.

Any of the general-purpose timers can be used to generate PWM outputs. They both have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

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67

Description STM32F102x4, STM32F102x6

2.3.19 I

²

C bus

One I²C bus interface can operate in multi-master and slave modes. It can support standard and fast modes. It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded.

The I 2 C interface can be served by DMA and they support SM Bus 2.0/PM Bus.

The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability.

The USART interfaces can be served by the DMA controller.

2.3.21 Serial peripheral interface (SPI)

The SPI is able to communicate up to 12 Mbit/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

The SPI can be served by the DMA controller.

The STM32F102xx medium-density USB access line embeds an USB device peripheral compatible with the USB full-speed 12 Mbit/s. The USB interface implements a full-speed

(12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main

PLL (the clock source must use a HSE crystal oscillator).

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

The 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Description

The temperature sensor has to generate a a voltage that varies linearly with temperature.

The conversion range is between 2 V < V

DDA

< 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel, which is used to convert the sensor output voltage into a digital value.

The Arm ® SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

DS5934 Rev 6

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67

Pinout and pin description

3 Pinout and pin description

STM32F102x4, STM32F102x6

Figure 3. STM32F102xx medium-density USB access line LQFP48 pinout

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1-OSC_OUT

NRST

VSSA

VDDA

PA0-WKUP

PA1

PA2

1

2

3

48 47 46 45 44 43 42 41 40 39 38 37

36

35

34

4

5

33

32

6 31

LQFP48

7

8

9

10

30

29

28

27

11

12

13 14 15 16 17 18 19 20 21 22 23 24

26

25

VDD_2

VSS_2

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12 ai14378d

Figure 4. STM32F102xx medium-density USB access line LQFP64 pinout

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VDDA

PA0-WKUP

PA1

PA2

1

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

2 47

3 46

4 45

5 44

6 43

7 42

8 41

LQFP64

9 40

10 39

11 38

12 37

13 36

14 35

15 34

16

17 18 19 20 21 22 23 24 25 26 27 28

33

29 30 31 32

VDD_2

VSS_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12 ai14387c

20/79

DS5934 Rev 6

STM32F102x4, STM32F102x6

Pins

Pinout and pin description

Table 4. Low-density STM32F102xx pin definitions

Alternate functions (3) (4)

Pin name

Main function

(3)

(after reset) Default Remap

11 15

12 16

13 17

-

18

19

14 20

15 21

16 22

17 23

24

25

18 26

19 27

3

4

5

1

2

6

7

-

8

9

-

-

-

9

10

11

12

13

6

7

8

1 V

BAT

2 PC13-TAMPER-RTC

(5)

3

4

PC14-OSC32_IN

(5)

PC15-OSC32_OUT

(5)

5 OSC_IN

OSC_OUT

NRST

PC0

PC1

PC2

PC3

V

SSA

V

DDA

I/O

I/O

I/O

S

S

S

I/O

I/O

I/O

I/O FT

-

-

-

-

I/O FT

I/O

I/O -

-

-

-

-

-

-

10 14 PA0-WKUP I/O -

PA1

PA2

PA3

V

SS_4

V

DD_4

PA4

PA5

PA6

I/O

I/O

PA7 I/O

PC4 I/O

PC5 I/O

PB0 I/O

PB1 I/O

I/O

I/O

I/O

I/O

S

S

-

-

-

-

-

-

-

-

-

-

-

-

-

PA1

PA2

PA3

V

SS_4

V

DD_4

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

V

BAT

PC13

(6)

PC14

(6)

PC15

(6)

OSC_IN

OSC_OUT

NRST

PC0

PC1

PC2

PC3

V

SSA

V

DDA

PA0

-

TAMPER-RTC -

-

OSC32_IN

OSC32_OUT

-

-

-

PD0 (7)

PD1

(7)

-

-

ADC_IN10 -

ADC_IN11 -

ADC_IN12 -

ADC_IN13 -

-

-

WKUP/USART2_CTS/

ADC_IN0/

TIM2_CH1_ETR

(8)

USART2_RTS/

ADC_IN1/TIM2_CH2

(8)

-

-

-

-

USART2_TX/

ADC_IN2/TIM2_CH3

(8)

USART2_RX/

ADC_IN3/TIM2_CH4

(8)

-

-

SPI_NSS

(8)

/ADC_IN4

USART2_CK/

SPI_SCK

(8)

/ADC_IN5 -

SPI_MISO

(8)

/ADC_IN6/

TIM3_CH1 (8)

-

SPI_MOSI

(8)

/ADC_IN7/

TIM3_CH2

(8)

-

-

-

ADC_IN14 -

ADC_IN15 -

ADC_IN8/TIM3_CH3

(8)

-

ADC_IN9/TIM3_CH4

(8)

-

-

-

-

DS5934 Rev 6

21/79

67

20 28

21 29

22 30

23 31

24 32

25 33

26 34

27 35

28 36

37

38

39

40

29 41

30 42

31 43

32 44

33 45

34 46

35 47

36 48

37 49

38 50

-

-

-

-

39 55

51

52

53

54

Pinout and pin description

Pins

STM32F102x4, STM32F102x6

Table 4. Low-density STM32F102xx pin definitions (continued)

Alternate functions (3) (4)

Pin name

Main function

(3)

(after reset) Default Remap

PB15

PC6

PC7

PC8

PC9

PA8

PB2 I/O FT PB2/BOOT1

PB10 I/O FT PB10

PB11

V

SS_1

V

DD_1

PB12

PB13

PB14

I/O

S

S

I/O

FT

-

-

FT

I/O FT

I/O FT

PB11

V

SS_1

V

DD_1

PB12

PB13

PB14

PA9

PA10

PA11

PA12

PA13

V

V

SS_2

DD_2

PA14

I/O

I/O

I/O

I/O

FT

FT

FT

FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O

I/O

I/O

S

S

I/O

FT

FT

FT

-

-

FT

PB15

PC6

PC7

PC8

PC9

PA8

PA9

PA10

PA11

PA12

JTMS-

SWDIO

V

SS_2

V

DD_2

JTCK/

SWCLK

PA15

PC10

PC11

PC12

PD2

PB3

I/O

I/O

I/O

I/O

I/O

I/O

FT

FT

FT

FT

FT

FT

JTDI

PC10

PC11

PC12

PD2

JTDO

-

(8)

(8)

-

-

(8)

-

TIM2_CH3

TIM2_CH4

-

-

-

-

-

-

-

-

-

-

-

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

USART1_CK/MCO -

USART1_TX

(8)

USART1_RX

(8)

-

-

USART1_CTS/USB_DM -

USART1_RTS/USB_DP -

-

-

-

-

PA13

-

-

PA14

-

-

-

-

TIM2_CH1_ETR

/ PA15

/SPI_NSS

-

-

-

-

- -

TIM2_CH2/ PB3/

TRACESWO/

SPI_SCK

22/79

DS5934 Rev 6

STM32F102x4, STM32F102x6

Pins

Pinout and pin description

Table 4. Low-density STM32F102xx pin definitions (continued)

Alternate functions (3) (4)

Pin name

Main function

(3)

(after reset) Default Remap

40

41

42

43

56

57

58

59

PB4

PB5

PB6

PB7

I/O

I/O

I/O

I/O

FT

-

FT

FT

JNTRST

PB5

PB6

PB7

-

TIM3_CH1 / PB4

SPI_MISO

I2C_SMBA

TIM3_CH2 /

SPI_MOSI

I2C_SCL (8) USART1_TX

I2C_SDA

(8)

USART1_RX

-

- I2C_SCL

44 60

45 61

BOOT0

PB8

I -

I/O FT

BOOT0

PB8

46 62 PB9 I/O FT PB9 - I2C_SDA

47

48

63

64

V

SS_3

V

DD_3

S

S -

V

SS_3

V

DD_3

-

-

-

-

1. I = input, O = output, S = supply.

2. FT= 5 V-tolerant.

3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to

Table 3 .

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the

Battery backup domain and BKP register description sections in the STM32F102xx reference manual, available from www.st.com

.

7. The pins number 5 and 6 in the LQFP48 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function

I/O and debug configuration section in the STM32F10xxx reference manual.

The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.

8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from www.st.com

.

DS5934 Rev 6

23/79

67

Memory mapping STM32F102x4, STM32F102x6

The memory map is shown in Figure 5 .

Figure 5. Memory map

0xFFFF FFFF

7

0xE010 0000

0xE000 0000

Cortex-M3 internal peripherals

6

0xC000 0000

5

0xA000 0000

4

0x8000 0000

3

0x6000 0000

2

0x4000 0000

Peripherals

1

0x2000 17FF

0x2000 0000

0

SRAM

0x0000 0000

Reserved

0x1FFF FFFF

0x1FFF F80F

0x1FFF F800 reserved

Option Bytes

System memory

0x1FFF F000 reserved

0x0800 FFFF

Flash memory

0x0800 0000

0x0000 0000

Aliased to Flash or system memory depending on

BOOT pins

APB memory space

0xFFFF FFFF reserved

0xE010 0000

0xE000 0000

Cortex-M3 internal peripherals

0x4002 3400 reserved

CRC

0x4002 3000 reserved

0x4002 2400

0x4002 2000

Flash interface

0x4002 1400 reserved

0x4002 1000

RCC

0x4002 0400 reserved

0x4002 0000

0x4000 0000

DMA reserved

0x4001 3C00

USART1

0x4001 3800 reserved

0x4001 3400

SPI

0x4001 3000 reserved

0x4001 2C00 reserved

0x4001 2800

ADC1

0x4001 2400 reserved

0x4001 1800

0x4001 1400

0x4001 1000

Port C

0x4001 0C00

Port B

0x4001 0800

Port A

0x4001 0400

0x4000 5400

EXTI

0x4001 0000

AFIO reserved

0x4000 7400

PWR

0x4000 7000

BKP

0x4000 6C00 reserved

0x4000 6400

0x4000 6000

512 byte USB SRAM

0x4000 5C00

USB registers reserved

0x4000 5800

I2C

0x4000 4800 reserved

0x4000 4400

USART2 reserved

0x4000 3400

Port D

0x4000 3000

IWDG

0x4000 2C00

WWDG

0x4000 2800

RTC

0x4000 0800 reserved

0x4000 0400

TIM3

TIM2 ai15454b

24/79

DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

5.1.1

Unless otherwise specified, all voltages are referred to V

SS

.

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

A

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3

σ

).

Unless otherwise specified, typical data are based on T

A

= 25 °C, V

DD

2 V ≤ V tested.

DD

= 3.3 V (for the

≤ 3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2

σ

)

.

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.5

The loading conditions used for pin parameter measurement are shown in Figure 6 .

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 7 .

DS5934 Rev 6

25/79

67

Electrical characteristics

Figure 6. Pin loading conditions

STM32F102x4, STM32F102x6

Figure 7. Pin input voltage

STM32F102 pin STM32F102 pin

C = 50 pF

VIN ai14972 ai14973

5.1.6 Power supply scheme

Figure 8. Power supply scheme

VBAT

1.8-3.6 V

Po wer swi tch

Backup circuitry

(OSC32K,RTC,

Wake-up logic

Backup registers)

GP I/O s

OUT

IN

IO

Logic

VDD

3 × 100 nF

+ 1 × 4.7 µF

VDD

VDD

1/2/3/4

VSS

1/2/3/4

VDDA

Regulator

10 nF

+ 1 µF

V

REF+

ADC

V

REF-

Analog:

RCs, PLL,

...

VSSA

Caution: In Figure 8 , the 4.7 µF capacitor must be connected to V

DD3

.

Kernel logic

(CPU,

Digital

& Memories) ai14882c

26/79

DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

Figure 9. Current consumption measurement scheme

IDD_VBAT

VBAT

5.2

IDD

VDD

VDDA ai14126

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 5

,

Table 6

, and

Table 7

may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile

(application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Symbol

Table 5. Voltage characteristics

Ratings Min Max Unit

V

|V

V

|

DD

V

Δ

V

IN

(2)

V

SSX

DDx

− V

SS

|

SS

ESD(HBM)

|

External main supply voltage (including

V

DDA and V

DD

)

(1)

Input voltage on 5 V-tolerant pin

Input voltage on any other pin

Variations between different V

DD power pins

Variations between all the different ground pins

Electrostatic discharge voltage

(human body model)

V

V

–0.3

SS

SS

-

-

−

−

0.3

0.3

4.0

V

DD

+ 4.0

4.0

50

50

V mV

See

Section 5.3.11: Absolute maximum ratings (electrical sensitivity)

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

SS

, V

SSA

) pins must always be connected to the external power

2. V

IN

maximum must always be respected. Refer to Table 6

for the maximum allowed injected current values.

DS5934 Rev 6

27/79

67

Electrical characteristics STM32F102x4, STM32F102x6

Symbol

Table 6. Current characteristics

Ratings Max.

Unit

I

I

VDD

VSS

I

INJ(PIN)

(2)

Total current into V

DD

/V

DDA power lines (source)

(1)

Total current out of V

SS ground lines (sink)

(1)

Output current sunk by any I/O and control pin

150

150

25

I

IO

Output current source by any I/Os and control pin

Injected current five volt tolerant pins

(3)

Injected current on any other pin

(4)

Total injected current (sum of all I/O and control pins)

(5)

-25

-5/+0

± 5 mA

Σ I

INJ(PIN)

± 25

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

SS

, V

SSA

) pins must always be connected to the external power

2. Negative injection disturbs the analog performance of the device.

3. Positive injection is not possible on these I/Os. A negative injection is induced by V

never be exceeded. Refer to Table 5

for maximum allowed input voltage values.

IN

<V

SS

. I

INJ(PIN)

must

4. A positive injection is induced by V

never be exceeded. Refer to Table 5

>V

DD

while a negative injection is induced by V for maximum allowed input voltage values.

IN

<V

SS

. I

INJ(PIN) must

5. When several inputs are submitted to a current injection, the maximum Σ I positive and negative injected currents (instantaneous values).

INJ(PIN) is the absolute sum of the

Symbol

T

STG

T

J

Table 7. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

°C

28/79

DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

5.3.1 General operating conditions

Symbol

Table 8. General operating conditions

Parameter Conditions Min Max Unit f f

V f

HCLK

PCLK1

PCLK2

V

DD

DDA

(1)

V

P

T

IN

D

A

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage -

-

-

-

0

2

0

0

48

24

48

3.6

MHz

V

Analog operating voltage

(ADC not used)

Analog operating voltage

(ADC used)

Must be the same potential as V

DD

(2)

2

2.4

3.6

3.6

I/O input voltage

Standard IO

FTIO

(3)

–0.3

V

DD

0.3

+

2 V < V

DD

≤ 3.6 V –0.3

5.5

V

DD

= 2 V –0.3

5.2

0 5.5

BOOT0

LQFP48

Power dissipation at T

A

= 85 °C

(4)

LQFP64

Ambient temperature

Maximum power dissipation

Low power dissipation

(5)

-

-

–40

363

444

85

–40 105

V mW

°C

°C

T J Junction temperature range –40 105 °C

1. When the ADC is used, refer to

Table 45: ADC characteristics .

2. It is recommended to power V between V

DD

and V

DDA

DD

and V

DDA

from the same source. A maximum difference of 300 mV

can be tolerated during power-up and operation.

3. To sustain a voltage higher than V

DD

+0.3 V, the internal pull-up/pull-down resistors must be disabled.

4. If T is lower, higher P

Thermal characteristics

values are allowed as long as T

).

J

does not exceed T

J

max (see Section 6.3:

5. In low power dissipation state, T

A

can be extended to this range as long as T

Section 6.3: Thermal characteristics ).

J

does not exceed T

J max (see

Subject to general operating conditions for T

A

.

Symbol t

VDD

Table 9. Operating conditions at power-up / power-down

Parameter Conditions Min

V

DD

rise time rate

V

DD

fall time rate

-

0

20

Max

∞

∞

Unit

µs/V

DS5934 Rev 6

29/79

67

Electrical characteristics

5.3.3

STM32F102x4, STM32F102x6

Embedded reset and power control block characteristics

The parameters given in

Table 10 are derived from tests performed under ambient

temperature and V

DD

supply voltage conditions summarized in

Table 8

.

.

Symbol

Table 10. Embedded reset and power control block characteristics

Parameter Conditions Min Typ Max Unit

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

2.1

2.18

2.26

2.0

2.08

2.16

2.19

2.28

2.37

2.09

2.18

2.27

2.28

2.38

2.48

2.18

2.28

2.38

2.38

2.48

2.58

V

PVD

Programmable voltage detector level selection

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

2.28

2.38

2.48

2.47

2.58

2.69

2.37

2.48

2.59

2.57

2.68

2.79

2.47

2.58

2.69

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

2.66

2.56

2.76

2.78

2.68

2.88

2.9

2.8

3

V

PVDhyst

(2) PVD hysteresis

PLS[2:0]=111 (falling edge)

-

2.66

2.78

2.9

-

1.8

(1)

100

1.88

-

1.96

V mV

V

POR/PDR

V

PDRhyst t

RSTTEMPO

(2)

Power on/power down reset threshold

PDR hysteresis

Reset temporization

Falling edge

Rising edge

-

-

1.84

1.92

2.0

-

1.5

1. The product behavior is guaranteed by design down to the minimum V

POR/PDR

value.

2. Guaranteed by design, not tested in production.

40

2.5

-

4.5

V

V mV ms

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

The parameters given in

Table 11 are derived from tests performed under ambient

temperature and V

DD

supply voltage conditions summarized in

Table 8

.

30/79

DS5934 Rev 6

STM32F102x4, STM32F102x6

5.3.5

Electrical characteristics

Symbol

Table 11. Embedded internal reference voltage

Parameter Conditions Min Typ Max Unit

T

S_vrefint

(1)

V

V

REFINT

RERINT

(2)

Internal reference voltage

ADC sampling time when reading the internal reference voltage

–40 °C < T

A

< +85 °C 1.16

1.20

1.24

5.1

17.1

(2)

Internal reference voltage spread over the temperature range

V

DD

= 3 V ±10 mV 10

V

µs mV

T

Coeff

(2)

Temperature coefficient 100 ppm/

°C

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design, not tested in production.

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as shown in Figure 9

.

All Run mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

DD

or V

SS

(no load)

• All peripherals are disabled except if it is explicitly mentioned

• The Flash access time is adjusted to f

HCLK wait state from 24 to 48 MHz)

frequency (0 wait state from 0 to 24 MHz, 1

• Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)

• When the peripherals are enabled f

PCLK1

= f

HCLK/2

, f

PCLK2

= f

HCLK

The parameters given in

Table 12 are derived from tests performed under ambient

temperature and V

DD

supply voltage conditions summarized in

Table 8

.

DS5934 Rev 6

31/79

67

Electrical characteristics STM32F102x4, STM32F102x6

Table 12. Maximum current consumption in Run mode, code with data processing running from Flash memory

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

T

A

= 85 °C

48 MHz 32

I

DD

Supply current in Run mode

External clock

(2)

, all peripherals enabled

External clock

(2)

, all peripherals Disabled

36 MHz

24 MHz

16 MHz

8 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

23

19

13

10

6

26

18

13

7 mA

1. Based on characterization results, not tested in production.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

Table 13. Maximum current consumption in Run mode, code with data processing running from RAM

Max

Symbol Parameter Conditions f

HCLK

Unit

T

A

= 85 °C (1)

External clock

(2)

, all peripherals enabled

48 MHz

36 MHz

24 MHz

I

DD

Supply current in

Run mode

16 MHz

8 MHz

48 MHz

36 MHz

24 MHz

External clock

(2)

all peripherals disabled

16 MHz

8 MHz

1. Based on characterization, tested in production at V

DD max, f

HCLK

max.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

10

6

19

15

10

7

5

27

20

14 mA

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

Figure 10. Typical current consumption in Run mode versus temperature (at 3.6 V), code with data processing running from RAM, peripherals enabled

30

25

20

15

10

48 MHz

36MHz

16 MHz

8 MHz

5

0

–40 °C 25 °C 0 °C

Temperature (°C)

70 °C 85 °C

Figure 11. Typical current consumption in Run mode versus temperature (at 3.6 V), code with data processing running from RAM, peripherals disabled

12

10

8

6

4

2

0

20

18

16

14

48 MHz

36 MHz

16 MHz

8 MHz

–40 °C 25 °C 0 °C

Temperature (°C)

70 °C 85 °C

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Electrical characteristics STM32F102x4, STM32F102x6

Table 14. Max. current consumption in Sleep mode, code running from Flash memory or RAM

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

T

A

= 85 °C

48 MHz 17

I

DD

Supply current in

Sleep mode

External clock

(2)

, all peripherals enabled

External clock

(2)

, all peripherals disabled

36 MHz

24 MHz

16 MHz

8 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

6

5

4.5

4

3

7

4

14

10 mA

1. Based on characterization, tested in production at V

DD max and f

HCLK

max with peripherals enabled.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

Table 15. Typical and maximum current consumptions in Stop and Standby modes

Typ

(1)

Max

Symbol Parameter Conditions V

DD

/

V

BAT

2.4 V

=

V

DD

/V

BAT

= 3.3 V

V

DD

/V

BAT

= 2.0 V

T

A

=

85 °C

Unit

I

DD

I

DD_VBAT

Supply current in Stop mode

Regulator in Run mode.

Low-speed and high-speed internal

RC oscillators and high-speed oscillator OFF (no independent watchdog)

Regulator in Low Power mode.

Low-speed and high-speed internal

RC oscillators and high-speed oscillator OFF (no independent watchdog)

Low-speed internal RC oscillator and independent watchdog ON

Supply current in Standby mode

(2)

Low-speed internal RC oscillator ON, independent watchdog OFF

Low-speed internal RC oscillator and independent watchdog OFF, lowspeed oscillator and RTC OFF

Backup domain supply current

Low-speed oscillator and RTC ON

1. Typical values are measured at T

A

= 25 °C.

21.3

11.3

2.75

2.55

1.55

1.1

21.7

11.7

3.4

3.2

1.9

1.4

-

-

-

-

-

0.9

160

145

-

-

3.2

1.9

(3)

µA

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

2. To have the Standby consumption with RTC ON, add I

V

DD

is present the Backup Domain is powered by V

DD_VBAT

(Low-speed oscillator and RTC ON) to I

DD

Standby (when

DD

supply).

3. Based on characterization, not tested in production.

15

10

5

0

30

25

20

Figure 12. Typical current consumption on V

BAT for different V

BAT

with RTC on versus temperature

values

2.5

2

1.5

1

0.5

0

2 V

2.4 V

3 V

3.6 V

–40 °C 25 °C 70 °C

Temperature (°C)

85 °C 105 °C ai17351

Figure 13. Typical current consumption in Stop mode with regulator in Run mode versus temperature, V

DD

= 3.3 / 3.6 V

45

40

35

3.3 V

3.6 V

–45 °C 25 °C

Temperature (°C)

85 °C

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Electrical characteristics STM32F102x4, STM32F102x6

Figure 14. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature, V

DD

= 3.3 / 3.6 V

30

5

0

15

10

25

20

3.3 V

3.6 V

–45 °C 25 °C

Temperature (°C)

85 °C

Figure 15. Typical current consumption in Standby mode versus temperature, V

DD

= 3.3 / 3.6 V

3.5

3

2.5

2

1.5

1

0.5

0

3.3 V

3.6 V

–45 °C 25 °C 85 °C

Temperature (°C)

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

Typical current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

DD

or V

SS

(no load)

• All peripherals are disabled except if it is explicitly mentioned

• The Flash access time is adjusted to f

HCLK wait state from 24 to 48 MHz)

frequency (0 wait state from 0 to 24 MHz, 1

• Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)

• When the peripherals are enabled f

PCLK1 f

ADCCLK

= f

PCLK2

/ 4

= f

HCLK/4

, f

PCLK2

= f

HCLK/2

,

The parameters given in

Table 16 are derived from tests performed under ambient

temperature and V

DD

supply voltage conditions summarized in

Table 8

.

Table 16. Typical current consumption in Run mode, code with data processing running from Flash memory

Typ

(1)

Typ

(1)

Symbol Parameter Conditions f

HCLK All peripherals enabled

(2)

All peripherals disabled

Unit

I

DD

Supply current in

Run mode

External clock (3)

Running on high speed internal RC

(HSI), AHB prescaler used to reduce the frequency

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

21.9

17.2

11.2

8.1

5

3

2

1.5

1.2

1.05

21.2

16.5

10.5

7.4

4.3

2.4

1.5

1.0

0.7

0.5

1. Typical values are measures at T

A

= 25 °C, V

DD

= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

1.4

1.2

1

16.7

13.1

8.2

17.4

13.8

8.9

6.6

4.2

2.6

1.8

5.9

3.6

2

1.3

0.9

0.65

0.45

mA

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67

Electrical characteristics STM32F102x4, STM32F102x6

3. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

Table 17. Typical current consumption in Sleep mode, code running from Flash memory or RAM

Typ

(1)

Typ

(1)

Symbol Parameter Conditions f

HCLK All peripherals enabled

(2)

All peripherals disabled

Unit

I

DD

Supply current in

Sleep mode

External clock

Running on High

Speed Internal

RC (HSI), AHB prescaler used to reduce the frequency

(3)

1 MHz

500 kHz

125 kHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

1. Typical values are measures at T

A

= 25 °C, V

DD

= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

6.1

4.2

2.8

1.4

1.1

1.05

1

8.1

0.9

0.7

0.55

0.48

0.4

8.7

6.7

4.8

3.4

2

1.5

1.25

2.5

1.7

1.2

0.55

0.98

0.96

0.95

3.2

0.5

0.45

0.42

0.4

0.38

3.8

3.1

2.3

1.8

1.2

1.1

1 mA

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

Table 18 . The MCU is placed

under the following conditions:

• all I/O pins are in input mode with a static value at V

DD

or V

SS

(no load)

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

• ambient operating temperature and V

DD

Table 5

.

supply voltage conditions as summarized in

Table 18. Peripheral current consumption (1)

Peripheral µA/MHz

AHB (up to 48 MHz)

APB1 (up to 24 MHz)

DMA1

CRC

BusMatrix

(2)

15.97

1.67

8.33

7.22

APB1-Bridge

TIM2

TIM3

USART2

I2C1

USB

WWDG

PWR

BKP

IWDG

1.94

2.78

1.39

APB2-Bridge 3.33

GPIOA 7.50

33.33

33.61

12.78

10.83

16.94

3.33

APB2 (up to 48 MHz)

GPIOB

GPIOC

GPIOD

6.81

7.22

6.94

SPI1

USART1

4.86

12.78

ADC1

(3) (4) 15.54

1. f

HCLK

= 48 MHz, f

APB1

= f

HCLK

/2, f

APB2

= f

HCLK

, default prescaler value for each peripheral.

2. The BusMatrix is automatically active when at least one master is ON.

3. Specific conditions for ADC: f

HCLK

= 48 MHz, f

APB1

= f

HCLK

/2, f

APB2

= f

HCLK

, f

ADCCLK

= f

APB2

/4.

4. When ADON bit in the ADC_CR2 register is set to 1, there is an additional current consumption of 0.68 mA.

When the ADC is enabled there is an additional current consumption of 0.06 mA.

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Electrical characteristics STM32F102x4, STM32F102x6

High-speed external user clock generated from an external source

The characteristics given in

Table 19 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

Table 8

.

Symbol

Table 19. High-speed external user clock characteristics

Parameter f

HSE_ext

V

HSEH

V

HSEL t w(HSE) t w(HSE) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

I

L

User external clock source frequency

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

(1)

(1)

OSC_IN input capacitance

Duty cycle

(1)

OSC_IN Input leakage current

1. Guaranteed by design, not tested in production.

(1)

Conditions

-

V

SS

≤ V

IN

≤ V

DD

Min

1

0.7V

DD

V

SS

5

-

-

45

Typ

-

-

8

-

-

-

-

5

20

-

55

±1

Max

25

V

DD

0.3V

DD

-

Unit

MHz

V ns pF

%

µA

Low-speed external user clock generated from an external source

The characteristics given in

Table 20 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in Table 8 .

Symbol

Table 20. Low-speed external user clock characteristics

Parameter f

LSE_ext

V

LSEH

V

LSEL t w(LSE) t w(LSE) t r(LSE) t f(LSE)

C in(LSE)

DuCy

(LSE)

I

L

User external clock source frequency

OSC32_IN high or low time

OSC32_IN rise or fall time

(1)

(1)

OSC32_IN input capacitance

(1)

(1)

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

Duty cycle

OSC32_IN Input leakage current

1. Guaranteed by design, not tested in production.

Conditions

-

V

SS

≤ V

IN

≤ V

DD

Min

-

0.7V

DD

V

SS

450

-

-

30

-

Typ

32.768

5

-

-

-

-

-

-

Max

1000

V

DD

0.3V

DD

-

50

-

70

±1

Unit kHz

V ns pF

%

µA

40/79

DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

Figure 16. High-speed external clock source AC timing diagram

VHSEH

VHSEL

90%

10% tr(HSE)

THSE tf(HSE) tW(HSE) tW(HSE) t

External clock source fHSE_ext

OSC _IN

IL

STM32F102xx

Figure 17. Low-speed external clock source AC timing diagram ai14975b

VLSEH

VLSEL

90%

10% tr(LSE)

TLSE tf(LSE)

External clock source fLSE_ext

OSC32_IN tW(LSE)

IL

STM32F102xx tW(LSE) t ai14976b

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Electrical characteristics STM32F102x4, STM32F102x6

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in

Table 21 . In

the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 21. HSE 4-16 MHz oscillator characteristics (1)(2)

Parameter Conditions Min Typ Max Unit f

OSC_IN

R

F

Oscillator frequency

Feedback resistor -

4

-

8

200

16

-

MHz k Ω i

C

2

Recommended load capacitance versus equivalent serial resistance of the crystal (R

S

)

(3)

R

S

= 30 Ω

HSE driving current

Oscillator transconductance

V

DD

V

IN

= 3.3 V

= V

SS with 30 pF load

Startup

-

30

-

-

1 pF mA g m t

SU(HSE)

(4)

Startup time V

DD

is stabilized

25

-

-

2 -

mA/V ms

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization results, not tested in production.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

L1

and C

L2

it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to

match the requirements of the crystal or resonator (see Figure 18

). C

L1

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance that is the series combination of C

L1

and C

L2

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

C

L1

and C

L2 www.st.com

.

. Refer to Oscillator design guide for ST microcontrollers (AN2867) available on

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

Figure 18. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

CL1

OSC_IN fHSE

8 MH z resonator

RF

Bias controlled gain

REXT(1)

OSC_OU T STM32F102xx

CL2 ai14977b

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in

Table 22 . In

the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 22. LSE oscillator characteristics (f

LSE

= 32.768 kHz)

Parameter Conditions Min Typ Max Unit

R

F

Feedback resistor 5 M Ω

C

(1)

Recommended load capacitance versus equivalent serial resistance of the crystal (R

S

)

R

S

= 30 k Ω 15 pF

I

2

LSE driving current

V

DD

= 3.3 V

V

IN

= V

SS

-

1.4

µA g m

Oscillator transconductance 5 µA/V t

SU(LSE)

(2)

Startup time V

DD

is stabilized

T

A

= 50 °C

T

A

= 25 °C

T

A

= 10 °C

T

A

= 0 °C

T

A

= -10 °C

T

A

= -20 °C

T

A

= -30 °C

T

A

= -40 °C -

-

-

-

-

-

-

1.5

2.5

4.0

6.0

10.0

17.0

32.0

60.0

-

-

-

-

-

-

-

s

1. Refer to the note and caution paragraphs below the table, and to Oscillator design guide for ST microcontrollers (AN2867).

2. t

SU(LSE)

is the startup time measured from the moment it is enabled by software to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and can vary significantly with the crystal manufacturer, PCB layout and humidity.

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Electrical characteristics STM32F102x4, STM32F102x6

Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to

15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.

Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + C stray where C stray is between 2 pF and 7 pF.

is the pin capacitance and board or trace PCB-related capacitance. Typically, it

Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF.

Example: For a resonator with a load capacitance of CL = 6 pF, and C stray

CL1 = CL2 = 8 pF.

= 2 pF, then

Figure 19. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

C

L1

OSC32_IN f

HSE

32.768 kHz resonator

R

F

Bias controlled gain

OSC32_OUT

C

L2

STM32 ai17531c

5.3.7 Internal clock source characteristics

The parameters given in

Table 23 are derived from tests performed under ambient

temperature and V

DD

supply voltage conditions summarized in

Table 8

.

High-speed internal (HSI) RC oscillator

Symbol

Table 23. HSI oscillator characteristics (1)

Parameter Conditions Min Typ Max Unit f

HSI

DuCy

(HSI)

I t

ACC

HSI su(HSI)

(4)

DD(HSI)

(4)

Frequency

Duty cycle

-

-

User-trimmed with the RCC_CR register

(2)

-

45

-

Accuracy of the HSI oscillator

Factorycalibrated

(4)(5)

T

A

= –40 to 105 °C –2.0

T

A

= –10 to 85 °C –1.5

T

A

= 0 to 70 °C

T

A

= 25 °C

–1.3

–1.1

HSI oscillator startup time

HSI oscillator power consumption

-

1

-

8

-

-

-

-

-

-

-

80

55

1

-

(3)

2.5

2.2

2

1.8

2

100

1. V

DD

= 3.3 V, T

A

= –40 to 105 °C unless otherwise specified.

2. Refer to STM32F10xxx internal RC oscillator (HSI) calibration (AN2868) “” available from www.st.com

.

MHz

%

%

µs

µA

%

%

%

%

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

3. Guaranteed by design, not tested in production.

4. Based on characterization, not tested in production.

5. The actual frequency of HSI oscillator may be impacted by a reflow, but does not drift out of the specified range.

Low-speed internal (LSI) RC oscillator

Symbol

Table 24. LSI oscillator characteristics (1)

Parameter Min

(2) f

LSI t su(LSI)

(3)

I

DD(LSI)

(3)

Frequency 30

LSI oscillator startup time

LSI oscillator power consumption

1. V

DD

= 3 V, T

A

= −

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production.

-

-

Typ

40

-

0.65

Max

60

85

1.2

Unit kHz

µs

µA

Wakeup time from Low-power mode

The wakeup times given in

Table 25 is measured on a wakeup phase with a 8-MHz HSI RC

oscillator. The clock source used to wake up the device depends from the current operating mode:

• Stop or Standby mode: the clock source is the RC oscillator

• Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and V

DD voltage conditions summarized in

Table 8

.

supply

Table 25. Low-power mode wakeup timings

Symbol Parameter Typ Unit t

WUSLEEP

(1)

Wakeup from Sleep mode 1.8

t

WUSTOP

(1)

Wakeup from Stop mode (regulator in run mode) 3.6

µs

Wakeup from Stop mode (regulator in low-power mode) 5.4

t

WUSTDBY

(1)

Wakeup from Standby mode 50

1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction.

The parameters given in

Table 26 are derived from tests performed under ambient

temperature and V

DD

supply voltage conditions summarized in

Table 8

.

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67

Electrical characteristics STM32F102x4, STM32F102x6

Table 26. PLL characteristics

Value

Symbol Parameter Unit

Min

(1)

Typ Max

(1) f

PLL_IN f

PLL_OUT t

LOCK

Jitter

PLL input clock (2)

PLL input clock duty cycle

PLL multiplier output clock

PLL lock time

Cycle-to-cycle jitter

1

40

16

-

-

8.0

-

-

-

-

25

60

48

200

300

1. Based on characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

.

MHz

%

MHz

µs ps

Flash memory

The characteristics are given at T

A

= –40 to 85 °C unless otherwise specified.

Symbol

Table 27. Flash memory characteristics

Parameter Conditions t t

ERASE

I t prog

ME

DD

16-bit programming time

Page (1 KB) erase time

Mass erase time

Supply current

T

A

= –40 to +85 °C

T

A

= –40 to +85 °C

T

A

= –40 to +85 °C

Read mode f

HCLK

= 48 MHz with 2 wait states, V

DD

= 3.3 V

Write / Erase modes f

HCLK

3.3 V

= 48 MHz, V

DD

=

Power-down mode / Halt,

V

DD

= 3.0 to 3.6 V

V prog

Programming voltage

1. Guaranteed by design, not tested in production.

-

Min (1)

40

20

20

-

-

-

2

Typ Max (1)

52.5

-

-

70

40

40

-

-

-

20

5

50

3.6

Unit

µs ms ms mA mA

µA

V

Symbol

Table 28. Flash memory endurance and data retention

Value

Parameter Conditions

Min

(1)

Typ Max

N

END t

RET

Endurance

Data retention T

A

= 85 °C, 1000 cycles

1. Based on characterization not tested in production.

10

30 -

-

-

-

Unit kcycles

Years

46/79

DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling two LEDs through I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A burst of fast transient voltage (positive and negative) is applied to V

DD

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 29

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

V

FESD

V

EFTB

Table 29. EMS characteristics

Parameter Conditions

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

DD

and V to induce a functional disturbance

SS pins

V

DD

= 3.3 V, T

A

= +25 °C, f

HCLK

= 48 MHz conforms to IEC 61000-4-2

V

DD

= 3.3 V, T

A

= +25 °C, f

HCLK

= 48 MHz conforms to IEC 61000-4-4

Level/Class

2B

4A

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application.

Software recommendations: the software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical data corruption (control registers, etc.)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for one second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

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Electrical characteristics STM32F102x4, STM32F102x6

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling two LEDs through the I/O ports), This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 30. EMI characteristics

Symbol Parameter

S

EMI

Conditions

Monitored frequency band

0.1 MHz to 30 MHz

Peak level V

DD

= 3.3 V, T

A

= 25 °C.

30 MHz to 130 MHz

130 MHz to 1GHz

SAE EMI Level

Max vs. [f

HSE

/f

HCLK

]

8/48 MHz

7

8

13

3.5

Unit dBµV

-

5.3.11 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Symbol

Table 31. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value

(1)

Unit

V

V

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage

(human body model)

T

A

= +25 °C, conforming to JESD22-A114

Electrostatic discharge voltage

(charge device model)

T

A

= +25 °C, conforming to ANSI/ESD STM5.3.1

1. Based on characterization results, not tested in production.

2

II

2000

500

V

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78 IC latch-up standard.

Symbol

LU

Parameter

Table 32. Electrical sensitivities

Conditions

Static latch-up class T

A

= +105 °C conforming to JESD78A

Class

II level A

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

DD

or

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation).

The test results are given in Table 33

.

Symbol

I

INJ

Table 33. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

Injected current on OSC_IN32,

OSC_OUT32, PA4, PA5, PC13

Injected current on all FT pins

Injected current on any other pin

-0

-5

-5

+0

+0

+5

Unit mA

General input/output characteristics

Unless otherwise specified, the parameters given in

Table 34 are derived from tests

performed under the conditions summarized in Table 8 . All I/Os are CMOS and TTL

compliant.

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Electrical characteristics STM32F102x4, STM32F102x6

Symbol Parameter

Table 34. I/O static characteristics

Conditions Min Typ Max

V

IL

V

IH

V hys

I lkg

R

PU

Low level input voltage

Standard IO input low level voltage

IO FT

(3)

input low level voltage

All I/Os except

BOOT0

High level input voltage

Standard IO input high level voltage

IO FT

(3)

input high level voltage

All I/Os except

BOOT0

0.41*(V

DD

-2 V)+1.3 V

(1)

0.42*(V

DD

-

-

-

-2 V)+1 V

0.65V

DD

(2)

(1)

Standard IO Schmitt trigger voltage hysteresis

(4)

IO FT Schmitt trigger voltage hysteresis (4)

-

200

5% V

DD

(5)

Input leakage current

(6)

V

SS

≤ V

IN

≤ V

DD

Standard I/Os

V

IN

= 5 V

I/O FT

-

-

Weak pull-up equivalent resistor (7)

V

IN

= V

SS

30

-

-

-

-

-

-

-

-

0.28*(V

DD

-2 V)+0.8 V (1)

0.32*(V

DD

-2V)+0.75 V

(1)

40

0.35V

DD

(2)

-

-

-

-

-

± 1

3

50

R

PD

Weak pull-down equivalent resistor

(7)

V

IN

= V

DD

30 40 50

C

IO

I/O pin capacitance 5 -

1. Data based on design simulation.

2. Tested in production.

3. FT = 5-Volt tolerant, In order to sustain a voltage higher than V disabled.

DD

+0.3 the internal pull-up/pull-down resistors must be

4. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

5. With a minimum of 100 mV.

6. Leakage can be higher than max if negative current is injected on adjacent pins.

7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. The

PMOS/NMOS contribution to the series resistance is small (~10%)

.

Unit

V mV

µA k Ω pF

50/79

DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in

Figure 20 and Figure 21 for standard I/Os, and

in

Figure 22 and Figure 23 for 5 V tolerant I/Os.

V

IH

/ V

IL

(V)

Figure 20. Standard I/O input characteristics - CMOS port

V

IH min

1.3

V

IL max

0.8

0.7

Area not determined

Tested in production

CMOS standard requirement V

1.71

1.59

1.0

1.08

IH

= 0.65 V

DD

1.71

1.96

V

IH

= 0.41 (V

DD

- 2) + 1.3 V

1.08

1.25

V

IL

= 0.28 (V

DD

IL

= 0.35 V DD

Tested in production CMOS standard requirement V

V

DD

(V)

2.0

2.7

3.0

3.3

3.6

MS52673V1

V

IH

/ V

IL

(V)

Figure 21. Standard I/O input characteristics - TTL port

Area not determined

TTL requirement V

IH

= 2.0 V

V

IH min

2.0

1.96

1.25

V

IH

= 0.41 (V

DD

- 2) + 1.3 V

Based on simulations

- 2) + 0.8 V

V

IL

= 0.28 (V

DD

1.3

V

IL max

0.8

TTL requirement V

IL

= 0.8 V

V

DD

(V)

2.0

2.16

3.6

MS52674V1

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Electrical characteristics STM32F102x4, STM32F102x6

Figure 22. 5 V tolerant I/O input characteristics - CMOS port

V

IH

/ V

IL

(V)

Area not determined

IH

= 0.65 V

DD

V

IH min

1.3

V

IL max

0.7

Tested in production

1.00

0.75

CMOS standard requirement V

1.295

0.975

1.42

1.07

Tested in production CMOS standard requirement V

1.67

V

IH

= 0.42 (V

DD

- 2) + 1.0 V

1.55

1.16

1.25

IL

= 0.35 V DD

V

IL

= 0.32 (V

DD

V

DD

(V)

2.0

2.7

3.0

3.3

3.6

MS52672V1

V

IH

/ V

IL

(V)

Figure 23. 5 V tolerant I/O input characteristics - TTL port

Area not determined

TTL requirement V

IH

= 2.0 V

2.0

1.67

1.00

V

IH

= 0.42 (V

DD

- 2) + 1.0 V

Based on simulations

V

IL

= 0.32 (V

DD

- 2) + 0.75 V

V

IH min

V

IL max

0.80

0.75

TTL requirement V

IL

= 0.8 V

V

DD

(V)

2.0

2.16

3.6

MS52675V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ± 8 mA, and sink or source up to ± 20 mA (with a relaxed V

OL

/V

OH

) except PC13, PC14 and PC15, which can sink or source up to ± 3 mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum ratings specified in

Section 5.2

.

• The sum of the currents sourced by all the I/Os on V

DD,

I consumption of the MCU sourced on V

DD

VDD

(see

Table 6

). plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

SS

I consumption of the MCU sunk on V

SS

VSS

(see

Table 6

).

plus the maximum Run

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in

Table 35 are derived from tests

performed under ambient temperature and V

DD

Table 8 . All I/Os are CMOS and TTL compliant.

supply voltage conditions summarized in

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

Symbol

Table 35. Output voltage characteristics

Parameter Conditions Min Max Unit

V

V

V

V

V

V

V

V

OL

(1)

OH

(3)

OL

(1)

OH

(3)

OL

(1)

OH

(3)

OL

(1)

OH

(3)

Output Low level voltage for an I/O pin when 8 pins are sunk at the same time

Output High level voltage for an I/O pin when 8 pins are sourced at the same time

Output low level voltage for an I/O pin when 8 pins are sunk at the same time

Output high level voltage for an I/O pin when 8 pins are sourced at the same time

CMOS port

I

IO

= +8 mA.

2.7 V < V

DD

< 3.6 V

TTL port

(2)

(2)

I

IO

= +8 mA

.

2.7 V < V

DD

< 3.6 V

Output low level voltage for an I/O pin when 8 pins are sunk at the same time

Output high level voltage for an I/O pin when 8 pins are sourced at the same time

I

IO

= +20 mA

(4)

2.7 V < V

DD

< 3.6 V

Output low level voltage for an I/O pin when 8 pins are sunk at the same time

Output high level voltage for an I/O pin when 8 pins are sourced at the same time

I

IO

= +6 mA

(4)

2.0 V < V

DD

< 2.7 V

V

V

V

DD

-

-

–0.4

2.4

DD

DD

-

-

–1.3

–0.4

0.4

-

-

0.4

-

1.3

-

0.4

1. The I

IO

current sunk by the device must always respect the absolute maximum rating specified in

Table 6

and the sum of I

IO

(I/O ports and control pins) must not exceed I

VSS

.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I

Table 6

current sourced by the device must always respect the absolute maximum rating specified in

and the sum of I

IO

(I/O ports and control pins) must not exceed I

VDD

.

4. Based on characterization data, not tested in production.

V

V

V

V

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Electrical characteristics STM32F102x4, STM32F102x6

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 24

and

Table 36 , respectively.

Unless otherwise specified, the parameters given in

Table 36 are derived from tests

performed under ambient temperature and V

DD

Table 8 .

supply voltage conditions summarized in

Table 36. I/O AC characteristics (1)

MODEx

[1:0] bit value (1)

Symbol Parameter Conditions Max Unit

10

01

11

f f max(IO)out t t f(IO)out r(IO)out max(IO)out t t f(IO)out r(IO)out

F max(IO)out t t f(IO)out r(IO)out

Maximum frequency

(2)

Output high to low level fall time

Output low to high level rise time

Maximum frequency

(2)

C

C

L

L

= 50 pF, V

= 50 pF, V

DD

DD

= 2 V to 3.6 V

= 2 V to 3.6 V

C

L

= 50 pF, V

DD

= 2 V to 3.6 V

Output high to low level fall time

Output low to high level rise time

C

L

= 50 pF, V

DD

= 2 V to 3.6 V

Maximum Frequency

(2)

Output high to low level fall time

Output low to high level rise time

2

125

125

10

25

25

(3)

(3)

(3)

(3)

MHz ns

MHz ns

C

L

= 30 pF, V

DD

= 2.7 V to 3.6 V 50 MHz

C

L

= 50 pF, V

DD

= 2.7 V to 3.6 V 30 MHz

C

L

= 50 pF, V

DD

= 2 V to 2.7 V 20

C

L

= 30 pF, V

DD

= 2.7 V to 3.6 V 5 (3)

MHz

C

L

= 50 pF, V

DD

= 2.7 V to 3.6 V 8

(3)

C

L

= 50 pF, V

DD

= 2 V to 2.7 V 12

(3) ns

C

L

= 30 pF, V

DD

= 2.7 V to 3.6 V 5

(3)

C

L

= 50 pF, V

DD

= 2.7 V to 3.6 V 8

(3)

C

L

= 50 pF, V

DD

= 2 V to 2.7 V 12

(3) t

EXTIpw

Pulse width of external signals detected by the EXTI controller

10 ns

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register.

2. The maximum frequency is defined in

Figure 24 .

3. Guaranteed by design, not tested in production.

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

Figure 24. I/O AC characteristics definition

90% 10%

50%

10%

50%

90%

EXTERNAL

OUTPUT

ON 50pF tr(IO)out

T tf(IO)out

Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131c

5.3.14 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

PU

(see

Table 34 ).

Unless otherwise specified, the parameters given in

Table 37 are derived from tests

performed under ambient temperature and V

DD

Table 8 .

supply voltage conditions summarized in

Table 37. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

V

IL(NRST)

(1)

V

IH(NRST)

(1)

NRST Input low level voltage

NRST Input high level voltage -

–0.5

2 -

0.8

V

DD

+0.5

V

V hys(NRST)

R

PU

V

F(NRST)

(1)

V

NF(NRST)

(1)

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST Input filtered pulse

NRST Input not filtered pulse

V

-

IN

=

-

-

V

SS

-

30

-

300

200

40

-

-

-

50

100

mV

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10%).

k Ω ns ns

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Electrical characteristics STM32F102x4, STM32F102x6

Figure 25. Recommended NRST pin protection

External reset circuit (1)

NRST(2)

VDD

RPU

0.1 μF

Filter

Internal Reset

STM32F ai14132c

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 39 . Otherwise the reset will not be taken into account by the device.

max level specified in

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

The parameters given in

Table 38 are guaranteed by design.

Refer to Section 5.3.13

for details on the input/output alternate function characteristics

(output compare, input capture, external clock, PWM output).

Symbol

Table 38. TIMx

(1)

characteristics

Parameter Conditions Min

1 t res(TIM)

Timer resolution time f

EXT

Res

TIM

Timer external clock frequency on CH1 to CH4

Timer resolution

f

TIMxCLK

= 48 MHz 20.84

0 f

TIMxCLK

= 48 MHz

-

0

t

COUNTER

16-bit counter clock period when internal clock is selected

f

TIMxCLK

1

= 48 MHz 0.0208

t

MAX_COUNT

-

Maximum possible count

f

TIMxCLK

= 48 MHz -

1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.

Max

-

f

TIMxCLK

/2

24

16

65536

Unit t

TIMxCLK ns

MHz

MHz bit t

TIMxCLK

µs 1365

65536 × 65536 t

TIMxCLK

89.48

s

I

2

C interface characteristics

The STM32F102xx medium-density USB access line I 2 C interface meets the requirements of the standard I 2 C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the

PMOS connected between the I/O pin and V

DD is disabled, but is still present.

The I 2 C characteristics are described in

Table 39

. Refer also to

Section 5.3.13

for more

details on the input/output alternate function characteristics (SDA and SCL).

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Electrical characteristics STM32F102x4, STM32F102x6

Symbol

Table 39. I 2 C characteristics

Standard mode I

2

C

(1)(2)

Parameter

Min Max

Fast mode I

2

C

(1) (2)

Min Max

Unit t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

4.7

4.0

250

-

-

-

-

-

-

3450

(3)

1000

300

1.3

0.6

100

-

-

-

-

-

-

900

(3)

300

300

µs ns t su(STA)

Start condition hold time

Repeated Start condition setup time

4.0

4.7

-

0.6

-

0.6 -

µs t su(STO)

Stop condition setup time t w(STO:STA)

Stop to Start condition time (bus free)

4.0

4.7

-

0.6

1.3

-

µs

µs t

SP

Pulse width of spikes that are suppressed by the analog filter

0 50

(4)

0

50

(4)

ns

C b

Capacitive load for each bus line 400 400 pF

1. Values guaranteed by design, not tested in production.

2. f

PCLK1

must be at least 2 MHz to achieve standard mode I achieve fast mode I mode clock.

2

C frequencies. It must be at least 4 MHz to

C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C fast

3. The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL signal.

4. The analog filter minimum filtered spikes is above t filtered.

SP(max)

to ensure that spikes width up to t

SP(max)

are

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

Figure 26. I 2 C bus AC waveforms and measurement circuit (1)

VDD_I2C VDD_I2C

I²C bus

Rp Rp

Rs

Rs

STM32F10x

SDA

SCL

Start repeated

Start

Start tsu(STA)

SDA tf(SDA) th(STA) tr(SDA) tw(SCLL) tsu(SDA) th(SDA)

Stop tsu(STO:STA)

SCL tw(SCLH) tr(SCL) tf(SCL) tsu(STO) ai14133e

1. Measurement points are done at CMOS levels: 0.3V

DD

and 0.7V

DD.

Table 40. SCL frequency (f

PCLK1

= 36 MHz, V

DD_I2C

= 3.3 V)

(1)(2)

I2C_CCR value f

SCL

(kHz)

R

P

= 4.7 k Ω

400

300

200

100

0x801E

0x8028

0x803C

0x00B4

50 0x0168

20 0x0384

1. R

P

= External pull-up resistance, f

SCL

= I

2

C speed.

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ± 5%. For other speed ranges, the tolerance on the achieved speed ± 2%. These variations depend on the accuracy of the external components used to design the application.

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67

Electrical characteristics STM32F102x4, STM32F102x6

SPI interface characteristics

Unless otherwise specified, the parameters given in

Table 41 are derived from tests

performed under ambient temperature, f

PCLKx summarized in

Table 8

.

frequency and V

DD

supply voltage conditions

Refer to Section 5.3.13

for more details on the input/output alternate function characteristics

(NSS, SCK, MOSI, MISO).

Symbol Parameter

Table 41. SPI characteristics

Conditions Min Max Unit

1/t f

SCK c(SCK)

SPI clock frequency

Master mode

Slave mode

-

-

18

18

MHz t r(SCK) t f(SCK)

SPI clock rise and fall time

Capacitive load: C = 30 pF 8 ns

DuCy(SCK)

SPI slave input clock duty cycle

Slave mode 30 70 % t su(NSS)

(1) t h(NSS)

(1) t t w(SCKH)

(1) w(SCKL)

(1) t t su(MI)

(1) su(SI)

(1)

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Slave mode

Slave mode

Master mode, f presc = 4

Master mode

PCLK

= 36 MHz,

4t

2t

PCLK

PCLK

50

5 -

-

-

60

Slave mode 5 t h(MI)

(1) t h(SI)

(1) t a(SO)

(1)(2) t dis(SO)

(1)(3) t v(SO)

(1) t v(MO)

(1) t h(SO)

(1) t h(MO)

(1)

Data input hold time

Master mode

Slave mode

Data output access time Slave mode, f

Data output disable time Slave mode

Data output valid time

Data output valid time

Data output hold time

PCLK

= 20 MHz

Slave mode (after enable edge)

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

5

4

0

2

-

-

15

2

3t

PCLK

10

-

-

-

-

25

5

1. Based on characterization, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z ns

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DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

Figure 27. SPI timing diagram - slave mode and CPHA=0

Figure 28. SPI timing diagram - slave mode and CPHA=1 (1)

NSS input t

SU(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t w(SCKH) t w(SCKL) t a(SO)

MISO

OUTPUT

MOSI

INPUT t su(SI) t v(SO)

MSB OUT t h(SI)

MSB IN t c(SCK) t h(SO)

BIT6 OUT

BIT 1 IN t h(NSS) t r(SCK) t f(SCK) t dis(SO)

LSB OUT

LSB IN

1. Measurement points are done at CMOS levels: 0.3V

DD

and 0.7V

DD.

ai14135b

DS5934 Rev 6

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67

Electrical characteristics STM32F102x4, STM32F102x6

Figure 29. SPI timing diagram - master mode (1)

NSS input

High

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tc(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

B I T1 OUT th(MO)

1. Measurement points are done at CMOS levels: 0.3V

DD

and 0.7V

DD.

USB characteristics

The USB interface is USB-IF certified (full speed).

Symbol t

STARTUP

Table 42. USB startup time

Parameter

USB transceiver startup time

Max

1 tr(SCK) tf(SCK)

LSB IN

LSB OUT

Unit

µs ai14136c

62/79

DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

Symbol

Table 43. USB DC electrical characteristics

Parameter Conditions Min.

(1)

Max.

(1)

Unit

Input levels

Output levels

V

DD

V

DI

(4)

V

CM

(4)

V

SE

(4)

V

OL

V

OH

USB operating voltage

(2)

Differential input sensitivity

-

I(USB_DP, USB_DM)

Differential common mode range Includes V

DI range

Single ended receiver threshold -

Static output level low

Static output level high

R

L

of 1.5 k Ω to 3.6 V

(5)

R

L

of 15 k Ω to V

SS

(5)

3.0

(3)

0.2

0.8

1.3

-

2.8

3.6

-

2.5

2.0

0.3

3.6

1. All the voltages are measured from the local ground potential.

2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 k Ω resistor to a 3.0-to-3.6 V voltage range.

3. The STM32F102xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V V

DD

voltage range.

4. Guaranteed by design, not tested in production.

5. R

L

is the load connected on the USB drivers

V

V

V

Differential data lines

Figure 30. USB timings: definition of data signal rise and fall time

Cross over points

V

CRS

V

SS t f t r ai14137b

Table 44. USB: Full speed electrical characteristics of the driver

(1)

Symbol Parameter Conditions Min Max t r t f t rfm

V

CRS

Rise time

Fall time

(2)

(2)

Rise/ fall time matching

Output signal crossover voltage

C

L

C

L

= 50 pF

= 50 pF t r

/ t f

-

4

4

90

1.3

20

20

110

2.0

1. Guaranteed by design, not tested in production.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

Unit ns ns

%

V

Note:

Unless otherwise specified, the parameters given in

Table 45 are derived from tests

performed under ambient temperature, f

conditions summarized in Table 8 .

PCLK2 frequency and V

DDA

supply voltage

It is recommended to perform a calibration after each power-up.

DS5934 Rev 6

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67

Electrical characteristics STM32F102x4, STM32F102x6

Symbol Parameter

Table 45. ADC characteristics

Conditions Min Typ Max f

V

V

DDA f

ADC f

S

(1)

TRIG

(1)

AIN

Power supply

ADC clock frequency

Sampling rate

External trigger frequency

Conversion voltage range

(2)

-

f

ADC

= 12 MHz

-

-

-

2.4

0.6

0.05

-

-

0 (V

SSA

V

REFground) or

tied to

-

-

-

-

-

V

3.6

12

0.85

823

17

REF+

R

AIN

(1) External input impedance

See Equation 1 and

Table 46

for details

-

50

R

C

ADC

(1)

ADC

(1)

Sampling switch resistance

Internal sample and hold capacitor

-

-

-

1

8 t t t t

CAL

(1) t t lat

(1) latr

(1)

S

(1)

STAB

(1)

CONV

(1)

Calibration time

Injection trigger conversion latency

Regular trigger conversion latency

Sampling time

Power-up time

Total conversion time

(including sampling time) f f

ADC

= 12 MHz

f

ADC

= 12 MHz

f

ADC

= 12 MHz

-

ADC

= 12 MHz

-

-

-

-

-

0.125

1.5

0

5.9

83

-

-

-

-

-

-

0

0.214

3

(3)

0.143

2

(3)

19.95

239.5

1 f

ADC

= 12 MHz

-

1.2

21

14 to 252 (t

S

for sampling +12.5 for successive approximation)

1. Guaranteed by design, not tested in production.

2. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.

3. For external triggers, a delay of 1/f

PCLK2

must be added to the latency specified in Table 46 .

V

κΩ

κΩ pF

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

µs

Unit

V

MHz

Msps kHz

1/f

ADC

1/f

ADC

Equation 1: R

AIN

R

AIN

< f

ADC

× C

max formula:

T

S

ADC

× ln ( 2 )

ADC

The formula above ( Equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

64/79

DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

T s

(cycles)

1.5

7.5

13.5

28.5

41.5

55.5

71.5

239.5

Table 46. R

AIN

max for f

ADC

= 12 MHz (1) t

S

(µs)

0.13

0.63

1.13

2.38

3.46

4.63

5.96

19.96

1. Data guaranteed by design, not tested in production.

R

AIN

max (k Ω )

0.4

5.9

11.4

25.2

37.2

50

NA

NA

Symbol

Table 47. ADC accuracy - limited test conditions

(1)

Parameter Test conditions

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f f

PCLK2

ADC

V

T

DDA

A

= 48 MHz.

= 12 MHz, R < 10 k Ω .

Measurements made after

ADC calibration

AIN

= 3 V to 3.6 V

= 25 °C

1. ADC DC accuracy values are measured after internal calibration.

2. Based on characterization, not tested in production.

Typ

±1.3

±1

±0.5

±0.7

±0.8

Max

(2)

±2

±1.5

±1.5

±1

±1.5

Unit

LSB

Symbol Parameter

Table 48. ADC accuracy (1) (2) (3)

Test conditions Typ Max

(4)

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

PCLK2 f

ADC

= 48 MHz.

= 12 MHz, R

AIN

V

DDA

= 2.4 V to 3.6 V

Measurements made after

ADC calibration

< 10 k Ω .

±2

±1.5

±1.5

±1

±1.5

±5

±2.5

±3

±2

±3

LSB

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V

DD

, frequency and temperature ranges.

3. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I affect the ADC accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

in Section 5.3.13

does not

4. Based on characterization, not tested in production.

DS5934 Rev 6

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67

Electrical characteristics STM32F102x4, STM32F102x6

Figure 31. ADC accuracy characteristics

[1LSB

IDEAL

=

V

DDA

4096

4095

4094

4093

E

T

5

4

3

2

1

7

6

E

O

0

V

SSA

1 2 3 4 5

1 LSB

E

L

IDEAL

6 7

(2)

E

D

(3)

(1)

E

G

4093 4094 4095 4096

V

DDA

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

E

T

=Total u nadjusted er ror: maximum deviation between the actual and the ideal transfer curves.

E

O

=Offset e rror: deviation between the first actual transition and the first ideal one.

E

G

=Gain er ror: deviation between the last ideal transition and the last actual one.

E

D

=Differential linearity error: maximum deviation between actual steps and the ideal one.

E

L

=Integral linearity error: maximum deviation between any actual transition and the end point correlation line.

ai15497

Figure 32. Typical connection diagram using the ADC

VAIN

RAIN(1)

AINx

Cparasitic

VDD

VT

0.6 V

VT

0.6 V

IL±1 µA

STM32F102

Sample and hold ADC converter

RADC(1)

12-bit converter

CADC(1) ai14974b

1. Refer to Table 46 for the values of R

AIN

, R

ADC

and C

ADC

.

2. C parasitic this, f

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

ADC

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

66/79

DS5934 Rev 6

STM32F102x4, STM32F102x6 Electrical characteristics

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 33

. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip.

Figure 33. Power supply and reference decoupling

STM32F102xx

V

DDA

1 µF // 10 nF

V

SSA ai14980b

5.3.18 Temperature sensor characteristics

Table 49. TS characteristics

Symbol

T

L

(1)

Avg_Slope

(1)

V

25

(1) t

START

(2)

V

SENSE

linearity with temperature

Average slope

Voltage at 25°C

Parameter Min

-

-

-

4

Typ

T

S_temp

(3)(2)

Startup time

ADC sampling time when reading the temperature

-

1. Guaranteed by characterization, not tested in production.

2. Data guaranteed by design, not tested in production.

3. Shortest sampling time can be determined in the application by multiple iterations.

-

±1.5

4.35

1.42

-

Max

-

-

-

10

17.1

Unit

°C mV/°C

V

µs

µs

DS5934 Rev 6

67/79

67

Package characteristics STM32F102x4, STM32F102x6

6.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

.

LQFP48 package information

Figure 34. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

SEATING

PLANE

C ccc C b

37

36

D

D1

D3

25

24

0.25 mm

GAUGE PLANE

K

L1

L

48

PIN 1

IDENTIFICATION

1

1. Drawing is not to scale.

12 e

13

5B_ME_V2

68/79

DS5934 Rev 6

STM32F102x4, STM32F102x6 Package characteristics

Symbol

Table 50. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max e

L

L1

D3

E

E1

E3 k ccc b c

D

D1

A

A1

A2

-

0.050

1.350

0.170

0.090

8.800

6.800

-

8.800

6.800

-

-

0.450

-

0°

-

-

-

1.400

0.220

-

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

-

1.600

0.150

1.450

0.270

0.200

9.200

7.200

-

9.200

7.200

-

-

0.750

-

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

0.3465

0.2677

-

-

0.0177

-

0°

-

-

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

-

-

-

0.0551

0.0087

-

0.3543

0.2756

-

0.3622

0.2835

-

-

0.0295

-

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

DS5934 Rev 6

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76

Package characteristics STM32F102x4, STM32F102x6

Figure 35. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint

0.50

1.20

0.30

37

36 25

24

0.20

7.30

9.70

5.80

7.30

48

1 12

13

1.20

5.80

9.70

ai14911d

1. Dimensions are expressed in millimeters.

Device marking for LQFP48

Figure 36

gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

The printed markings may differ depending upon the supply chain.

Figure 36. LQFP48 marking example (package top view)

Product identification

(1)

Pin 1 identifier

STM32F

102C4T6A R

A

Y WW

Revision code

Date code

(year + week)

70/79

MS38213V1

1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.

Only if ST has authorized in writing the customer qualification Engineering Samples can be used for

DS5934 Rev 6

STM32F102x4, STM32F102x6 reliability qualification trials.

6.2

Package characteristics

LQFP64 package information

Figure 37. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

SEATING PLANE

C

0.25 mm

GAUGE PLANE ccc C

D

D1

D3 L1

L

K

48 33

32 b

49

64 17

PIN 1

IDENTIFICATION

1 e

16

5W_ME_V3

D

D1 b c

A

A1

A2

D3

E

1. Drawing is not to scale.

Table 51. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min

-

0.050

1.350

0.170

0.090

-

-

-

-

Typ

-

-

1.400

0.220

-

12.000

10.000

7.500

12.000

Max

1.600

0.150

1.450

0.270

0.200

-

-

-

-

Min

-

0.0020

0.0531

0.0067

0.0035

-

-

-

-

Typ

-

-

0.0551

0.0087

-

0.4724

0.3937

0.2953

0.4724

Max

0.0630

0.0059

0.0571

0.0106

0.0079

-

-

-

-

DS5934 Rev 6

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76

Package characteristics STM32F102x4, STM32F102x6

Table 51. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

K

L

L1 ccc

E1

E3 e -

-

-

0°

0.450

-

-

10.000

7.500

0.500

3.5°

0.600

1.000

-

-

-

-

7°

0.750

-

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

-

-

0°

0.0177

-

-

Typ

0.3937

0.2953

0.0197

3.5°

0.0236

0.0394

-

Max

-

-

-

7°

0.0295

-

0.0031

Figure 38. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint

72/79

49

48

0.5

33

32

0.3

12.7

10.3

10.3

64 17

1.2

1 16

7.8

12.7

1. Dimensions are expressed in millimeters.

Device marking for LQFP64

Figure 39

is an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

The printed markings may differ depending upon the supply chain.

DS5934 Rev 6 ai14909c

STM32F102x4, STM32F102x6 Package characteristics

Figure 39. LQFP64 marking example (package top view)

Product identification

(1)

Pin 1 identifier

STM32F102

R6T6A R

Y WW

Revision code

Date code

(year + week)

MS38214V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

DS5934 Rev 6

73/79

76

Package characteristics STM32F102x4, STM32F102x6

The maximum chip junction temperature (T

J

Table 8: General operating conditions .

max) must never exceed the values given in

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

T

J

max = T

A

max + (P

D

max × Θ

JA

)

Where:

• T

A

max is the maximum ambient temperature in ° C,

• Θ

JA

is the package junction-to-ambient thermal resistance, in ° C/W,

• P

D

max is the sum of P

INT

max and P

I/O max (P

D

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

V

DD

, expressed in Watts. This is the maximum chip

P

I/O

max represents the maximum power dissipation on output pins where:

P

I/O

max = Σ (V

OL

× I

OL

) + Σ ((V

DD

– V

OH

) × I

OH

), taking into account the actual V

OL application.

/ I

OL

and V

OH

/ I

OH of the I/Os at low and high level in the

Symbol

Θ

JA

Table 52. Package thermal characteristics

Parameter Value

Thermal resistance junction-ambient

LQFP48 - 7 × 7 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP64 - 10 × 10 mm / 0.5 mm pitch

55

45

Unit

°C/W

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

74/79

DS5934 Rev 6

STM32F102x4, STM32F102x6

6.4.1

Package characteristics

Evaluating the maximum junction temperature for an application

When ordering the microcontroller, the temperature range is specified in

Section 7: Ordering information scheme .

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. Here, only temperature range 6 is available (–40 to 85 °C).

The following example shows how to calculate the temperature range needed for a given application, making it possible to check whether the required temperature range is compatible with the STM32F102xx junction temperature range.

Example: High-performance application

Assuming the following application conditions:

Maximum ambient temperature T

Amax

I

DDmax

= 50 mA, V

DD

= 82 °C (measured according to JESD51-2),

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

OL

= 8 mA, V

OL

= 0.4 V and maximum 8 I/Os used at the same time in output mode at low level with I

OL

= 20 mA, V

OL

= 1.3 V

P

INTmax =

50 mA × 3.5 V= 175 mW

P

IOmax = 20

× 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

This gives: P

INTmax

= 175 mW and P

IOmax

= 272 mW

P

Dmax =

175

+

272 = 447 mW

Thus: P

Dmax

= 447 mW

Using the values obtained in Table 52

T

Jmax

is calculated as follows:

– For LQFP64, 45 °C/W

T

Jmax

= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C

This is within the junction temperature range of the STM32F102xx (–40 < T

J

< 105 °C).

Figure 40. LQFP64 P

D

max vs. T

A

700

600

500

400

300

200

100

0

65 75 85 95

T

A

(°C)

105 115

Suffix 6

DS5934 Rev 6

75/79

76

Ordering information scheme

7 Ordering information scheme

STM32F102x4, STM32F102x6

Example:

Device family

STM32 = Arm ® -based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

102 = USB access line, USB 2.0 full-speed interface

STM32 F 102 C 6 T 6 A xxx

Pin count

C = 48 pins

R = 64 pins

Flash memory size

4 = 16 Kbytes of Flash memory

6 = 32 Kbytes of Flash memory

Package

T = LQFP

Temperature range

6 = Industrial temperature range, –40 to 85 °C.

Internal code

“A” or blank

(1)

Options xxx = programmed parts

TR = tape and reel

1. For STM32F102x6 devices with a blank Internal code, please refer to the STM32F103x8/B datasheet available from the ST website: www.st.com

.

76/79

DS5934 Rev 6

STM32F102x4, STM32F102x6 Revision history

Date

23-Sep-2008

Revision

1

09-Apr-2009

24-Sep-2009

2

3

Table 53. Document revision history

Changes

Initial release.

I/O information clarified on page 1 . Figure 1: STM32F102T8 mediumdensity USB access line block diagram and Figure 5: Memory map modified.

In Table 4: low-density STM32F102xx pin definitions : PB4, PB13, PB14,

PB15, PB3/TRACESWO moved from Default column to Remap column,

Note 4.

added.

P

D

value added for LQFP64 package in Table 8: General operating conditions .

Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM .

Figure 13 , Figure 14 and Figure 15 show typical curves.

Figure 31: ADC accuracy characteristics modified.

Figure 33: Power supply and reference decoupling modified. Small text changes.

Table 20: High-speed external user clock characteristics and Table 21:

Low-speed external user clock characteristics modified.

ACC

HSI

max values modified in Table 24: HSI oscillator characteristics .

Note 5.

updated and Note 4.

added in Table 4: low-density STM32F102xx pin definitions . Typical I

DD_VBAT

value added in Table 16: Typical and maximum current consumptions in Stop and Standby modes . Figure 12:

Typical current consumption on V

BAT different V

BAT

values added.

with RTC on versus temperature at f

HSE_ext

min modified in Table 20: High-speed external user clock characteristics .

C

L1

and C

L2

replaced by C in Table 22: HSE 4-16 MHz oscillator characteristics and Table 23: LSE oscillator characteristics (f

LSE

= 32.768 kHz) , notes modified and moved below the tables. Table 24: HSI oscillator characteristics modified. Conditions removed from Table 26: Low-power mode wakeup timings .

Note 1.

modified below Figure 18: Typical application with an 8 MHz crystal .

Figure 25: Recommended NRST pin protection modified.

IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to

IEC 61967-2 in Section 5.3.10: EMC characteristics on page 46 .

Jitter added to Table 27: PLL characteristics .

C

ADC

R

AIN

and R

AIN

parameters modified in Table 47: ADC characteristics .

max values modified in Table 48: R

AIN

max for f

ADC

= 12 MHz .

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78

Revision history STM32F102x4, STM32F102x6

Date

02-Aug-2013

14-May-2015

06-Aug-2019

Table 53. Document revision history (continued)

Revision Changes

4

5

6

Figure 2: Clock tree : added FLITFCLK and Note 3.

, and modified Note 1.

.

Removed sentence in “Unless otherwise specified the parameters ...” in

I2C interface characteristics section.

Added V

IN

in Table 8: General operating conditions .

Added note 5 in

Table 23: HSI oscillator characteristics

Added DuCy

(HSI) in

Table 23: HSI oscillator characteristics

Table 24: LSI oscillator characteristics : removed note 2 related to

oscillator selection, updated Note 2.

, and t

SU(LSE ambient temperature values.

) specified for various

Modified charge device model in

Table 33: I/O current injection susceptibility

.

Updated ‘V

IL

’ and ‘V

IH

’ in Table 34: I/O static characteristics

.

Added notes to

Figure 20: Standard I/O input characteristics - CMOS port

,

Figure 21: Standard I/O input characteristics - TTL port

,

Figure 22: 5 V tolerant I/O input characteristics - CMOS port and Figure 23: 5 V tolerant

I/O input characteristics - TTL port

Table 37: Output voltage characteristics : updated V for TTL and CMOS outputs and added Note 2.

OL

and V

OH conditions

Updated Figure 24: I/O AC characteristics definition

Updated Figure 25: Recommended NRST pin protection

Updated footnotes 2 and 3 in

Table 39: I

2

C characteristics

Updated Figure 26: I2C bus AC waveforms and measurement circuit(1)

Updated title of Table 40: SCL frequency (f

PCLK1

V)

= 36 MHz, V

DD_I2C

= 3.3

In Table 43: SPI characteristics , removed note 1 related to SPI1 remapped characteristics.

Updated Table 47: ADC characteristics

Updated Section 6.1: Package mechanical data

Updated Table 18: Peripheral current consumption and

Table 39: I

2

C characteristics .

Updated Section 6: Package characteristics .

Updated Section 6.2: LQFP64 package information with addition of

Device marking for LQFP64

and Figure 39

.

Updated Section 6.1: LQFP48 package information with addition of

Device marking for LQFP48 and Figure 36

.

Updated Disclaimer.

Updated Section 1: Introduction ,

Section 5.2: Absolute maximum ratings

,

Device marking for LQFP48

and Device marking for LQFP64

.

Updated Figure 19: Typical application with a 32.768 kHz crystal

,

Figure 20: Standard I/O input characteristics - CMOS port , Figure 21:

Standard I/O input characteristics - TTL port ,

Figure 22: 5 V tolerant I/O input characteristics - CMOS port and Figure 23: 5 V tolerant I/O input characteristics - TTL port .

Minor text edits across the whole document.

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DS5934 Rev 6

STM32F102x4, STM32F102x6

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