The STM1403 family of security supervisors are a low-power family of intrusion (tamper) detection chips targeted at manufacturers of POS terminals and other systems, to enable them to meet physical and/or environmental intrusion monitoring requirements as mandated by various standards, such as Federal Information Processing Standards (FIPS)

Pub 140 entitled “Security Requirements for Cryptographic Modules,” published by the

National Institute of Standards and Technology, U.S. Department of Commerce), EMVCo,

ISO, ZKA, and VISA PED. STM1403 supports target levels 3 and lower.

The STM1403 includes automatic battery switchover, RST output (open drain), manual

(push-button) reset input (MR), power-fail comparator (PFI/PFO), physical and/or environmental tamper detect/security alarm, and battery low voltage detect features.

The STM1403A also offers a V

REF

(1.237 V) as an option on pin 9. On the STM1403B/C, this pin is V

TPU

(internally switched V

or V

BAT

1.1 V

OUT

pin modes

The STM1403 is available in three versions, corresponding to three modes of the V

OUT

(supply voltage out), when the SAL (security alarm) is asserted (active-low) upon tamper detection:

1.1.1 STM1403A

OUT

stays ON (at V

or V

BAT

) when SAL is driven low (activated).

1.1.2 STM1403B

OUT

is set to High-Z when SAL is driven low (activated).

1.1.3 STM1403C

OUT

is driven to ground when SAL is activated (may be used when V directly to the V

OUT

is connected

pin of the external SRAM that holds the cryptographic codes).

All variants (see Table 1: Device summary ) are pin-compatible and available in a securityfriendly, low profile, 16-pin QFN package.

Obsolete Product(s) - Obsolete Product(s)

6/34 Doc ID 13232 Rev 6

STM1403 Description

Figure 1.

Logic diagram

BLD

REF

(3)

V or

TPU

(1)

BAT

CCSW

(2)

PFI

TP1 (NH)

STM1403

OUT

RST

(3)

PFO

(3)

SAL

(3)

TP2

(NL)

TP3

(NH)

TP4

(NL)

AI09682

REF

only for STM1403A; V

TPU

for STM1403B/C.

Normal mode: low when V

OUT battery.

is internally switched to V

and high when V

OUT

is internally switched to

SAL, RST, PFO, and BLD are open drain.

Signal names Table 2.

Vccsw

(1)

PFI

switch output

Manual (push-button) reset input

Power-fail Input

- TP

OUT

RST

(2)

PFO

(2)

SAL

(2)

BLD

(2)

REF

(3)

TPU

(3)

BAT

Independent physical tamper detect pins 1 through 4

Supply voltage output

Active-low reset output

Power-fail output

Security alarm output

Battery low voltage detect

1.237 V reference voltage

Tamper pull-up (V

or V

BAT

)

Backup supply voltage

Supply voltage

Ground

Normal mode: low when V

OUT battery.

is internally switched to V

and high when V

OUT

is internally switched to

Obsolete Product(s) - Obsolete Product(s)

REF

only for STM1403A; V

TPU

for STM1403B/C.

Note: See

Section 2: Pin descriptions on page 11 for details.

Doc ID 13232 Rev 6 7/34

Description STM1403

Figure 2.

QFN16 connections

BLD

(2)

PFI V

CCSW

(1)

RST

(2)

SAL

(2)

16 15

5 6

OUT

BAT

PFO

(2)

REF or

TPU

(3)

Note:

TP1

(NH)

TP2

(NL)

TP3

(NH)

TP4

(NL)

AI09683

See

Section 2: Pin descriptions on page 11 for details.

Normal mode: low when V

OUT battery.

is internally switched to V

and high when V

OUT

is internally switched to

SAL, RST, PFO, and BLD are open drain.

REF

only for STM1403A; V

TPU

for STM1403B/C

Figure 3.

Block diagram

VCC

BAT54J

(1,2)

VBAT

(1)

VSO COMPARE

VOUT

VCCSW

VINT VRST COMPARE

PFI trec

Generator

VPFI COMPARE

RST

(3)

PFO

(3)

VDET

COMPARE @

POWER-UP

1.237V VREF

Generator

BLD

(3)

VTPU

(4)

VREF

(4)

VHV COMPARE

VLV COMPARE Obsolete Product(s) - Obsolete Product(s)

TP1 (NH)

TP2 (NL)

TP3 (NH)

TP4 (NL)

SAL

(3)

AI09684

BAT54J (from STMicroelectronics) recommended

Required for battery-reverse charging protection

Open drain

REF

only for STM1403; V

TPU

for STM1403B/C

8/34 Doc ID 13232 Rev 6

STM1403

Figure 4.

Hardware hookup

Description

Unregulated

Voltage

Regulator

VIN VCC

0.1µF

VCCSW

(1)

VCC VOUT

(2)

VCC

LPSRAM

STM1403

Push-Button

BAT54J

(4)

1.0µF

PFI PFO

(3)

MR RST

(3)

VBAT BLD

(3)

To Microprocessor NMI

To Microprocessor Reset

To Microprocessor

From Actuator Device

(e.g., Switches, Wire Mesh)

TP1

TP2

TP3

TP4

SAL

(3)

VREF

(5) or

VTPU

To ADC

To Physical Tamper Pins TPX

AI09690

Normal mode: low when V

OUT battery.

is internally switched to V

and high when V

OUT

is internally switched to

Capacitor (C) is typically

≥

10 µF.

Open drain

Diode is required for battery reverse charge protection.

REF

only for STM1403; V

TPU

for STM1403B/C.

Figure 5.

Tamper pin (TP

or TP

) normally high (NH) external hookup (switch closed)

Switch Normally Closed;

Tamper Detection on Open

(1)

TP1 or TP3

R typical is 10 M Ω . Resistors must be protected against conductive materials.

Doc ID 13232 Rev 6

AI09698

9/34

Description STM1403

Figure 6.

Tamper pin (TP

or TP

) normally high (NH) external hookup (switch open)

VOUT (STM1403A) or

VTPU (STM1403B/C)

(1)

TP1 or TP3

Switch Normally Open

Tamper Detection when Closed

R typical is 10M Ω . Resistors must be protected against conductive materials.

Figure 7.

Tamper pin (TP

or TP

) normally low (NL) external hookup (switch closed)

AI10461

VOUT (STM1403A) or

VTPU (STM1403B/C)

(1)

TP2 or TP4

Switch Normally Closed;

Tamper Detection on Open

AI09699

R typical is 10 M Ω . Resistors must be protected against conductive materials.

Figure 8.

Tamper pin (TP

or TP

) normally low (NL) external hookup (switch open)

VOUT (STM1403A) or

VTPU (STM1403B/C)

Switch Normally Open;

Tamper Detection when Closed

TP2 or TP4

(1)

AI10462

10/34 Doc ID 13232 Rev 6

STM1403 Pin descriptions

See

Figure 1: Logic diagram and Table 2: Signal names

for a brief overview of the signals connected to this device.

2.1 SAL, security alarm output (open drain)

This signal can be generated when ANY of the following conditions occur:

●

INT

> V

BAT

;

, where V

= upper voltage trip limit (4.2 V typ); and where V

INT

= V

INT

< V

, where V

= lower voltage trip limit (2.0 V typ); and where V

INT

= V

BAT

; or

When any of the physical tamper inputs, TP

to TP

, change from their normal states to the opposite (i.e., intrusion of a physical enclosure).

Note: 1 The default state of the SAL output during initial power-up is undetermined.

2 The alarm function will operate either with V

on or when the part is internally switched from V

to V

BAT

2.1.1 TP

, TP

Physical tamper detect pin set normally to high (NH). They are connected externally through a closed switch or a high-impedance resistor to V

OUT

(in the case of STM1403A) or V

TPU

(in the case of STM1403B/C. A tamper condition will be detected when the input pin is pulled

low (see Figure 5

and

Figure 6 ). If not used, tie the pin to V

OUT

STM1403B/C).

(for STM1403A) or V

TPU

(for

2.1.2 TP

, TP

Physical tamper detect pin set normally to low (NL). They are connected externally through a high-impedance resistor or a closed switch to V

. A tamper condition will be detected when the input pin is pulled high (see

Figure 7 and Figure 8

). If not used, tie the pin to V

2.1.3 Vccsw, V

switch output

This output is low when V

OUT to V

(see

Section 2.1.10: V

OUT

on page 13

) is internally switched

; in this mode it may be used to turn on an external p-channel MOSFET switch which

for currents greater than 80 mA (bypassing can source an external device directly from V

CC the STM1403).

Obsolete Product(s) - Obsolete Product(s)

This pin goes high when V

OUT

is internally switched to V

BAT

and may be used as a “BATT

ON” indicator.

If a security alarm (SAL) is issued on tamper, then the state of the Vccsw pin is as follows:

Doc ID 13232 Rev 6 11/34

Pin descriptions STM1403

STM1403A (V

OUT

remains ON when SAL is active-low): Vccsw pin will continue to operate in normal mode;

OUT

is taken to High-Z when SAL is active-low): Vccsw pin will be set to high when this occurs; and

OUT

is driven to ground when SAL is active-low): Vccsw pin will be set to high when this occurs.

2.1.4 BLD, V

BAT

low voltage detect output (open drain)

This is an internally loaded test of the battery, activated only during a power-up sequence to insure that the battery is good either prior to or after encapsulation of the module. There are three customer options for V

DET

● 2.3 V (2.5 V – external diode drop of about 0.2 V) for a 3 V lithium cell

● 2.5 V (2.7 V – 0.2 V) for a 3 V lithium cell or

● 3.2 V (3.4 V – 0.2 V) for a 3.68 V lithium “AA” battery

This output pin will go active-low when it detects a voltage on the V

BAT

pin below V

DET

. BLD will be released when V

drops below V

RST

Goes low and stays low when V

drops below V

RST

(reset threshold selected by the customer), or when MR is logic low. It remains low for t rec

(200ms, typical) AFTER V

rises above V

RST

and MR goes from low to high.

2.1.6 MR, manual reset input

A logic low on MR asserts the RST output. The RST output remains asserted as long as MR is low and for t rec

after MR returns to high. This active low input has an internal 40 k Ω

(typical) pull-up resistor. It can be driven from a TTL or CMOS logic line or shorted to ground with a switch. Leave it open if unused.

2.1.7 PFO, power-fail output (open drain)

When PFI is less than V

PFI

(power-fail input threshold voltage) or V

falls below V

(battery switchover threshold ~ 2.4 V), PFO goes low, otherwise, PFO remains high. Leave this pin open if unused.

2.1.8 PFI, power-fail input

When PFI is less than V

PFI

, or when V

falls below V

SW active-low. If this function is unused, connect this pin to V

(see PFO, above), PFO goes

Obsolete Product(s) - Obsolete Product(s)

2.1.9 V

REF

, reference voltage output (1.237, typ)

This is valid only when V

REF

is between 2.4 V and 3.6 V. When V

falls below 2.4 V (V

is pulled to ground with an internal 100 k Ω resistor. This is an optional feature

), available on the STM1403A. On the STM1403B/C, this pin is V

TPU

(internally switched V

CC or V

BAT

). If unused, this pin should float.

12/34 Doc ID 13232 Rev 6

STM1403 Pin descriptions

2.1.10 V

OUT

This is the supply voltage output. When V

rises above V

(battery backup switchover voltage), V

OUT

is supplied from V

. In this condition, V

OUT

may be connected externally to

through a p-channel MOSFET switch. When V

(~2.4 V), or V

BAT

, V

OUT

is supplied from V

BAT

falls below the lower value of V

. It is recommended that the V

OUT

pin be connected externally to a capacitor that will retain a charge for a period of time, in case an intruder forces V

or V

BAT

to ground. The rectifying diode connected from the positive terminal of the battery to the V

BAT

pin of the STM1403 will prevent discharge of the capacitor.

Three variations of parts will be offered with the following options:

STM1403A: V

OUT

remains ON when SAL is active-low; Vccsw pin will continue to operate in normal mode (see

Section 2.1.3: Vccsw, V

switch output on page 11 );

OUT

is taken to High-Z when SAL is active-low; Vccsw pin will be set to high when this occurs; and

is driven to ground when SAL is active-low; Vccsw pin will be set to high when this occurs.

2.1.11 V

TPU

Note:

For STM1403B and STM1403C, this pin provides pull-up voltage for the physical tamper pins (TP1-4). This pin is not to be used as voltage supply source for any other purpose.

TPU

is the internally switched supply voltage from either the V

pin or the V

BAT

pin.

2.1.12 V

This is the supply voltage (2.2 V to 3.6 V).

2.1.13 V

BAT

This is the secondary (backup battery) supply voltage. The pin is connected to the positive terminal of the battery with a rectifying diode like the BAT54J from STMicroelectronics for reverse charge protection. Voltage at this pin, after diode rectification, will be approximately

0.2 V less than the battery voltage, and will depend on the type of battery used as well as the I

BAT

being drawn. (A capacitor of at least 1.0 µF connected between the V

BAT

pin and

is required.) If no battery is used, connect the V

BAT

pin to the V

pin.

2.1.14 V

Ground, V

, is the reference for the power supply. It must be connected to system ground.

Obsolete Product(s) - Obsolete Product(s)

Doc ID 13232 Rev 6 13/34

STM1403 Operation

3 Operation

3.2

The STM1403 security supervisor asserts a reset signal to the MCU whenever V

goes below the reset threshold (V

RST

), or when the push-button reset input (MR) is taken low.

RST is guaranteed to be a logic low for 0 V < V

< V

RST

if V

BAT

is greater than 1 V. Without a backup battery, RST is guaranteed valid down to V

=1 V.

During power-up, once V

exceeds the reset threshold an internal timer keeps RST low for the reset time-out period, t rec

. After this interval RST returns high.

If V

drops below the reset threshold, RST goes low. Each time RST is asserted, it stays low for at least the reset time-out period (t rec

). Any time V

goes below the reset threshold the internal timer clears. The reset timer starts when V

returns above the reset threshold.

Push-button reset input

A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t rec

(see

Figure 25 on page 24 ) after it returns high. The MR input has an internal 40 k

pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from

MR to ground to create a manual reset function; external debounce circuitry is not required.

If MR is driven from long cables or the device is used in a noisy environment, connect a

0.1 µF capacitor from MR to V

to provide additional noise immunity. MR may float, or be tied to V

when not used.

3.3 Backup battery switchover

Note:

In the event of a power failure, it may be necessary to preserve the contents of external

SRAM through V

OUT

. With a backup battery installed with voltage V

BAT

, the devices automatically switch the SRAM to the backup supply when V

falls.

If backup battery is not used, connect both V

BAT

and V

OUT

to V

This family of security supervisors does not always connect V

BAT

to V

OUT greater than V

. V

BAT

when V

BAT

connects to V

OUT

(through a 100 Ω switch) when V

is below V

(~2.4 V) or V

BAT

(whichever is lower). This is done to allow the backup battery (e.g., a 3.6 V battery) to have a higher voltage than V

Assuming that V

BAT

> 2.0 V, switchover at V

ensures that battery backup mode is entered

Obsolete Product(s) - Obsolete Product(s) external SRAMs. When V point. V

OUT

recovers, hysteresis is used to avoid oscillation around the V

is connected to V

through a 3 Ω PMOS power switch.

Note: The backup battery may be removed while V

is valid, assuming V

BAT

is adequately decoupled (0.1 µF typ), without danger of triggering a reset.

14/34 Doc ID 13232 Rev 6

Operation STM1403

Table 3.

Pin

OUT

PFI

PFO

RST

BAT

Vccsw

REF

BLD

TPU

I/O status in battery backup

Status

Connected to V

BAT

through internal switch

Disconnected from V

OUT

Disabled

Logic low

Disabled

Logic low

Connected to V

OUT

Logic high

Pulled to V

below 2.4 V (V

)

Logic high

Connected to V

BAT

through an internal switch

The power-fail input (PFI) is compared to an internal reference voltage (independent from the V

RST

comparator). If PFI is less than the power-fail threshold (V

PFI

), the power-fail output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider

(see Figure 4 on page 9

) to either the unregulated DC input (if it is available) or the regulated output of the V

regulator. The voltage divider can be set up such that the voltage at PFI falls below V

PFI

several milliseconds before the regulated V

input to the

STM1403 or the microprocessor drops below the minimum operating voltage.

During battery backup, the power-fail comparator is turned off and PFO goes (or remains) low (see

Figure 9 on page 16 ). This occurs after V

drops below V

(~2.4V). When power returns, the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI should be connected to V

and PFO left unconnected. PFO may be connected to MR so that a low voltage on PFI will generate a reset output.

These supervisor circuits are not short-circuit protected. Shorting V

OUT

to ground - excluding power-up transients such as charging a decoupling capacitor - destroys the

and V

BAT

pins to ground by placing 0.1 µF capacitors as close to device. Decouple both V

Obsolete Product(s) - Obsolete Product(s)

Doc ID 13232 Rev 6 15/34

Operation

Figure 9.

Power-fail comparator waveform

VCC

VRST

VSW (2.4V)

PFO

PFO follows PFI

RST

STM1403 trec

PFO follows PFI

AI08861a

The STM1403 devices are relatively immune to negative-going V

transients (glitches).

Figure 23 on page 22

was generated using a negative pulse applied to V

, starting at V

RST

+ 0.3 V and ending below the reset threshold by the magnitude indicated (comparator overdrive). The graph indicates the maximum pulse width a negative V

transient can have without causing a reset pulse. As the magnitude of the transient increases (further below the threshold), the maximum allowable pulse width decreases. Any combination of duration and overdrive which lies under the curve will NOT generate a reset signal. Typically, a V

CC transient that goes 100 mV below the reset threshold and lasts 40 µs or less will not cause a reset pulse. A 0.1 µF bypass capacitor mounted as close as possible to the V

pin provides additional transient immunity (see

Figure 10

In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V

that drive it to values below V

by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a Schottky diode from V

to V

(cathode connected to V

, anode to V

Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.

Figure 10.

Supply voltage protection

VCC Obsolete Product(s) - Obsolete Product(s)

VCC

0.1

µ F DEVICE

AI02169

16/34 Doc ID 13232 Rev 6

STM1403 Tamper detection

4.1 Physical

There are four (4) high-impedance physical tamper detect input pins, 2 normally set to high

(NH) and 2 normally set to low (NL). Each input is designed with a glitch immunity (see

Table 7 on page 28

). These inputs can be connected externally to several types of actuator devices (e.g., switches, wire mesh). A tamper on any one of the four inputs that causes its state to change will trigger the security alarm (SAL) and drive it to active-low. Once the tamper condition no longer exists, the SAL will return to its normal high state.

and TP

are set normally to high (NH). They are connected externally through a closed switch or a high-impedance resistor to V

OUT

(in the case of STM1403A) or V

TPU

(in the case of STM1403B/C), A tamper condition will be detected when the input pin is pulled low (see

Figure 5

and Figure 6

). If not used, tie the pin to V

OUT

or V

TPU

and TP

are set normally to low (NL). They are connected externally through a highimpedance resistor or a closed switch to V

. A tamper condition will be detected when the input pin is pulled high (see

Figure 7 and Figure 8

). If not used, tie the pin to V

The internally switched supply voltage, V

INT

(either V

CC monitored. If V

INT

input or V

should exceed the over voltage trip point, V

BAT

input) is continuously

(set at 4.2V, typical), or should go below the under voltage trip point, V

(set at 2.0 V, typical). SAL will be driven active-low. Once the tamper condition no longer exists, the SAL pin will return to its normal high state.

When no tamper condition exists, SAL is normally high (see

Section 2: Pin descriptions on page 11

●

When a tamper is detected, the SAL is activated (driven low), independent of the part type.

OUT

can be driven to one of three states, depending on which variant of STM1403 is being used (see Table 1: Device summary on page 1 ):

High-Z or

Ground (V

)

Note: The STM1403 must be initially powered above V

RST

to enable the tamper detection alarms.

For example, if the battery is on while V

= 0 V, no alarm condition can be detected until

rises above V

RST

(and t rec

expires). From this point on, alarms can be detected either

Obsolete Product(s) - Obsolete Product(s) its operational state.

Doc ID 13232 Rev 6 17/34

STM1403 Typical operating characteristics

5 Typical operating characteristics

Note: Typical values are at T

= 25 °C.

Figure 11.

BAT

-to-V

OUT

on-resistance vs. temperature

220

200

180

160

140

120

100

–60

= 0V

–40 –20

BAT

= 2V

BAT

= 3V

20 40 60

TEMPERATURE [ ° C]

BAT

= 3.3V

100 120 140

AI09691

Figure 12.

Supply current vs. temperature (no load)

2.5V

3.3V

3.6V

–50 –40 –30 –20 –10 0 10 20 30 40

TEMPERATURE [°C]

50 60 70 80 90 100 Obsolete Product(s) - Obsolete Product(s)

18/34 Doc ID 13232 Rev 6

STM1403 Typical operating characteristics

Figure 13.

PFI

threshold vs. temperature

1.255

1.250

1.245

1.240

1.235

1.230

1.225

–50 –30 –10

= 3.3V

= 2.5V

BAT

= 3.0V

10 30 50

TEMPERATURE [°C]

70 90 110 130

AI09693

Figure 14.

Reset comparator propagation delay vs. temperature

–60 –40 –20

BAT

= 3.0V

100mV OVERDRIVE

0 20 40

TEMPERATURE [°C]

60 80 100

AI09143

Figure 15.

Power-up t rec

vs. temperature

215

210

Obsolete Product(s) - Obsolete Product(s)

205

200

195

–50 –30 –10 10 30 50

TEMPERATURE [°C]

70 90 110 130

AI09144

Doc ID 13232 Rev 6 19/34

STM1403 Typical operating characteristics

Figure 16.

Normalized reset threshold vs. temperature

1.002

1.000

0.998

0.996

0.994

–60 –40 –20 0

BAT

= 3.0V

20 40 60

TEMPERATURE [°C]

80 100 120 140

AI09145

Figure 17.

PFI to PFO propagation delay vs. temperature

–60 –40 –20 0 20 40 60

TEMPERATURE [°C]

80 100 120 140

AI09148

Figure 18.

RST output voltage vs. supply voltage

3.5

3.0

2.5

Obsolete Product(s) - Obsolete Product(s)

2.0

RST

1.5

1.0

0.5

500 ms/div

AI09149b

20/34 Doc ID 13232 Rev 6

STM1403 Typical operating characteristics

Figure 19.

RST response time (assertion)

4.0

3.0

2.0

RST

1.0

0.0

2 µs/div

AI09151b

Figure 20.

Power-fail comparator response time (assertion)

4.0

1.45

1.40

3.0

2.0

PFI

PFO

1.35

1.30

1.25

1.0

0.0

1.20

1.15

2µs/div

AI09153b

Figure 21.

Power-fail comparator response time (de-assertion)

4.0

1.45

3.5

1.40

3.0

2.5

PFO

1.35

Obsolete Product(s) - Obsolete Product(s)

2.0

1.30

1.5

PFI

1.25

1.0

1.20

0.5

0.0

1.15

2 µs/div

AI09154

Doc ID 13232 Rev 6 21/34

Typical operating characteristics STM1403

Figure 22.

to reset propagation delay vs. temperature

–60 –40 –20 0 20 40

TEMPERATURE [°C]

60 80 100

10V/ms

1V/ms

0.25V/ms

AI09155

Figure 23.

Maximum transient duration vs. reset threshold overdrive

250

200

150

100

1 10 100 1000

RESET COMPARATOR OVERDRIVE, V

RST

– V

[mV]

10000

AI09156

Obsolete Product(s) - Obsolete Product(s)

22/34 Doc ID 13232 Rev 6

STM1403 Maximum ratings

Stressing the device above the ratings listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 4.

Symbol

Absolute maximum ratings

Parameter Value Unit

STG

SLD

(1)

BAT

Storage temperature (V

Input or output voltage

Supply voltage

Output current

Power dissipation

off, V

BAT

off)

Lead solder temperature for 10 seconds

–55 to 150

260

–0.3 to V

+0.3

–0.3 to 4.5

320

Reflow at peak temperature of 255 °C to 260 °C for < 30 seconds (total thermal budget not to exceed

180 °C for between 90 to 150 seconds).

°C

V mA mW

Obsolete Product(s) - Obsolete Product(s)

Doc ID 13232 Rev 6 23/34

DC and AC parameters

7 DC and AC parameters

STM1403

This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in

Table 5: Operating and AC measurement condition . Designers should check that the

operating conditions in their circuit match the operating conditions when relying on the quoted parameters.

Table 5.

Operating and AC measurement condition

Parameter

BAT

supply voltage

Ambient operating temperature (T

)

Input rise and fall times

Input pulse voltages

Input and output timing ref. voltages

STM1403

2.2 to 3.6

–40 to 85

≤ 5

0.2 to 0.8V

0.3 to 0.7V

Unit

°C ns

Figure 24.

AC testing input/output waveforms

8 VCC

0.2VCC

0.7VCC

3 VCC

AI0256 8

Figure 25.

MR timing waveform

MR tMLRL

RST tMLMH trec

AI09694

Figure 26.

STM1403 switchover diagram, condition A (V

BAT

< V

)

VOUT VCC = 3.3V

VRST

VSW = 2.4V

VBAT

VBAT – 75mV

VBAT – 35mV

Figure 27.

STM1403 switchover diagram, condition B (V

BAT

> V

)

VOUT VCC = 3.3V

VBAT

VSW = 2.4V

VSW + 40mV

AI10464

24/34 Doc ID 13232 Rev 6

STM1403 DC and AC parameters

Table 6.

Sym

DC and AC characteristics

Alternative

Description Test condition

(1)

Min Typ Max Unit

BAT

(2)

Operating voltage T

= –40 to +85 °C 2.2

3.6

supply current

(STM1403A)

45 60

Typ @ 3.3 V, 25 °C

supply current

(STM1403B,C)

30 45

BAT

(3)

OUT1

OUT2

TPU1

TPU2

supply current in battery backup mode

BAT

supply current in battery backup mode

OUT

voltage (active)

OUT

voltage (battery backup)

Internal switched supply voltage (active)

Internal switched supply voltage (battery backup)

Input leakage current (MR)

Input leakage current (PFI)

Input leakage current

(TP1-TP4)

Output low voltage (RST)

Excluding I

OUT

BAT

= 2.3 V, V

= 2.0

V, MR = V

)

Excluding I

OUT

BAT

= 3.6 V)

OUT1

= 5 mA

(4)

> V

)

OUT1

= 80 mA

> V

)

OUT1

= 250 µA,

> V

(4)

OUT2

= 250 µA,

BAT

= 2.2 V

OUT2

= 1 mA,

BAT

= 2.2 V

SOURCE

= 500 µA

> V

)

SOURCE

= 100 µA

BAT

= 2.2 V)

MR = 0 V; V

= 3 V

0 V = V

= V

0 V = V

= V

= 40 µA; V

= 1.0 V;

BAT

= V

;

= 0 °C to 85 °C

= 200 µA;

= 1.2 V; V

BAT

= V

–

0.03

–

0.3

–

0.0015

BAT

–

0.1

–

0.3

–25

–1

2.8

–

0.015

–

0.15

–

0.0006

BAT

–

0.04

BAT

–

0.16

BAT

–

0.10

4.0

350

+25

Output leakage current –1 +1 I

0 V = V

= V

(5)

Input high voltage (MR) 0.7V

Obsolete Product(s) - Obsolete Product(s)

Output low voltage (PFO,

0.3V

0.3

V V

OL RST, Vccsw, SAL, BLD)

RST

(max) < V

< 3.6 V

= V

RST

(max),

SINK

= 3.2 mA

µA

0.3

µA

µA nA

µA

Doc ID 13232 Rev 6 25/34

DC and AC parameters STM1403

Table 6.

Sym

DC and AC characteristics (continued)

Alternative

Description Test condition

(1)

OHB

battery backup (Vccsw)

Pull-up supply voltage

(open drain)

Power-fail comparator t

PFI

PFD

PFI input threshold

PFI hysteresis

PFI to PFO propagation delay

Battery switchover

SOURCE

= 100 µA,

RST, SAL, BLD, PFO

PFI falling (V

< 3.6 V)

PFI Rising (V

< 3.6 V)

Battery backup switchover voltage

(6)(7)

Powerdown

Power-up

BAT

> V

BAT

< V

BAT

> V

BAT

< V

Hysteresis

Battery low voltage detect

DET

Battery detect threshold

On power-up only

Voltage reference (option for STM1403A)

(8)

Min

0.8V

BAT

1.212

2.25

2.45

3.14

Typ

1.237

BAT

2.4

2.30

2.50

3.20

Max

3.6

1.262

2.34

2.55

3.26

Unit

V mV

µs

REF

Voltage reference

(see

Section 2.1.9: V

REF

, reference voltage output

(1.237, typ) on page 12

)

0 °C to 85 °C

–40 ° to 0 °C

1.212

1.200

1.237

1.262

1.274

REF+

REF–

V n

Source current

Sink current

Output voltage noise

0 °C to 85 °C

–40 ° to 0 °C f = 100 Hz to 100 kH

10-100

Obsolete Product(s) - Obsolete Product(s)

µA

µV rms

V mV

26/34 Doc ID 13232 Rev 6

STM1403 DC and AC parameters

Table 6.

Sym

DC and AC characteristics (continued)

Alternative

Description Test condition

(1)

Min Typ Max Unit

Reset thresholds

RST

(9)

Reset threshold

falling

rising

falling

rising

falling

rising

3.00

2.85

2.55

140

3.075

3.085

2.925

2.935

2.625

2.635

200

3.15

3.17

3.00

3.02

2.70

2.72

280 t rec

RST pulse width

Push-button reset input t

MLMH t

MLRL t

MR t

MRD

MR pulse width

MR to RST output delay

100

60 500 ns ns

Valid for ambient operating temperature: T

= –40 to 85 °C; V

= V

RST noted); typical values are for 3.3 V and 25 °C.

(max) to 3.6 V; and V

BAT

= 2.8 V (except where

supply current, logic input leakage, push-button reset functionality, PFI functionality, state of RST tested at

BAT pin.

= 3.6 V, and V

= 3.6 V. The state of RST and PFO is tested at V

= V

(min). V

BAT

is voltage measured at the

Tested at V

BAT

= 3.6 V, V

= 3.5 V and 0 V.

Guaranteed by design.

The leakage current measured on the RST, SAL, PFO, and BLD pins are tested with the output not asserted (output high impedance).

When V

BAT

> V

, V

OUT

remains connected to V

until V

drops below V

When V

> V

BAT

, V

OUT

remains connected to V

until V

drops below the battery voltage (V

BAT

) – 75 mV.

Maximum external capacitive load on V

REF

pin cannot exceed 1nF.

The reset threshold tolerance is wider for V

CC internal oscillation.

rising than for V

falling due to the 10 mV (typ) hysteresis, which prevents

V ms

Obsolete Product(s) - Obsolete Product(s)

Doc ID 13232 Rev 6 27/34

DC and AC parameters STM1403

Table 7.

Sym

Physical and environmental tamper detection levels

Parameter

Test conditions

(1)

Min Typ Max Unit

Overvoltage trip level

Undervoltage trip level

SAL propagation delay time

(after over/under voltage detection)

HTP

LTP

Trip point for NH physical tamper input pins (TP

or TP

)

Trip point for NL physical tamper input pins (TP

or TP

)

+ 200 mV or

– 200 mV

4.0

1.9

OUT

1.3 V

0.3

–

(2)

4.2

2.0

4.4

2.1

OUT

0.3 V

1.0

–

(2)

µs

SAL propagation delay time

(after physical tamper pin detection)

(3)

HTP

OUT

TPU

;

LTP

= V

= 3.6

30 50 µs

Physical tamper input (TP

) glitch immunity

Valid for ambient operating temperature: T

= –40 to 85 °C; V

= V

to V

(except where noted).

In the case of STM1403A, physical tamper input pins (TP

STM1403B or C, TP

are referenced to V

TPU

pin (pin 9).

) are referenced to V

OUT

(pin 12). In the case of

= V

RST

(max) to 3.6 V

µs

Obsolete Product(s) - Obsolete Product(s)

28/34 Doc ID 13232 Rev 6

STM1403

8 Package mechanical data

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

ECOPACK

is an ST trademark.

Figure 28.

QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline

A3 ddd C

L b

A e

QFN16-A

Note: Drawing is not to scale.

Obsolete Product(s) - Obsolete Product(s)

Doc ID 13232 Rev 6 29/34

Package mechanical data STM1403 e

L ddd

A3 b

Table 8.

Symb

QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, mechanical data mm inches

Typ

0.50

0.20

0.40

–

3.00

1.70

3.00

1.70

0.90

0.02

0.20

0.25

Min

–

0.30

0.08

0.33

2.90

1.55

2.90

1.55

0.80

0.00

–

0.18

Max

–

0.50

–

3.10

1.80

3.10

1.80

1.00

0.05

–

0.30

Typ

0.020

0.008

0.016

–

0.035

0.001

0.008

0.010

0.118

0.067

0.118

0.067

Min

–

0.012

0.003

0.013

0.032

0.000

–

0.007

0.114

0.061

0.114

0.061

Max

–

0.020

–

0.039

0.002

–

0.012

0.122

0.071

0.122

0.071

Figure 29.

QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended footprint

1.60

3.55

2.0

0.28

AI09126

Note: Substrate pad should be tied to V

Obsolete Product(s) - Obsolete Product(s)

30/34 Doc ID 13232 Rev 6

STM1403 Part numbering

Table 9.

Example:

Ordering information scheme (see Figure 30 on page 32 for marking information)

STM1403 A T M Q 6 F

Device type

STM1403: physical, voltage tamper detect

OUT

status (SAL = active-low)

A: V

OUT

= ON; Vccsw = normal mode

(1)

: V

OUT

= High-Z; Vccsw = high

C: V

OUT

= ground; Vccsw = high

Reset threshold voltage

T: V

RST

= 3.00 V to 3.15 V

S: V

RST

= 2.85 V to 3.00 V

R: V

RST

= 2.55 V to 2.70 V

Battery low voltage detect threshold (V

DET

)

M: V

DET

= 2.3 V (typ)

N: V

DET

= 2.5 V (typ)

O: V

DET

= 3.2 V (typ)

Package

Q = QFN16 (3 mm x 3 mm)

Temperature range

6 = –40 to 85 °C

Shipping method

F = ECOPACK

package, tape & reel

Contact local ST sales office for availability.

Note: The parts cited in

Table 10 are not recommended for new design. Please contact local ST

sales office for availability.

Table 10.

Obsolete Product(s) - Obsolete Product(s)

Part not recommended for new design Replacement options

STM1403CSMQ6F

STM1403CSNQ6F

STM1403CTNQ6F

STM1403ASMQ6F or STM1403ATNQ6F or STM1403ATOQ6F

For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.

Doc ID 13232 Rev 6 31/34

Part numbering

Figure 30.

Topside marking information

XXX

(1)

YWW

(2)

Options codes:

X = A, B, or C (for V

OUT

)

X = T, S, or R (for reset threshold)

X = M, N, or O (for battery low voltage detect threshold)

Traceability codes

Y = Year

WW = Work Week

STM1403

AI11878

Obsolete Product(s) - Obsolete Product(s)

32/34 Doc ID 13232 Rev 6

STM1403 Revision history

Table 11.

Document revision history

Date Revision

11-Oct-2004

26-Nov-2004

22-Dec-2004

03-Feb-2005

25-Feb-2005

06-May-2005

05-Aug-2005

18-Oct-2005

07-Feb-2007

20-Aug-2008

17-Nov-2010

1.1

1.2

1.3

1.4

1.5

Changes

First edition

Corrected footprint dimensions; update characteristics (Figure

4 , 5

; Table 1 ,

Update characteristics (

Figure 4

;

Table 6 ,

7 , )

Update characteristics ( Figure 4 ;

Table 6

)

Update temperature trip limits ( Table )

Update characteristics ( Figure 3 ,

4 ,

;

Table 6 ,

7 )

Removed STM1404 references ( Figure 1 ,

Table 1 ,

Update hardware hookup, characteristics, Lead-free text; add

marking information ( Figure 4 ,

;

Table 6 ,

7 , )

Update cover page, Table 7

, and part numbering ( Table ).

Minor formatting changes, updated Table 1

and 7 .

Added Table 10: Replacement options for terminated parts

; updated ECOPACK

text in Section 8 ; reformatted document.

Obsolete Product(s) - Obsolete Product(s)

Doc ID 13232 Rev 6 33/34

STM1403

Please Read Carefully:

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Information in this document supersedes and replaces all information previously supplied.

Obsolete Product(s) - Obsolete Product(s)

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34/34 Doc ID 13232 Rev 6

ನಮಸ್ಕಾರ! STMicroelectronics STM1403 Datasheet ನೊಂದಿಗೆ ನಿಮಗೆ ಸಹಾಯ ಮಾಡಲು ನಿರ್ದಿಷ್ಟವಾಗಿ ತರಬೇತಿ ಪಡೆದ AI ಚಾಟ್‌ಬಾಟ್ ನಾನು. ನಾನು ಡಾಕ್ಯುಮೆಂಟ್ ಅನ್ನು ಸಂಪೂರ್ಣವಾಗಿ ಪರಿಶೀಲಿಸಿದ್ದೇನೆ ಮತ್ತು ನಿಮಗೆ ಅಗತ್ಯವಿರುವ ನಿಖರವಾದ ಮಾಹಿತಿಯನ್ನು ಪತ್ತೆಹಚ್ಚಲು ಅಥವಾ ವಿಷಯವನ್ನು ಸ್ಪಷ್ಟ ಮತ್ತು ಸರಳ ಪದಗಳಲ್ಲಿ ವಿವರಿಸಲು ನಾನು ನಿಮಗೆ ಸಹಾಯ ಮಾಡಬಹುದು. ನಿರ್ದಿಷ್ಟ ವೈಶಿಷ್ಟ್ಯಗಳು, ದೋಷನಿವಾರಣೆ ಹಂತಗಳು ಅಥವಾ ಸಾಮಾನ್ಯ ಬಳಕೆಯ ಕುರಿತು ನೀವು ಮಾರ್ಗದರ್ಶನವನ್ನು ಹುಡುಕುತ್ತಿರಲಿ, ನಿಮ್ಮ ಪ್ರಶ್ನೆಗಳನ್ನು ಕೇಳಲು ಮುಕ್ತವಾಗಿರಿ. ನಿಮ್ಮ ಕಾಳಜಿಗಳು ಅಥವಾ ಅಗತ್ಯಗಳ ಬಗ್ಗೆ ನೀವು ಹೆಚ್ಚು ವಿವರಗಳನ್ನು ಒದಗಿಸಿದರೆ, ನಾನು ಹೆಚ್ಚು ನಿಖರವಾಗಿ ಮತ್ತು ಪರಿಣಾಮಕಾರಿಯಾಗಿ ನಿಮಗೆ ಸಹಾಯ ಮಾಡಬಹುದು!