STM32F102x4, STM32F102x6 Electrical characteristics
The parameters given in
Table 38 are guaranteed by design.
Refer to Section 5.3.13
for details on the input/output alternate function characteristics
(output compare, input capture, external clock, PWM output).
Symbol
Table 38. TIMx
(1)
characteristics
Parameter Conditions Min
1 t res(TIM)
Timer resolution time f
EXT
Res
TIM
Timer external clock frequency on CH1 to CH4
Timer resolution
f
TIMxCLK
= 48 MHz 20.84
0 f
TIMxCLK
= 48 MHz
-
0
t
COUNTER
16-bit counter clock period when internal clock is selected
f
TIMxCLK
1
= 48 MHz 0.0208
t
MAX_COUNT
-
Maximum possible count
f
TIMxCLK
= 48 MHz -
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.
Max
-
f
TIMxCLK
/2
24
16
65536
Unit t
TIMxCLK ns
MHz
MHz bit t
TIMxCLK
µs 1365
65536 × 65536 t
TIMxCLK
89.48
s
I
2
C interface characteristics
The STM32F102xx medium-density USB access line I 2 C interface meets the requirements of the standard I 2 C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the
PMOS connected between the I/O pin and V
DD is disabled, but is still present.
The I 2 C characteristics are described in
Table 39
. Refer also to
Section 5.3.13
for more
details on the input/output alternate function characteristics (SDA and SCL).
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Electrical characteristics STM32F102x4, STM32F102x6
Symbol
Table 39. I 2 C characteristics
Standard mode I
2
C
(1)(2)
Parameter
Min Max
Fast mode I
2
C
(1) (2)
Min Max
Unit t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
4.7
4.0
250
-
-
-
-
-
-
3450
(3)
1000
300
1.3
0.6
100
-
-
-
-
-
-
900
(3)
300
300
µs ns t su(STA)
Start condition hold time
Repeated Start condition setup time
4.0
4.7
-
0.6
-
0.6 -
µs t su(STO)
Stop condition setup time t w(STO:STA)
Stop to Start condition time (bus free)
4.0
4.7
-
0.6
1.3
-
µs
µs t
SP
Pulse width of spikes that are suppressed by the analog filter
0 50
(4)
0
50
(4)
ns
C b
Capacitive load for each bus line 400 400 pF
1. Values guaranteed by design, not tested in production.
2. f
PCLK1
must be at least 2 MHz to achieve standard mode I achieve fast mode I mode clock.
2
C frequencies. It must be at least 4 MHz to
C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C fast
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL signal.
4. The analog filter minimum filtered spikes is above t filtered.
SP(max)
to ensure that spikes width up to t
SP(max)
are
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STM32F102x4, STM32F102x6 Electrical characteristics
Figure 26. I 2 C bus AC waveforms and measurement circuit (1)
VDD_I2C VDD_I2C
I²C bus
Rp Rp
Rs
Rs
STM32F10x
SDA
SCL
Start repeated
Start
Start tsu(STA)
SDA tf(SDA) th(STA) tr(SDA) tw(SCLL) tsu(SDA) th(SDA)
Stop tsu(STO:STA)
SCL tw(SCLH) tr(SCL) tf(SCL) tsu(STO) ai14133e
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD.
Table 40. SCL frequency (f
PCLK1
= 36 MHz, V
DD_I2C
= 3.3 V)
(1)(2)
I2C_CCR value f
SCL
(kHz)
R
P
= 4.7 k Ω
400
300
200
100
0x801E
0x8028
0x803C
0x00B4
50 0x0168
20 0x0384
1. R
P
= External pull-up resistance, f
SCL
= I
2
C speed.
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ± 5%. For other speed ranges, the tolerance on the achieved speed ± 2%. These variations depend on the accuracy of the external components used to design the application.
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Electrical characteristics STM32F102x4, STM32F102x6
SPI interface characteristics
Unless otherwise specified, the parameters given in
Table 41 are derived from tests
performed under ambient temperature, f
PCLKx summarized in
Table 8
.
frequency and V
DD
supply voltage conditions
Refer to Section 5.3.13
for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO).
Symbol Parameter
Table 41. SPI characteristics
Conditions Min Max Unit
1/t f
SCK c(SCK)
SPI clock frequency
Master mode
Slave mode
-
-
18
18
MHz t r(SCK) t f(SCK)
SPI clock rise and fall time
Capacitive load: C = 30 pF 8 ns
DuCy(SCK)
SPI slave input clock duty cycle
Slave mode 30 70 % t su(NSS)
(1) t h(NSS)
(1) t t w(SCKH)
(1) w(SCKL)
(1) t t su(MI)
(1) su(SI)
(1)
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Slave mode
Slave mode
Master mode, f presc = 4
Master mode
PCLK
= 36 MHz,
4t
2t
PCLK
PCLK
50
5 -
-
-
60
Slave mode 5 t h(MI)
(1) t h(SI)
(1) t a(SO)
(1)(2) t dis(SO)
(1)(3) t v(SO)
(1) t v(MO)
(1) t h(SO)
(1) t h(MO)
(1)
Data input hold time
Master mode
Slave mode
Data output access time Slave mode, f
Data output disable time Slave mode
Data output valid time
Data output valid time
Data output hold time
PCLK
= 20 MHz
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
5
4
0
2
-
-
15
2
3t
PCLK
10
-
-
-
-
25
5
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z ns
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STM32F102x4, STM32F102x6 Electrical characteristics
Figure 27. SPI timing diagram - slave mode and CPHA=0
Figure 28. SPI timing diagram - slave mode and CPHA=1 (1)
NSS input t
SU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1 t w(SCKH) t w(SCKL) t a(SO)
MISO
OUTPUT
MOSI
INPUT t su(SI) t v(SO)
MSB OUT t h(SI)
MSB IN t c(SCK) t h(SO)
BIT6 OUT
BIT 1 IN t h(NSS) t r(SCK) t f(SCK) t dis(SO)
LSB OUT
LSB IN
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD.
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Electrical characteristics STM32F102x4, STM32F102x6
Figure 29. SPI timing diagram - master mode (1)
NSS input
High
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1 tc(SCK)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO
INP UT
MOSI
OUTPUT tsu(MI) tw(SCKH) tw(SCKL)
MSB IN th(MI)
MSB OUT tv(MO)
BIT6 IN
B I T1 OUT th(MO)
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD.
USB characteristics
The USB interface is USB-IF certified (full speed).
Symbol t
STARTUP
Table 42. USB startup time
Parameter
USB transceiver startup time
Max
1 tr(SCK) tf(SCK)
LSB IN
LSB OUT
Unit
µs ai14136c
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