This datasheet should be read in conjunction with the STM32F301x6/8 and STM32F318x8 advanced ARM ® -based 32-bit MCUs reference manual (RM0366). The reference manual is available from the STMicroelectronics website www.st.com

For information on the ARM ® Cortex ® -M4 core, refer to the Cortex ® -M4 Technical

Reference Manual, available from ARM website www.arm.com.

8/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8

2 Description

Description

The STM32F318x8 family is based on the high-performance ARM

Cortex

-M4

32-bit RISC core operating at a frequency of up to 72 MHz and embedding a floating point unit (FPU). The family incorporates high-speed embedded memories (64 Kbytes of Flash memory, 16 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses.

The devices offer a fast 12-bit ADC (5 Msps), three comparators, an operational amplifier, up to 17 capacitive sensing channels, one DAC channel, a low-power RTC, one generalpurpose 32-bit timer, one timer dedicated to motor control, and up to three general-purpose

16-bit timers, and one timer to drive the DAC. They also feature standard and advanced communication interfaces: three I 2 Cs, up to three USARTs, up to two SPIs with multiplexed full-duplex I2S, and an infrared transmitter.

The STM32F318x8 family operates in the –40 to +85°C and –40 to +105°C temperature ranges from at 1.8 V ± 8% power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F318x8 family offers devices in 32-, 48- and 49-pin packages.

The set of included peripherals changes with the device chosen.

DocID026294 Rev 6 9/126

Description STM32F318C8 STM32F318K8

Table 1. STM32F318x8 device features and peripheral counts

Peripheral STM32F318K8 STM32F318C8

Flash (Kbyte)

SRAM (Kbyte)

Advanced control

General purpose

Timers

Basic

SysTick timer

Watchdog timers

(independent, window)

PWM channels (all)

(1)

PWM channels

(except complementary)

Comm. interfaces

SPI/I2S

USART

Normal I/Os (TC, TTa)

GPIOs

5-Volt tolerant I/Os (FT, FT1)

DMA channels

Capacitive sensing channels

12-bit ADC

Number of ADC channels

12-bit DAC channels

1 (16-bit)

3 (16-bit)

1 (32 bit)

Analog comparator

Operational amplifier

CPU frequency

72 MHz

Operating voltage

Operating temperature

Packages

= 1.8 V ± 8%

DDA

voltage range = 1.65 V to 3.6 V

Ambient operating temperature:

- 40 to 85 °C / - 40 to 105 °C

Junction temperature: - 40 to 125 °C

UFQFPN32

LQFP48

WLCSP49

1. This total number considers also the PWMs generated on the complementary output channels.

10/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Description

Figure 1. STM32F318x8 block diagram

-7567

-7',

-7&.6:&/.

-7066:',2

-7'2

$V$)

73,8

6:-7$*

)38

,EXV

&RUWH[0&38

)

PD[

0+]

'EXV

19,&

*3'0$

6\VWHP

FKDQQHOV

5()

7HPSVHQVRU

ELW$'& ,)

3$>@

3%>@

3&>@

3)>@

JURXSVRI

FKDQQHOV

DV$)

;;

&KDQQHOV&RPS

&KDQQHO%5.DV$)

&KDQQHO&RPS

&KDQQHO%5.DV$)

&KDQQHO&RPS

&KDQQHO%5.DV$)

&KDQQHOV

&RPSFKDQQHOV

(75%5.DV$)

5;7;&76576

6PDUW&DUGDV$)

*3,23257$

*3,23257%

*3,23257&

*3,23257)

7RXFK6HQVLQJ

&RQWUROOHU

(;7,7

:.83

7,0(5

7,0(53:0

86$57

$+%

$3%

3RZHU

'',2

65$0

)/$6+.%

ELWV

5HVHW

''$

5&+60+]

5&/6

3//

6XSSO\

6XSHUYLVLRQ

''$

5HVHW

FORFN

FRQWURO

&5&

$+%3&/.

$3%3&/.

+&/.

)&/.

86$57&/.

,&&/.

$'&6$5

&/.

'',2

;7$/26&

0+]

,QG:'*.

6WDQGE\

LQWHUIDFH

#96:

;7$/N+]

%DFNXS

57&

5HJ

$:8

%\WH

%DFNXS

LQWHUIDFH

7,0(5

ELW3:0

'',2

15(6(7

''$

66$

1325

26&B,1

26&B287

%$7

9WR9

26&B,1

26&B287

$17,7$03

&KDQQHOV(75DV$)

$+%

$3%

:LQ:$7&+'2*

65$0IRU86%

DQG&$1.%

7,0(5

6<6&)*&7/

''$

*3&RPSDUDWRU

;[,QV287VDV$)

63,,6

86$57

E[&$1

86%)6

026,0,62

6&.166DV$)

026,0,62

6&.166DV$)

5;7;&76576DV$)

6&/6'$60%$DV$)

&$17;&$15;

86%B'386%B'0

,) ELW'$&

''$

2S$PS

''$

'$&B&+DV$)

,1[[

287[[

069

DocID026294 Rev 6 11/126

Functional overview STM32F318C8 STM32F318K8

3.1 ARM

®

Cortex

®

SRAM

-M4 core with FPU, embedded Flash and

The ARM

Cortex

-M4 processor with FPU is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The ARM

Cortex

-M4 32-bit RISC processor with FPU features exceptional codeefficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single-precision FPU speeds up software development by using metalanguage development tools while avoiding saturation.

With its embedded ARM core, the STM32F318x8 family is compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the STM32F318x8 family devices.

3.2 Memories

All STM32F318x8 devices feature 64 Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above).

STM32F318x8 devices feature 16 Kbytes of embedded SRAM.

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10) or USART2 (PA2/Pa3) or I2C1 (PB6/PB7) or I2C3 (PA8, PB5).

12/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Functional overview

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.5.1

3.5.2

Power supply schemes

• V

, V

DD =

1.8 V ± 8% V : external power supply for I/Os and the internal regulator. It is provided externally through V

DD pins.

• V

SSA

, V

DDA

= 1.65 to 3.6 V: external analog power supply for ADC, DAC, comparators, operational amplifier, reset blocks, RCs and PLL. The minimum voltage to be applied to

DDA

differs from one analog peripheral to another. Table 2

provides the summary of the V

DDA ranges for analog peripherals. The V

DDA than or equal to the V

voltage level must always be greater

voltage level and must be provided first.

Table 2. External analog supply values for analog peripherals

Analog peripheral Minimum V

DDA

supply Maximum V

DDA

supply

ADC/COMP

DAC/OPAMP

1.8 V

2.4 V

3.6 V

• V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch which is guaranteed in the full range of V

DD when V

DD is not present.

)

Power supply supervisor

The device power-on reset (POR) is controlled through the external NPOR pin. The device remains in reset state when NPOR pin is held low.

To guarantee a proper power-on reset, the NPOR pin must be held low when V

DDA applied. Then, when V

is stable, the reset state can be exited by:

• either putting the NPOR pin in high impedance, NPOR pin has an internal pull up

• on forcing the pin to high level by connecting it to V

DDA

DocID026294 Rev 6 13/126

Functional overview STM32F318C8 STM32F318K8

Note:

The STM32F318x8 supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm, COMPx,

I2C or USARTx.

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop.

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

Table 3. STM32F318x8 peripheral interconnect matrix

Interconnect source

Interconnect destination

Interconnect action

Timers synchronization or chaining

TIMx

ADC1

DAC1

DMA

Compx

TIMx

TIM1

Conversion triggers

Memory to memory transfer trigger

Comparator output blanking

Timer input: OCREF_CLR input, input capture

Timer triggered by analog watchdog

COMPx

ADC1

GPIO

RTCCLK

HSE/32

MC0

CSS

CPU (hard fault)

COMPx

PVD

GPIO

TIM16

TIM1

TIM15, 16, 17

Clock source used as input channel for HSI and

LSI calibration

Timer break

14/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Functional overview

Table 3. STM32F318x8 peripheral interconnect matrix (continued)

Interconnect source

Interconnect destination

Interconnect action

External trigger, timer break

GPIO

DAC1

TIMx

ADC1

DAC1

COMPx

Conversion external trigger

Comparator inverting input

Note: For more details about the interconnect actions, refer to the corresponding sections in the

STM32F301x6/8 and STM32F318x8 reference manual RM0366.

DocID026294 Rev 6 15/126

Functional overview

3.7 Clocks and startup

STM32F318C8 STM32F318K8

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed

APB domain is 36 MHz.

The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. To achieve audio class performance, an audio crystal can be used.

16/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Functional overview

Figure 2. Clock tree

+6,

6<6&/.

)/,7)&/.

WR)ODVKSURJUDPPLQJLQWHUIDFH

WR,&[[

6<6&/.

([WFORFN

,665&

WR,6[[

,6B&.,1

0+]

+6,5&

+6,

26&B287

26&B,1

0+]

+6(26&

+&/.

3//65&

3//08/

3//

[[

[

+6,

3//&/.

+6(

&66

$+%

SUHVFDOHU

6<6&/.

$3%

SUHVFDOHU

3&/.

WR$+%EXVFRUH

PHPRU\DQG'0$

WRFRUWH[6\VWHPWLPHU

)+&/.&RUWH[IUHH

UXQQLQJFORFN

WR$3%SHULSKHUDOV

$3%

SUHVFDOHU

,I$3%SUHVFDOHU

[HOVH[

3&/.

6<6&/.

+6,

/6(

3&/.

WR7,0

WR86$57

WR$3%SHULSKHUDOV

26&B,1

26&B287

,I$3%SUHVFDOHU

[HOVH[

0&2

/6(26&

N+]

57&&/.

/6(

57&6(/>@

WR57&

/6,5&

N+]

/6, ,:'*&/.

WR,:'*

0&235(

0DLQFORFN

RXWSXW

3//12',9

0&2

3//&/.

+6,

/6,

+6(

6<6&/.

/6(

$'&

3UHVFDOHU

[ 7,0

WR$'&

$'&

3UHVFDOHU

069

DocID026294 Rev 6 17/126

Functional overview

3.8 General-purpose inputs/outputs (GPIOs)

STM32F318C8 STM32F318K8

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

Fast I/O handling allows I/O toggling up to 36 MHz.

The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-tomemory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each of the 7 DMA channels is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I 2 C, USART, timers, DAC and ADC.

3.10.1 Nested vectored interrupt controller (NVIC)

The STM32F318x8 devices embed a nested vectored interrupt controller (NVIC) able to handle up to 60 maskable interrupt channels and 16 priority levels.

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

18/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Functional overview

3.11 Fast analog-to-digital converter (ADC)

An analog-to-digital converter, with selectable resolution between 12 and 6 bit, is embedded in the STM32F318x8 family devices. The ADC has up to 11 external channels performing conversions in single-shot or scan modes. Channels can be configured to be either singleended input or differential input. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

• Simultaneous sample and hold

• Single-shunt phase current reading techniques.

The ADC can be served by the DMA controller.

Three analog watchdogs are available. The analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) and the advanced-control timer

(TIM1) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.

The temperature sensor (TS) generates a voltage V

SENSE temperature.

that varies linearly with

The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

3.11.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

ADC and Comparators. V

REFINT

The precise voltage of V

REFINT

) provides a stable (bandgap) voltage output for the

is internally connected to the ADC1_IN18 input channel.

is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

DocID026294 Rev 6 19/126

Functional overview STM32F318C8 STM32F318K8

3.11.3 V

BAT

battery voltage monitoring

This embedded hardware feature allows the application to measure the V

BAT

battery voltage using the internal ADC channel ADC1_IN17. As the V and thus outside the ADC input range, the V

BAT

voltage may be higher than V

DDA

pin is internally connected to a bridge divider by 2. As a consequence, the converted digital value is half the V

BAT

voltage.

One 12-bit buffered DAC channel (DAC1_OUT1) can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This digital interface supports the following features:

• One DAC output channel

• 8-bit or 12-bit monotonic output

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• DMA capability

• External triggers for conversion

The STM32F318x8 devices embed one operational amplifier with external or internal follower routing and PGA capability (or even amplifier and filter capability with external components). When the operational amplifier is selected, an external ADC channel is used to enable output measurement.

The operational amplifier features:

• 8.2 MHz bandwidth

• 0.5 mA output capability

• Rail-to-rail input/output

• In PGA mode, the gain can be programmed to be 2, 4, 8 or 16.

20/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Functional overview

3.14 Ultra-fast comparators (COMP)

The STM32F318x8 devices embed up to three ultra-fast rail-to-rail comparators which offer the features below:

• Programmable internal or external reference voltage

• Selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• DAC output

•

Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 22: Embedded internal reference voltage for the value and precision of the internal reference voltage.

All comparators can wake up from STOP mode, and also generate interrupts and breaks for the timers.

3.15 Timers and watchdogs

The STM32F318x8 devices include advanced control timer, up to general-purpose timers, basic timer, two watchdog timers and a SysTick timer.

Table 4

compares the features of the advanced control, general purpose and basic timers.

Timer type Timer

Table 4. Timer feature comparison

Counter resolution

Counter type

Prescaler factor

DMA request generation

Capture/ compare

Channels

Complementary outputs

Advanced control

Generalpurpose

Basic

TIM1

TIM2

TIM15

TIM16

TIM17

(1)

TIM6

(1)

16-bit

32-bit

16-bit

Up, Down,

Up/Down

Up, Down,

Up/Down

Any integer between 1 and 65536

Yes

1. TIM1/15/16/17 can be clocked from the PLL running at 144 MHz when the system clock source is the PLL and AHB or

APB2 subsystem clocks are not divided by more than 2 cumulatively.

DocID026294 Rev 6 21/126

Functional overview STM32F318C8 STM32F318K8

3.15.1 Advanced timer (TIM1)

The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

• One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIM timers (described in

Section 3.15.2

using the same architecture, so the advanced-control timers can work

together with the TIM timers via the Timer Link feature for synchronization or event chaining.

There are up to four synchronizable general-purpose timers embedded in the

STM32F318x8 devices (see

Table 4

for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.

TIM2

TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler

It features 4 independent channels for input capture/output compare, PWM or one-pulse mode output. It can work together, or with the other general-purpose timers via the Timer

Link feature for synchronization or event chaining.

The counter can be frozen in debug mode.

It has independent DMA request generation and supports quadrature encoders.

TIM15, TIM16 and TIM 17

These three timers general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

• TIM15 has 2 channels and 1 complementary channel

• TIM16 and TIM17 have 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output.

The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

22/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Functional overview

3.15.3 Basic timer (TIM6)

This timer is mainly used for DAC trigger generation. It can also be used as a generic 16-bit time base.

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop mode. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option byte. The counter can be frozen in debug mode.

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

The RTC and the 20 backup registers are supplied through a switch that takes power from either the V

supply when present or the VBAT pin. The backup registers are five 32-bit registers used to store 20 byte of user application data when V

power is not present.

They are not reset by a system or power reset.

DocID026294 Rev 6 23/126

Functional overview STM32F318C8 STM32F318K8

The RTC is an independent BCD timer/counter. It supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

• Two programmable alarms with wake up from Stop mode capability.

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.

• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy.

• Two anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop mode on tamper event detection.

• Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop mode on timestamp event detection.

• 17-bit Auto-reload counter for periodic interrupt with wakeup from STOP capability.

The RTC clock sources can be:

• A 32.768 kHz external crystal

• A resonator or oscillator

• The internal low-power RC oscillator (typical frequency of 40 kHz)

• The high-speed external clock divided by 32.

24/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Functional overview

circuit interfaces (I

2

C)

The devices feature three I

C bus interfaces which can operate in multimaster and slave mode. Each I2C interface can support standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz) modes.

All I

C interfaces support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses

(2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters.

Pulse width of suppressed spikes

Benefits

Drawbacks

Table 5. Comparison of I2C analog and digital filters

Analog filter Digital filter

≥ 50 ns

Available in Stop mode

Variations depending on temperature, voltage, process

Programmable length from 1 to 15

I2C peripheral clocks

1. Extra filtering capability vs. standard requirements.

2. Stable length

Wakeup from Stop on address match is not available when digital filter is enabled.

In addition, it provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,

Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and

ALERT protocol management. It also has a clock domain independent from the CPU clock, allowing the I2Cx (x=1,3) to wake up the MCU from Stop mode on address match.

The I2C interfaces can be served by the DMA controller.

Refer to Table 6

for the features available in I2C1, I2C2 and I2C3.

Table 6. STM32F318x8 I

C implementation

I2C features

(1)

I2C1

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)

Independent clock

SMBus

Wakeup from STOP

1. X = supported.

I2C2

I2C3

DocID026294 Rev 6 25/126

Functional overview STM32F318C8 STM32F318K8

(USART)

The STM32F318x8 devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3).

The USART interfaces are able to communicate at speeds of up to 9 Mbit/s.

All USARTs support hardware management of the CTS and RTS signals, multiprocessor communication mode, single-wire half-duplex communication mode and synchronous mode.

USART1 supports SmartCard mode, IrDA SIR ENDEC, LIN Master capability and autobaudrate detection.

All USART interfaces can be served by the DMA controller.

Refer to Table 7

for the features available in all USARTs interfaces.

Table 7. USART features

USART modes/features

(1)

USART1

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

SmartCard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from Stop mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

1. X = supported.

USART2

USART3

3.19 Serial peripheral interfaces (SPI)/inter-integrated sound interfaces (I2S)

Two SPI interfaces (SPI2 and SPI3) allow communication up to 18 Mbit/s in slave and master modes in full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to

192 kHz are supported. When either or both of the I2S interfaces is/are configured in master

26/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Functional overview mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

Refer to Table 8

for the features available in SPI2 and SPI3.

Hardware CRC calculation

Rx/Tx FIFO

NSS pulse mode

I2S mode

TI mode

1. X = supported.

Table 8. STM32F318x8 SPI/I2S implementation

SPI features (1) SPI2

SPI3

3.20 Touch sensing controller (TSC)

The STM32F318x8 devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 17 capacitive sensing channels distributed over 6 analog I/O groups.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (for example glass, plastic). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate.

DocID026294 Rev 6 27/126

Functional overview STM32F318C8 STM32F318K8

Table 9. Capacitive sensing GPIOs available on STM32F318x8 devices

Group Capacitive sensing signal name Pin name

TSC_G1_IO1

TSC_G1_IO2

TSC_G1_IO3

TSC_G1_IO4

TSC_G2_IO1

TSC_G2_IO2

TSC_G2_IO3

TSC_G2_IO4

TSC_G3_IO2

TSC_G3_IO3

TSC_G4_IO1

TSC_G4_IO2

TSC_G4_IO3

TSC_G4_IO4

TSC_G5_IO1

TSC_G5_IO2

TSC_G5_IO3

TSC_G5_IO4

TSC_G6_IO1

TSC_G6_IO2

TSC_G6_IO3

TSC_G6_IO4

PB0

PB1

PA9

PA10

PA13

PA14

PA4

PA5

PA6

PA7

PA0

PA1

PA2

PA3

PB3

PB4

PB6

PB7

PB11

PB12

PB13

PB14

Table 10. No. of capacitive sensing channels available on

STM32F318x8 devices

Number of capacitive sensing channels

Analog I/O group

STM32F318C8 STM32F318K8

Number of capacitive sensing channels

28/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Functional overview

The STM32F318x8 devices provide an infrared transmitter solution. The solution is based on internal connections between TIM16 and TIM17 as shown in the figure below.

TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be sent. The infrared output signal is available on PB9 or PA13.

To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must be properly configured to generate correct waveforms. All standard IR pulse modulation modes can be obtained by programming the two timers output compare channels.

Figure 3. Infrared transmitter

7,0(5

IRUHQYHORS

3%3$

7,0(5

IRUFDUULHU

069

DocID026294 Rev 6 29/126

Functional overview STM32F318C8 STM32F318K8

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

30/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8

4 Pinouts and pin description

Pinouts and pin description

Figure 4. STM32F318x8 UFQFPN32 pinout

9''B

3)26&B,1

3)26&B287

1567

9''$95()

966$95()

1. The above figure shows the package top view.

8)4)31

9''B

069

DocID026294 Rev 6 31/126

Pinouts and pin description STM32F318C8 STM32F318K8

Figure 5. STM32F318x8 LQFP48 pinout

9%$7

3&26&B,1

3&26&B287

3)26&B,1

3)26&B287

1567

966$95()

9''$

/4)3

9''B

966B

069

1. The above figure shows the package top view.

32/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Pinouts and pin description

Figure 6. STM32F318x8 WLCSP49 ballout

(

)

3$ 3$ 3% 3% %227 9''$ 1&

966 9'' 3$ 3% 3% 9%$7 9''

3$ 3$ 3$ 3% 3% 3& 3&

9''

966

3% 3% 3%

3% 3&

26&B287

26&B,1

3$ 3$

966$

95()

1567

3$ 3$ 3$ 966

3% 3% 1325 3% 3% 3$ 3$

069

1. The above figure shows the package top view.

DocID026294 Rev 6 33/126

Pinouts and pin description STM32F318C8 STM32F318K8

Name

Table 11. Legend/abbreviations used in the pinout table

Abbreviation Definition

Pin name

Pin type

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

FTf

TTa

Input / output pin

5 V tolerant I/O

5 V tolerant I/O, I2C FM+ option

3.3 V tolerant I/O directly connected to ADC1

I/O structure

POR

3.3 V tolerant I/O

Standard 3.3V I/O

Dedicated to NPOR pin

Pin functions

Notes

RST

Dedicated BOOT0 pin

Bi-directional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Alternate functions

Functions selected through GPIOx_AFR registers

Additional functions

Functions directly selected/enabled through peripheral registers

34/126 DocID026294 Rev 6

Pin Number

Pin name

(function after reset)

Table 12. STM32F318x8 pin definitions

Alternate functions

Additional functions

VBAT

PC13

(1)

TAMPER1

WKUP2 (PC13)

PC14

(1)

OSC32_IN

(PC14)

PC15

(1)

OSC32_OUT

(PC14)

PF0 OSC_IN (PF0)

PF1 OSC_OUT (PF1)

NRST

VSSA/VREF-

VDDA/VREF+

PA0 -TAMPER2-

WKUP1

I/O

11 G7 PA1 I/O

PA2

PA3

I/O

FTf

RST

TTa

(1)

TIM1_CH1N

Backup power supply

WKUP2, RTC_TAMP1,

RTC_TS, RTC_OUT

OSC32_IN

(2)

(1)

(2)

OSC32_OUT

I2C2_SDA, SPI2_NSS/I2S2_WS,

TIM1_CH3N

I2C2_SCL, SPI2_SCK/I2S2_CK

OSC_IN

OSC_OUT

Device reset input/internal reset output (active low)

Analog ground/Negative reference voltage

Analog power supply/Positive reference voltage

TIM2_CH1/TIM2_ETR, TSC_G1_IO1,

USART2_CTS, EVENTOUT

ADC1_IN1, RTC_TAMP2, WKUP1

RTC_REFIN, TIM2_CH2, TSC_G1_IO2,

USART2_RTS_DE, TIM15_CH1N,

EVENTOUT

ADC1_IN2

TIM2_CH3, TSC_G1_IO3, USART2_TX,

COMP2_OUT, TIM15_CH1, EVENTOUT

ADC1_IN3, COMP2_INM

TIM2_CH4, TSC_G1_IO4, USART2_RX,

TIM15_CH2, EVENTOUT

ADC1_IN4

11 14 G6

12 15 F5

16 F4

19 G4

Pin Number

Pin name

(function after reset)

VSS_4

VDD_4

PA4

PA5

PA6

PA7

PB0

PB1

PB10

PB11

VSS_2

VDD_2

Table 12. STM32F318x8 pin definitions (continued)

Alternate functions

Additional functions

I/O

S -

TTa

(2)(3)

(3)

TSC_G2_IO1, SPI3_NSS/I2S3_WS,

USART2_CK, EVENTOUT

TSC_G3_IO2, TIM1_CH2N, EVENTOUT

ADC1_IN5, DAC1_OUT1,

COMP2_INM, COMP4_INM,

COMP6_INM

TIM2_CH1/TIM2_ETR, TSC_G2_IO2,

EVENTOUT

TIM16_CH1, TSC_G2_IO3, TIM1_BKIN,

EVENTOUT

OPAMP2_VINM

ADC1_IN10, OPAMP2_VOUT

TIM17_CH1, TSC_G2_IO4,

TIM1_CH1N, EVENTOUT

ADC1_IN15, COMP2_INP,

OPAMP2_VINP

ADC1_IN11, COMP4_INP,

OPAMP2_VINP

TSC_G3_IO3, TIM1_CH3N,

COMP4_OUT, EVENTOUT

TIM2_CH3, TSC_SYNC, USART3_TX,

EVENTOUT

ADC1_IN12

TIM2_CH4, TSC_G6_IO1, USART3_RX,

EVENTOUT

ADC1_IN14, COMP6_INP

Digital ground

Digital power supply

Pin Number

25 E2

26 G1

27 F1

28 E1

18 29 D1

19 30 D2

20 31 C2

21 32 C1

22 33 C3

Pin name

(function after reset)

PB12

PB13

PB14

PB15

PA8

PA9

PA10

PA11

PA12

Table 12. STM32F318x8 pin definitions (continued)

Alternate functions

Additional functions

I/O

I/O TT

I/O TTa

I/O FT

I/O FTf

FTf

TSC_G6_IO2, I2C2_SMBAL,

SPI2_NSS/I2S2_WS, TIM1_BKIN,

USART3_CK, EVENTOUT

TSC_G6_IO3, SPI2_SCK/I2S2_CK,

TIM1_CH1N, USART3_CTS,

EVENTOUT

TIM15_CH1, TSC_G6_IO4,

SPI2_MISO/I2S2ext_SD, TIM1_CH2N,

USART3_RTS_DE, EVENTOUT

RTC_REFIN, TIM15_CH2,

TIM15_CH1N, TIM1_CH3N,

SPI2_MOSI/I2S2_SD, EVENTOUT

MCO, I2C3_SCL, I2C2_SMBAL,

I2S2_MCK, TIM1_CH1, USART1_CK,

EVENTOUT

I2C3_SMBAL, TSC_G4_IO1, I2C2_SCL,

I2S3_MCK, TIM1_CH2, USART1_TX,

TIM15_BKIN, TIM2_CH3, EVENTOUT

TIM17_BKIN, TSC_G4_IO2, I2C2_SDA,

SPI2_MISO/I2S2ext_SD, TIM1_CH3,

USART1_RX, COMP6_OUT, TIM2_CH4,

EVENTOUT

SPI2_MOSI/I2S2_SD, TIM1_CH1N,

USART1_CTS, TIM1_CH4,

TIM1_BKIN2, EVENTOUT

TIM16_CH1, I2SCKIN, TIM1_CH2N,

USART1_RTS_DE, COMP2_OUT,

TIM1_ETR, EVENTOUT

ADC1_IN13

OPAMP2_VINP

COMP6_INM

Pin Number

24 37 A1

25 38 A2

26 39 A3

27 40 A4

28 41 B4

29 42 C4

Pin name

(function after reset)

PA13

VSS_3

VDD_3

PA14

PA15

PB3

PB4

PB5

PB6

PB7

NPOR

Table 12. STM32F318x8 pin definitions (continued)

Alternate functions

Additional functions

I/O

FTf

I/O FT

I/O

FTf

POR -

SWDIO, TIM16_CH1N, TSC_G4_IO3,

IR-OUT, USART3_CTS, EVENTOUT

Digital ground

Digital power supply

SWCLK-JTCK, TSC_G4_IO4,

I2C1_SDA, TIM1_BKIN, USART2_TX,

EVENTOUT

JTDI, TIM2_CH1/TIM2_ETR,

TSC_SYNC, I2C1_SCL,

SPI3_NSS/I2S3_WS, USART2_RX,

TIM1_BKIN, EVENTOUT

JTDO-TRACESWO, TIM2_CH2,

TSC_G5_IO1, SPI3_SCK/I2S3_CK,

USART2_TX, EVENTOUT

JTRST, TIM16_CH1, TSC_G5_IO2,

SPI3_MISO/I2S3ext_SD, USART2_RX,

TIM17_BKIN, EVENTOUT

TIM16_BKIN, I2C1_SMBAl,

SPI3_MOSI/I2S3_SD, USART2_CK,

I2C3_SDA, TIM17_CH1, EVENTOUT

TIM16_CH1N, TSC_G5_IO3, I2C1_SCL,

USART1_TX, EVENTOUT

TIM17_CH1N, TSC_G5_IO4, I2C1_SDA,

USART1_RX, EVENTOUT

Device power-on reset input

Pin Number

Pin name

(function after reset)

Table 12. STM32F318x8 pin definitions (continued)

Alternate functions

Additional functions

31 44 A5 BOOT0 I B Boot memory selection

PB8

PB9

I/O

FTf

FTf -

TIM16_CH1, TSC_SYNC, I2C1_SCL,

USART3_RX TIM1_BKIN, EVENTOUT

TIM17_CH1, I2C1_SDA, IR-OUT,

USART3_TX, COMP2_OUT,

EVENTOUT

Digital ground

32 47 D3 VSS_1 S -

"1" 48 B7 VDD_1 S Digital power supply

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (e.g. to drive an LED).

After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the Battery backup domain and BKP register description sections in the RM0366 reference manual.

2. Fast ADC channel.

3. These GPIOs offer a reduced touch sensing sensitivity. It is thus recommended to use them as sampling capacitor I/O.

Table 13. Alternate functions for Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8

TIM2

_CH1/

TIM2

_ETR

RTC

_REFIN

TIM2

_CH2

TIM2

_CH3

TIM2

_CH4

MCO

TIM2

_CH1/

TIM2

_ETR

TIM16

_CH1

TIM17

_CH1

TSC

_G1_IO1

TSC

_G1_IO2

TSC

_G1_IO3

TSC

_G1_IO4

TSC

_G2_IO1

TSC

_G2_IO2

TSC

_G2_IO3

TSC

_G2_IO4

I2C3

_SCL

I2C2

_SMBAL

I2S2

_MCK

USART2

_CTS

USART2

_RTS_D

USART2

_TX

COMP2

_OUT

USART2

_RX

SPI3_NSS/

I2S3_WS

USART2

_CK

TIM15

_CH1N

TIM15

_CH1

TIM15

_CH2

TIM1_BKIN -

TIM1

_CH1N

TIM1_CH1

USART1

_CK

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Table 13. Alternate functions for Port A (continued)

PA9

PA10

PA11

PA12

TIM17

_BKIN

I2C3

_SMBAL

TSC

_G4_IO1

I2C2

_SCL

TSC

_G4_IO2

I2C2

_SDA

TIM16

_CH1

PA13

PA14

PA15

SWDAT-

JTMS

SWCLK-

JTCK

TIM16

_CH1N

JTDI

TIM2_C

H1/

TIM2_E

TSC

_G4_IO3

TSC

_G4_IO4

I2C1

_SDA

TSC

_SYNC

I2C1

_SCL

I2S3

_MCK

SPI2_MO

SI/I2S2

_SD

TIM1_CH2

SPI2_MIS

O/I2S2ext

_SD

TIM1_CH3

TIM1

_CH1N

I2SCKIN

IR-OUT

USART1

_TX

USART1

_RX

USART1

_CTS

COMP6

_OUT

TIM1

_CH2N

USART1

_RTS_D

COMP2

_OUT

USART3

_CTS

TIM1_BKIN

USART2

_TX

TIM15

_BKIN

TIM2

_CH3

TIM2

_CH4

TIM1

_CH4

TIM1

_BKIN2

TIM1

_ETR

SPI3_NSS/

I2S3_WS

USART2

_RX

TIM1

_BKIN

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Table 14. Alternate functions for Port B

Port & pin name

PB0

PB1

PB3

PB4

PB5

PB6

PB7

PB8

PB9

JTDO-

TRACE

SWO

TIM2

_CH2

JTRST

TIM16

_CH1

TIM16

_BKIN

TIM16

_CH1N

TIM17

_CH1N

TIM16

_CH1

TIM17

_CH1

TSC

_G3_IO2

TSC

_G3_IO3

TSC

_G5_IO1

TSC

_G5_IO2

I2C1

_SMBAl

TSC

_G5_IO3

I2C1

_SCL

TSC

_G5_IO4

I2C1

_SDA

TSC

_SYNC

I2C1

_SCL

I2C1

_SDA

TIM1

_CH2N

TIM1

_CH3N

SPI3_SC

K/I2S3_

USART2

_TX

COMP4_

OUT

SPI3_MI

SO/I2S3

_SD

SPI3

_MOSI/

I2S3ext_

USART2

_RX

USART2

_CK

I2C3

_SDA

IR-OUT

USART1

_TX

USART1

_RX

USART3

_RX

USART3

_TX

COMP2_

OUT

TIM17

_BKIN

TIM17

_CH1

TIM1

_BKIN

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Table 14. Alternate functions for Port B (continued)

Port & pin name

PB10

PB11

PB12

PB13

PB14

PB15

TIM2

_CH3

TIM2

_CH4

TIM15

_CH1

RTC

_REFIN

TIM15

_CH2

TIM15

_CH1N

TSC

_SYNC

TSC

_G6_IO1

TSC

_G6_IO2

I2C2

_SMBAL

TSC

_G6_IO3

TSC

_G6_IO4

TIM1

_CH3N

SPI2_NS

S/I2S2_

TIM1

_BKIN

SPI2_SC

I2S2_CK

TIM1

_CH1N

SPI2_MI

SO/I2S2 ext_SD

SPI2_M

OSI/

I2S2_SD

TIM1

_CH2N

USART3

_TX

USART3

_RX

USART3

_CK

USART3

_CTS

USART3

_RTS

_DE

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

AF0

Port & pin name SYS_AF

PF0 -

PF1 -

AF1

TIM2/TIM15/

TIM16/TIM17/

EVENT

Table 15. Alternate functions for Port F

AF2

I2C3/TIM1/TIM2/

TIM15

I2C3/TIM15/TSC

AF3 AF4 AF5

I2C1/I2C2/TIM1/

TIM16/TIM17

SPI2/I2S2/

SPI3/I2S3/

Infrared

I2C2_SDA

I2C2_SCL

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

AF6 AF7

SPI2/I2S2/SPI3/

I2S3/TIM1/

Infrared

USART1/USAR

T2/USART3/

GPCOMP6

TIM1_CH3N -

STM32F318C8 STM32F318K8 Memory mapping

Figure 7. STM32F318x8 memory mapping

[

))

[))))))))

&RUWH[0

ZLWK)38

,QWHUQDO

3HULSKHUDOV

[(

[

$+%

5HVHUYHG

$+%

5HVHUYHG

[))

$+%

[&

[

5HVHUYHG

[&

[$

$3%

[

5HVHUYHG

[$

$3%

[

[)))))))

2SWLRQE\WHV

[))))

6\VWHPPHPRU\

[)))'

[ 3HULSKHUDOV

[

65$0

&2'(

5HVHUYHG

[

)ODVKPHPRU\

[

5HVHUYHG

[

)ODVKV\VWHP

PHPRU\RU65$0

GHSHQGLQJRQ%227

FRQILJXUDWLRQ

06Y9

DocID026294 Rev 6 45/126

Memory mapping STM32F318C8 STM32F318K8

Bus

Table 16. STM32F318x8 peripheral register boundary addresses (1)

Boundary address Size (byte) Peripheral

AHB3

AHB2

AHB1

APB2

0x5000 0000 - 0x5000 03FF

0x4800 1800 - 0x4FFF FFFF

0x4800 1400 - 0x4800 17FF

0x4800 1000 - 0x4800 13FF

0x4800 0C00 - 0x4800 0FFF

0x4800 0800 - 0x4800 0BFF

0x4800 0400 - 0x4800 07FF

0x4800 0000 - 0x4800 03FF

0x4002 4400 - 0x47FF FFFF

0x4002 4000 - 0x4002 43FF

0x4002 3400 - 0x4002 3FFF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0400 - 0x4002 0FFF

0x4002 0000 - 0x4002 03FF

0x4001 8000 - 0x4001 FFFF

0x4001 4C00 - 0x4001 7FFF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3000 - 0x4001 37FF

0x4001 2C00 - 0x4001 2FFF

0x4001 0800 - 0x4001 2BFF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 9C00 - 0x4000 FFFF

1 K

2 K

3 K

1 K

3 K

1 K

32 K

13 K

1 K

8 K

1 K

~132 M

1 K

~128 M

1 K

3 K

1 K

3 K

1 K

25 K

Reserved

RCC

Reserved

DMA1

Reserved

TIM17

TIM16

TIM15

Reserved

USART1

Reserved

ADC1

Reserved

GPIOF

Reserved

GPIOC

GPIOB

GPIOA

Reserved

TSC

Reserved

CRC

Reserved

Flash interface

TIM1

Reserved

EXTI

SYSCFG + COMP +

OPAMP

Reserved

46/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Memory mapping

Table 16. STM32F318x8 peripheral register boundary addresses (continued) (1)

Bus Boundary address Size (byte) Peripheral

APB1

0x4000 7C00 - 0x4000 9BFF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 5C00 - 0x4000 6FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 4C00 - 0x4000 53FF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 1400 - 0x4000 27FF

0x4000 1000 - 0x4000 13FF

0x4000 0400 - 0x4000 0FFF

0x4000 0000 - 0x4000 03FF

SRAM

0x2000 4000 - 3FFF FFFF

0x2000 0000 - 0x2000 3FFF

Option bytes 0x1FFF F800 - 0x1FFF FFFF

Memory

0x1FFF D800 - 0x1FFF F7FF

0x0801 0000 - 0x1FFF D7FF

0x0800 0000 - 0x0800 FFFF

0x0001 0000 - 0x07FF FFFF

Memory or

SRAM

0x0000 000 - 0x0000 FFFF

1 K

5 K

1 K

2 K

8 K

1 K

3 K

1 K

~512 M

16 K

2 K

8 K

~384 M

64 K

~128 M

64 K

Reserved

I2C3

DAC1

PWR

Reserved

I2C2

I2C1

Reserved

USART3

USART2

I2S3ext

SPI3/I2S3

SPI2/I2S2

I2S2ext

IWDG

WWDG

RTC

Reserved

TIM6

Reserved

TIM2

Reserved

SRAM

Option bytes

System memory

Reserved

Main Flash memory

Reserved

Main Flash memory, system memory or SRAM depending on BOOT configuration

1. The gray color is used for reserved Flash memory addresses.

DocID026294 Rev 6 47/126

Electrical characteristics STM32F318C8 STM32F318K8

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 σ ).

Unless otherwise specified, typical data are based on T

= 25 °C, V

= 1.8 V,V

DDA

= 3.3 V.

They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 8 .

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9

Figure 8. Pin loading conditions Figure 9. Pin input voltage

0&8SLQ 0&8SLQ

& S)

069

48/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8

6.1.6 Power supply scheme

Figure 10. Power supply scheme

Electrical characteristics

%$7

±9

3RZHU

VZLWFK

%DFNXSFLUFXLWU\

/6(57&

:DNHXSORJLF

%DFNXSUHJLVWHUV

*3,2V

287

,2ORJLF

.HUQHOORJLF

&38

GLJLWDO

PHPRULHV

[Q)

[)

''$

5HJXODWRU

)

5()

$'&'$&

$QDORJ5&V3//

FRPSDUDWRUV23$03

66$

069

Caution: Each power supply pair (for example V

, V

DDA

SSA

) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

DocID026294 Rev 6 49/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Figure 11. Current consumption measurement scheme

,''B9%$7

9%$7

,''

9''

,''$

9''$

069

50/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 17: Voltage characteristics

Table 18: Current characteristics

, and

Table 19: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 17. Voltage characteristics

(1)

Ratings Min Max Unit

DDA

–V

DDA

(2)

DDx

SSX

− V

ESD(HBM)

External main supply voltage (including V

BAT

)

and

External main supply voltage

Allowed voltage difference for V

> V

Input voltage on FT and FTf pins

Input voltage on TTa and TT pins

Input voltage on POR pin

Input voltage on any other pin

Input voltage on Boot0 pin

Variations between different V

DD power pins

Variations between all the different ground pins

(3)

Electrostatic discharge voltage (human body model)

DDA

-0.3

1.95

-0.3

4.0

− 0.3

0.4

+ 4.0

4.0

DDA

+ 4.0

4.0

50 see

Section 6.3.11: Electrical sensitivity characteristics

1. All main power (V

DDA

, V

DDA

) and ground (V

, V

SSA

) pins must always be connected to the external power supply, in the

must power on before or at the same time as V

must be greater than or equal to V

DDA

and V

in the power up sequence.

2. V

maximum must always be respected. Refer to

Table 18: Current characteristics for the maximum allowed injected

current values.

3. Include V

REF-

pin.

V mV

DocID026294 Rev 6 51/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Symbol

Table 18. Current characteristics

Ratings Max.

Unit

Σ I

VDD

VSS

VDD

VSS

INJ(PIN)

Total current into sum of all VDD_x power lines (source)

Total current out of sum of all VSS_x ground lines (sink)

Maximum current into each V

DD_x power line (source)

(1)

Maximum current out of each V

SS _x ground line (sink) (1)

Output current sunk by any I/O and control pin

130

-130

100

-100

IO(PIN)

Output current sourced by any I/O and control pin

Total output current sunk by sum of all IOs and control pins

(2)

Total output current sourced by sum of all IOs and control pins

(2)

Injected current on TT, FT, FTf and B pins

(3)

Injected current on TC and RST pin (4)

Injected current on TTa pins

(5)

Total injected current (sum of all I/O and control pins)

(6)

-25

-80

-5/+0

+/-5

+/-5 mA

Σ I

INJ(PIN)

+/-25

1. All main power (V permitted range.

, V

DDA

) and ground (V

and V

SSA

) pins must always be connected to the external power supply, in the

2. This current consumption must be correctly distributed over all I/Os and control pins.The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.

3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

4. A positive injection is induced by V

exceeded. Refer to

> V

while a negative injection is induced by V

Table 17: Voltage characteristics

< V

. I

for the maximum allowed input voltage values.

must never be

5. A positive injection is induced by V

exceeded. Refer also to

> V

DDA

while a negative injection is induced by V disturbs the analog performance of the device. See note

for the maximum allowed input voltage values. Negative injection

(2) below

Table 61

< V

. I

INJ

(PIN) must never be

6. When several inputs are submitted to a current injection, the maximum Σ I negative injected currents (instantaneous values).

INJ(PIN)

is the absolute sum of the positive and

Symbol

STG

Table 19. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

52/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

6.3.1 General operating conditions

Symbol

Table 20. General operating conditions

Parameter Conditions Min Max Unit f f f

HCLK

PCLK1

PCLK2

DDA

BAT

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

Analog operating voltage

(OPAMP and DAC not used)

Analog operating voltage

(OPAMP and DAC used)

Must have a potential equal to or higher than

Analog operating voltage

Backup operating voltage -

I/O input voltage

Power dissipation at

A suffix version suffix version

= 85 °C for suffix 6 or

= 105 °C for suffix 7

(2)

Ambient temperature for 6

Ambient temperature for 7

Junction temperature range

BOOT0

WLCSP49

LQFP48

UFQFPN32

Maximum power dissipation

Low power dissipation

(3)

Maximum power dissipation

Low power dissipation

(3)

6 suffix version

7 suffix version

1.65

2.4

1.8

1.65

1.95

3.6

TC I/O

TT I/O

(1)

–0.3

-0.3

+0.3

3.6

TTa I/O pins and POR pin –0.3

DDA

+0.3

FT and FTf I/O

(1)

–0.3

5.2

408

364

540

–40 85

–40 105

–40 125

–40

105

125

MHz

V mW

°C

1. To sustain a voltage higher than V

+0.3 V, the internal pull-up/pull-down resistors must be disabled.

2. If T is lower, higher P

thermal characteristics .

values are allowed as long as T

does not exceed T

Jmax

. See

Table 74: Package

3. In low power dissipation state, T can be extended to this range as long as T

Table 74: Package thermal characteristics

does not exceed T

Jmax

. See

DocID026294 Rev 6 53/126

109

Electrical characteristics STM32F318C8 STM32F318K8

The parameters given in

Table 21 are derived from tests performed under the ambient

temperature condition summarized in

Table 20 .

Symbol t

VDD t

VDDA

Table 21. Operating conditions at power-up / power-down

Parameter Conditions Min Max

rise time rate

fall time rate

DDA

rise time rate

DDA

fall time rate

∞

Unit

µs/V

54/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

6.3.4

Note:

The parameters given in

Table 22 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Table 20 .

Symbol

Table 22. Embedded internal reference voltage

Parameter Conditions Min Typ Max Unit

REFINT

S_vrefint

RERINT

Internal reference voltage –40 °C < T

< +105 °C 1.20

1.23

1.25

ADC sampling time when reading the internal reference voltage

2.2

Internal reference voltage spread over the temperature range

= 1.8 V ±10 mV 10

(1)

Temperature coefficient -

100

(1)

µs mV

Coeff ppm/°

T Internal reference voltage temporization

1.5

2.5

4.5

1. Guaranteed by design.

2. Guaranteed by design. Latency between the time when pin NPOR is set to 1 by the application and the time when V

REFINTRDYF

is set to 1 by the hardware.

Table 23. Internal reference voltage calibration values

Calibration value name Description Memory address

REFINT_CAL

Raw data acquired at temperature of 30 °C

DDA

= 3.3 V

0x1FFF F7BA - 0x1FFF F7BB

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 11: Current consumption measurement scheme

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.

The total current consumption is the sum of I

and I

DDA

DocID026294 Rev 6 55/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

or V

(no load)

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted to the f

HCLK

frequency (0 wait state from 0 to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)

• Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)

• When the peripherals are enabled f

PCLK2

= f

HCLK

and f

PCLK1

= f

HCLK/2

• When f

HCLK

> 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or

HSE (8 MHz) in bypass mode.

The parameters given in

Table 24 to

Table 30

are derived from tests performed under ambient temperature and supply voltage conditions summarized in

Table 20 .

Table 24. Typical and maximum current consumption from VDD supply at VDD = 1.8V

All peripherals enabled All peripherals disabled

Symbol Parameter Conditions f

HCLK

Typ

Supply

current in

Run mode,

executing

from Flash

72 MHz 43.8

47.6

48.9

64 MHz 39.3

42.6

43.7

External clock (HSE bypass)

48 MHz 30.0

32.3

33.2

32 MHz 20.5

21.8

22.5

24 MHz 15.7

16.6

17.2

Internal clock (HSI)

8 MHz 5.3

5.6

5.8

1 MHz 0.99

1.13

1.19

64 MHz 36.2

39.0

39.8

48 MHz 27.7

29.7

30.4

32 MHz 19.0

20.3

20.7

24 MHz 14.6

15.5

15.9

8 MHz 5.2

5.5

5.7

Max @ T

(1)

25°C 85°C 105°C

Typ

25°C

Max @ T

85°C

52.0

24.7

26.3

26.9

46.2

22.1

23.6

24.1

34.8

16.9

18.0

18.4

23.4

11.6

12.3

12.6

17.7

8.9

9.4

9.7

6.4

3.11

3.24

3.45

1.36

0.71

0.84

0.88

41.8

21.9

23.3

23.7

31.6

16.7

17.8

18.1

21.4

11.5

12.2

12.3

16.3

6.0

6.4

6.5

5.8

3.09

3.31

3.38

(1)

105°C

3.59

1.03

24.5

18.6

12.6

28.1

25.0

19.0

12.9

10.0

6.7

3.51

Unit mA

56/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Table 24. Typical and maximum current consumption from VDD supply at VDD = 1.8V (continued)

All peripherals enabled All peripherals disabled

Symbol Parameter Conditions f

HCLK

Max @ T

(1)

Max @ T

(1)

Typ Typ

25°C 85°C 105°C 25°C 85°C 105°C

72 MHz 43.4 47.2

(2)

48.5

64 MHz 38.9

42.0

43.2

51.3

(2)

45.6

24.3 26.0

21.6

(2)

23.1

26.5

23.7

27.6

(2)

24.5

Supply current in

Run mode, executing from RAM

Supply current in

Sleep mode, executing from Flash or RAM

External clock (HSE bypass)

48 MHz 29.4

31.6

32.6

32 MHz 20.0

21.3

22.0

24 MHz 15.1

16.2

16.6

8 MHz 4.95

5.31

5.52

Internal clock (HSI)

External clock (HSE bypass)

48 MHz 16.5

17.6

18.3

32 MHz 13.3

14.2

14.7

24 MHz 10.1

10.7

11.2

8 MHz 3.28

3.54

3.76

Internal clock (HSI)

1 MHz 0.60

0.73

0.83

64 MHz 35.6

38.3

39.1

48 MHz 27.1

29.0

29.6

34.1

16.6

17.6

18.1

22.8

11.1

11.8

12.1

17.1

8.4

8.9

9.2

5.69

2.73

2.95

3.10

32 MHz 18.4

19.6

20.0

24 MHz 13.9

14.8

15.2

20.7

10.8

11.6

11.8

15.6

5.4

5.8

6.0

8 MHz 4.69

5.02

5.19

72 MHz 29.1 31.2

(2)

32.4

5.34

33.9

(2)

2.60

5.9

2.81

6.3

(2)

2.92

6.6

64 MHz 26.0

27.9

28.8

30.1

5.3

5.6

5.9

1 MHz 0.40

0.50

0.61

64 MHz 22.6

24.2

24.9

48 MHz 17.2

18.4

18.9

32 MHz 11.7

12.4

12.8

24 MHz 8.9

9.4

9.7

8 MHz 3.02

3.26

3.42

0.99

0.33

0.40

0.52

41.0

21.3

22.8

23.2

30.8

19.0

16.1

3.37

17.2

3.63

17.4

3.83

15.2

2.74

2.94

3.10

11.5

2.12

2.30

2.42

3.93

0.66

0.77

0.88

0.78

0.09

0.14

0.27

25.9

4.89

5.21

5.41

19.5

3.70

3.96

4.12

13.2

2.49

2.66

2.81

10.0

1.28

1.46

1.59

3.58

0.53

0.64

0.74

0.41

5.58

4.27

2.96

1.68

0.91

18.7

12.4

9.4

3.24

0.69

23.9

17.9

12.0

6.1

3.05

6.8

(2)

6.1

3.98

3.26

2.56

1.05

1. Guaranteed by characterization results.

2. Data based on characterization results and tested in production with code executing from RAM.

Unit mA mA

DocID026294 Rev 6 57/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Table 25. Typical and maximum current consumption from the V

DDA

supply

DDA

= 2.4 V V

DDA

= 3.6 V

Symbol Parameter

Conditions

(1) f

HCLK

Typ

Max @ T

(2)

25 °C 85 °C 105 °C

Typ

Max @ T

(2)

25 °C 85 °C 105 °C

Unit

DDA

Supply current in

Run mode, code executing from Flash or RAM

HSE bypass

HSI clock

72 MHz 225 248 (3)

64 MHz 198 221

48 MHz 149 169

32 MHz 102 120

24 MHz 79 96

8 MHz 3.1

1 MHz 3.1

4.1

64 MHz 263 287

48 MHz 214 236

32 MHz 167 187

24 MHz 144 164

8 MHz 67 81

261 266 (3)

234

178

239

182

128

101

4.1

131

104

5.1

301

248

196

306

252

199

171

173

248 270 (3)

219

163

241

182

112

3.1

131

104

4.1

292

237

185

317

260

206

161

179

290 296 (3)

258

196

263

200

139

110

4.1

142

112

5.1

333

272

216

339

277

219

188

191

µA

1. Current consumption from the V

DDA

PLL is off, I

DDA

supply is independent of whether the peripherals are on or off. Furthermore when the

is independent from the frequency.

2. Guaranteed by characterization results.

3. Data based on characterization results and tested in production with code executing from RAM.

Symbol

Table 26. Typical and maximum V

consumption in Stop mode

Parameter Conditions

Typ @V

= 1.8 V

DDA

= 3.3 V)

Max

Supply current in Stop mode All oscillators off

1.8 V

3.11

Unit

= 25°C T

= 85°C T

= 105°C

7.3

160 359 µA

Symbol

Table 27. Typical and maximum V

DDA

consumption in Stop mode

Typ @V

= 1.8 V) Max

Parameter Conditions Unit

DDA

Supply current in

Stop mode

All oscillators off 0.70 0.71 0.73 0.76 0.81 0.87 0.94

1.6

2.1

2.7

µA

58/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Symbol

Table 28. Typical and maximum current consumption from V

BAT

supply

Para meter

Conditions

(1)

Typ.@V

BAT

Max.

BAT

= 3.6V

(2)

(°C)

85 105 1.65V 1.8V 2V 2.4V 2.7V

3V 3.3V 3.6V

DD_VBAT

Backup domain supply current

LSE & RTC

ON; “Xtal mode” lower driving capability;

LSEDRV[1:

0] = '00'

LSE & RTC

ON; “Xtal mode” higher driving capability;

LSEDRV[1:

0] = '11'

0.41

0.65

0.43 0.46 0.54

0.68 0.73 0.80

0.59 0.66 0.74 0.82

0.87 0.95 1.03 1.14

1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.

2. Guaranteed by characterization results.

Unit

µA

Figure 12. Typical V

BAT

current consumption (LSE and RTC ON/LSEDRV[1:0] = ‘00’)

& &

06[[[[[9\

DocID026294 Rev 6 59/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Typical current consumption

The MCU is placed under the following conditions:

• V

= 1.8 V, V

DDA

= 3.3 V

• All I/O pins available on each package are in analog input configuration

• The Flash access time is adjusted to f

HCLK

frequency (0 wait states from 0 to 24 MHz,

1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash prefetch is ON

• When the peripherals are enabled, f

APB1

= f

AHB/2

, f

APB2

= f

AHB

• PLL is used for frequencies greater than 8 MHz

• AHB prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz,

500 kHz and 125 kHz respectively.

Symbol

Table 29. Typical current consumption in Run mode, code with data processing

running from Flash

Typ

Parameter Conditions f

HCLK Peripherals enabled

Peripherals disabled

DDA

(1)

Supply current in

Run mode from

supply

Supply current in

Run mode from

DDA

supply

Running from HSE crystal clock 8 MHz, code executing from

Flash

72 MHz

64 MHz

48 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

72 MHz

64 MHz

48 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

42.6

38.2

29.1

19.9

15.2

10.2

5.2

2.97

1.76

1.16

0.86

0.63

237.3

208.7

154.6

105.1

81.3

57.7

0.87

24.0

21.6

16.5

11.3

8.6

5.9

3.08

1.79

1.13

0.80

0.63

0.50

Unit mA

µA

1. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,

OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.

60/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Table 30. Typical current consumption in Sleep mode, code running from Flash or RAM

Typ

Symbol Parameter Conditions f

HCLK Peripherals enabled

Peripherals disabled

Unit

Supply current in

Sleep mode from

supply

125 kHz

72 MHz

64 MHz

48 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

72 MHz

64 MHz

48 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

27.5

24.5

18.5

12.5

9.4

6.3

3.08

1.93

1.24

0.90

0.73

0.59

5.6

5.0

3.82

2.62

2.02

1.42

0.65

0.55

0.48

0.44

0.42

0.41

DDA

(1)

Supply current in

Sleep mode from

DDA

supply

Running from HSE crystal clock 8 MHz, code executing from

Flash or RAM

237.3

208.7

154.6

105.1

81.3

57.7

0.87

µA

1. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,

OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.

DocID026294 Rev 6 61/126

109

Electrical characteristics STM32F318C8 STM32F318K8

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 48: I/O static characteristics .

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 32: Peripheral current consumption ), the I/Os used by an application also contribute to the current consumption.

When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

× f

× C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

62/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Symbol

Table 31. Switching output I/O current consumption

Parameter Conditions

(1)

I/O toggling frequency (f

)

2 MHz

I/O current consumption

= 1.8 V

C ext

C = C

INT

= 0 pF

+ C

EXT

+ C

C ext

C = C

INT

= 1.8 V

= 10 pF

+ C

EXT

C ext

C = C

INT

= 1.8 V

= 22 pF

+ C

EXT

C ext

C = C

INT

= 1.8 V

= 33 pF

+ C

EXT

+ C

C ext

C = C

INT

= 1.8 V

= 47 pF

+ C

EXT

+ C

4 MHz

8 MHz

18 MHz

36 MHz

48 MHz

2 MHz

4 MHz

8 MHz

18 MHz

36 MHz

48 MHz

2 MHz

4 MHz

8 MHz

18 MHz

36 MHz

2 MHz

4 MHz

8 MHz

18 MHz

36 MHz

2 MHz

4 MHz

8 MHz

18 MHz

1. CS = 5 pF (estimated value).

Unit mA

Typ

0.94

1.97

3.62

0.28

0.55

1.15

2.42

0.36

0.75

1.59

3.25

0.23

0.45

0.25

0.57

1.16

2.45

3.03

0.19

0.10

0.17

0.40

0.78

1.51

2.06

0.14

DocID026294 Rev 6 63/126

109

Electrical characteristics STM32F318C8 STM32F318K8

On-chip peripheral current consumption

The MCU is placed under the following conditions:

• all I/O pins are in analog input configuration

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

• ambient operating temperature at 25°C and V

= 1.8 V, V

DDA

= 3.3 V.

64/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Table 32. Peripheral current consumption

Typical consumption (1)

Peripheral

BusMatrix

(2)

DMA1

CRC

GPIOA

GPIOB

GPIOC

GPIOD

GPIOF

TSC

ADC1

APB2-Bridge

(3)

SYSCFG

TIM1

USART1

TIM15

TIM16

TIM17

APB1-Bridge

(3)

TIM2

TIM6

WWDG

SPI2

SPI3

USART2

USART3

I2C1

I2C2

PWR

DAC

I2C3

35.2

34.2

13.9

13.1

5.8

40.7

7.4

4.6

9.4

4.5

8.3

10.5

21.0

14.3

10.1

10.4

15.9

2.7

3.2

27.6

8.6

1.5

1.0

4.7

11.3

6.7

2.0

8.5

8.3

Unit

µA/MHz

1. The power consumption of the analog part (I

DDA

) of peripherals such as ADC, DAC, Comparators, OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.

2. BusMatrix is automatically active when at least one master is ON (CPU or DMA1).

3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus.

DocID026294 Rev 6 65/126

109

Electrical characteristics STM32F318C8 STM32F318K8

6.3.5 Wakeup time from low-power mode

The wakeup times given in Table 33

are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:

• For Stop or Sleep mode: the wakeup event is WFE.

• WKUP1 (PA0) pin is used to wakeup from Stop and Sleep modes.

All timings are derived from tests performed under ambient temperature and V

DD voltage conditions summarized in

Table 20 .

supply

Symbol t

WUSTOP

Table 33. Low-power mode wakeup timings

Parameter Typ @ V

= 1.8 V, V

DDA

= 3.3 V

Wakeup from Stop mode 3.9

WUSLEEP

Wakeup from Sleep mode 6.0

WUPOR

Wakeup from Power Off mode

72.8

Max

4.5

103

Unit

µs

CPU clock cycles

µs

66/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The

external clock signal has to respect the I/O characteristics in Section 6.3.13

. However, the

Symbol

Table 34. High-speed external user clock characteristics

Parameter f

HSE_ext

User external clock source frequency

(1)

HSEH

HSEL t w(HSEH) t w(HSEL) t r(HSE) t f(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

1. Guaranteed by design.

(1)

Conditions

Min

0.7V

Typ Max Unit

0.3V

MHz

V ns

Figure 13. High-speed external clock source AC timing diagram

WZ+6(+

9+6(+

9+6(/

WU+6(

7+6(

WI+6( WZ+6(/

069

DocID026294 Rev 6 67/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The

external clock signal has to respect the I/O characteristics in Section 6.3.13

. However, the

Symbol

Table 35. Low-speed external user clock characteristics

Parameter f

LSE_ext

LSEH

User External clock source frequency

(1)

OSC32_IN input pin high level voltage

LSEL

OSC32_IN input pin low level voltage t w(LSEH) t w(LSEL) t r(LSE) t f(LSE)

OSC32_IN high or low time

OSC32_IN rise or fall time

1. Guaranteed by design.

(1)

Conditions

Min

0.7V

450

Typ

32.768

Max

1000

0.3V

Unit kHz

V ns

Figure 14. Low-speed external clock source AC timing diagram

WZ/6(+

9/6(+

9/6(/

WU/6(

7/6(

WI/6(

WZ/6(/

069

68/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 36 . In the

application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Symbol

Table 36. HSE oscillator characteristics

Parameter Conditions

(1)

Min

(2)

Typ Max

(2)

Unit f

OSC_IN

Oscillator frequency

Feedback resistor

HSE current consumption

During startup

(3)

=3.3 V, Rm= 30 Ω ,

CL=10 pF@8 MHz

=3.3 V, Rm= 45 Ω ,

CL=10 pF@8 MHz

=3.3 V, Rm= 30 Ω ,

CL= 5 pF@32 MHz

=3.3 V, Rm= 30 Ω ,

CL=10 pF@32 MHz

200

0.4

0.5

0.8

8.5

MHz k Ω mA

=3.3 V, Rm= 30 Ω ,

CL=20 pF@32 MHz

1.5

g m t

SU(HSE)

(4)

Oscillator transconductance

Startup time

Startup

is stabilized

2 -

mA/V ms

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by design.

3. This consumption level occurs during the first 2/3 of the t

SU(HSE)

startup time.

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

DocID026294 Rev 6 69/126

109

Electrical characteristics

Note:

STM32F318C8 STM32F318K8

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (Typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 15

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 15. Typical application with an 8 MHz crystal

5HVRQDWRUZLWKLQWHJUDWHG

FDSDFLWRUV

26&B,1 I

+6(

0+]

UHVRQDWRU

)

%LDV

FRQWUROOHG

JDLQ

(;7

26&B287

069

1. R

EXT

value depends on the crystal characteristics.

70/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 37 . In the

(frequency, package, accuracy).

Symbol

Table 37. LSE oscillator characteristics (f

LSE

= 32.768 kHz)

Parameter Conditions

(1)

Min

(2)

Typ Max

(2)

Unit

LSE current consumption

LSEDRV[1:0]=00 lower driving capability

LSEDRV[1:0]=10 medium low driving capability

LSEDRV[1:0]=01 medium high driving capability

LSEDRV[1:0]=11 higher driving capability

LSEDRV[1:0]=00 lower driving capability

0.5

0.9

1.3

1.6

µA g m

Oscillator transconductance

LSEDRV[1:0]=10 medium low driving capability

LSEDRV[1:0]=01 medium high driving capability

15 -

µA/V

LSEDRV[1:0]=11 higher driving capability

25 t

SU(LSE)

(3)

Startup time V

is stabilized 2 s

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

2. Guaranteed by design.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

DocID026294 Rev 6 71/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Figure 16. Typical application with a 32.768 kHz crystal

5HVRQDWRUZLWKLQWHJUDWHG

FDSDFLWRUV

26&B,1 I

/6(

N+]

UHVRQDWRU

'ULYH

SURJUDPPDEOH

DPSOLILHU

26&B287

Note:

069

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

72/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8

6.3.7 Internal clock source characteristics

Electrical characteristics

The parameters given in

Table 38 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 20

High-speed internal (HSI) RC oscillator

Symbol

Table 38. HSI oscillator characteristics (1)

Parameter Conditions Min f

HSI

TRIM

DuCy

ACC

(HSI)

HSI

Frequency

HSI user trimming step

Duty cycle

Accuracy of the HSI oscillator

(2)

= -40 to

105°C

-2.8

(3)

= -10 to 85°C -1.9

(3)

= 0 to 85°C -1.9

(3)

= 0 to 70°C -1.3

(3)

= 0 to 55°C

= 25°C (4)

-1

(3)

-1

(2)

I t su(HSI)

DDA(HSI)

HSI oscillator startup time

HSI oscillator power consumption

1. V

DDA

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Factory calibrated, parts not soldered.

Typ

Max

(2)

100

Figure 17. HSI oscillator accuracy characterization results for soldered parts

."9

.*/

Unit

MHz

µs

µA

DocID026294 Rev 6

069

73/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Low-speed internal (LSI) RC oscillator

Symbol

Table 39. LSI oscillator characteristics

(1)

Parameter Min f

LSI t su(LSI)

(2)

DD(LSI)

(2)

Frequency 30

LSI oscillator startup time

LSI oscillator power consumption

1. V

DDA

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design.

Typ

0.75

Max

1.2

Unit kHz

µs

µA

The parameters given in

Table 40 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 20

Table 40. PLL characteristics

Value

Symbol f

PLL_IN

Parameter

PLL input clock

(1)

PLL input clock duty cycle

PLL multiplier output clock

PLL lock time

Cycle-to-cycle jitter

Min

(2)

40 (2)

(2)

Typ

Unit f

PLL_OUT t

LOCK

Jitter

Max

(2)

60 (2)

200

(2)

300

(2)

1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

2. Guaranteed by design.

MHz

µs ps

74/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Flash memory

The characteristics are given at T

= –40 to 105 °C unless otherwise specified.

Symbol

Table 41. Flash memory characteristics

Parameter Conditions t t

I prog

ERASE t

16-bit programming time T

= –40 to +105 °C

Page (2 KB) erase time T

= –40 to +105 °C

Mass erase time T

= –40 to +105 °C

Write mode

Supply current

Erase mode

1. Guaranteed by design.

Min

Typ Max

(1)

53.5

Unit

µs ms ms mA mA

Symbol

Table 42. Flash memory endurance and data retention

Value

Parameter Conditions

Min

(1)

N t

END

RET

Endurance

Data retention

= –40 to +85 °C (6 suffix versions)

= –40 to +105 °C (7 suffix versions)

1 kcycle (2) at T

= 85 °C

1 kcycle

(2)

at T

= 105 °C

10 kcycles (2) at T

= 55 °C

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

Unit kcycles

Years

DocID026294 Rev 6 75/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

SS compliant with the IEC 61000-4-4 standard.

and

through a 100 pF capacitor, until a functional disturbance occurs. This test is

A device reset allows normal operations to be resumed.

The test results are given in

Table 43

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

Table 43. EMS characteristics

Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

= 1.8 V, LQFP64, T

= +25°C, f

HCLK

= 72 MHz conforms to IEC 61000-4-2

= 1.8 V, LQFP64, T

= +25°C, f

HCLK

= 72 MHz conforms to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

76/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 44. EMI characteristics

Symbol Parameter

EMI

Conditions

Monitored frequency band

Peak level

= 1.8 V, T

= 25 °C,

LQFP64 package compliant with IEC

61967-2

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

Max vs. [f

HSE

HCLK

]

8/72 MHz

Unit dBµV

Symbol

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Ratings

Table 45. ESD absolute maximum ratings

Conditions Packages Class

Maximum value (1)

Unit

ESD(HBM)

Electrostatic discharge voltage

(human body model)

= +25 °C, conforming to JESD22-A114

All

ESD(CDM)

Electrostatic discharge voltage

(charge device model)

= +25 °C, conforming to ANSI/ESD STM5.3.1

WLCSP49

All other

1. Guaranteed by characterization results.

2000

250

500

DocID026294 Rev 6 77/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol

Parameter

Table 46. Electrical sensitivities

Conditions

Static latch-up class T

= +105 °C conforming to JESD78A

Class

2 level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator frequency deviation).

The test results are given in

Table 47

Symbol

Table 47. I/O current injection susceptibility

Functional susceptibility

Description

Injected current on BOOT0

Negative injection

-0

Positive injection

(1)

Unit

-0 +5

INJ

Injected current on PC0 pin (TTa pin)

Injected current PC0, PC1, PC2, PC3, PA0, PA1, PA2,

PA3, PA4, PA6, PA7, PC4, PB0, PB10, PB11, PB13 with induced leakage current on other pins from this group less than -100 µA or more than +100 µA

Injected current on any other TT, FT, FTf and NPOR pins

Injected current on all other TC, TTa and RESET pins

-5

(1)

+5 mA

1. Injection is not possible.

78/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8

Note:

Electrical characteristics

It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

General input/output characteristics

Unless otherwise specified, the parameters given in Table 48

are derived from tests

performed under the conditions summarized in Table 20

. All I/Os are CMOS and TTL compliant.

Symbol

V hys

I lkg

Parameter

Low level input voltage

High level input voltage

Schmitt trigger hysteresis

Input leakage current

(3)

Weak pull-up equivalent resistor (5)

Table 48. I/O static characteristics

Conditions Min Typ

TTa and TT I/O

FT and FTf I/O -

NPOR I/O input low-level voltage

BOOT0 I/O

All I/Os except BOOT0

TTa and TT I/O

FT and FTf I/O

0.445 V

+0.398

(1)

0.5 V

+0.2

(1)

NPOR I/O input high-level voltage

BOOT0

0.5 V

DDA

+0.2 -

All I/Os except BOOT0

TC and TTa I/O

FT, FTf I/O and NPOR pin

0.2 V

+0.95

(1)

0.7 V

(2)

200

(1)

100

(1)

300

(1)

BOOT0

TC, FT and FTf I/O

TTa I/O in digital mode

≤ V

TTa I/O in digital mode

≤ V

DDA

TTa I/O in analog mode

≤ V

DDA

FT and FTf I/O

(4)

≤ V

≤ 5 V

POR

DDA

≤ V

≤ 5 V

Max

0.3 V

+ 0.07

(1)

0.475 V

-0.2

(1)

0.475 V

0.3 V

– 0.3

(1)

0.3 V

(2)

DDA

±0.1

±0.2

-0.2

Unit

V mV

µA

= V

25 40 55 k Ω

DocID026294 Rev 6 79/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Symbol Parameter

Table 48. I/O static characteristics (continued)

Conditions Min Typ Max Unit

Weak pull-down equivalent resistor (5)

= V

25 40 55 k Ω

I/O pin capacitance 5 -

1. Data based on design simulation

2. Tested in production.

3. Leakage could be higher than the maximum value. if negative current is injected on adjacent pins. Refer to Table 47: I/O current injection susceptibility

4. To sustain a voltage higher than V

+0.3 V, the internal pull-up/pull-down resistors must be disabled.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimum (~10% order).

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in

Figure 18

and

Figure 19

for standard I/Os.

Figure 18. TC and TTa I/O input characteristics

,+PLQ

,/PD[

7HVWHGLQSURGXFWLRQ

$UHDQRWGHWHUPLQHG

7HVWHGLQSURGXFWLRQ

&026VWDQGDUGUHTXLUHPHQWV9

,+PLQ

%DVHGRQGHVLJQVLPXODWLRQV

,/PD[

%DVHGRQGHVLJQVLPXODWLRQV

&026VWDQGDUGUHTXLUHPHQWV9

,/PD[

80/126

069

,+PLQ

Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics

&026VWDQGDUGUHTXLUHPHQWV9 ,+PLQ

,+PLQ

%DVHGRQGHVLJQVLPXODWLRQV

7HVWHGLQSURGXFWLRQ

$UHDQRWGHWHUPLQHG

,/PD[

7HVWHGLQSURGXFWLRQ

,/PD[

%DVHGRQGHVLJQVLPXODWLRQV

&026VWDQGDUGUHTXLUHPHQWV9

,/PD[

069

DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed V

OL/

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

• The sum of the currents sourced by all the I/Os on V

DD, consumption of the MCU sourced on V

Σ I

VDD

(see Table 18 ).

DD, plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

SS consumption of the MCU sunk on V

Σ I

VSS

(see

Table 18 ).

plus the maximum Run

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in Table 49

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 20 . All I/Os (FT, TTa and TC unless otherwise specified) are CMOS and TTL

compliant.

Symbol

Table 49. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)

(2)

OLFM+

(1)(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an FTf I/O pin in

FM+ mode

= +4 mA

1.65 V < V

< 1.95 V

= -4 mA

1.65 V < V

< 1.95 V

= +10 mA

= 1.65 V to 1.95 V

–0.4

0.4

1. The I

current sunk by the device must always respect the absolute maximum rating specified in Table 18 and the sum of

(I/O ports and control pins) must not exceed Σ I

IO(PIN)

2. The I of I

current sourced by the device must always respect the absolute maximum rating specified in Table 18 and the sum

(I/O ports and control pins) must not exceed Σ I

IO(PIN)

3. Guaranteed by design.

DocID026294 Rev 6 81/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 20 and

Table 50 , respectively.

Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 20

Table 50. I/O AC characteristics (1)

OSPEEDRy [1:0] value

(1)

Symbol Parameter Conditions Min Max Unit x0

FM+ configuration

(4)

f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out t

EXTIpw

Maximum frequency (2)

Output high to low level fall time

= 50 pF, V

= 1.65 V to 1.95 V -

125

(3)

Output low to high level rise time

Maximum frequency

(2)

Output high to low level fall time

= 50 pF, V

= 1.65 V to 1.95 V

= 50 pF, V

= 1.65 V to 1.95 V -

Output low to high level rise time

Maximum frequency

(2)

Output high to low level fall time

= 50 pF, V

= 1.65 V to 1.95 V

= 50 pF, V

= 1.65 V to 1.95 V -

= 50 pF, V

= 1.65 V to 1.95 V -

125

(3)

62.5

(3)

MHz ns

MHz

Output low to high level rise time

Maximum frequency

(2)

Output high to low level fall time

Output low to high level rise time

Pulse width of external signals detected by the

EXTI controller

= 50 pF, V

= 1.65 V to 1.95 V -

= 50 pF, V

= 1.65 V to 1.95 V

(3)

0.5

(3)(4)

MHz

(4)

(3)(4)

10 -‘ ns ns ns

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0366 reference manual for a description of

GPIO Port configuration register.

2. The maximum frequency is defined in Figure 20 .

3. Guaranteed by design.

4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F318C8 STM32F318K8 reference manual

RM0366 for a description of FM+ I/O mode configuration.

82/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Figure 20. I/O AC characteristics definition

([WHUQDO

RXWSXWRQ&

WU,2RXW WI,2RXW

0D[LPXPIUHTXHQF\LVDFKLHYHGLIWUWI7DQGLIWKHGXW\F\FOHLV

ZKHQORDGHGE\& / VHHQRWH

069

1. See

Table 50: I/O AC characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Table 48 ).

Unless otherwise specified, the parameters given in Table 51

are derived from tests performed under ambient temperature and V

Table 20 .

supply voltage conditions summarized in

Symbol

Table 51. NRST pin characteristics

Parameter Conditions Min Typ Max

IL(NRST)

(1)

NRST Input low level voltage -

0.3V

0.07

IH(NRST)

(1)

NRST Input high level voltage -

0.445V

0.398

V hys(NRST)

F(NRST)

(1)

NF(NRST)

(1)

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST Input filtered pulse

NRST Input not filtered pulse

= V

700

(1)

200

100

(1)

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution resistance must be minimum (~10% order)

to the series

Unit

V mV k Ω ns ns

DocID026294 Rev 6 83/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Figure 21. Recommended NRST pin protection

([WHUQDO

UHVHWFLUFXLW

)

1567

)LOWHU

,QWHUQDOUHVHW

069

1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip.

2. The user must ensure that the level on the NRST pin can go below the V

Table 51 . Otherwise the reset will not be taken into account by the device.

max level specified in

3. The user must place the external capacitor on NRST as close as possible to the chip.

The NPOR pin input driver uses the CMOS technology. It is connected to a permanent pull-

up resistor, Rpu (see Table 52

) connected to V

DDA

supply.

Unless otherwise specified, the parameters given in Table 52

are derived from tests performed under ambient temperature and V

DDA

Table 20 .

supply voltage conditions summarized in

Symbol

(1) Parameter

Table 52. NPOR pin characteristics

Conditions Min Typ Max Unit

IL(NPOR)

NPOR Input low level voltage

IH(NPOR)

NPOR Input low level voltage

V hys(NPOR)

NPOR Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

= V

0.5 V

DDA

+0.2

100

0.475 V

DDA

- 0.2

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order).

mV k

84/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

The parameters given in

Table 53 are guaranteed by design.

Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol Parameter

Table 53. TIMx

(1)(2)

characteristics

Conditions Min Max Unit t res(TIM)

Timer resolution time

TIMxCLK

= 72 MHz f

TIMxCLK

= 144 MHz, x = 1, 15,16, 17

13.9

6.95

TIMxCLK ns ns f

EXT

Res

TIM

Timer external clock frequency on CH1 to CH4

Timer resolution

TIMxCLK

= 72 MHz

TIMx (except TIM2)

TIM2

TIMxCLK

65536

910

MHz

MHz bit t

COUNTER

16-bit counter clock period

TIMxCLK

= 72 MHz 0.0139

TIMxCLK

= 144 MHz, x= 1/15/16/17

0.0069

455 t

TIMxCLK

µs

µs t

MAX_COUNT

Maximum possible count with 32-bit counter

TIMxCLK

= 72 MHz f

TIMxCLK

= 144 MHz, x= 1/15/16/17

65536 × 65536 t

59.65

29.825

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM15, TIM16 and TIM17 timers.

2. Guaranteed by design.

TIMxCLK s s

Table 54. IWDG min/max timeout period at 40 kHz (LSI)

(1)

Prescaler divider PR[2:0] bits

Min timeout (ms) RL[11:0]=

0x000

Max timeout (ms) RL[11:0]=

0xFFF

/16

/32

/64

/128

/256

0.1

0.2

0.4

0.8

1.6

3.2

6.4

409.6

819.2

1638.4

3276.8

6553.6

13107.2

26214.4

1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

DocID026294 Rev 6 85/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Prescaler

Table 55. WWDG min-max timeout value @72 MHz (PCLK) (1)

WDGTB Min timeout value Max timeout value

1. Guaranteed by design.

0.05687 3.6409

0.1137 7.2817

0.2275 14.564

0.4551 29.127

86/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

I

C interface characteristics

The I2C interface meets the timings requirements of the I 2 C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s

• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to Reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement. Refer to

Section 6.3.13: I/O port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

Symbol

Table 56. I2C analog filter characteristics

(1)

Parameter t

Maximum pulse width of spikes that are suppressed by the analog filter

1. Guaranteed by design.

2. Spikes with widths below t

AF(min) are filtered.

3. Spikes with widths above t

AF(max)

are not filtered

Min

(2)

Max

260

(3)

Unit ns

DocID026294 Rev 6 87/126

109

Electrical characteristics STM32F318C8 STM32F318K8

SPI/I

S characteristics

Unless otherwise specified, the parameters given in Table 57

for SPI or in

Table 58 for I

2 S are derived from tests performed under ambient temperature, f

supply voltage conditions summarized in Table 20 .

PCLKx frequency and V

Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I 2 S).

Symbol Parameter

Table 57. SPI characteristics (1)

Conditions Min Typ Max Unit

1/t f

SCK c(SCK)

SPI clock frequency

Master mode

Slave mode

Slave mode transmitter/full duplex

(2)

MHz t t su(NSS) h(NSS)

NSS setup time

NSS hold time

Slave mode, SPI presc = 2

4*Tpcl k

2*Tpcl k

t t w(SCKH) w(SCKL)

SCK high and low time

Master mode, f

PCLK

MHz, presc = 4

= 36

Master mode

Tpclk-

Tpclk

Tpclk+

t su(MI) t su(SI) t h(MI) t h(SI)

Data input setup time

Data input hold time

Slave mode

Master mode

Slave mode

6.5

2.5

ns t a(SO)

Data output access time

Slave mode 8 40 t dis(SO)

Data output disable time

Slave mode 8 14 t v(SO) t v(MO) t h(SO) t h(MO)

Data output valid time

Data output hold time

Slave mode

Master mode

Slave mode

Master mode

9.5

1.5

1. Guaranteed by characterization results.

2. 2.Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the

SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%.

88/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Figure 22. SPI timing diagram - slave mode and CPHA = 0

Figure 23. SPI timing diagram - slave mode and CPHA = 1 (1)

166LQSXW

W 68166

&3+$

&32/

&3+$

&32/

W Z6&.+

W Z6&./

W D62

0,62

287387

026,

,1387

W VX6,

W Y62

06%287

W K6,

06%,1

W F6&.

W K62

%,7287

%,7,1

W K166

W U6&.

W I6&.

W GLV62

/6%287

/6%,1

1. Measurement points are done at 0.5V

and with external C

= 30 pF.

DLE

DocID026294 Rev 6 89/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Figure 24. SPI timing diagram - master mode (1)

166LQSXW

+LJK

WF6&.

&3+$

&32/

&3+$

&32/

&3+$

&32/

&3+$

&32/

0,62

,13 87

026,

287387

WVX0,

WZ6&.+

WZ6&./

06%,1

WK0,

06%287

WY02

%,7,1

% , 7287

WK02

1. Measurement points are done at 0.5V

and with external C

= 30 pF.

Table 58. I2S characteristics

(1) f

Symbol Parameter

MCK

I2S Main clock output f

I2S clock frequency

Master data: 32 bits

Slave data: 32 bits

I2S clock frequency duty cycle

Slave receiver

WU6&.

WI6&.

/6%,1

/6%287

DLF

256 x 8K 256xFs

(2)

64xFs

30 70

MHz

90/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics t h(SD_ST) t h(SD_MT)

Table 58. I2S characteristics (1) (continued) t

Symbol Parameter v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST)

WS valid time

WS hold time

WS setup time

WS hold time

Data input setup time

Data input hold time

Data output valid time t v(SD_MT)

Data output hold time

Master mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

1. Guaranteed by characterization results.

2. 256xFs maximum is 36 MHz (APB1 Maximum frequency)

2.5

1 -

22 ns

Note: Refer to RM0366 Reference Manual I2S Section for more details about the sampling frequency (Fs), fMCK, fCK, DCK values reflect only the digital peripheral behavior, source clock precision might slightly change the values DCK depends mainly on ODD bit value.

Digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max

(I2SDIV+ODD)/(2*I2SDIV+ODD) and Fs max supported for each mode/condition.

DocID026294 Rev 6 91/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Figure 25. I 2 S slave timing diagram (Philips protocol) (1)

1. Measurement points are done at 0.5V

and with external C

=30 pF.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 26. I

S master timing diagram (Philips protocol)

(1)

92/126

1. Measurement points are done at 0.5V

and with external C

=30 pF.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

DocID026294 Rev 6

Symbol

DDA

DDA f

ADC f

(1) f

TRIG

(1)

AIN

(1)

Unless otherwise specified, the parameters given in Table 59

to Table 61

are guaranteed by design, with conditions summarized in

Table 20 .

Table 59. ADC characteristics

Conditions Min Typ Max Unit Parameter

Analog supply voltage for

ADC

1.8

3.6

ADC current consumption

(see Figure 27

)

ADC clock frequency

Sampling rate

External trigger frequency

Conversion voltage range

External input impedance

Single-ended mode,

5 MSPS

Single-ended mode,

1 MSPS

Single-ended mode,

200 KSPS

Differential mode, 5 MSPS

Differential mode, 1 MSPS

Differential mode,

200 KSPS

Resolution = 12 bits,

Fast Channel

Resolution = 10 bits,

Fast Channel

Resolution = 8 bits,

Fast Channel

Resolution = 6 bits,

Fast Channel

ADC

= 72 MHz

Resolution = 12 bits

0.14

0.01

0.012

0.014

0.0175

1011.3

214.7

54.7

1061.5

246.6

56.4

1172.0

322.3

81.1

1243.6

337.6

83.0

5.14

7.2

5.14

DDA

100

µA

MHz

MSPS

MHz

1/f

ADC

V k Ω

Symbol

ADC

(1) t

CAL

(1) t latr

(1) t latrinj

(1)

Parameter

Internal sample and hold capacitor

Calibration time t

(1)

Sampling time

TADCVREG_STUP

(1)

ADC Voltage Regulator

Start-up time t

STAB

(1)

Power-up time t

CONV

(1)

Trigger conversion latency

Regular and injected channels without conversion abort

Trigger conversion latency

Injected channels aborting a regular conversion

Total conversion time

(including sampling time)

CMIR

(1) Common mode input signal

1. Data guaranteed by design.

Table 59. ADC characteristics (continued)

Conditions Min

ADC

= 72 MHz

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11 f

ADC

= 72 MHz

ADC

= 72 MHz

Resolution = 12 bits

ADC differential mode

2.5

1.5

0.021

1.5

Typ

1.56

112

Max

2.5

2.25

2.125

3.5

3.25

3.125

8.35

601.5

0.19

8.52

14 to 614 (t

for sampling + 12.5 for successive approximation)

SSA

+ V

REF+

)/2

- 0.18

SSA

+ V

REF+

)/2

SSA

+ V

REF+

+ 0.18

)/2

Unit pF

µs

1/f

ADC

1/f

ADC

1/f

ADC

1/f

ADC

1/f

ADC

1/f

ADC

1/f

ADC

1/f

ADC

1/f

ADC

µs

1/f

ADC

µs conversion cycle

µs

1/f

ADC

STM32F318C8 STM32F318K8 Electrical characteristics

Figure 27

illustrates the ADC current consumption as per the clock frequency in singleended and differential modes.

Figure 27. ADC typical current consumption in single-ended and differential modes

Resolution

12 bits

&ORFNIUHTXHQF\0636

069

Sampling cycle @

72 MHz

1.5

2.5

4.5

7.5

19.5

61.5

181.5

601.5

Table 60. Maximum ADC R

AIN

(1)

Sampling time [ns] @

72 MHz

20.83

34.72

62.50

104.17

270.83

854.17

2520.83

8354.17

Fast channels

(2)

0.018

0.150

0.470

0.820

2.70

8.20

22.0

82.0

AIN

max (k Ω )

Slow channels

0.220

0.560

1.80

6.80

18.0

68.0

Other channels

(3)

0.022

0.180

0.470

1.50

4.70

15.0

47.0

DocID026294 Rev 6 95/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Resolution

10 bits

8 bits

6 bits

1.5

2.5

4.5

7.5

19.5

61.5

181.5

1.5

2.5

4.5

7.5

19.5

61.5

181.5

601.5

1.5

2.5

4.5

7.5

19.5

61.5

181.5

601.5

1. Guaranteed by characterization results.

2. All fast channels, expect channel on PA6.

3. Channel available on PA6.

Table 60. Maximum ADC R

AIN

(1) (continued)

AIN

max (k Ω )

Sampling cycle @

72 MHz

Sampling time [ns] @

72 MHz

Fast channels

(2)

Slow channels

0.150

0.390

0.820

1.50

3.90

12.00

39.00

0.082

0.270

0.560

1.20

3.30

10.0

33.0

100.0

100.00

0.270

0.560

1.200

2.20

5.60

18.0

56.0

100.00

20.83

34.72

62.50

104.17

270.83

854.17

2520.83

20.83

34.72

62.50

104.17

270.83

854.17

2520.83

8354.17

20.83

34.72

62.50

104.17

270.83

854.17

2520.83

8354.17

0.180

0.560

1.20

3.30

12.00

33.00

0.082

0.390

0.82

2.70

8.2

27.0

82.0

100.00

0.100

0.390

0.820

1.80

4.70

15.0

47.0

100.0

Other channels

(3)

0.039

0.180

0.470

1.00

2.70

8.20

27.00

0.100

0.330

0.68

2.20

6.8

22.0

68.0

82.00

0.150

0.330

0.820

1.50

3.90

12.0

39.0

100.0

96/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Table 61. ADC accuracy - limited test conditions (1)(2)

Symbol Parameter Conditions

Min

(3)

Typ

Max

(3)

Unit

ENOB

(4)

SINAD

(4)

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Effective number of bits

Signal-tonoise and distortion ratio

ADC clock freq. ≤

Sampling freq. ≤

DDA

= 3.3 V

25°C

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Differential

±4

±1.5

±3

±4.5

±5.5

±6

±3.5

±4

±2

±4

Differential

Single ended

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Single ended

±5 ±5.5

LSB

±3

±3 ±3.5

±1 ±1

±1

±1.5

±2

±3

±1

±2

±3

±1.5 ±1.5

Slow channel 4.8 Ms ±1.5

±2

Fast channel 5.1 Ms 10.8 10.8

Slow channel 4.8 Ms 10.8 10.8

Fast channel 5.1 Ms 11.2 11.3

bit

Slow channel 4.8 Ms 11.2 11.3

Fast channel 5.1 Ms 66 67 -

Single ended

±3.5

±4

±2 ±2

±1.5

±2

±1.5

±2

Slow channel 4.8 Ms 66 67

Fast channel 5.1 Ms 69 70 -

Differential

Slow channel 4.8 Ms 69 70 -

DocID026294 Rev 6 97/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Table 61. ADC accuracy - limited test conditions (1)(2) (continued)

Symbol Parameter Conditions

Min

(3)

Typ

Max

(3)

Unit

SNR

THD

(4)

Signal-tonoise ratio

Total harmonic distortion

ADC clock freq.

Sampling freq

DDA

≤

72 MHz

5 Msps

= 3.3 V

25°C

Single ended

Fast channel 5.1 Ms 66 67

Slow channel 4.8 Ms 66 67

Fast channel 5.1 Ms 69 70

Differential

Slow channel 4.8 Ms 69 70

Fast channel 5.1 Ms -80

-80

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms -

-78 -77

-83 -82

Differential

Slow channel 4.8 Ms -81 -80 dB

1. ADC DC accuracy values are measured after internal calibration.

2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

in Section 6.3.13

does not affect the ADC

3. Guaranteed by characterization results.

4. Value measured with a –0.5dB Full Scale 50kHz sine wave input signal.

98/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Symbol Parameter

Table 62. ADC accuracy (1)(2)(3)

Conditions Min

(4)

ENOB

(5)

SINAD

(5)

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Effective number of bits

Signal-tonoise and distortion ratio

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Differential

ADC clock freq. ≤ 72 MHz,

Sampling freq. ≤ 5 Msps

1.8 V ≤ V

DDA

≤ 3.6 V

Single ended

Differential

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Single ended

Differential

10.4

Slow channel 4.8 Ms 10.4

Fast channel 5.1 Ms 10.8

Slow channel 4.8 Ms 10.8

Fast channel 5.1 Ms 64

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms 67

Max

(4)

±2.5

±1.5

±3

±3.5

±2

±4

±1.5

±6.5

±4

±4.5

±3

±2.5

±6

±3.5

Unit

LSB bits dB

DocID026294 Rev 6 99/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Table 62. ADC accuracy (1)(2)(3) (continued)

Symbol Parameter Conditions Min

(4)

Max

(4)

Unit

SNR

THD

(5)

Signal-tonoise ratio

Total harmonic distortion

Single ended

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

ADC clock freq. ≤ 72 MHz,

Sampling freq ≤ 5 Msps,

1.8 V ≤ V

DDA

≤ 3.6 V

Differential

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms

-75

-79

-78

1. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

Section 6.3.13

does not affect the ADC

3. Better performance may be achieved in restricted V

DDA

, frequency and temperature ranges.

4. Guaranteed by characterization results.

5. Value measured with a –0.5dB Full Scale 50kHz sine wave input signal.

Symbol Parameter

Table 63. ADC accuracy (1)(2)

Test conditions Typ Max

(3)

Unit

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Fast channel

Slow channel

ADC Freq ≤ 72 MHz

Sampling Freq ≤ 1MSPS

2.4 V ≤ V

DDA

= V

REF+

≤ 3.6 V

Single-ended mode

Fast channel

Slow channel

Fast channel

Slow channel

Fast channel

Slow channel

Fast channel

Slow channel

±2.5

±3.5

±1

±1.5

±2

±3

±0.7

±1

±1.2

±5

±2.5

±3

±4

±2

±3

LSB

1. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ∑

IINJ(PIN) in Section 6.3.13: I/O port characteristics

does not affect the ADC accuracy.

3. Guaranteed by characterization results.

100/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8

Figure 28. ADC accuracy characteristics

/6%

,'($/

''$

(

Electrical characteristics

([DPSOHRIDQDFWXDOWUDQVIHUFXUYH

7KHLGHDOWUDQVIHUFXUYH

(QGSRLQWFRUUHODWLRQOLQH

(

7RWDO 8QDGMXVWHG (UURU PD[LPXP GHYLDWLRQ

EHWZHHQWKHDFWXDODQGWKHLGHDOWUDQVIHUFXUYHV

(

2IIVHW(UURUGHYLDWLRQEHWZHHQWKHILUVWDFWXDO

WUDQVLWLRQDQGWKHILUVWLGHDORQH

(

*DLQ (UURU GHYLDWLRQ EHWZHHQ WKH ODVW LGHDO

WUDQVLWLRQDQGWKHODVWDFWXDORQH

(

'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ

EHWZHHQDFWXDOVWHSVDQGWKHLGHDORQH

(

,QWHJUDO /LQHDULW\ (UURU PD[LPXP GHYLDWLRQ

EHWZHHQ DQ\ DFWXDO WUDQVLWLRQ DQG WKH HQG SRLQW

FRUUHODWLRQOLQH

/ 6%

,'($/

66$

''$

069

$,1

$,1 $,1[

& SDUDVLWLF

Figure 29. Typical connection diagram using the ADC

9 ''

9 7

6DPSOHDQGKROG$'&

FRQYHUWHU

5 $'&

ELW

FRQYHUWHU

& $'&

069

1. Refer to Table 59 for the values of R

AIN

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 this, f

ADC pF). A high C

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 10

. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

DocID026294 Rev 6 101/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Symbol Parameter

Table 64. DAC characteristics

Conditions

DDA

Analog supply voltage DAC output buffer ON

LOAD

(1)

Resistive load DAC output buffer ON

Connected to V

SSA

Connected to V

DDA

DAC output buffer ON R

(1)

LOAD

(1)

Output impedance

Capacitive load DAC output buffer ON

Voltage on DAC_OUT output

Corresponds to 12-bit input code (0x0E0) to

(0xF1C) at V

DDA

= 3.6 V and (0x155) and (0xEAB) at V

DDA

DAC output buffer ON.

= 2.4 V

DAC output buffer OFF

DDA

(3)

DNL

INL

(3)

DAC DC current consumption in quiescent mode

(2)

With no load, middle code (0x800) on the input.

With no load, worst code (0xF1C) on the input.

Differential non linearity Difference between two consecutive code-

1LSB)

Given for a 10-bit input code

Given for a 12-bit input code

Integral non linearity

(difference between measured value at

Code i and the value at Code i on a line drawn between Code

0 and last Code 4095)

Given for a 10-bit input code

Given for a 12-bit input code

Offset

(3)

Offset error (difference between measured value at Code (0x800)

Given for a 10-bit input code at V

DDA

= 3.6 V and the ideal value =

DDA

/2)

Given for a 12-bit input code at V

DDA

= 3.6 V

Gain error

(3)

Gain error Given for a 12-bit input code

SETTLING

(3)

Settling time (full scale: for a 12-bit input code transition between the lowest and the highest input codes when

DAC_OUT reaches

LOAD

≤

50 pF,

≥

5 k Ω

Min Typ

2.4

Max

3.6

Unit

V k Ω k Ω pF

0.2 V

DDA

– 0.2

0.5

DDA

1LSB

380

480

±0.5

±2

±1

±4

±10

±3

±12

±0.5

4 mV

µA

LSB

LSB mV

LSB

µs

102/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Symbol Parameter

Table 64. DAC characteristics (continued)

Conditions Min Typ Max

Update

rate

(3)

Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB)

LOAD

≤

50 pF,

≥

5 k Ω t

WAKEUP

(3)

Wakeup time from off state (Setting the ENx bit in the DAC Control register)

LOAD

≤

50 pF,

≥

5 k Ω

PSRR+

(1)

Power supply rejection ratio (to V

DDA

) (static

DC measurement

LOAD

50 pF,

No R

LOAD

≥

5 k Ω,

6.5

–67 –40

1. Guaranteed by design.

2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is involved.

3. Guaranteed by characterization results.

Unit

MS/s

µs dB

Figure 30. 12-bit buffered /non-buffered DAC

%XIIHUHG1RQEXIIHUHG'$&

%XIIHU

ELWGLJLWDO

WRDQDORJ

FRQYHUWHU

'$&B287[

& /

069

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

Symbol

DDA

Parameter

Table 65. Comparator characteristics (1)(2)

Conditions Min.

Analog supply voltage

REFINT scaler not in use

REFINT

scaler in use

1.8

Comparator input voltage range

Scaler input voltage

Scaler offset voltage -

Typ.

REFINIT

±5

Max.

3.6

DDA

±10

Unit

V mV

DocID026294 Rev 6 103/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Symbol

Table 65. Comparator characteristics (1)(2) (continued)

Parameter Conditions Min.

Typ.

t t

S_SC

START

REFINT

scaler startup time from power down

REFINT

scaler activation after device power on

Next activations

Comparator startup time

DDA

≥ 2.7 V

DDA

< 2.7 V

Propagation delay for

200 mV step with 100 mV overdrive

DDA

≥ 2.7 V

DDA

< 2.7 V

28 t

Propagation delay for full range step with 100 mV overdrive

DDA

≥ 2.7 V 32

OFFSET

Comparator offset error

DDA

< 2.7 V

DDA

≥ 2.7 V

DDA

< 2.7 V

Full temperature range

± 5

OFFSET

DD(COMP)

Total offset variation

COMP current consumption

400

1. Guaranteed by design.

2. The comparators do not have built-in hysteresis.

3. For more details and conditions, see Figure 31: Maximum V

REFINT

scaler startup time from power down .

± 10

± 25

600

Max.

(3)

0.2

Unit s ms

µs ns mV mV

µA

104/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Figure 31. Maximum V

REFINT

scaler startup time from power down

DocID026294 Rev 6 105/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Symbol

Table 66. Operational amplifier characteristics (1)

Parameter Condition Min

DDA

CMIR

Δ VI

OFFSET

LOAD

CMRR

PSRR

GBW

LOAD

Analog supply voltage

Common mode input range

Input offset voltage

Maximum calibration range

Input offset voltage drift

Drive current

25°C, No Load on output. t

IDDOPAMP t t

OFFSET

VOH

VOL ϕ

SAT

SAT m

OFFTRIM

WAKEUP

S_OPAM_VOUT

Consumption

After offset calibration

All voltage/Temp.

25°C, No Load on output.

All voltage/Temp.

No load, quiescent mode

Common mode rejection ratio

Power supply rejection ratio

Bandwidth

Slew rate -

Resistive load

Capacitive load

High saturation voltage

Low saturation voltage

(2)

R load

= min, Input at V

DDA

R load

= 20K,

Input at V

DDA

Rload = min, input at 0V

Rload = 20K, input at 0V.

Phase margin

Offset trim time: during calibration, minimum time needed between two steps to have 1 mV accuracy

Wake up time from OFF state.

LOAD

≤

≥

50 pf,

4 k

Follower

Ω, configuration

ADC sampling time when reading the OPAMP output

2.4

DDA

-100

DDA

-20

400

Typ

690

2.8

117

8.2

4.7

1.6

500

1450

Max

3.6

DDA

Unit

V mV

µV/°C

µA

µA dB dB

MHz

V/µs k Ω pF

100

µs ns

106/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

Symbol

PGA gain

Table 66. Operational amplifier characteristics (1) (continued)

Parameter Condition Min Typ

Non inverting gain value -

R network

PGA BW

R2/R1 internal resistance values in PGA mode

(3)

PGA gain error PGA gain error

I bias

OPAMP input bias current

PGA bandwidth for different non inverting gain

Gain=2

Gain=4

Gain=8

Gain=16

PGA Gain = 2,

Cload = 50pF,

Rload = 4 K Ω

PGA Gain = 4,

Cload = 50pF,

Rload = 4 K Ω

PGA Gain = 8,

Cload = 50pF,

Rload = 4 K Ω

PGA Gain = 16,

Cload = 50pF,

Rload = 4 K Ω

@ 1KHz, Output loaded with 4 K Ω

-1%

5.4/5.4

16.2/5.4

37.8/5.4

40.5/2.7

0.5

109

Max

± 0.2

(4)

Unit

k Ω

µA

MHz

V n

Voltage noise density

@ 10KHz, Output loaded with 4 K Ω

43 -

1. Guaranteed by design.

2. The saturation voltage can also be limited by the I

LOAD

(drive current).

3. R2 is the internal resistance between OPAMP output and OPAMP inverting input.

R1 is the internal resistance between OPAMP inverting input and ground.

The PGA gain =1+R2/R1

4. Mostly TTa I/O leakage, when used in analog mode.

DocID026294 Rev 6 107/126

109

Electrical characteristics STM32F318C8 STM32F318K8

Figure 32. OPAMP Voltage Noise versus Frequency

108/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Electrical characteristics

6.3.22 Temperature sensor characteristics

Symbol

(1)

Avg_Slope

(1)

25 t

START

(1)

S_temp

(1)(2)

Table 67. TS characteristics

Parameter

SENSE

linearity with temperature

Average slope

Voltage at 25 °C

Startup time

ADC sampling time when reading the temperature

Min

2.2

4.0

1.34

Typ

1. Guaranteed by design.

2. Shortest sampling time can be determined in the application by multiple iterations.

± 1

4.3

1.43

Max

± 2

4.6

1.52

Table 68. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at temperature of 30 °C,

DDA

= 3.3 V

TS ADC raw data acquired at temperature of 110 °C

DDA

= 3.3 V

0x1FFF F7B8 - 0x1FFF F7B9

0x1FFF F7C2 - 0x1FFF F7C3

Unit

°C mV/°C

µs

6.3.23 V

BAT monitoring characteristics

Symbol

Table 69. V

BAT

monitoring characteristics

Parameter Min Typ

(1)

S_vbat

(1)(2)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q

ADC sampling time when reading the V

BAT

1mV accuracy

-1

2.2

1. Guaranteed by design.

2. Shortest sampling time can be determined in the application by multiple iterations.

Max

Unit

K Ω

µs

DocID026294 Rev 6 109/126

109

STM32F318C8 STM32F318K8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

DocID026294 Rev 6 109/126

122

Package information STM32F318C8 STM32F318K8

Figure 33. WLCSP49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package outline

)

$EDOOORFDWLRQ

EEE =

H (

'HWDLO$

%RWWRPYLHZ

%XPSVLGH

)URQWYLHZ

6LGHYLHZ

$ 2ULHQWDWLRQ

UHIHUHQFH

7RSYLHZ

:DIHUEDFNVLGH

1. Drawing is not to scale.

%XPS

HHH =

(

[

1RWH

'HWDLO$

URWDWHG

6HDWLQJSODQH

1RWH

[

$;-B0(B9

110/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Package information

Table 70. WLCSP49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches

(1)

Symbol millimeters

Min Typ Max Min Typ Max

G aaa e e1 e2

A3 (2) b

(3)

E bbb ccc ddd eee

0.525

0.220

3.382

3.116

0.555

0.175

0.380

0.025

0.250

3.417

3.151

0.400

2.400

0.5085

0.3755

0.585

0.280

3.452

3.186

0.100

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Back side coating

3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

0.0207

0.0087

0.1331

0.1227

0.0200

0.0148

0.0219

0.0069

0.0150

0.0010

0.0098

0.1345

0.1241

0.0157

0.0945

0.0039

0.0020

0.0230

0.0110

0.1359

0.1254

Figure 34. WLCSP49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package recommended footprint

'SDG

'VP

DocID026294 Rev 6

069

111/126

122

Package information STM32F318C8 STM32F318K8

Table 71. WLCSP49 recommended PCB design rules (0.4 mm pitch)

Dimension Recommended values

Pitch

Dpad

Dsm

PCB pad design

0.4

260 µm max. (circular)

220 µm recommended

300 µm min. (for 260 µm diameter pad)

Non-solder mask defined via underbump allowed.

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 35. WLCSP49 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

'DWHFRGH

: 88 3

5HYLVLRQFRGH

069

1. Parts marked as ES or E are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

112/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8

7.2 LQFP48 package information

Package information

Figure 36. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

3%!4).'

0,!.%

CCC #

'!5'%0,!.%

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

"?-%?6

DocID026294 Rev 6 113/126

122

Package information STM32F318C8 STM32F318K8

Symbol

Table 72. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max e

E3 k ccc b c

0.050

1.350

0.170

0.090

8.800

6.800

8.800

6.800

0.450

0°

1.400

0.220

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

1.600

0.150

1.450

0.270

0.200

9.200

7.200

9.200

7.200

0.750

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.3465

0.2677

0.0177

0°

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

0.0551

0.0087

0.3543

0.2756

0.3622

0.2835

0.0295

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

114/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Package information

Figure 37. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint

1. Dimensions are expressed in millimeters.

AID

DocID026294 Rev 6 115/126

122

Package information STM32F318C8 STM32F318K8

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 38. LQFP48 marking example (package top view)

3URGXFW

LGHQWLILFDWLRQ 45.'

'DWHFRGH

: 88

3LQ

LGHQWLILFDWLRQ

5HYLVLRQFRGH

069

116/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8

7.3 UFQFPN32 package information

Package information

Figure 39. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline

GGG &

6($7,1*

3/$1(

(

( (

' /

3,1,GHQWLILHU

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

!"?-%?6

DocID026294 Rev 6 117/126

122

Package information STM32F318C8 STM32F318K8

Table 73. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

E2 e

L ddd b

0.500

0.000

0.180

4.900

3.400

4.900

3.400

0.300

0.550

0.020

0.152

0.230

5.000

3.500

5.000

3.500

0.500

0.400

0.600

0.050

0.280

5.100

3.600

5.100

3.600

0.500

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0000

0.0071

0.1929

0.1339

0.1929

0.1339

0.0118

0.0217

0.0008

0.0060

0.0091

0.1969

0.1378

0.1969

0.1378

0.0197

0.0157

0.2008

0.1417

0.0197

0.0031

0.0236

0.0020

0.0110

0.2008

0.1417

Figure 40. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package recommended footprint

118/126

1. Dimensions are expressed in millimeters.

DocID026294 Rev 6

$%B)3B9

STM32F318C8 STM32F318K8 Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 41. UFQFPN32 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

'DWHFRGH

5HYLVLRQFRGH

3LQLGHQWLILHU

069

DocID026294 Rev 6 119/126

122

Package information STM32F318C8 STM32F318K8

The maximum chip junction temperature (T

Table 20: General operating conditions .

max) must never exceed the values given in

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

max = T

max + (P

max x Θ

)

Where:

• T

max is the maximum ambient temperature in °C,

• Θ

is the package junction-to-ambient thermal resistance, in ° C/W,

• P

max is the sum of P

INT

max and P

I/O max (P

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Symbol

Table 74. Package thermal characteristics

Parameter Value

Thermal resistance junction-ambient

WCSP49 - 3.4 x 3.4 mm

Thermal resistance junction-ambient

LQFP48 - 7 × 7 mm

Thermal resistance junction-ambient

UFQPFN32 - 5 x 5 mm

Unit

°C/W

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

120/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8

7.4.2 Selecting the product temperature range

Package information

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Section 8: Ordering information .

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F318C8 STM32F318K8 at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature T

Amax

DDmax

= 50 mA, V

= 82 °C (measured according to JESD51-2),

= 3.5 V, maximum 3 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V and maximum 2 I/Os used at the same time in output at low level with I

= 20 mA, V

= 1.3 V

INTmax

= 50 mA × 3.5 V= 175 mW

IOmax

= 3 × 8 mA × 0.4 V + 2 × 20 mA × 1.3 V = 61.6 mW

This gives: P

INTmax

= 175 mW and P

IOmax

= 61.6 mW:

Dmax

= 175 + 61.6 = 236.6 mW

Thus: P

Dmax

= 236.6 mW

Using the values obtained in Table 74

Jmax

is calculated as follows:

– For WLCSP49, 49°C/W

Jmax

= 82 °C + (49°C/W x 236.6 mW) = 82°C + 11.6°C = 93.6°C

This is within the range of the suffix 6 version parts (–40 < T

< 105 °C).

In this case, parts must be ordered at least with the temperature range suffix 6 (see

Section 8: Ordering information

DocID026294 Rev 6 121/126

122

Package information STM32F318C8 STM32F318K8

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature T

J specified range.

remains within the

Assuming the following application conditions:

Maximum ambient temperature T

Amax

DDmax

= 20 mA, V

= 115 °C (measured according to JESD51-2),

= 3.5 V, maximum 9 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V

INTmax

= 20 mA × 3.5 V= 70 mW

IOmax

= 9 × 8 mA × 0.4 V = 28.8 mW

This gives: P

INTmax

= 70 mW and P

IOmax

= 28.8 mW:

Dmax

= 70 + 28.8 = 98.8 mW

Thus: P

Dmax

= 98.8 mW

Using the values obtained in Table 74

Jmax

is calculated as follows:

– For WLCSP49, 49°C/W

Jmax

= 115 °C + (49°C/W x 98.8 mW) = 115°C + 4.8°C = 119.8°C

This is within the range of the suffix 7 version parts (–40 < T

< 125 °C).

In this case, parts must be ordered at least with the temperature range suffix 7 (see

Section 8: Ordering information

122/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Ordering information

Example:

Table 75. Ordering information scheme

STM32

Device family

STM32 = ARM

-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

318 = STM32F318xx, 1.65 to 1.94 V operating voltage

Pin count

K = 32 pins

C = 48 or 49 pins

Flash memory size

8 = 64 Kbytes of Flash memory

Package

T = LQFP

Y= WLCSP

U= UFQFPN

Temperature range

6 = Industrial temperature range, –40 to 85 °C

7 = Industrial temperature range, –40 to 105 °C

Options xxx = programmed parts

TR = tape and reel

F 318 K 8 T 6 xxx

DocID026294 Rev 6 123/126

123

Revision history STM32F318C8 STM32F318K8

Date

27-May-2014

10-Jun-2014

02-Dec-2014

09-Feb-2015

Revision

Table 76. Document revision history

Changes

Initial release.

Added the number of comparators in the document title.

Updated the position of VSSA/VREF- pin in WLCSP49 package in

Table 12: STM32F318x8 pin definitions .

Added the maximum value for wake up time from stop mode in

Table 33: Low-power mode wakeup timings

Applied the following changes:

– updated the comparator analog supply range in Features ,

– added “Interconnect matrix” in Features

– added some information related to timers in Table 1: STM32F318x8 device features and peripheral counts

– updated

Section 3.5.1: Power supply schemes and added Table 2:

External analog supply values for analog peripherals

– added the last footnote to

Table 12: STM32F318x8 pin definitions

– updated

Table 38: HSI oscillator characteristics and Figure 17: HSI oscillator accuracy characterization results for soldered parts ,

– updated V

DDA

min value in Table 65: Comparator characteristics ,

– updated

Table 27: Typical and maximum V

DDA mode ,

consumption in Stop

– updated

Table 33: Low-power mode wakeup timings

– updated UFQFPN32 and WLCSP49 marking in

Chapter 7: Package information .

Updated:

– the order of columns in Table 25: Typical and maximum current consumption from the V

DDA

supply

–

Table 36: HSE oscillator characteristics ,

–

Table 41: Flash memory characteristics

–

Table 52: NPOR pin characteristics ,

–

Table 65: Comparator characteristics .

Added:

–

Figure 31: Maximum V

REFINT

scaler startup time from power down .

124/126 DocID026294 Rev 6

STM32F318C8 STM32F318K8 Revision history

Date

22-Jun-2015

08-Jun-2017

Table 76. Document revision history (continued)

Revision Changes

Added LQFP48 package, updated the following:

–

Section 2: Description

–

Table 1: STM32F318x8 device features and peripheral counts

–

Table 12: STM32F318x8 pin definitions ,

–

Table 20: General operating conditions

–

Table 45: ESD absolute maximum ratings ,

–

Table 74: Package thermal characteristics ,

–

Table 75: Ordering information scheme .

Added:

–

Figure 5: STM32F318x8 LQFP48 pinout ,

–

Section 7.2: LQFP48 package information

– Updated all document table notes by removing the “not tested in production” specification.

– Updated V

REFINT

line on Table 22: Embedded internal reference voltage .

– Updated “Conditions” column on Table 37: LSE oscillator characteristics (f

LSE

= 32.768 kHz) .

– Added CMIR and t

STAB lines on

Table 59: ADC characteristics .

– Updated R

LOAD line on

Table 64: DAC characteristics .

– Updated VOH

SAT

and VOL

SAT

lines on Table 66: Operational amplifier characteristics

– Added

Section 7.3: UFQFPN32 package information

note 2.

– Updated

Section 7: Package information adding information about

other optional marking or inset/upset marks.

– Updated note 1 below all the package device marking figures.

– Updated Table 47: I/O current injection susceptibility note by ‘injection

is not possible’.

– Updated

Figure 21: Recommended NRST pin protection note about

the 0.1uF capacitor.

DocID026294 Rev 6 125/126

125

STM32F318C8 STM32F318K8

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

126/126 DocID026294 Rev 6