This datasheet should be read in conjunction with the STM32F301x6/8 and STM32F318x8 advanced Arm ® -based 32-bit MCUs reference manual (RM0366). The reference manual is available from the STMicroelectronics website www.st.com

For information on the Arm ®(a) Cortex ® -M4 core, refer to the Cortex

Reference Manual, available from Arm website www.arm.com.

® -M4 Technical a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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Description

2 Description

STM32F301x6 STM32F301x8

The STM32F301x6/8 family is based on the high-performance Arm

Cortex

-M4

32-bit RISC core operating at a frequency of up to 72 MHz and embedding a floating point unit (FPU). The family incorporates high-speed embedded memories (up to 64 Kbytes of

Flash memory, 16 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses.

The devices offer a fast 12-bit ADC (5 Msps), three comparators, an operational amplifier, up to 18 capacitive sensing channels, one DAC channel, a low-power RTC, one generalpurpose 32-bit timer, one timer dedicated to motor control, and up to three general-purpose

16-bit timers, and one timer to drive the DAC. They also feature standard and advanced communication interfaces: three I 2 Cs, up to three USARTs, up to two SPIs with multiplexed full-duplex I2S, and an infrared transmitter.

The STM32F301x6/8 family operates in the –40 to +85°C and –40 to +105°C temperature ranges from at a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F301x6/8 family offers devices in 32-, 48-, 49- and 64-pin packages.

The set of included peripherals changes with the device chosen.

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Table 2. STM32F301x6/8 device features and peripheral counts

Peripheral STM32F301Kx STM32F301Cx STM32F301Rx

Flash (Kbytes)

SRAM (Kbytes)

Advanced control

General purpose

32 64 32

1 (16-bit)

3 (16-bit)

1 (32 bit)

64 32

Timers

Comm. interfaces

Basic

SysTick timer

Watchdog timers

(independent, window)

PWM channels (all)

(1)

PWM channels

(except complementary)

SPI/I2S

USART

Normal I/Os (TC, TTa)

GPIOs

5-Volt tolerant I/Os (FT, FT1)

DMA channels

Capacitive sensing channels

12-bit ADC

Number of channels

12-bit DAC channels

Analog comparator

9 (UFQFPN32)

10 (LQFP32)

Operational amplifier

CPU frequency

Operating voltage

72 MHz

2.0 to 3.6 V

Operating temperature

Packages

Ambient operating temperature:

- 40 to 85°C / - 40 to 105°C

Junction temperature: - 40 to 125°C

UFQFPN32

LQFP32

LQFP48,

WLCSP49

LQFP64

1. This total number considers also the PWMs generated on the complementary output channels.

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Description STM32F301x6 STM32F301x8

JTRST

JTDI

JTCK/SWCLK

JTMS/SWDIO

JTDO

As AF

PA[15:0]

PB[15:0]

PC[15:0]

PD[2]

PF[1:0]

6 Groups of

4 channels as AF

REF+

REF-

XX AF

2 Channels,1 Comp

Channel, BRK as AF

1 Channel, 1 Comp

Channel, BRK as AF

1 Channel, 1 Comp

Channel, BRK as AF

4 Channels,

4 Comp channels,

ETR, BRK as AF

RX, TX, CTS, RTS,

SmartCard as AF

TPIU

SWJTAG

FPU

Cortex M4 CPU

F max

: 72 MHz

Ibus

Dbus

System

NVIC

GP DMA1

7 channels

Temp. sensor

12-bit ADC1 IF

Figure 1. STM32F301x6/8 block diagram

SRAM

16 KB

FLASH 64 KB

64 bits

DDA

RC HS 8MHz

RC LS

PLL

POR

Reset

Int.

DD18

Power

Voltage reg.

3.3 V to 1.8V

DDIO

Supply

Supervision

POR /PDR

PVD

DDA

DDIO

XTAL OSC

4 -32 MHz

Ind. WDG32K

Standby interface

Reset & clock control

AHBPCLK

APBP1CLK

APBP2CLK

HCLK

FCLK

USARTCLK

I2CCLK

ADC SAR

1 CLK

@VSW

XTAL 32kHz

RTC

AWU

Backup

Reg

(20Byte)

Backup interface

CRC

TIMER2

(32-bit/PWM)

GPIO PORT A

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT F

Touch Sensing

Controller

AHB2

APB2

AHB2

APB1

SPI2/I2S2

SPI3/I2S3

USART2

USART3

I2C1

I2C2

I2C3

EXT.IT

WKUP

TIMER 15

TIMER 16

TIMER 17

TIMER 1 / PWM

USART1

WinWATCHDOG

TIMER6

SYSCFG CTL

DDA

GP Comparator 6

GP Comparator 4

GP Comparator 2

IF 12bit DAC1

DDA

OpAmp2

DDA

DDIO

= 2 to 3.6 V

NRESET

DDA

SSA

OSC_IN

OSC_OUT

BAT

= 1.65V to 3.6V

OSC32_IN

OSC32_OUT

ANTI-TAMP

4 Channels, ETR as AF

MOSI, MISO,

SCK, NSS as AF

MOSI, MISO,

SCK, NSS as AF

RX, TX, CTS, RTS, as AF

SCL, SDA, SMBA as AF

DAC1_CH1 as AF

INxx / OUTxx

Xx Ins, 4 OUTs as AF

MSv31671V1

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3.1 Arm

®

Cortex

®

-M4 core with FPU, embedded Flash and SRAM

The Arm

Cortex

-M4 processor with FPU is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm

Cortex

-M4 32-bit RISC processor with FPU features exceptional codeefficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single-precision FPU speeds up software development by using metalanguage development tools while avoiding saturation.

With its embedded Arm core, the STM32F301x6/8 family is compatible with all Arm tools and software.

Figure 1 shows the general block diagram of the STM32F301x6/8 family devices.

3.2 Memories

All STM32F301x6/8 devices feature up to 64 Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above).

STM32F301x6/8 devices feature 16 Kbytes of embedded SRAM.

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10) and USART2 (PA2/PA3).

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Functional overview STM32F301x6 STM32F301x8

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.5.1

3.5.2

Power supply schemes

• V

, V

DD =

2.0 to 3.6 V : external power supply for I/Os and the internal regulator. It is provided externally through V

DD pins.

• V

SSA

, V

DDA

= 2.0 to 3.6 V: external analog power supply for ADC, DAC, comparators, operational amplifier, reset blocks, RCs and PLL. The minimum voltage to be applied to

DDA

differs from one analog peripheral to another. Table 3

provides the summary of the V

DDA ranges for analog peripherals. The V

DDA than or equal to the V

voltage level must always be greater

voltage level and must be provided first.

Analog peripheral

ADC/COMP

Table 3. External analog supply values for analog peripherals

Minimum V

DDA

supply

2.0 V

Maximum V

DDA

supply

3.6 V

DAC/OPAMP 2.4 V 3.6 V

• V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

DD is not present.

Power supply supervisor

The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits.

They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold,

V POR/PDR , without the need for an external reset circuit.

• The POR monitors only the V

DD that V

DDA

supply voltage. During the startup phase it is required

should arrive first and be greater than or equal to V

• The PDR monitors both the V

and V

DDA

supply voltages, however the V

DDA

power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that V

DDA equal to V

is higher than or

The device features an embedded programmable voltage detector (PVD) that monitors the

DD power supply and compares it to the V PVD threshold. An interrupt can be generated when V

DD drops below the V

PVD threshold and/or when V

DD is higher than the V

PVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

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The regulator has three operation modes: main (MR), low-power (LPR), and power-down.

• The MR mode is used in the nominal regulation mode (Run)

• The LPR mode is used in Stop mode.

• The power-down mode is used in Standby mode: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The voltage regulator is always enabled after reset. It is disabled in Standby mode.

Note:

The STM32F301x6/8 supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm, COMPx,

I2C or USARTx.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

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Functional overview

Note:

STM32F301x6 STM32F301x8

Table 4. STM32F301x6/8 peripheral interconnect matrix

Interconnect source

Interconnect destination

Interconnect action

Timers synchronization or chaining

TIMx

ADC1

DAC1

DMA

Compx

TIMx

TIM1

Conversion triggers

Memory to memory transfer trigger

Comparator output blanking

Timer input: OCREF_CLR input, input capture

Timer triggered by analog watchdog

COMPx

ADC1

GPIO

RTCCLK

HSE/32

MC0

CSS

CPU (hard fault)

COMPx

PVD

GPIO

TIM16

TIM1

TIM15, 16, 17

Clock source used as input channel for HSI and

LSI calibration

Timer break

GPIO

DAC1

TIMx

ADC1

DAC1

COMPx

External trigger, timer break

Conversion external trigger

Comparator inverting input

For more details about the interconnect actions, refer to the corresponding sections in the

STM32F301x6/8 and STM32F318x8 reference manual RM0366.

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3.7 Clocks and startup

Functional overview

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed

APB domain is 36 MHz.

The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. To achieve audio class performance, an audio crystal can be used.

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Functional overview STM32F301x6 STM32F301x8

Figure 2. Clock tree

HSI

SYSCLK

FLITFCLK to Flash programming interface to I2Cx (x = 1,2,3)

SYSCLK

Ext. clock

I2SSRC to I2Sx (x = 2,3)

I2S_CKIN

OSC_OUT

OSC_IN

OSC32_IN

OSC32_OUT

MCO

8 MHz

HSI RC

HSI

PLLSRC

PLLMUL

PLL x2,x3,..

HSI

PLLCLK

SW x16

HSE prescaler

/1,2,..512

SYSCLK

/2,/3,...

/16

CSS

HCLK

APB1 prescaler

/1,2,4,8,16

4-32 MHz

HSE OSC

PCLK1 to AHB bus, core, memory and DMA to cortex System timer

FHCLK Cortex free running clock to APB1 peripherals

APB2 prescaler

/1,2,4,8,16

If (APB1 prescaler

=1) x1 else x2

PCLK1

SYSCLK

HSI

LSE to TIM 2, 6, 7 to USART1

PCLK2 to APB2 peripherals

/32

LSE OSC

32.768kHz

RTCCLK

LSE

RTCSEL[1:0] to RTC

LSI RC

40kHz

LSI IWDGCLK to IWDG

MCOPRE

/1,2,4,

.. 128

Main clock output

PLLNODIV

MCO

/1,2 PLLCLK

HSI

LSI

HSE

SYSCLK

LSE

If (APB2 prescaler

=1) x1 else x2

ADC

Prescaler

/1,2,4

ADC

Prescaler

/1,2,4,6,8,10,12,16,

32,64,128,256 x2

TIM1,15,16,17 to ADC1

MS32660V4

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Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

Fast I/O handling allows I/O toggling up to 36 MHz.

The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-tomemory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each of the 7 DMA channels is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I 2 C, USART, timers, DAC and ADC.

3.10.1 Nested vectored interrupt controller (NVIC)

The STM32F301x6/8 devices embed a nested vectored interrupt controller (NVIC) able to handle up to 60 maskable interrupt channels and 16 priority levels.

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

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Functional overview STM32F301x6 STM32F301x8

An analog-to-digital converter, with selectable resolution between 12 and 6 bit, is embedded in the STM32F301x6/8 family devices. The ADC has up to 15 external channels performing conversions in single-shot or scan modes. Channels can be configured to be either singleended input or differential input. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

• Simultaneous sample and hold

• Single-shunt phase current reading techniques.

The ADC can be served by the DMA controller.

Three analog watchdogs are available. The analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) and the advanced-control timer

(TIM1) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.

The temperature sensor (TS) generates a voltage V

SENSE temperature.

that varies linearly with

The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

3.11.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

ADC and Comparators. V

REFINT

The precise voltage of V

REFINT

) provides a stable (bandgap) voltage output for the

is internally connected to the ADC1_IN18 input channel.

is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

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3.11.3 V

BAT

battery voltage monitoring

This embedded hardware feature allows the application to measure the V

BAT

battery voltage using the internal ADC channel ADC1_IN17. As the V and thus outside the ADC input range, the V

BAT

voltage may be higher than V

pin is internally connected to a bridge divider by 2. As a consequence, the converted digital value is half the V

BAT

voltage.

DDA

One 12-bit buffered DAC channel (DAC1_OUT1) can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This digital interface supports the following features:

• One DAC output channel

• 8-bit or 12-bit monotonic output

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• DMA capability

• External triggers for conversion

The STM32F301x6/8 devices embed one operational amplifier with external or internal follower routing and PGA capability (or even amplifier and filter capability with external components). When the operational amplifier is selected, an external ADC channel is used to enable output measurement.

The operational amplifier features:

• 8.2 MHz bandwidth

• 0.5 mA output capability

• Rail-to-rail input/output

• In PGA mode, the gain can be programmed to be 2, 4, 8 or 16.

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Functional overview STM32F301x6 STM32F301x8

3.14 Ultra-fast comparators (COMP)

The STM32F301x6/8 devices embed up to three ultra-fast rail-to-rail comparators which offer the features below:

• Programmable internal or external reference voltage

• Selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• DAC output

•

Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 27: Embedded internal reference voltage

for the value and precision of the internal reference voltage.

All comparators can wake up from STOP mode, and also generate interrupts and breaks for the timers.

3.15 Timers and watchdogs

The STM32F301x6/8 devices include advanced control timer, up to general-purpose timers, basic timer, two watchdog timers and a SysTick timer.

Table 5

compares the features of the advanced control, general purpose and basic timers.

Timer type Timer

Table 5. Timer feature comparison

Counter resolution

Counter type

Prescaler factor

DMA request generation

Capture/ compare

Channels

Complementary outputs

Advanced control

Generalpurpose

Basic

TIM1

TIM2

TIM15

TIM16

TIM17

(1)

TIM6

(1)

16-bit

32-bit

16-bit

Up, Down,

Up/Down

Up, Down,

Up/Down

Any integer between 1 and 65536

Yes

1. TIM1/15/16/17 can be clocked from the PLL running at 144 MHz when the system clock source is the PLL and AHB or

APB2 subsystem clocks are not divided by more than 2 cumulatively.

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3.15.1 Advanced timer (TIM1)

The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

• One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIM timers (described in

Section 3.15.2

using the same architecture, so the advanced-control timers can work

together with the TIM timers via the Timer Link feature for synchronization or event chaining.

There are up to four synchronizable general-purpose timers embedded in the

STM32F301x6/8 devices (see Table 5 for differences). Each general-purpose timer can be

used to generate PWM outputs, or act as a simple time base.

TIM2

TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler

It features 4 independent channels for input capture/output compare, PWM or one-pulse mode output. It can work together, or with the other general-purpose timers via the Timer

Link feature for synchronization or event chaining.

The counter can be frozen in debug mode.

It has independent DMA request generation and supports quadrature encoders.

TIM15, TIM16 and TIM 17

These three timers general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

• TIM15 has 2 channels and 1 complementary channel

• TIM16 and TIM17 have 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output.

The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

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Functional overview STM32F301x6 STM32F301x8

3.15.3 Basic timer (TIM6)

This timer is mainly used for DAC trigger generation. It can also be used as a generic 16-bit time base.

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option byte. The counter can be frozen in debug mode.

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

The RTC and the 20 backup registers are supplied through a switch that takes power from either the V

supply when present or the VBAT pin. The backup registers are five 32-bit registers used to store 20 byte of user application data when V

power is not present.

They are not reset by a system or power reset, or when the device wakes up from Standby mode.

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The RTC is an independent BCD timer/counter. It supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

• Two programmable alarms with wake up from Stop and Standby mode capability.

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.

• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy.

• Two anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection.

• Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection.

• 17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY capability.

The RTC clock sources can be:

• A 32.768 kHz external crystal

• A resonator or oscillator

• The internal low-power RC oscillator (typical frequency of 40 kHz)

• The high-speed external clock divided by 32.

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Functional overview STM32F301x6 STM32F301x8

circuit interfaces (I

2

C)

The devices feature three I

C bus interfaces which can operate in multimaster and slave mode. Each I2C interface can support standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz) modes.

All I

C interfaces support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses

(2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters.

Pulse width of suppressed spikes

Benefits

Drawbacks

Table 6. Comparison of I2C analog and digital filters

Analog filter Digital filter

≥ 50 ns

Available in Stop mode

Variations depending on temperature, voltage, process

Programmable length from 1 to 15

I2C peripheral clocks

1. Extra filtering capability vs. standard requirements.

2. Stable length

Wakeup from Stop on address match is not available when digital filter is enabled.

In addition, it provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,

Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and

ALERT protocol management. It also has a clock domain independent from the CPU clock, allowing the I2Cx (x=1,3) to wake up the MCU from Stop mode on address match.

The I2C interfaces can be served by the DMA controller.

Refer to Table 7

for the features available in I2C1, I2C2 and I2C3.

Table 7. STM32F301x6/8 I

C implementation

I2C features

(1)

I2C1

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)

Independent clock

SMBus

Wakeup from STOP

1. X = supported.

I2C2

I2C3

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STM32F301x6 STM32F301x8 Functional overview

(USART)

The STM32F301x6/8 devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3).

The USART interfaces are able to communicate at speeds of up to 9 Mbit/s.

All USARTs support hardware management of the CTS and RTS signals, multiprocessor communication mode, single-wire half-duplex communication mode and synchronous mode.

USART1 supports SmartCard mode, IrDA SIR ENDEC, LIN Master capability and autobaudrate detection.

All USART interfaces can be served by the DMA controller.

Refer to Table 8

for the features available in all USARTs interfaces.

Table 8. USART features

USART modes/features

(1)

USART1

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

SmartCard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from Stop mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

1. X = supported.

USART2

USART3

3.19 Serial peripheral interfaces (SPI)/inter-integrated sound interfaces (I2S)

Two SPI interfaces (SPI2 and SPI3) allow communication up to 18 Mbit/s in slave and master modes in full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to

192 kHz are supported. When either or both of the I2S interfaces is/are configured in master

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Functional overview STM32F301x6 STM32F301x8 mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

Refer to Table 9

for the features available in SPI2 and SPI3.

Hardware CRC calculation

Rx/Tx FIFO

NSS pulse mode

I2S mode

TI mode

1. X = supported.

Table 9. STM32F301x6/8 SPI/I2S implementation

SPI features (1) SPI2

SPI3

3.20 Touch sensing controller (TSC)

The STM32F301x6/8 devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 18 capacitive sensing channels distributed over 6 analog I/O groups.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (for example glass, plastic). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate.

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STM32F301x6 STM32F301x8 Functional overview

Table 10. Capacitive sensing GPIOs available on STM32F301x6/8 devices

Group Capacitive sensing signal name Pin name

TSC_G1_IO1

TSC_G1_IO2

TSC_G1_IO3

TSC_G1_IO4

TSC_G2_IO1

TSC_G2_IO2

TSC_G2_IO3

TSC_G2_IO4

TSC_G3_IO1

TSC_G3_IO2

TSC_G3_IO3

TSC_G3_IO4

TSC_G4_IO1

TSC_G4_IO2

TSC_G4_IO3

TSC_G4_IO4

TSC_G5_IO1

TSC_G5_IO2

TSC_G5_IO3

TSC_G5_IO4

TSC_G6_IO1

TSC_G6_IO2

TSC_G6_IO3

TSC_G6_IO4

PC5

PB0

PB1

PB2

PA9

PA10

PA4

PA5

PA6

PA7

PA0

PA1

PA2

PA3

PA13

PA14

PB3

PB4

PB6

PB7

PB11

PB12

PB13

PB14

Table 11. No. of capacitive sensing channels available on

STM32F301x6/8 devices

Number of capacitive sensing channels

Analog I/O group

STM32F301Rx STM32F301Cx STM32F301Kx

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Functional overview STM32F301x6 STM32F301x8

Table 11. No. of capacitive sensing channels available on

STM32F301x6/8 devices (continued)

Number of capacitive sensing channels

Analog I/O group

STM32F301Rx STM32F301Cx STM32F301Kx

3 3 0 G6

Number of capacitive sensing channels

18 17 13

The STM32F301x6/8 devices provide an infrared transmitter solution. The solution is based on internal connections between TIM16 and TIM17 as shown in the figure below.

TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be sent. The infrared output signal is available on PB9 or PA13.

To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must be properly configured to generate correct waveforms. All standard IR pulse modulation modes can be obtained by programming the two timers output compare channels.

Figure 3. Infrared transmitter

TIMER 16

(for envelop)

PB9/PA13

TIMER 17

(for carrier)

MS30365V1

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DS9895 Rev 8

STM32F301x6 STM32F301x8 Functional overview

The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

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Pinouts and pin description

4 Pinouts and pin description

STM32F301x6 STM32F301x8

Figure 4. STM32F301x6/8 UFQFN32 pinout

VDD

PF0/OSC_IN

PF1/OSC_OUT

NRST

VDDA/VREF+

VSSA/VREF-

PA0

PA1

32 31 30 29 28 27 26 25

UFQFN32

9 10 11 12 13 14 15 16

PA14

PA13

PA12

PA11

PA10

PA9

PA8

VDD

MS30483V4

1. The above figure shows the package top view.

Figure 5. STM32F301x6/8 LQFP32 pinout

VDD 1

PF0/OSC_IN 2

PF1/OSC_OUT

NRST

VDDA/VREF+ 5

PA0

PA1

PA2

32 31 30 29 28 27 26 25

LQFP32

24 PA14

23 PA13

22 PA12

21 PA11

20 PA10

19 PA9

18 PA8

9 10 11 12 13 14 15 16

17 VDD

1. The above figure shows the package top view.

MS31949V3

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DS9895 Rev 8

STM32F301x6 STM32F301x8 Pinouts and pin description

Figure 6. STM32F301x6/8 LQFP48 pinout

VBAT

PC13

PC14/OSC32_IN

PC15/OSC32_OUT

PF0/OSC_IN

PF1/OSC_OUT

NRST

VSSA/VREF-

VDDA

PA0

PA1

PA2

48 47 46 45 44 43 42 41 40 39 38 37

LQFP48

7 30

8 29

9 28

10 27

14 15 16 17 18 19 20

21 22 23 24

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

MS19819V9

1. The above figure shows the package top view.

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Pinouts and pin description STM32F301x6 STM32F301x8

Figure 7. STM32F301x6/8 LQFP64 pinout

VBAT

PC13

PC14/OSC32_IN

PC15/OSC32_OUT

PF0/OSC_IN

PF1/OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA

PA0

PA1

PA2

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

5 44

6 43

7 42

8 41

LQFP64

10 39

11 38

12 37

13 36

14 35

15 34

17 18 19 20 21 22 23 24 25 26 27 28

29 30 31 32

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VDD_3

VSS_3

PA13

PA12

PA11

PA10

PA9 ai18484V7

1. The above figure shows the package top view.

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DS9895 Rev 8

STM32F301x6 STM32F301x8 Pinouts and pin description

Figure 8. STM32F301x6/8 WLCSP49 ballout

1 2 3 4 5 6 7

PA14 PA15 PB3 PB4 BOOT0 VDDA NC

B VSS VDD PA13 PB5 PB8 VBAT VDD

PA11 PA10 PA12 PB6 PB9 PC15 PC14

PA8 PA9 VSS

PB15 PB12 PB10

PB14 VDD PA7

PB7 PC13

PF1

OSC_OUT

PF0

OSC_IN

PA3 PA2

VSSA

VREF-

NRST

PA6 PA5 PA0 VSS

PB13 PB11 PB2 PB1 PB0 PA4 PA1

MS31495V3

1. The above figure shows the package top view.

2. NC: Not connected.

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Pinouts and pin description STM32F301x6 STM32F301x8

Name

Table 12. Legend/abbreviations used in the pinout table

Abbreviation Definition

Pin name

Pin type

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

FTf

TTa

Input / output pin

5 V tolerant I/O

5 V tolerant I/O, I2C FM+ option

3.3 V tolerant I/O

I/O structure

3.3 V tolerant I/O

Standard 3.3V I/O

Dedicated BOOT0 pin

Pin functions

Notes

RST Bi-directional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Alternate functions

Functions selected through GPIOx_AFR registers

Additional functions

Functions directly selected/enabled through peripheral registers

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DS9895 Rev 8

Pin Number

Pin name

(function after reset)

Table 13. STM32F301x6/8 pin definitions

Alternate functions

Additional functions

2 2 D7 5 5

VBAT

PC13

(2)

TAMPER1

WKUP2 (PC13)

PC14

(2)

OSC32_IN

(PC14)

PC15

(2)

OSC32_OUT

(PC14)

PF0 OSC_IN (PF0)

3 3 D6 6 6 PF1 OSC_OUT (PF1)

4 4 E7 7 7 NRST

8 PC0

PC1

PC2

11 PC3

6 E6 8 12

5 5 A6 9 13

VSSA/VREF-

VDDA/VREF+

I/O

FTf

RST

TTa

(1)

TIM1_CH1N

Backup power supply

WKUP2, RTC_TAMP1,

RTC_TS, RTC_OUT

OSC32_IN

(1)

OSC32_OUT

I2C2_SDA, SPI2_NSS/I2S2_WS,

TIM1_CH3N

I2C2_SCL, SPI2_SCK/I2S2_CK

OSC_IN

OSC_OUT

Device reset input/internal reset output (active low)

EVENTOUT, TIM1_CH1 ADC1_IN6

EVENTOUT, TIM1_CH2 ADC1_IN7

EVENTOUT, TIM1_CH3

EVENTOUT, TIM1_CH4,

TIM1_BKIN2

ADC1_IN8

ADC1_IN9

Analog ground/Negative reference voltage

Analog power supply/Positive reference voltage

Pin Number

Table 13. STM32F301x6/8 pin definitions (continued)

Pin name

(function after reset)

Alternate functions

Additional functions

6 7 F6 10 14 PA0 -TAMPER2-WKUP1 I/O

7 8 G7 11 15 PA1 I/O

8 9 E5 12 16

9 10 E4 13 17

F7 18

F2 19

10 11 G6 14 20

11 12 F5 15 21

12 13 F4 16 22

13 14 F3 17 23

PA2

PA3

VSS

VDD

PA4

PA5

PA6

PA7

I/O

TTa

(3)

(3)(4)

(4)

TIM2_CH1/TIM2_ETR,

TSC_G1_IO1, USART2_CTS,

EVENTOUT

RTC_REFIN, TIM2_CH2,

TSC_G1_IO2, USART2_RTS_DE,

TIM15_CH1N, EVENTOUT

TIM2_CH3, TSC_G1_IO3,

USART2_TX, COMP2_OUT,

TIM15_CH1, EVENTOUT

TIM2_CH4, TSC_G1_IO4,

USART2_RX, TIM15_CH2,

EVENTOUT

ADC1_IN1, RTC_TAMP2, WKUP1

ADC1_IN2

ADC1_IN3, COMP2_INM

ADC1_IN4

TSC_G2_IO1, SPI3_NSS/I2S3_WS,

USART2_CK, EVENTOUT

ADC1_IN5, DAC1_OUT1,

COMP2_INM, COMP4_INM,

COMP6_INM

TIM2_CH1/TIM2_ETR,

TSC_G2_IO2, EVENTOUT

TIM16_CH1, TSC_G2_IO3,

TIM1_BKIN, EVENTOUT

TIM17_CH1, TSC_G2_IO4,

TIM1_CH1N, EVENTOUT

OPAMP2_VINM

ADC1_IN10, OPAMP2_VOUT

ADC1_IN15, COMP2_INP,

OPAMP2_VINP

Pin Number

Table 13. STM32F301x6/8 pin definitions (continued)

Pin name

(function after reset)

Alternate functions

Additional functions

14 15 G5 18 26

15 G4 19 27

G3 20 28

E3 21 29

G2 22 30

16 16 D3 23 31

17 17 B2 24 32

E2 25 33

G1 26 34

PC4

PC5

PB0

PB1

PB2

PB10

PB11

VSS

VDD

PB12

PB13

TTa

I/O

I/O TTa

EVENTOUT, TIM1_ETR,

USART1_TX

EVENTOUT, TIM15_BKIN,

TSC_G3_IO1, USART1_RX

TSC_G3_IO2, TIM1_CH2N,

EVENTOUT

TSC_G3_IO3, TIM1_CH3N,

COMP4_OUT, EVENTOUT

TSC_G3_IO4, EVENTOUT

TIM2_CH3, TSC_SYNC,

USART3_TX, EVENTOUT

TIM2_CH4, TSC_G6_IO1,

USART3_RX, EVENTOUT

OPAMP2_VINM

ADC1_IN11, COMP4_INP,

OPAMP2_VINP

ADC1_IN12

COMP4_INM

ADC1_IN14, COMP6_INP

Digital ground

Digital power supply

TSC_G6_IO2, I2C2_SMBAL,

SPI2_NSS/I2S2_WS, TIM1_BKIN,

USART3_CK, EVENTOUT

TSC_G6_IO3, SPI2_SCK/I2S2_CK,

TIM1_CH1N, USART3_CTS,

EVENTOUT

ADC1_IN13

Pin Number

Table 13. STM32F301x6/8 pin definitions (continued)

Pin name

(function after reset)

Alternate functions

Additional functions

F1 27 35

E1 28 36

18 18 D1 29 41

19 19 D2 30 42

PB14

PB15

PC6

PC7

PC8

PC9

PA8

PA9

I/O TTa

I/O

TTa

FTf

TIM15_CH1, TSC_G6_IO4,

SPI2_MISO/I2S2ext_SD,

TIM1_CH2N, USART3_RTS_DE,

EVENTOUT

RTC_REFIN, TIM15_CH2,

TIM15_CH1N, TIM1_CH3N,

SPI2_MOSI/I2S2_SD, EVENTOUT

EVENTOUT, I2S2_MCK,

COMP6_OUT

EVENTOUT, I2S3_MCK

EVENTOUT

EVENTOUT, I2C3_SDA, I2SCKIN

MCO, I2C3_SCL, I2C2_SMBAL,

I2S2_MCK, TIM1_CH1,

USART1_CK, EVENTOUT

I2C3_SMBAL, TSC_G4_IO1,

I2C2_SCL, I2S3_MCK, TIM1_CH2,

USART1_TX, TIM15_BKIN,

TIM2_CH3, EVENTOUT

OPAMP2_VINP

COMP6_INM

Pin Number

Table 13. STM32F301x6/8 pin definitions (continued)

Pin name

(function after reset)

Alternate functions

Additional functions

20 20 C2 31 43

21 21 C1 32 44

22 22 C3 33 45

23 23 B3 34 46

B1 35 47

B2 36 48

24 24 A1 37 49

25 25 A2 38 50

PA10

PA11

PA12

PA13

VSS

VDD

PA14

PA15

I/O FTf

I/O

FTf

TIM17_BKIN, TSC_G4_IO2,

I2C2_SDA, SPI2_MISO/I2S2ext_SD,

TIM1_CH3, USART1_RX,

COMP6_OUT, TIM2_CH4,

EVENTOUT

SPI2_MOSI/I2S2_SD, TIM1_CH1N,

USART1_CTS, TIM1_CH4,

TIM1_BKIN2, EVENTOUT

TIM16_CH1, I2SCKIN, TIM1_CH2N,

USART1_RTS_DE, COMP2_OUT,

TIM1_ETR, EVENTOUT

SWDIO, TIM16_CH1N,

TSC_G4_IO3, IR-OUT,

USART3_CTS, EVENTOUT

Digital ground

Digital power supply

SWCLK-JTCK, TSC_G4_IO4,

I2C1_SDA, TIM1_BKIN,

USART2_TX, EVENTOUT

JTDI, TIM2_CH1/TIM2_ETR,

TSC_SYNC, I2C1_SCL,

SPI3_NSS/I2S3_WS, USART2_RX,

TIM1_BKIN, EVENTOUT

Pin Number

Table 13. STM32F301x6/8 pin definitions (continued)

Pin name

(function after reset)

Alternate functions

26 26 A3 39 55

27 27 A4 40 56

28 28 B4 41 57

29 29 C4 42 58

30 30 D4 43 59

PC10

PC11

PC12

PD2

PB3

PB4

PB5

PB6

PB7

I/O

FTf

I/O FTf

EVENTOUT, SPI3_SCK/I2S3_CK,

USART3_TX

EVENTOUT,

SPI3_MISO/I2S3ext_SD,

USART3_RX

EVENTOUT, SPI3_MOSI/I2S3_SD,

USART3_CK

EVENTOUT

JTDO-TRACESWO, TIM2_CH2,

TSC_G5_IO1, SPI3_SCK/I2S3_CK,

USART2_TX, EVENTOUT

JTRST, TIM16_CH1, TSC_G5_IO2,

SPI3_MISO/I2S3ext_SD,

USART2_RX, TIM17_BKIN,

EVENTOUT

TIM16_BKIN, I2C1_SMBAl,

SPI3_MOSI/I2S3_SD, USART2_CK,

I2C3_SDA, TIM17_CH1, EVENTOUT

TIM16_CH1N, TSC_G5_IO3,

I2C1_SCL, USART1_TX,

EVENTOUT

TIM17_CH1N, TSC_G5_IO4,

I2C1_SDA, USART1_RX,

EVENTOUT

Additional functions

Pin Number

Table 13. STM32F301x6/8 pin definitions (continued)

Pin name

(function after reset)

Alternate functions

Additional functions

31 A5 44

B5 45

C5 46

BOOT0

PB8

PB9

VSS

VDD

I/O

FTf

Boot memory selection

TIM16_CH1, TSC_SYNC,

I2C1_SCL, USART3_RX,

TIM1_BKIN, EVENTOUT

TIM17_CH1, I2C1_SDA, IR-OUT,

USART3_TX, COMP2_OUT,

EVENTOUT

Digital ground

32 32 D3 47 63

1 "1" B7 48 64 Digital power supply

1. All the I/Os available in the LQFP48 package and not available in the LQFP32 package must be configured by software in output push pull mode at "0".

2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (e.g. to drive an LED).

After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the Battery backup domain and BKP register description sections in the RM0366 reference manual.

3. Fast ADC channel.

4. These GPIOs offer a reduced touch sensing sensitivity. It is thus recommended to use them as sampling capacitor I/O.

Table 14. Alternate functions for Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8

TIM2

_CH1/

TIM2

_ETR

RTC

_REFIN

TIM2

_CH2

TIM2

_CH3

TIM2

_CH4

MCO

TIM2

_CH1/

TIM2

_ETR

TIM16

_CH1

TIM17

_CH1

TSC

_G1_IO1

TSC

_G1_IO2

TSC

_G1_IO3

TSC

_G1_IO4

TSC

_G2_IO1

TSC

_G2_IO2

TSC

_G2_IO3

TSC

_G2_IO4

I2C3

_SCL

I2C2

_SMBAL

I2S2

_MCK

USART2

_CTS

USART2

_RTS_D

USART2

_TX

COMP2

_OUT

USART2

_RX

SPI3_NSS/

I2S3_WS

USART2

_CK

TIM15

_CH1N

TIM15

_CH1

TIM15

_CH2

TIM1_BKIN -

TIM1

_CH1N

TIM1_CH1

USART1

_CK

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Table 14. Alternate functions for Port A (continued)

PA9 -

PA10 -

PA11 -

PA12 -

TIM17

_BKIN

TIM16

_CH1

PA13

PA14

SWDAT-

JTMS

SWCLK-

JTCK

TIM16

_CH1N

PA15 JTDI

TIM2_C

H1/

TIM2_E

I2C3

_SMBAL

TSC

_G4_IO1

TSC

_G4_IO2

I2C2

_SCL

I2C2

_SDA

TSC

_G4_IO3

TSC

_G4_IO4

I2C1

_SDA

TSC

_SYNC

I2C1

_SCL

I2S3

_MCK

SPI2_MO

SI/I2S2

_SD

TIM1_CH2

SPI2_MIS

O/I2S2ext

_SD

TIM1_CH3

TIM1

_CH1N

I2SCKIN

IR-OUT

USART1

_TX

USART1

_RX

USART1

_CTS

COMP6

_OUT

TIM1

_CH2N

USART1

_RTS_D

COMP2

_OUT

USART3

_CTS

TIM1_BKIN

USART2

_TX

TIM15

_BKIN

TIM2

_CH3

TIM2

_CH4

TIM1

_CH4

TIM1

_BKIN2

TIM1

_ETR

SPI3_NSS/

I2S3_WS

USART2

_RX

TIM1

_BKIN

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Table 15. Alternate functions for Port B

Port & pin name

PB0

PB1

PB2

PB3

PB4

PB5 -

PB6

PB7

PB8

JTDO-

TRACE

SWO

TIM2

_CH2

JTRST

TIM16

_CH1

TIM16

_BKIN

TIM16

_CH1N

TIM17

_CH1N

TIM16

_CH1

TSC

_G3_IO2

TSC

_G3_IO3

TSC

_G3_IO4

TSC

_G5_IO1

TSC

_G5_IO2

I2C1

_SMBAl

TSC

_G5_IO3

I2C1

_SCL

TSC

_G5_IO4

I2C1

_SDA

TSC

_SYNC

I2C1

_SCL

TIM1

_CH2N

TIM1

_CH3N

COMP4_

OUT

SPI3_SC

K/I2S3_

USART2

_TX

SPI3_MI

SO/I2S3

_SD

SPI3

_MOSI/

I2S3ext_

USART2

_RX

USART2

_CK

I2C3

_SDA

USART1

_TX

USART1

_RX

USART3

_RX

TIM17

_BKIN

TIM17

_CH1

TIM1

_BKIN

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Table 15. Alternate functions for Port B (continued)

Port & pin name

PB9

PB10

PB11

PB12

PB13

PB14

PB15

TIM17

_CH1

TIM2

_CH3

TIM2

_CH4

TIM15

_CH1

RTC

_REFIN

TIM15

_CH2

TIM15

_CH1N

TSC

_SYNC

TSC

_G6_IO1

I2C1

_SDA

IR-OUT

TSC

_G6_IO2

I2C2

_SMBAL

TSC

_G6_IO3

TSC

_G6_IO4

TIM1

_CH3N

SPI2_NS

S/I2S2_

TIM1

_BKIN

SPI2_SC

I2S2_CK

TIM1

_CH1N

SPI2_MI

SO/I2S2 ext_SD

SPI2_M

OSI/

I2S2_SD

TIM1

_CH2N

USART3

_TX

COMP2_

OUT

USART3

_TX

USART3

_RX

USART3

_CK

USART3

_CTS

USART3

_RTS

_DE

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

PC11

PC12

PC13

PC14

PC15

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PC8

PC9

PC10

AF0

Port & pin name

SYS_AF

AF1

Table 16. Alternate functions for Port C

AF2 AF3

EVENTOUT

TIM2/TIM15/

TIM16/TIM17/

EVENT

I2C3/TIM1/TIM2

/TIM15

I2C3/TIM15/

TSC

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM1_ETR

TIM15_BKIN

TSC_G3_IO1

I2C3_SDA

AF4 AF5

I2C1/I2C2/TIM1/

TIM16/TIM17

SPI2/I2S2/

SPI3/I2S3

Infrared

I2SCKIN

EVENTOUT

TIM1_CH1N

AF6 AF7

I2S3_MCK

SPI3_SCK/

I2S3_CK

SPI3_MISO/

I2S3ext_SD

SPI3_MOSI/

I2S3_SD

SPI2/I2S2/SPI3/

I2S3/TIM1/

Infrared

USART1/

USART2/

USART3/

GPCOMP6

TIM1_BKIN2

I2S2_MCK

USART1_TX

USART1_RX

COMP6_OUT

USART3_TX

USART3_RX

USART3_CK

AF0

Port & pin name SYS_AF

PD2 -

AF0

Port & pin name SYS_AF

PF0 -

PF1 -

AF1

TIM2/TIM15/

TIM16/TIM17/

EVENT

EVENTOUT

Table 17. Alternate functions for Port D

AF2 AF3 AF4 AF5

I2C3/TIM1/TIM2/

TIM15

I2C3/TIM15/TSC

I2C1/I2C2/TIM1/

TIM16/TIM17

SPI2/I2S2/

SPI3/I2S3/

Infrared

AF1

TIM2/TIM15/

TIM16/TIM17/

EVENT

Table 18. Alternate functions for Port F

AF2

I2C3/TIM1/TIM2/

TIM15

I2C3/TIM15/TSC

AF3 AF4 AF5

I2C1/I2C2/TIM1/

TIM16/TIM17

SPI2/I2S2/

SPI3/I2S3/

Infrared

I2C2_SDA

I2C2_SCL

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

AF6 AF7

SPI2/I2S2/SPI3/

I2S3/TIM1/

Infrared

USART1/

USART2/

USART3/

GPCOMP6

AF6 AF7

SPI2/I2S2/SPI3/

I2S3/TIM1/

Infrared

USART1/USAR

T2/USART3/

GPCOMP6

TIM1_CH3N -

Memory mapping STM32F301x6 STM32F301x8

50/141

Figure 9. STM32F301x6/8 memory mapping

0x5000

07FF

0xFFFF FFFF

Cortex-M4 with FPU

Internal

Peripherals

0xE000 0000

0x5000 0000

0x4800 1800

0x4800 0000

AHB3

Reserved

AHB2

Reserved

0x4002 43FF

AHB1

0xC000 0000

0x4002 0000

Reserved

0x4001 6C00

APB2

0xA000 0000

0x4001 0000

Reserved

0x4000 A000

APB1

0x8000 0000

0x4000 0000

0x1FFF FFFF

Option bytes

0x6000 0000

0x1FFF F800

System memory

0x1FFF D800

0x4000 0000

Peripherals

0x2000 0000 SRAM

0x0000 0000

CODE

Reserved

0x0804 0000

Flash memory

0x0800 0000

Reserved

0x0001 0000

0x0000 0000

Flash, system memory or SRAM, depending on BOOT configuration

MSv30355V3

DS9895 Rev 8

STM32F301x6 STM32F301x8 Memory mapping

Bus

AHB3

AHB2

AHB1

APB2

Table 19. STM32F301x6 STM32F301x8 peripheral register boundary addresses (1)

Boundary address Size (bytes) Peripheral

0x5000 0000 - 0x5000 03FF

0x4800 1800 - 0x4FFF FFFF

0x4800 1400 - 0x4800 17FF

0x4800 1000 - 0x4800 13FF

0x4800 0C00 - 0x4800 0FFF

0x4800 0800 - 0x4800 0BFF

0x4800 0400 - 0x4800 07FF

0x4800 0000 - 0x4800 03FF

0x4002 4400 - 0x47FF FFFF

0x4002 4000 - 0x4002 43FF

0x4002 3400 - 0x4002 3FFF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0400 - 0x4002 0FFF

0x4002 0000 - 0x4002 03FF

0x4001 8000 - 0x4001 FFFF

0x4001 4C00 - 0x4001 7FFF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3000 - 0x4001 37FF

0x4001 2C00 - 0x4001 2FFF

0x4001 0800 - 0x4001 2BFF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 9C00 - 0x4000 FFFF

1 K

2 K

3 K

1 K

3 K

1 K

32 K

13 K

1 K

8 K

1 K

~132 M

1 K

~128 M

1 K

3 K

1 K

3 K

1 K

25 K

Reserved

RCC

Reserved

DMA1

Reserved

TIM17

TIM16

TIM15

Reserved

USART1

Reserved

ADC1

Reserved

GPIOF

Reserved

GPIOD

GPIOC

GPIOB

GPIOA

Reserved

TSC

Reserved

CRC

Reserved

Flash interface

TIM1

Reserved

EXTI

SYSCFG + COMP +

OPAMP

Reserved

DS9895 Rev 8

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Memory mapping STM32F301x6 STM32F301x8

Bus

APB1

Table 19. STM32F301x6 STM32F301x8 peripheral register boundary addresses (continued) (1)

Boundary address Size (bytes) Peripheral

0x4000 7C00 - 0x4000 9BFF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 5C00 - 0x4000 6FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 4C00 - 0x4000 53FF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 1400 - 0x4000 27FF

0x4000 1000 - 0x4000 13FF

0x4000 0400 - 0x4000 0FFF

0x4000 0000 - 0x4000 03FF

0x2000 4000 - 3FFF FFFF

0x2000 0000 - 0x2000 3FFF

0x1FFF F800 - 0x1FFF FFFF

0x1FFF D800 - 0x1FFF F7FF

0x0801 0000 - 0x1FFF D7FF

0x0800 0000 - 0x0800 FFFF

0x0001 0000 - 0x07FF FFFF

0x0000 000 - 0x0000 FFFF

1 K

5 K

1 K

2 K

8 K

1 K

3 K

1 K

~512 M

16 K

2 K

8 K

~384 M

64 K

~128 M

64 K

Reserved

I2C3

DAC1

PWR

Reserved

I2C2

I2C1

Reserved

USART3

USART2

I2S3ext

SPI3/I2S3

SPI2/I2S2

I2S2ext

IWDG

WWDG

RTC

Reserved

TIM6

Reserved

TIM2

Reserved

SRAM

Option bytes

System memory

Reserved

Main Flash memory

Reserved

Main Flash memory, system memory or SRAM depending on BOOT configuration

1. The gray color is used for reserved Flash memory addresses.

52/141

DS9895 Rev 8

STM32F301x6 STM32F301x8 Electrical characteristics

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 σ ).

Unless otherwise specified, typical data are based on T

A are given only as design guidelines and are not tested.

= 25 °C, V

= V

DDA

= 3.3 V. They

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 10

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 11 .

Figure 10. Pin loading conditions Figure 11. Pin input voltage

MCU pin MCU pin

C = 50 pF

MS19210V1

DS9895 Rev 8

MS19211V1

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115

Electrical characteristics

6.1.6 Power supply scheme

STM32F301x6 STM32F301x8

Figure 12. Power supply scheme

BAT

1.65 – 3.6 V

Power switch

Backup circuitry

(LSE, RTC,

Wakeup logic,

Backup registers)

GP I/Os

OUT

I/O logic

Kernel logic

(CPU, digital

& memories)

4 x 100 nF

+ 1 x 4.7 μF

DDA

4 x V

DDA

Regulator

10 nF

+ 1 μF

REF+

REF-

ADC/DAC

Analog: RCs,

PLL,comparators, OPAMP,

....

SSA

MS19875V5

Caution: Each power supply pair (for example V

, V

DDA

SSA

) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

54/141

DS9895 Rev 8

STM32F301x6 STM32F301x8 Electrical characteristics

Figure 13. Current consumption measurement scheme

IDD_VBAT

VBAT

IDD

VDD

IDDA

VDDA

MS19213V1

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115

Electrical characteristics STM32F301x6 STM32F301x8

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 20: Voltage characteristics

Table 21: Current characteristics

, and

Table 22: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 20. Voltage characteristics

(1)

Ratings Min Max Unit

–V

(2)

–V

DDA

DDx

SSX

− V

ESD(HBM)

External main supply voltage (including V

DDA, and V

)

BAT

Allowed voltage difference for V

> V

DDA

Input voltage on FT and FTf pins

Input voltage on TTa and TT pins

Input voltage on any other pin

Input voltage on Boot0 pin

Variations between different V

Electrostatic discharge voltage (human body model)

DD power pins

Variations between all the different ground pins

(3)

-0.3

4.0

− 0.3

0.4

+ 4.0

4.0

50 -

50 see

Section 6.3.12: Electrical sensitivity characteristics

1. All main power (V

DDA

, V

DDA

) and ground (V

, V

SSA

) pins must always be connected to the external power supply, in the

must power on before or at the same time as V

must be greater than or equal to V

DDA

and V

in the power up sequence.

2. V

maximum must always be respected. Refer to

Table 21: Current characteristics for the maximum allowed injected

current values.

3. Include V

REF-

pin.

V mV

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DS9895 Rev 8

STM32F301x6 STM32F301x8 Electrical characteristics

Symbol

Table 21. Current characteristics

Ratings Max.

Unit

Σ I

VDD

VSS

VDD

VSS

INJ(PIN)

Total current into sum of all VDD power lines (source)

Total current out of sum of all VSS ground lines (sink)

Maximum current into each V

DD power line (source)

(1)

Maximum current out of each V

SS ground line (sink) (1)

Output current sunk by any I/O and control pin

130

-130

100

-100

IO(PIN)

Output current sourced by any I/O and control pin

Total output current sunk by sum of all IOs and control pins

(2)

Total output current sourced by sum of all IOs and control pins

(2)

Injected current on TT, FT, FTf and B pins

(3)

Injected current on TC and RST pin (4)

Injected current on TTa pins

(5)

Total injected current (sum of all I/O and control pins)

(6)

-25

-80

-5/+0

+/-5

+/-5 mA

Σ I

INJ(PIN)

+/-25

1. All main power (V permitted range.

, V

DDA

) and ground (V

and V

SSA

) pins must always be connected to the external power supply, in the

2. This current consumption must be correctly distributed over all I/Os and control pins.The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.

3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

4. A positive injection is induced by V

exceeded. Refer to

> V

while a negative injection is induced by V < V

. I

INJ(PIN)

must never be

5. A positive injection is induced by V

exceeded. Refer also to

> V

DDA

while a negative injection is induced by V

Table 20: Voltage characteristics

< V

. I (PIN) must never be

for the maximum allowed input voltage values. Negative injection disturbs the analog performance of the device. See note (2) below

Table 65

6. When several inputs are submitted to a current injection, the maximum Σ I negative injected currents (instantaneous values).

INJ(PIN)

is the absolute sum of the positive and

Symbol

STG

Table 22. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

DS9895 Rev 8

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115

Electrical characteristics STM32F301x6 STM32F301x8

6.3.1 General operating conditions

Symbol

Table 23. General operating conditions

Parameter Conditions Min Max Unit f f f

HCLK

PCLK1

PCLK2

DDA

BAT

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

Analog operating voltage

(OPAMP and DAC not used)

Analog operating voltage

(OPAMP and DAC used)

Must have a potential equal to or higher than

Backup operating voltage

I/O input voltage

TC I/O

TT I/O

(1)

TTa I/O pins

FT and FTf I/O

(1)

BOOT0

Power dissipation at

= 85 °C for suffix 6 or

= 105 °C for suffix 7

(2)

Ambient temperature for 6 suffix version

Ambient temperature for 7 suffix version

Junction temperature range

LQFP64

LQFP48

WLCSP49

UFQFPN32

LQFP32

Maximum power dissipation

Low power dissipation (3)

Maximum power dissipation

Low power dissipation

(3)

6 suffix version

7 suffix version

2.4

3.6

1.65

3.6

–0.3

+0.3

-0.3

3.6

–0.3

DDA

+0.3

–0.3

5.5

0 5.5

444

364

408

540

333

–40 85

–40 105

–40 125

–40 105

–40 125

MHz

V mW

°C

1. To sustain a voltage higher than V

+0.3 V, the internal pull-up/pull-down resistors must be disabled.

2. If T is lower, higher P

thermal characteristics .

values are allowed as long as T

does not exceed T

Jmax

. See

Table 80: Package

3. In low power dissipation state, T

can be extended to this range as long as T

Table 80: Package thermal characteristics

does not exceed T

Jmax

. See

58/141

DS9895 Rev 8

STM32F301x6 STM32F301x8 Electrical characteristics

6.3.3

The parameters given in

Table 24 are derived from tests performed under the ambient

temperature condition summarized in

Table 23 .

Symbol t

VDD t

VDDA

Table 24. Operating conditions at power-up / power-down

Parameter Conditions Min Max

rise time rate

fall time rate

DDA

rise time rate

DDA

fall time rate

∞

Unit

µs/V

Embedded reset and power control block characteristics

The parameters given in

Table 25 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Table 23 .

Symbol

Table 25. Embedded reset and power control block characteristics

Parameter Conditions Min Typ Max Unit

POR/PDR

(1)

PDRhyst

(1) t

RSTTEMPO

(3)

Power on/power down reset threshold

PDR hysteresis

POR reset temporization

Falling edge

Rising edge

1.8

(2)

1.84

1.5

1.88

1.92

2.5

1.96

2.0

4.5

1. The PDR detector monitors V monitors only V

and also V

DDA

(if kept enabled in the option bytes). The POR detector

2. The product behavior is guaranteed by design down to the minimum V

POR/PDR

value.

3. Based on characterization, not tested in production.

V mV ms

DS9895 Rev 8

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115

Electrical characteristics STM32F301x6 STM32F301x8

Symbol

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6

PVD7

Table 26. Programmable voltage detector characteristics

Parameter Conditions Min

(1)

Typ Max

(1)

PVD threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

PVD threshold 7

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

2.47

2.37

2.57

2.47

2.66

2.56

2.28

2.18

2.38

2.28

2.1

2.19

2.09

2.76

2.66

PVDhyst

(2)

IDD(PVD)

PVD hysteresis

PVD current consumption

1. Guaranteed by characterization results.

2. Guaranteed by design.

2.18

2.26

2.08

2.16

2.28

2.37

2.18

2.27

2.38

2.48

2.28

2.38

2.48

2.58

2.38

2.48

2.58

2.69

2.48

2.59

2.68

2.79

2.58

2.69

2.78

2.9

2.68

2.8

2.88

2.78

100

2.9

0.15

0.26

Unit

V mV

µA

60/141

DS9895 Rev 8

STM32F301x6 STM32F301x8 Electrical characteristics

6.3.5

Note:

The parameters given in

Table 27 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Table 23 .

Symbol

REFINT

S_vrefint

RERINT

Coeff

Table 27. Embedded internal reference voltage

Parameter Conditions Min Typ Max Unit

V Internal reference voltage –40 °C < T

< +105 °C 1.20

1.23

1.25

ADC sampling time when reading the internal reference voltage

2.2

Internal reference voltage spread over the temperature range

= 3 V ±10 mV 10

(1)

Temperature coefficient -

100

(1)

µs mV ppm/°

1. Guaranteed by design.

Table 28. Internal reference voltage calibration values

Calibration value name Description Memory address

REFINT_CAL

Raw data acquired at temperature of 30 °C

DDA

= 3.3 V

0x1FFF F7BA - 0x1FFF F7BB

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 13: Current consumption measurement scheme

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.

The total current consumption is the sum of I

and I

DDA

DS9895 Rev 8

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115

Electrical characteristics STM32F301x6 STM32F301x8

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

or V

(no load)

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted to the f

HCLK

frequency (0 wait state from 0 to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)

• Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)

• When the peripherals are enabled f

PCLK2

= f

HCLK

and f

PCLK1

= f

HCLK/2

• When f

HCLK

> 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or

HSE (8 MHz) in bypass mode.

The parameters given in

Table 29 to

Table 35 are derived from tests performed under

ambient temperature and supply voltage conditions summarized in

Table 23 .

Table 29. Typical and maximum current consumption from VDD supply at VDD = 3.6V

All peripherals enabled All peripherals disabled

Symbol Parameter Conditions f

HCLK

Supply

current in

Run mode,

executing

from Flash

Typ

Max @ T

(1)

25 °C 85 °C 105 °C

72 MHz 45.7

48.6

50.0

64 MHz 40.6

43.6

44.5

External clock (HSE bypass)

48 MHz 30.8

33.6

34.1

32 MHz 21.0

22.9

23.5

24 MHz 16.0

16.8

18.0

8 MHz 5.4

5.6

6.1

Internal clock (HSI)

1 MHz 1.1

1.2

1.7

64 MHz 37.6

41.3

42.9

48 MHz 28.7

32.3

33.1

32 MHz 19.5

22.0

23.4

24 MHz 14.9

16.6

17.9

8 MHz 5.2

5.5

6.4

Typ

Max @ T

(1)

25 °C 85 °C 105 °C

52.0

25.5

27.5

28.1

46.4

22.7

24.6

25.2

35.5

17.3

19.0

19.5

25.6

11.7

13.2

13.7

18.9

9.0

10.4

10.8

7.2

3.3

3.8

2.7

0.8

0.9

1.3

44.7

22.5

24.7

25.0

34.0

17.2

19.1

19.4

24.6

11.5

12.9

13.5

18.4

6.0

7.0

7.4

7.0

3.2

3.8

4.3

1.6

25.8

19.6

13.7

7.9

4.7

28.8

25.9

20.0

14.1

11.4

4.2

Unit mA

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STM32F301x6 STM32F301x8 Electrical characteristics

Table 29. Typical and maximum current consumption from VDD supply at VDD = 3.6V (continued)

All peripherals enabled All peripherals disabled

Symbol Parameter Conditions f

HCLK

Max @ T

(1)

Max @ T

(1)

Typ Typ

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

72 MHz 45.8 49.1

(2)

50.1

64 MHz 40.8

43.6

44.9

51.4

(2)

46.9

25.1 27.3

22.3

(2)

24.1

28.0

25.0

28.6

(2)

25.5

Supply current in

Run mode, executing from RAM

Supply current in

Sleep mode, executing from Flash or RAM

External clock (HSE bypass)

48 MHz 30.2

32.9

33.5

32 MHz 20.5

23.1

24.1

24 MHz 15.4

17.1

18.3

8 MHz 5.0

5.9

6.3

Internal clock (HSI)

External clock (HSE bypass)

48 MHz 16.7

18.5

19.0

32 MHz 13.3

14.9

15.3

24 MHz 10.2

11.4

12.0

8 MHz 3.6

4.4

4.8

Internal clock (HSI)

1 MHz 0.8

1.1

64 MHz 37.3

41.1

41.8

48 MHz 28.0

31.1

1.9

31.6

34.8

17.0

18.7

19.1

25.4

11.1

12.2

13.2

19.5

6.9

8.5

3.1

9.7

3.7

10.1

4.1

32 MHz 18.8

24 MHz 14.2

21.3

15.9

22.1

16.8

23.1

10.9

11.9

12.8

17.9

5.5

6.4

6.7

4.1

8 MHz 4.8

5.1

72 MHz 30.0 32.8

(2)

6.0

64 MHz 26.7

29.2

29.6

6.5

33.1

34.1

(2)

30.5

2.9

3.5

5.9

6.8

(2)

5.3

5.9

6.9

6.2

1 MHz 0.5

0.8

1.1

64 MHz 23.2

25.3

25.6

48 MHz 17.5

19.2

19.4

32 MHz 11.7

12.9

13.2

24 MHz 8.9

10.2

10.6

8 MHz 3.4

4.0

4.6

2.6

43.3

22.0

23.8

24.4

33.2

19.7

15.4

12.3

5.3

1.3

26.2

19.9

13.3

10.8

5.1

0.5

16.4

2.9

2.2

0.9

0.8

18.0

3.6

4.5

3.7

2.7

1.2

0.1

0.4

5.0

5.7

3.9

4.7

2.6

3.4

1.4

2.1

0.7

1.1

1.2

18.3

4.5

3.8

2.9

1.5

0.8

6.1

4.8

3.6

2.4

1.4

0.8

6.2

5.3

4.2

2.7

1.9

5.3

4.3

3.2

2.1

19.6

13.3

10.2

4.7

1.4

24.9

18.6

13.1

7.3

4.2

7.4

(2)

6.7

1. Guaranteed by characterization results.

2. Data based on characterization results and tested in production with code executing from RAM.

Unit mA mA

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Electrical characteristics STM32F301x6 STM32F301x8

Table 30. Typical and maximum current consumption from the V

DDA

supply

DDA

= 2.4 V V

DDA

= 3.6 V

Symbol Parameter

Conditions

(1) f

HCLK

Typ

Max @ T

(2)

25 °C 85 °C 105 °C

Typ

Max @ T

(2)

25 °C 85 °C 105 °C

DDA

Supply current in

Run/Sleep mode, code executing from Flash or RAM

HSE bypass

HSI clock

72 MHz 231 254 (3)

64 MHz 203 226

48 MHz 153 174

32 MHz 105 124

24 MHz 82 98

8 MHz 3.1

1 MHz 3.1

4.1

64 MHz 270 294

48 MHz 219 242

32 MHz 171 192

24 MHz 148 169

8 MHz 69 84

266 271 (3)

239

182

243

186

251

222

165

274 (3)

245

185

294

261

198

300 (3)

266

203

131

104

4.1

133 114 132 141

105

5.1

3.6

106

4.7

111

5.2

143

113

5.5

307

253

201

312 296 322 338

257 240 263 276

203 188 209 219

343

281

222

175

177 163 182 190

87 79 92 94

193

Unit

µA

1. Current consumption from the V

PLL is off, I

DDA

supply is independent of whether the peripherals are on or off. Furthermore when the

is independent from the frequency.

2. Guaranteed by characterization results.

3. Data based on characterization results and tested in production.

Table 31. Typical and maximum V

consumption in Stop and Standby modes

Typ @V

DDA

) Max

(1)

Symbol Parameter Conditions

2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V

25 °C

85 °C

105 °C

Unit

Supply current in

Stop mode

Regulator in run mode, all oscillators OFF

Regulator in low-power mode, all oscillators OFF

16.92 17.09 17.16 17.27 17.39 17.50 29.7 359.1 564.5

5.29 5.46 5.55 5.70 5.73 5.95 16.40 267.1 407.4

Supply current in

Standby mode

LSI ON and IWDG ON 0.80 0.93 1.11 1.19 1.31 1.41

LSI OFF and IWDG OFF 0.63 0.76 0.84 0.95 1.02 1.10

5.00

6.30

12.60

1. Guaranteed by characterization results.

µA

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Table 32. Typical and maximum V

DDA

consumption in Stop and Standby modes

Typ @V

= V

DDA

) Max

(1)

Symbol Parameter Conditions

2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V

25 °C

85 °C

105 °C

Unit

DDA

Supply current in

Stop mode

Supply current in

Standby mode

Supply current in

Stop mode

Supply current in

Standby mode

Regulator in run/lowpower mode, all oscillators OFF

LSI ON and IWDG ON 2.08 2.25 2.41 2.59 2.79 3.01

LSI OFF and IWDG

OFF

Regulator in run/lowpower mode, all oscillators OFF

1.70 1.83 1.95 2.08 2.22 2.37 3.40

0.99 1.01 1.04 1.09 1.14 1.21

LSI ON and IWDG ON 1.36 1.43 1.50 1.60 1.72 1.85

LSI OFF and IWDG

OFF

1. Guaranteed by characterization results.

1.59 1.72 1.83 1.96 2.10 2.25 2.80

0.87 0.89 0.92 0.97 1.02 1.09

5.30

2.90

5.5

3.60

µA

Symbol

Table 33. Typical and maximum current consumption from V

BAT

supply

Para meter

Conditions

(1)

Typ.@V

BAT

Max.

BAT

= 3.6V

(2)

(°C)

85 105 1.65V 1.8V 2V 2.4V 2.7V

3V 3.3V 3.6V

DD_VBAT

Backup domain supply current

LSE & RTC

ON; “Xtal mode” lower driving capability;

LSEDRV[1:

0] = '00'

LSE & RTC

ON; “Xtal mode” higher driving capability;

LSEDRV[1:

0] = '11'

0.41

0.65

0.43 0.46 0.54

0.68 0.73 0.80

0.59 0.66 0.74 0.82

0.87 0.95 1.03 1.14

1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.

2. Guaranteed by characterization results.

Unit

µA

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Electrical characteristics STM32F301x6 STM32F301x8

Figure 14. Typical V

BAT

current consumption (LSE and RTC ON/LSEDRV[1:0] = ‘00’)

1.60

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

1.65V

1.8V

2.4V

2.7V

3.3V

3.6V

25°C 60°C 85°C 105°C

(°C)

MSxxxxxVy

MS3452591

Typical current consumption

The MCU is placed under the following conditions:

• V

= V

DDA

= 3.3 V

• All I/O pins available on each package are in analog input configuration

• The Flash access time is adjusted to f

HCLK

frequency (0 wait states from 0 to 24 MHz,

1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash prefetch is ON

• When the peripherals are enabled, f

APB1

= f

AHB/2

, f

APB2

= f

AHB

• PLL is used for frequencies greater than 8 MHz

• AHB prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz,

500 kHz and 125 kHz respectively.

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Table 34. Typical current consumption in Run mode, code with data processing running from

Flash

Typ

Symbol Parameter Conditions f

HCLK Peripherals enabled

Peripherals disabled

Unit

DDA

(1) (2)

Supply current in

Run mode from

supply

Supply current in

Run mode from

DDA

supply

Running from HSE crystal clock 8 MHz, code executing from

Flash

64 MHz

48 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

72 MHz

64 MHz

48 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

72 MHz

10.9

5.7

3.43

2.18

1.56

1.25

0.96

44.8

40.0

30.3

20.7

15.8

57.8

1.15

237.1

208.3

154.3

105.0

81.3

6.5

3.55

3.22

1.53

1.19

0.96

0.84

24.9

22.4

17.1

11.9

9.2

µA

1. V

DDA

supervisor is OFF.

2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,

OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.

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Electrical characteristics STM32F301x6 STM32F301x8

Table 35. Typical current consumption in Sleep mode, code running from Flash or RAM

Typ

Symbol Parameter Conditions f

HCLK Peripherals enabled

Peripherals disabled

Unit

Supply current in

Sleep mode from

supply

500 kHz

125 kHz

72 MHz

64 MHz

48 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

72 MHz

64 MHz

48 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

28.7

25.6

19.3

13.1

10.0

6.8

3.54

2.35

1.64

1.28

1.11

0.92

6.1

5.5

4.26

3.04

2.42

1.81

0.98

0.88

0.80

0.77

0.75

0.74

DDA

(1) (2)

Supply current in

Sleep mode from

DDA

supply

Running from HSE crystal clock 8 MHz, code executing from

Flash or RAM

237.1

208.3

154.3

105.0

81.3

57.8

1.15

µA

1. V

DDA

supervisor is OFF.

2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,

OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.

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I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 53: I/O static characteristics

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 37: Peripheral current consumption ), the I/Os used by an application also contribute to the current consumption.

When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

= V

× f

× C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

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Electrical characteristics STM32F301x6 STM32F301x8

Symbol

Table 36. Switching output I/O current consumption

Parameter Conditions

(1)

I/O toggling frequency (f

)

2 MHz

I/O current consumption

= 3.3 V

C ext

C = C

INT

= 0 pF

+ C

EXT

+ C

C ext

C = C

INT

= 3.3 V

= 10 pF

+ C

EXT

C ext

C = C

INT

= 3.3 V

= 22 pF

+ C

EXT

C ext

C = C

INT

= 3.3 V

= 33 pF

+ C

EXT

+ C

C ext

C = C

INT

= 3.3 V

= 47 pF

+ C

EXT

+ C

4 MHz

8 MHz

18 MHz

36 MHz

48 MHz

2 MHz

4 MHz

8 MHz

18 MHz

36 MHz

48 MHz

2 MHz

4 MHz

8 MHz

18 MHz

36 MHz

2 MHz

4 MHz

8 MHz

18 MHz

36 MHz

2 MHz

4 MHz

8 MHz

18 MHz

1. CS = 5 pF (estimated value).

Unit mA

Typ

2.06

3.47

8.35

1.20

1.54

2.46

4.51

1.30

1.79

3.01

5.99

1.10

1.31

1.06

1.47

2.26

3.39

5.99

1.03

0.90

0.93

1.16

1.60

2.51

2.97

0.93

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On-chip peripheral current consumption

The MCU is placed under the following conditions:

• all I/O pins are in analog input configuration

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

• ambient operating temperature at 25°C and V

= V

DDA

= 3.3 V.

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Electrical characteristics STM32F301x6 STM32F301x8

Table 37. Peripheral current consumption

Typical consumption (1)

Peripheral

BusMatrix

(2)

DMA1

CRC

GPIOA

GPIOB

GPIOC

GPIOD

GPIOF

TSC

ADC1

APB2-Bridge

(3)

SYSCFG

TIM1

USART1

TIM15

TIM16

TIM17

APB1-Bridge

(3)

TIM2

TIM6

WWDG

SPI2

SPI3

USART2

USART3

I2C1

I2C2

PWR

DAC

I2C3

35.2

34.2

13.9

13.1

5.8

40.7

7.4

4.6

9.4

4.5

8.3

10.5

21.0

14.3

10.1

10.4

15.9

2.7

3.2

27.6

8.6

1.5

1.0

4.7

11.3

6.7

2.0

8.5

8.3

Unit

µA/MHz

1. The power consumption of the analog part (I

DDA

) of peripherals such as ADC, DAC, Comparators, OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.

2. BusMatrix is automatically active when at least one master is ON (CPU or DMA1).

3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus.

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6.3.6 Wakeup time from low-power mode

The wakeup times given in Table 38

are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:

• For Stop or Sleep mode: the wakeup event is WFE.

• WKUP1 (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.

All timings are derived from tests performed under ambient temperature and V

DD voltage conditions summarized in

Table 23 .

supply

Symbol

Table 38. Low-power mode wakeup timings

Typ @V

DD,

= V

DDA

Parameter Conditions

2.0 V 2.4 V 2.7 V 3 V 3.3 V 3.6 V t

WUSTOP

Wakeup from

Stop mode t

WUSTANDBY

(1)

Wakeup from

Standby mode

Regulator in run mode

Regulator in low-power mode

LSI and

IWDG OFF

4.5

8.2

72.8

4.2

7.0

63.4

4.1

6.4

59.2

4.0

6.0

56.1

3.8

5.7

53.1

3.8

5.5

Max Unit

4.5

9.0

51.3

103

µs t

WUSLEEP

Wakeup from

Sleep mode

6 -

CPU clock cycles

1. Guaranteed by characterization results.

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Electrical characteristics STM32F301x6 STM32F301x8

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The

external clock signal has to respect the I/O characteristics in Section 6.3.14

. However, the

Symbol

Table 39. High-speed external user clock characteristics

Parameter f

HSE_ext

User external clock source frequency

(1)

HSEH

HSEL t w(HSEH) t w(HSEL) t r(HSE) t f(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

1. Guaranteed by design.

(1)

Conditions

Min

0.7V

Typ Max Unit

0.3V

MHz

V ns

Figure 15. High-speed external clock source AC timing diagram tw(HSEH)

VHSEH

VHSEL

90%

10% tr(HSE)

THSE tf(HSE) tw(HSEL) t

MS19214V2

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Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The

external clock signal has to respect the I/O characteristics in Section 6.3.14

. However, the

Symbol

Table 40. Low-speed external user clock characteristics

Parameter f

LSE_ext

LSEH

User External clock source frequency

(1)

OSC32_IN input pin high level voltage

LSEL

OSC32_IN input pin low level voltage t w(LSEH) t w(LSEL) t r(LSE) t f(LSE)

OSC32_IN high or low time

OSC32_IN rise or fall time

1. Guaranteed by design.

(1)

Conditions

Min

0.7V

450

Typ

32.768

Max

1000

0.3V

Unit kHz

V ns

Figure 16. Low-speed external clock source AC timing diagram tw(LSEH)

VLSEH

VLSEL

90%

10% tr(LSE)

TLSE tf(LSE) tw(LSEL) t

MS19215V2

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Electrical characteristics STM32F301x6 STM32F301x8

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 41 . In the

application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Symbol

Table 41. HSE oscillator characteristics

Parameter Conditions

(1)

Min

(2)

Typ Max

(2)

Unit f

OSC_IN

Oscillator frequency

Feedback resistor

HSE current consumption

During startup

(3)

=3.3 V, Rm= 30 Ω ,

CL=10 pF@8 MHz

=3.3 V, Rm= 45 Ω ,

CL=10 pF@8 MHz

=3.3 V, Rm= 30 Ω ,

CL= 5 pF@32 MHz

=3.3 V, Rm= 30 Ω ,

CL=10 pF@32 MHz

200

0.4

0.5

0.8

8.5

MHz k Ω mA

=3.3 V, Rm= 30 Ω ,

CL=20 pF@32 MHz

1.5

g m t

SU(HSE)

(4)

Oscillator transconductance

Startup time

Startup

is stabilized

2 -

mA/V ms

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by design.

3. This consumption level occurs during the first 2/3 of the t

SU(HSE)

startup time.

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

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Note:

Electrical characteristics

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (Typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 17

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 17. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

OSC_IN f

HSE

8 MHz resonator

EXT

(1) OSC_OUT

Bias controlled gain

MS19876V1

1. R

EXT

value depends on the crystal characteristics.

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Electrical characteristics STM32F301x6 STM32F301x8

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 42 . In the

(frequency, package, accuracy).

Symbol

Table 42. LSE oscillator characteristics (f

LSE

= 32.768 kHz)

Parameter Conditions

(1)

Min

(2)

Typ Max

(2)

Unit

LSE current consumption

LSEDRV[1:0]=00 lower driving capability

LSEDRV[1:0]=10 medium low driving capability

LSEDRV[1:0]=01 medium high driving capability

LSEDRV[1:0]=11 higher driving capability

LSEDRV[1:0]=00 lower driving capability

0.5

0.9

1.3

1.6

µA g m

Oscillator transconductance

LSEDRV[1:0]=10 medium low driving capability

LSEDRV[1:0]=01 medium high driving capability

15 -

µA/V

LSEDRV[1:0]=11 higher driving capability

25 t

SU(LSE)

(3)

Startup time V

is stabilized 2 s

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

2. Guaranteed by design.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

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Figure 18. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

OSC32_IN f

LSE

32.768 kHz resonator

Drive programmable amplifier

OSC32_OUT

Note:

MS30253V2

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

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Electrical characteristics

6.3.8 Internal clock source characteristics

STM32F301x6 STM32F301x8

The parameters given in

Table 43 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 23

High-speed internal (HSI) RC oscillator

Symbol

Table 43. HSI oscillator characteristics (1)

Parameter Conditions Min f

HSI

TRIM

DuCy

ACC

(HSI)

HSI

Frequency

HSI user trimming step

Duty cycle

Accuracy of the HSI oscillator

(2)

= -40 to

105°C

-2.8

(3)

= -10 to 85°C -1.9

(3)

= 0 to 85°C -1.9

(3)

= 0 to 70°C -1.3

(3)

= 0 to 55°C

= 25°C (4)

-1

(3)

-1

(2)

I t su(HSI)

DDA(HSI)

HSI oscillator startup time

HSI oscillator power consumption

1. V

DDA

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Factory calibrated, parts not soldered.

Typ

Figure 19. HSI oscillator accuracy characterization results for soldered parts

MAX

MIN

-40

-1%

-2%

-3%

-4%

-20 0 20 40 60 80 100 120

MS30985V4

Max

(2)

100

Unit

MHz

µs

µA

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Low-speed internal (LSI) RC oscillator

Symbol

Table 44. LSI oscillator characteristics

(1)

Parameter Min f

LSI t su(LSI)

(2)

DD(LSI)

(2)

Frequency 30

LSI oscillator startup time

LSI oscillator power consumption

1. V

DDA

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design.

Typ

0.75

Max

1.2

Unit kHz

µs

µA

The parameters given in

Table 45 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 23

Table 45. PLL characteristics

Value

Symbol f

PLL_IN

Parameter

PLL input clock

(1)

PLL input clock duty cycle

PLL multiplier output clock

PLL lock time

Cycle-to-cycle jitter

Min

(2)

40 (2)

(2)

Typ

Unit f

PLL_OUT t

LOCK

Jitter

Max

(2)

60 (2)

200

(2)

300

(2)

1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

2. Guaranteed by design.

MHz

µs ps

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Electrical characteristics STM32F301x6 STM32F301x8

Flash memory

The characteristics are given at T

= –40 to 105 °C unless otherwise specified.

Symbol

Table 46. Flash memory characteristics

Parameter Conditions t t

I prog

ERASE t

16-bit programming time T

= –40 to +105 °C

Page (2 KB) erase time T

= –40 to +105 °C

Mass erase time T

= –40 to +105 °C

Write mode

Supply current

Erase mode

1. Guaranteed by design.

Min

Typ Max

(1)

53.5

Unit

µs ms ms mA mA

Symbol

Table 47. Flash memory endurance and data retention

Value

Parameter Conditions

Min

(1)

N t

END

RET

Endurance

Data retention

= –40 to +85 °C (6 suffix versions)

= –40 to +105 °C (7 suffix versions)

1 kcycle (2) at T

= 85 °C

1 kcycle

(2)

at T

= 105 °C

10 kcycles (2) at T

= 55 °C

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

Unit kcycles

Years

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Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

and

A device reset allows normal operations to be resumed.

The test results are given in Table 48

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

Table 48. EMS characteristics

Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

= 3.3 V, LQFP64, T

= +25°C, f

HCLK

= 72 MHz conforms to IEC 61000-4-2

= 3.3 V, LQFP64, T

= +25°C, f

HCLK

= 72 MHz conforms to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

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Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 49. EMI characteristics

Symbol Parameter

EMI

Conditions

Monitored frequency band

Peak level

= 3.3 V, T

= 25 °C,

LQFP64 package compliant with IEC

61967-2

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

Max vs. [f

HSE

HCLK

]

8/72 MHz

Unit dBµV

Symbol

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Ratings

Table 50. ESD absolute maximum ratings

Conditions Packages Class

Maximum value (1)

Unit

ESD(HBM)

Electrostatic discharge voltage

(human body model)

= +25 °C, conforming to JESD22-A114

All

ESD(CDM)

Electrostatic discharge voltage

(charge device model)

= +25 °C, conforming to ANSI/ESD STM5.3.1

LQFP64,

WLCSP49

All other

1. Guaranteed by characterization results.

2000

250

500

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Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol

Parameter

Table 51. Electrical sensitivities

Conditions

Static latch-up class T

= +105 °C conforming to JESD78A

Class

2 level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator frequency deviation).

The test results are given in Table 52

Symbol

Table 52. I/O current injection susceptibility

Functional susceptibility

Description

Injected current on BOOT0

Negative injection

-0

Positive injection

(1)

Unit

-0 +5

INJ

Injected current on PC0 pin (TTa pin)

Injected current PC0, PC1, PC2, PC3, PA0, PA1, PA2,

PA3, PA4, PA6, PA7, PC4, PB0, PB10, PB11, PB13 with induced leakage current on other pins from this group less than -100 µA or more than +100 µA

Injected current on any other TT, FT and FTf pins

Injected current on all other TC, TTa and RESET pins

1. Injection is not possible.

-5

(1)

+5 mA

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Electrical characteristics

Note:

STM32F301x6 STM32F301x8

It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

General input/output characteristics

Unless otherwise specified, the parameters given in

Table 53 are derived from tests

performed under the conditions summarized in Table 23

. All I/Os are CMOS and TTL compliant.

Symbol Parameter

Table 53. I/O static characteristics

Conditions Min Typ Max Unit

IH hys

Low level input voltage

High level input voltage

Schmitt trigger hysteresis

TTa and TT I/O

FT and FTf I/O

BOOT0 I/O

All I/Os except BOOT0

TTa and TT I/O

FT and FTf I/O

BOOT0

All I/Os except BOOT0

TC and TTa I/O

FT and FTf I/O

0.445 V

+0.398

(1)

0.5 V

+0.2

(1)

0.2 V

+0.95

(1)

0.7 V

(2)

200

(1)

100 (1)

300

(1)

0.3 V

+ 0.07

(1)

0.475 V

-0.2

(1)

0.3 V

– 0.3

(1)

0.3 V

(2)

V mV

I lkg

Input leakage current

(3)

BOOT0

TC, FT and FTf I/O

TTa I/O in digital mode

≤ V

TTa I/O in digital mode

≤ V

DDA

TTa I/O in analog mode

≤ V

DDA

FT and FTf I/O

(4)

≤ V

≤ 5 V

±0.1

±0.2

µA

Weak pull-up equivalent resistor

(5)

Weak pull-down equivalent resistor

(5)

55 k k

I/O pin capacitance 5 -

1. Data based on design simulation

2. Tested in production.

3. Leakage could be higher than the maximum value. if negative current is injected on adjacent pins. Refer to Table 52: I/O current injection susceptibility

4. To sustain a voltage higher than V

+0.3 V, the internal pull-up/pull-down resistors must be disabled.

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5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimum (~10% order).

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 20 and Figure 21

for standard I/Os.

(V)

IHmin

2.0

1.3

Figure 20. TC and TTa I/O input characteristics - CMOS port

Tested in production

CMOS standard requirements V

IH min = 0.7V

IHmin

= 0.445V

+0.398

Based on design simulations

+0.07

ILmax

= 0.3V

Based on design simulations

Area not determined

CMOS standard requirements V IL max = 0.3V

ILmax

0.7

0.6

Tested in production

(V)

2.0

2.7

3.0

3.3

3.6

MS30255V2

Figure 21. TC and TTa I/O input characteristics - TTL port

(V)

IHmin

2.0

1.3

Area not determined

TTL standard requirements V IH min = 2V

IHmin

= 0.445V

+0.398

Based on design simulations

ILmax

= 0.3V

+0.07

Based on design simulations

ILmax

0.8

0.7

2.0

2.7

TTL standard requirements V IL max = 0.8V

(V)

3.0

3.3

3.6

MS30256V2

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Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port

(V)

2.0

1.0

0.5

2.0

Area not determined

IH min = 0.7V

CMOS standard requirements V

IHmin

= 0.5V

+0.2

Based on design simulations

-0.2

ILmax

= 0.475V

Based on design simulations

CMOS standard requirements V

IL max = 0.3V

(V)

2.7

3.6

MS30257V3

Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port

(V)

2.0

1.0

0.8

0.5

TTL standard requirements V

IH min = 2V

IHmin

= 0.5V

+0.2

Based on design simulations

Area not determined

ILmin

= 0.475V

-0.2

Based on design simulations

TTL standard requirements V

IL max = 0.8V

(V)

2.0

2.7

3.6

MS30258V2

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Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed V

OL/

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

• The sum of the currents sourced by all the I/Os on V

DD, consumption of the MCU sourced on V

DD,

Σ I

VDD

(see Table 21 ).

plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

SS consumption of the MCU sunk on V

Σ I

VSS

(see

Table 21 ).

plus the maximum Run

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in

Table 54 are derived from tests

performed under ambient temperature and V

supply voltage conditions summarized in

Table 23 . All I/Os (FT, TTa and TC unless otherwise specified) are CMOS and TTL

compliant.

Symbol

Table 54. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)

(3)

(1)

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

(2)

= +8 mA

2.7 V < V

< 3.6 V

TTL port (2)

= +8 mA

2.7 V < V

< 3.6 V

–0.4

2.4

0.4

(1)(4)

(3)(4)

(1)(4)

(3)(4)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

= +20 mA

2.7 V < V

2 V < V

< 3.6 V

= +6 mA

< 2.7 V

–1.3

–0.4

1.3

0.4

OLFM+

(1)(4)

Output low level voltage for an FTf I/O pin in

FM+ mode

= +20 mA

2.7 V < V

< 3.6 V

0.4

1. The I

current sunk by the device must always respect the absolute maximum rating specified in Table 21 and the sum of

(I/O ports and control pins) must not exceed Σ I

IO(PIN)

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I of I

current sourced by the device must always respect the absolute maximum rating specified in Table 21 and the sum

(I/O ports and control pins) must not exceed Σ I

IO(PIN)

4. Data based on design simulation.

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Electrical characteristics STM32F301x6 STM32F301x8

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 24

and

Table 55 , respectively.

Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in Table 23

Table 55. I/O AC characteristics (1)

OSPEEDRy [1:0] value

(1)

Symbol Parameter Conditions Min Max Unit x0

01 f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out

Maximum frequency (2)

Output high to low level fall time

Output low to high level rise time

Maximum frequency

(2)

Output high to low level fall time

Output low to high level rise time

= 50 pF, V

= 2 V to 3.6 V

2 (3)

125

(3)

125

(3)

MHz ns

11 f max(IO)out t t f(IO)out r(IO)out

Maximum frequency

(2)

Output high to low level fall time

Output low to high level rise time

= 30 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2 V to 2.7 V

= 30 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2 V to 2.7 V

= 30 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2 V to 2.7 V

MHz

MHz ns

FM+ configuration

(4) f max(IO)out t t t f(IO)out r(IO)out

EXTIpw

Maximum frequency

(2)

Output high to low level fall time

Output low to high level rise time

Pulse width of external signals detected by the

EXTI controller

= 50 pF, V

= 2 V to 3.6 V

-‘

(4)

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0366 reference manual for a description of

GPIO Port configuration register.

2. The maximum frequency is defined in Figure 24 .

3. Guaranteed by design.

4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F301x6 STM32F301x8 reference manual

RM0366 for a description of FM+ I/O mode configuration.

MHz ns ns

(3)

20 (3)

(3)

12 (3)

(4)

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Figure 24. I/O AC characteristics definition

10%

50%

90% 10%

50%

90%

External output on C

L tr(IO)out tf(IO)out

Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by C

(see note 1).

MS34942V1

1. See

Table 55: I/O AC characteristics

6.3.15 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Table 53 ).

Unless otherwise specified, the parameters given in

Table 56 are derived from tests

performed under ambient temperature and V

Table 23 .

supply voltage conditions summarized in

Symbol

Table 56. NRST pin characteristics

Parameter Conditions Min Typ Max

IL(NRST)

(1)

NRST Input low level voltage -

0.3V

0.07

IH(NRST)

(1)

NRST Input high level voltage -

0.445V

0.398

V hys(NRST)

F(NRST)

(1)

NF(NRST)

(1)

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST Input filtered pulse

NRST Input not filtered pulse

= V

500

(1)

200

100

(1)

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution resistance must be minimum (~10% order)

to the series

Unit

V mV k Ω ns ns

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Electrical characteristics STM32F301x6 STM32F301x8

Figure 25. Recommended NRST pin protection

External reset circuit

(1)

0.1 μF

(3)

NRST

(2)

Filter

Internal reset

MS19878V4

1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip.

2. The user must ensure that the level on the NRST pin can go below the V

Table 56 . Otherwise the reset will not be taken into account by the device.

max level specified in

3. The user must place the external capacitor on NRST as close as possible to the chip.

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The parameters given in

Table 57 are guaranteed by design.

Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol Parameter

Table 57. TIMx (1)(2) characteristics

Conditions Min Max Unit t res(TIM) f

EXT

Res

TIM

Timer resolution time

Timer external clock frequency on CH1 to CH4

Timer resolution

TIMxCLK

= 72 MHz f

TIMxCLK

= 144 MHz, x = 1, 15,16, 17

TIMxCLK

= 72 MHz

TIMx (except TIM2)

TIM2

13.9

6.95

COUNTER t

MAX_COUNT

16-bit counter clock period

TIMxCLK

= 72 MHz 0.0139

TIMxCLK

= 144 MHz, x= 1/15/16/17

0.0069

Maximum possible count with 32-bit counter

TIMxCLK

= 72 MHz f

TIMxCLK

= 144 MHz, x= 1/15/16/17

TIMxCLK

65536

910

455

65536 × 65536 t

59.65

29.825

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM15, TIM16 and TIM17 timers.

t t

TIMxCLK ns ns

MHz

MHz bit

TIMxCLK

µs

TIMxCLK s s

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STM32F301x6 STM32F301x8 Electrical characteristics

2. Guaranteed by design.

Table 58. IWDG min/max timeout period at 40 kHz (LSI)

(1)

Prescaler divider PR[2:0] bits

Min timeout (ms) RL[11:0]=

0x000

Max timeout (ms) RL[11:0]=

0xFFF

/16

/32

/64

/128

/256

0.1

0.2

0.4

0.8

1.6

3.2

6.4

409.6

819.2

1638.4

3276.8

6553.6

13107.2

26214.4

1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Prescaler

Table 59. WWDG min-max timeout value @72 MHz (PCLK) (1)

WDGTB Min timeout value Max timeout value

1. Guaranteed by design.

0.05687 3.6409

0.1137 7.2817

0.2275 14.564

0.4551 29.127

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Electrical characteristics STM32F301x6 STM32F301x8

I

C interface characteristics

The I2C interface meets the timings requirements of the I 2 C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s

• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to Reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement. Refer to

Section 6.3.14: I/O port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

Symbol

Table 60. I2C analog filter characteristics

(1)

Parameter t

Maximum pulse width of spikes that are suppressed by the analog filter

1. Guaranteed by design.

2. Spikes with widths below t

AF(min) are filtered.

3. Spikes with widths above t

AF(max)

are not filtered

Min

(2)

Max

260

(3)

Unit ns

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SPI/I

S characteristics

Unless otherwise specified, the parameters given in

Table 61 for SPI or in

Table 62 for I

2 S are derived from tests performed under ambient temperature, f

PCLKx

supply voltage conditions summarized in Table 23

frequency and V

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I 2 S).

Symbol f

SCK

1/t c(SCK) t su(NSS) t h(NSS)

Parameter

Table 61. SPI characteristics (1)

Conditions

SPI clock frequency

NSS setup time

NSS hold time

Master mode

Slave mode

Slave mode, SPI presc = 2

Slave mode, SPI presc = 2 t t w(SCKH) w(SCKL) t t su(MI) su(SI)

SCK high and low time

Data input setup time

Master mode, f

PCLK

MHz, presc = 4

= 36

Master mode

Slave mode t h(MI) t h(SI)

Data input hold time

Master mode

Slave mode t t a(SO) dis(SO)

Data output access time

Data output disable time

Slave mode

Slave mode t v(SO) t v(MO) t h(SO) t h(MO)

Data output valid time

Data output hold time

1. Guaranteed by characterization results.

Slave mode

Master mode

Slave mode

Master mode

Min

Tpclk-

6.5

2.5

4*Tpcl k

2*Tpcl k

Tpclk

Typ

7.5

1.5

Max Unit

MHz

Tpclk+

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Figure 26. SPI timing diagram - slave mode and CPHA = 0

Figure 27. SPI timing diagram - slave mode and CPHA = 1 (1)

NSS input t

SU(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t w(SCKH) t w(SCKL) t a(SO)

MISO

OUTPUT

MOSI

INPUT t su(SI) t v(SO)

MSB OUT t h(SI)

MSB IN t c(SCK) t h(SO)

BIT6 OUT

BIT 1 IN t h(NSS) t r(SCK) t f(SCK) t dis(SO)

LSB OUT

LSB IN

1. Measurement points are done at 0.5V

and with external C

= 30 pF.

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Figure 28. SPI timing diagram - master mode (1)

Electrical characteristics

NSS input

High tc(SCK)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

B I T1 OUT th(MO)

1. Measurement points are done at 0.5V

and with external C

= 30 pF.

Table 62. I2S characteristics

(1) f

Symbol Parameter

MCK

I2S Main clock output f

I2S clock frequency

Master data: 32 bits

Slave data: 32 bits

I2S clock frequency duty cycle

Slave receiver tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136c

256 x 8K 256xFs

(2)

64xFs

30 70

MHz

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115

Electrical characteristics STM32F301x6 STM32F301x8 t h(SD_ST) t h(SD_MT)

Table 62. I2S characteristics (1) (continued) t

Symbol Parameter v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST)

WS valid time

WS hold time

WS setup time

WS hold time

Data input setup time

Data input hold time

Data output valid time t v(SD_MT)

Data output hold time

Master mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

1. Guaranteed by characterization results.

2. 256xFs maximum is 36 MHz (APB1 Maximum frequency)

2.5

1 -

22 ns

Note: Refer to RM0366 Reference Manual I2S Section for more details about the sampling frequency (Fs), fMCK, fCK, DCK values reflect only the digital peripheral behavior, source clock precision might slightly change the values DCK depends mainly on ODD bit value.

Digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max

(I2SDIV+ODD)/(2*I2SDIV+ODD) and Fs max supported for each mode/condition.

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Figure 29. I 2 S slave timing diagram (Philips protocol) (1)

1. Measurement points are done at 0.5V

and with external C

=30 pF.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 30. I

S master timing diagram (Philips protocol)

(1)

1. Measurement points are done at 0.5V

and with external C

=30 pF.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

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115

Symbol

DDA

DDA f

ADC f

(1) f

TRIG

(1)

AIN

(1)

Unless otherwise specified, the parameters given in Table 63

to Table 65

are guaranteed by design, with conditions summarized in

Table 23 .

Table 63. ADC characteristics

Conditions Min Typ Max Unit Parameter

Analog supply voltage for

ADC

2 3.6

ADC current consumption

(see Figure 31

)

ADC clock frequency

Sampling rate

External trigger frequency

Conversion voltage range

External input impedance

Single-ended mode,

5 MSPS

Single-ended mode,

1 MSPS

Single-ended mode,

200 KSPS

Differential mode, 5 MSPS

Differential mode, 1 MSPS

Differential mode,

200 KSPS

Resolution = 12 bits,

Fast Channel

Resolution = 10 bits,

Fast Channel

Resolution = 8 bits,

Fast Channel

Resolution = 6 bits,

Fast Channel

ADC

= 72 MHz

Resolution = 12 bits

0.14

0.01

0.012

0.014

0.0175

1011.3

214.7

54.7

1061.5

246.6

56.4

1172.0

322.3

81.1

1243.6

337.6

83.0

5.14

7.2

5.14

DDA

100

µA

MHz

MSPS

MHz

1/f

ADC

V k Ω

Symbol

ADC

(1) t

CAL

(1) t latr

(1) t latrinj

(1)

Parameter

Internal sample and hold capacitor

Calibration time t

(1)

Sampling time

TADCVREG_STUP

(1)

ADC Voltage Regulator

Start-up time t

STAB

(1)

Power-up time t

CONV

(1)

Trigger conversion latency

Regular and injected channels without conversion abort

Trigger conversion latency

Injected channels aborting a regular conversion

Total conversion time

(including sampling time)

CMIR

(1) Common mode input signal

1. Data guaranteed by design.

Table 63. ADC characteristics (continued)

Conditions Min

ADC

= 72 MHz

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11 f

ADC

= 72 MHz

ADC

= 72 MHz

Resolution = 12 bits

ADC differential mode

2.5

1.5

0.021

1.5

Typ

1.56

112

Max

2.5

2.25

2.125

3.5

3.25

3.125

8.35

601.5

0.19

8.52

14 to 614 (t

for sampling + 12.5 for successive approximation)

SSA

+ V

REF+

)/2

- 0.18

SSA

+ V

REF+

)/2

SSA

+ V

REF+

+ 0.18

)/2

Unit pF

µs

1/f

ADC

1/f

ADC

1/f

ADC

1/f

ADC

1/f

ADC

1/f

ADC

1/f

ADC

1/f

ADC

1/f

ADC

µs

1/f

ADC

µs conversion cycle

µs

1/f

ADC

Electrical characteristics STM32F301x6 STM32F301x8

Figure 31

illustrates the ADC current consumption as per the clock frequency in singleended and differential modes.

Figure 31. ADC typical current consumption in single-ended and differential modes

Resolution

12 bits

Clock frequency (MSPS)

MS34994V1

Sampling cycle @

72 MHz

1.5

2.5

4.5

7.5

19.5

61.5

181.5

601.5

Table 64. Maximum ADC R

AIN

(1)

Sampling time [ns] @

72 MHz

20.83

34.72

62.50

104.17

270.83

854.17

2520.83

8354.17

Fast channels

(2)

0.018

0.150

0.470

0.820

2.70

8.20

22.0

82.0

AIN

max (k Ω )

Slow channels

0.220

0.560

1.80

6.80

18.0

68.0

Other channels

(3)

0.022

0.180

0.470

1.50

4.70

15.0

47.0

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STM32F301x6 STM32F301x8 Electrical characteristics

Resolution

10 bits

8 bits

6 bits

1.5

2.5

4.5

7.5

19.5

61.5

181.5

1.5

2.5

4.5

7.5

19.5

61.5

181.5

601.5

1.5

2.5

4.5

7.5

19.5

61.5

181.5

601.5

1. Guaranteed by characterization results.

2. All fast channels, expect channel on PA6.

3. Channel available on PA6.

Table 64. Maximum ADC R

AIN

(1) (continued)

AIN

max (k Ω )

Sampling cycle @

72 MHz

Sampling time [ns] @

72 MHz

Fast channels

(2)

Slow channels

0.150

0.390

0.820

1.50

3.90

12.00

39.00

0.082

0.270

0.560

1.20

3.30

10.0

33.0

100.0

100.00

0.270

0.560

1.200

2.20

5.60

18.0

56.0

100.00

20.83

34.72

62.50

104.17

270.83

854.17

2520.83

20.83

34.72

62.50

104.17

270.83

854.17

2520.83

8354.17

20.83

34.72

62.50

104.17

270.83

854.17

2520.83

8354.17

0.180

0.560

1.20

3.30

12.00

33.00

0.082

0.390

0.82

2.70

8.2

27.0

82.0

100.00

0.100

0.390

0.820

1.80

4.70

15.0

47.0

100.0

Other channels

(3)

0.039

0.180

0.470

1.00

2.70

8.20

27.00

0.100

0.330

0.68

2.20

6.8

22.0

68.0

82.00

0.150

0.330

0.820

1.50

3.90

12.0

39.0

100.0

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Electrical characteristics STM32F301x6 STM32F301x8

Table 65. ADC accuracy - limited test conditions (1)(2)

Symbol Parameter Conditions

Min

(3)

Typ

Max

(3)

Unit

ENOB

(4)

SINAD

(4)

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Effective number of bits

Signal-tonoise and distortion ratio

ADC clock freq. ≤

Sampling freq. ≤

DDA

= 3.3 V

25°C

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Differential

±4

±1.5

±3

±4.5

±5.5

±6

±3.5

±4

±2

±4

Differential

Single ended

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Single ended

±5 ±5.5

LSB

±3

±3 ±3.5

±1 ±1

±1

±1.5

±2

±3

±1

±2

±3

±1.5 ±1.5

Slow channel 4.8 Ms ±1.5

±2

Fast channel 5.1 Ms 10.8 10.8

Slow channel 4.8 Ms 10.8 10.8

Fast channel 5.1 Ms 11.2 11.3

bit

Slow channel 4.8 Ms 11.2 11.3

Fast channel 5.1 Ms 66 67 -

Single ended

±3.5

±4

±2 ±2

±1.5

±2

±1.5

±2

Slow channel 4.8 Ms 66 67

Fast channel 5.1 Ms 69 70 -

Differential

Slow channel 4.8 Ms 69 70 -

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Table 65. ADC accuracy - limited test conditions (1)(2) (continued)

Symbol Parameter Conditions

Min

(3)

Typ

Max

(3)

Unit

SNR

THD

(4)

Signal-tonoise ratio

Total harmonic distortion

ADC clock freq.

Sampling freq

DDA

≤

72 MHz

5 Msps

= 3.3 V

25°C

Single ended

Fast channel 5.1 Ms 66 67

Slow channel 4.8 Ms 66 67

Fast channel 5.1 Ms 69 70

Differential

Slow channel 4.8 Ms 69 70

Fast channel 5.1 Ms -80

-80

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms -

-78 -77

-83 -82

Differential

Slow channel 4.8 Ms -81 -80 dB

1. ADC DC accuracy values are measured after internal calibration.

2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

Section 6.3.14

does not affect the ADC

3. Guaranteed by characterization results.

4. Value measured with a –0.5dB Full Scale 50kHz sine wave input signal.

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Electrical characteristics STM32F301x6 STM32F301x8

Symbol Parameter

Table 66. ADC accuracy (1)(2)(3)

Conditions Min

(4)

ENOB

(5)

SINAD

(5)

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Effective number of bits

Signal-tonoise and distortion ratio

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Single ended

Slow channel 4.8 Ms

Differential

ADC clock freq. ≤ 72 MHz,

Sampling freq. ≤ 5 Msps

2.0 V ≤ V

DDA

≤ 3.6 V

Single ended

Differential

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Single ended

Differential

10.4

Slow channel 4.8 Ms 10.4

Fast channel 5.1 Ms 10.8

Slow channel 4.8 Ms 10.8

Fast channel 5.1 Ms 64

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms 67

Max

(4)

±2.5

±1.5

±3

±3.5

±2

±4

±1.5

±6.5

±4

±4.5

±3

±2.5

±6

±3.5

Unit

LSB bits dB

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Table 66. ADC accuracy (1)(2)(3) (continued)

Symbol Parameter Conditions Min

(4)

Max

(4)

Unit

SNR

THD

(5)

Signal-tonoise ratio

Total harmonic distortion

Single ended

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

ADC clock freq. ≤ 72 MHz,

Sampling freq ≤ 5 Msps,

2 V ≤ V

DDA

≤ 3.6 V

Differential

Single ended

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Slow channel 4.8 Ms

Fast channel 5.1 Ms

Differential

Slow channel 4.8 Ms

-75

-79

-78

1. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

Section 6.3.14

does not affect the ADC

3. Better performance may be achieved in restricted V

DDA

, frequency and temperature ranges.

4. Guaranteed by characterization results.

5. Value measured with a –0.5dB Full Scale 50kHz sine wave input signal.

Symbol Parameter

Table 67. ADC accuracy (1)(2)

Test conditions Typ Max

(3)

Unit

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Fast channel

Slow channel

ADC Freq ≤ 72 MHz

Sampling Freq ≤ 1MSPS

2.4 V ≤ V

DDA

= V

REF+

≤ 3.6 V

Single-ended mode

Fast channel

Slow channel

Fast channel

Slow channel

Fast channel

Slow channel

Fast channel

Slow channel

±2.5

±3.5

±1

±1.5

±2

±3

±0.7

±1

±1.2

±5

±2.5

±3

±4

±2

±3

LSB

1. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ∑

IINJ(PIN) in Section 6.3.14: I/O port characteristics does not affect the ADC

accuracy.

3. Guaranteed by characterization results.

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Electrical characteristics STM32F301x6 STM32F301x8

Figure 32. ADC accuracy characteristics

1LSB

IDEAL

DDA

4096

4095

4094

4093

SSA

1 L SB

3 4 5 6

IDEAL

(2)

(3)

(1)

4093 4094 4095 4096

DDA

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

=Offset Error: deviation between the first actual transition and the first ideal one.

=Gain Error: deviation between the last ideal transition and the last actual one.

=Differential Linearity Error: maximum deviation between actual steps and the ideal one.

=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

MS34980V1

AIN

AIN (1) AINx

C parasitic

Figure 33. Typical connection diagram using the ADC

0.6 V

± 1 μA

Sample and hold ADC converter

ADC

12-bit converter

ADC

MS19881V3

1. Refer to Table 63 for the values of R

AIN

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 this, f

ADC pF). A high C

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 12

. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

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Symbol Parameter

Table 68. DAC characteristics

Conditions

DDA

Analog supply voltage DAC output buffer ON

LOAD

(1)

Resistive load DAC output buffer ON

Connected to V

SSA

Connected to V

DDA

DAC output buffer ON R

(1)

LOAD

(1)

Output impedance

Capacitive load DAC output buffer ON

Voltage on DAC_OUT output

Corresponds to 12-bit input code (0x0E0) to

(0xF1C) at V

DDA

= 3.6 V and (0x155) and (0xEAB) at V

DDA

DAC output buffer ON.

= 2.4 V

DAC output buffer OFF

Min Typ

2.4

Max

3.6

DDA

1LSB

380

±10

±3

±12

±0.5

LSB

Unit

V k Ω

k Ω pF

0.2 V

DDA

– 0.2

DDA

(3)

DNL

(3)

DAC DC current consumption in quiescent mode

(Standby mode)

(2)

Differential non linearity Difference between two consecutive code-

1LSB)

With no load, middle code (0x800) on the input.

With no load, worst code (0xF1C) on the input.

Given for a 10-bit input code

Given for a 12-bit input code

INL

(3)

Integral non linearity

(difference between measured value at

Code i and the value at Code i on a line drawn between Code

0 and last Code 4095)

Given for a 10-bit input code

Given for a 12-bit input code

Offset

(3)

Offset error (difference between measured value at Code (0x800) and the ideal value =

DDA

/2)

Given for a 10-bit input code at V

DDA

= 3.6 V

Given for a 12-bit input code at V

DDA

= 3.6 V

Gain error

(3)

Gain error Given for a 12-bit input code t

SETTLING

(3)

Settling time (full scale: for a 12-bit input code transition between the lowest and the highest input codes when

DAC_OUT reaches

LOAD

≤

50 pF,

≥

5 k Ω

0.5

480

±0.5

±2

±1

±4

4 mV

µA

LSB

µs

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Electrical characteristics STM32F301x6 STM32F301x8

Symbol Parameter

Table 68. DAC characteristics (continued)

Conditions Min Typ Max

Update

rate

(3)

Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB)

LOAD

≤

50 pF,

≥

5 k Ω t

WAKEUP

(3)

Wakeup time from off state (Setting the ENx bit in the DAC Control register)

LOAD

≤

50 pF,

≥

5 k Ω

PSRR+

(1)

Power supply rejection ratio (to V

DDA

) (static

DC measurement

LOAD

50 pF,

No R

LOAD

≥

5 k Ω,

6.5

–67 –40

1. Guaranteed by design.

2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is involved.

3. Guaranteed by characterization results.

Unit

MS/s

µs dB

Figure 34. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer

(1)

12-bit digital to analog converter

DAC_OUTx

MS39009V1

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

Symbol

DDA

Parameter

Table 69. Comparator characteristics (1)(2)

Conditions Min.

2 Analog supply voltage

Comparator input voltage range

Scaler input voltage

Scaler offset voltage -

Typ.

REFINIT

±5

Max.

3.6

DDA

±10

Unit

V mV

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Symbol

Table 69. Comparator characteristics (1)(2) (continued)

Parameter Conditions Min.

Typ.

t t

S_SC

START

REFINT

scaler startup time from power down

REFINT

scaler activation after device power on

Next activations

Comparator startup time

DDA

≥ 2.7 V

DDA

< 2.7 V

Propagation delay for

200 mV step with 100 mV overdrive

DDA

≥ 2.7 V

DDA

< 2.7 V

28 t

Propagation delay for full range step with 100 mV overdrive

DDA

≥ 2.7 V 32

OFFSET

Comparator offset error

DDA

< 2.7 V

DDA

≥ 2.7 V

DDA

< 2.7 V

Full temperature range

± 5

OFFSET

DD(COMP)

Total offset variation

COMP current consumption

400

1. Guaranteed by design.

2. The comparators do not have built-in hysteresis.

3. For more details and conditions, see Figure 35: Maximum V

REFINT

scaler startup time from power down

± 10

± 25

600

Max.

(3)

0.2

Figure 35. Maximum V

REFINT

scaler startup time from power down

Unit s ms

µs ns mV mV

µA

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Electrical characteristics STM32F301x6 STM32F301x8

Symbol

Table 70. Operational amplifier characteristics (1)

Parameter Condition Min

DDA

CMIR

Δ VI

OFFSET

LOAD

CMRR

PSRR

GBW

LOAD

Analog supply voltage

Common mode input range

Input offset voltage

Maximum calibration range

Input offset voltage drift

Drive current

25°C, No Load on output. t

IDDOPAMP t t

OFFSET

VOH

VOL ϕ

SAT

SAT m

OFFTRIM

WAKEUP

S_OPAM_VOUT

Consumption

After offset calibration

All voltage/Temp.

25°C, No Load on output.

All voltage/Temp.

No load, quiescent mode

Common mode rejection ratio

Power supply rejection ratio

Bandwidth

Slew rate -

Resistive load

Capacitive load

High saturation voltage

Low saturation voltage

(2)

R load

= min, Input at V

DDA

R load

= 20K,

Input at V

DDA

Rload = min, input at 0V

Rload = 20K, input at 0V.

Phase margin

Offset trim time: during calibration, minimum time needed between two steps to have 1 mV accuracy

Wake up time from OFF state.

LOAD

≤

≥

50 pf,

4 k

Follower

Ω, configuration

ADC sampling time when reading the OPAMP output

2.4

DDA

-100

DDA

-20

400

Typ

690

2.8

117

8.2

4.7

1.6

500

1450

Max

3.6

DDA

Unit

V mV

µV/°C

µA

µA dB dB

MHz

V/µs k Ω pF

100

µs ns

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Symbol

PGA gain

Table 70. Operational amplifier characteristics (1) (continued)

Parameter Condition Min Typ

Non inverting gain value -

R network

PGA BW

R2/R1 internal resistance values in PGA mode

(3)

PGA gain error PGA gain error

I bias

OPAMP input bias current

PGA bandwidth for different non inverting gain

Gain=2

Gain=4

Gain=8

Gain=16

PGA Gain = 2,

Cload = 50pF,

Rload = 4 K Ω

PGA Gain = 4,

Cload = 50pF,

Rload = 4 K Ω

PGA Gain = 8,

Cload = 50pF,

Rload = 4 K Ω

PGA Gain = 16,

Cload = 50pF,

Rload = 4 K Ω

@ 1KHz, Output loaded with 4 K Ω

-1%

5.4/5.4

16.2/5.4

37.8/5.4

40.5/2.7

0.5

109

Max

± 0.2

(4)

Unit

k Ω

µA

MHz

V n

Voltage noise density

@ 10KHz, Output loaded with 4 K Ω

43 -

1. Guaranteed by design.

2. The saturation voltage can also be limited by the I

LOAD

(drive current).

3. R2 is the internal resistance between OPAMP output and OPAMP inverting input.

R1 is the internal resistance between OPAMP inverting input and ground.

The PGA gain =1+R2/R1

4. Mostly TTa I/O leakage, when used in analog mode.

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Electrical characteristics STM32F301x6 STM32F301x8

Figure 36. OPAMP Voltage Noise versus Frequency

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6.3.22 Temperature sensor characteristics

Symbol

(1)

Avg_Slope

(1)

25 t

START

(1)

S_temp

(1)(2)

Table 71. TS characteristics

Parameter

SENSE

linearity with temperature

Average slope

Voltage at 25 °C

Startup time

ADC sampling time when reading the temperature

Min

4.0

1.34

2.2

Typ

1. Guaranteed by design.

2. Shortest sampling time can be determined in the application by multiple iterations.

± 1

4.3

1.43

Max

± 2

4.6

1.52

Table 72. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at temperature of 30 °C,

DDA

= 3.3 V

TS ADC raw data acquired at temperature of 110 °C

DDA

= 3.3 V

0x1FFF F7B8 - 0x1FFF F7B9

0x1FFF F7C2 - 0x1FFF F7C3

Unit

°C mV/°C

µs

6.3.23 V

BAT monitoring characteristics

Symbol

Table 73. V

BAT

monitoring characteristics

Parameter Min Typ

(1)

S_vbat

(1)(2)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q

ADC sampling time when reading the V

BAT

1mV accuracy

-1

2.2

1. Guaranteed by design.

2. Shortest sampling time can be determined in the application by multiple iterations.

Max

Unit

K Ω

µs

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Package information STM32F301x6 STM32F301x8

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

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7.1 WLCSP49 package information

Package information

Figure 37. WLCSP49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package outline e1

A1 ball location bbb Z

G e e2 E

Detail A e

Bottom view

Bump side

Front view b

Side view

A1 Orientation reference

Top view

Wafer back side

1. Drawing is not to scale.

Bump eee Z

49x

Note 2

Detail A

(rotated 90 )

Seating plane

Note 1

(4x)

A0XJ_ME_V1

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Table 74. WLCSP49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches

(1)

Symbol millimeters

Min Typ Max Min Typ Max

G aaa e e1 e2

A3 (2) b

(3)

E bbb ccc ddd eee

0.525

0.220

3.382

3.116

0.555

0.175

0.380

0.025

0.250

3.417

3.151

0.400

2.400

0.5085

0.3755

0.585

0.280

3.452

3.186

0.100

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Back side coating

3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

0.0207

0.0087

0.1331

0.1227

0.0200

0.0148

0.0219

0.0069

0.0150

0.0010

0.0098

0.1345

0.1241

0.0157

0.0945

0.0039

0.0020

0.0230

0.0110

0.1359

0.1254

Figure 38. WLCSP49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package recommended footprint

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Dpad

Dsm

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STM32F301x6 STM32F301x8 Package information

Table 75. WLCSP49 recommended PCB design rules (0.4 mm pitch)

Dimension Recommended values

Pitch

Dpad

Dsm

PCB pad design

0.4

260 µm max. (circular)

220 µm recommended

300 µm min. (for 260 µm diameter pad)

Non-solder mask defined via underbump allowed.

WLCSP49 device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 39. WLCSP49 marking example (package top view)

Product identification

(1)

F301C86

Date code

Y WW R

Revision code

MS36423V1

1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

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Package information

7.2 LQFP64 package information

STM32F301x6 STM32F301x8

Figure 40. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

SEATING PLANE

0.25 mm

GAUGE PLANE ccc C

D3 L1

48 33

32 b

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64 17

PIN 1

IDENTIFICATION

1 e

5W_ME_V3

D1 b c

1. Drawing is not to scale.

Table 76. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min

0.050

1.350

0.170

0.090

Typ

1.400

0.220

12.000

10.000

7.500

12.000

10.000

Max

1.600

0.150

1.450

0.270

0.200

Min

0.0020

0.0531

0.0067

0.0035

Typ

0.0551

0.0087

0.4724

0.3937

0.2953

0.4724

0.3937

Max

0.0630

0.0059

0.0571

0.0106

0.0079

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STM32F301x6 STM32F301x8 Package information

Table 76. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

L1 ccc

E3 e

0°

0.450

7.500

0.500

3.5°

0.600

1.000

7°

0.750

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0°

0.0177

Typ

0.2953

0.0197

3.5°

0.0236

0.0394

Max

7°

0.0295

0.0031

Figure 41. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint

0.5

0.3

12.7

10.3

1.2

7.8

12.7

16 ai14909c

1. Dimensions are expressed in millimeters.

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Package information STM32F301x6 STM32F301x8

LQFP64 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 42. LQFP64 marking example (package top view)

Revision code

Product identification

(1)

STM32F301

R8T6

Date code

Y WW

Pin 1 identification

MS36425V1

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7.3 LQFP48 package information

Package information

Figure 43. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

SEATING

PLANE

C ccc C b

0.25 mm

GAUGE PLANE

PIN 1

IDENTIFICATION

1. Drawing is not to scale.

12 e

5B_ME_V2

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Package information STM32F301x6 STM32F301x8

Symbol

Table 77. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max e

E3 k ccc b c

0.050

1.350

0.170

0.090

8.800

6.800

8.800

6.800

0.450

0°

1.400

0.220

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

1.600

0.150

1.450

0.270

0.200

9.200

7.200

9.200

7.200

0.750

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.3465

0.2677

0.0177

0°

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

0.0551

0.0087

0.3543

0.2756

0.3622

0.2835

0.0295

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

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Figure 44. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint

0.50

1.20

0.30

36 25

0.20

7.30

9.70

5.80

7.30

1 12

1.20

5.80

9.70

ai14911d

1. Dimensions are expressed in millimeters.

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Package information STM32F301x6 STM32F301x8

LQFP48 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 45. LQFP48 marking example (package top view)

Product identification

(1)

STM32F

301C6T8

Date code

Y WW

Pin 1 identification

Revision code

MS36427V1

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7.4 UFQFPN32 package information

Package information

Figure 46. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline

D b

D1 e

A ddd C

SEATING

PLANE e

E2 b

E1 E

PIN 1 Identifier

D2 L

A0B8_ME_V2

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

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Table 78. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

E2 e

L ddd b

0.500

0.000

0.180

4.900

3.400

4.900

3.400

0.300

0.550

0.020

0.152

0.230

5.000

3.500

5.000

3.500

0.500

0.400

0.600

0.050

0.280

5.100

3.600

5.100

3.600

0.500

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0000

0.0071

0.1929

0.1339

0.1929

0.1339

0.0118

0.0217

0.0008

0.0060

0.0091

0.1969

0.1378

0.1969

0.1378

0.0197

0.0157

0.2008

0.1417

0.0197

0.0031

0.0236

0.0020

0.0110

0.2008

0.1417

Figure 47. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package recommended footprint

5.30

3.80

32 25

0.60

3.45

5.30

3.80

0.30

3.45

0.50

0.75

3.80

A0B8_FP_V2

1. Dimensions are expressed in millimeters.

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UFQFPN32 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 48. UFQFPN32 marking example (package top view)

Product identification

(1)

F301K8

Date code

Revision code

Pin 1 identifier

MS36429V1

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Package information

7.5 LQFP32 package information

STM32F301x6 STM32F301x8

Figure 49. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline

SEATING

PLANE

C ccc C

0.25 mm

GAUGE PLANE

PIN 1

IDENTIFICATION

1. Drawing is not to scale.

8 e

5V_ME_V2

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Symbol

Table 79. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max e

E3 k ccc b c

0.050

1.350

0.300

0.090

8.800

6.800

8.800

6.800

0.450

0°

1.400

0.370

9.000

7.000

5.600

9.000

7.000

5.600

0.800

0.600

1.000

3.5°

1.600

0.150

1.450

0.450

0.200

9.200

7.200

9.200

7.200

0.750

7°

0.100

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.3465

0.2677

0.0177

0°

0.0020

0.0531

0.0118

0.0035

0.3465

0.2677

0.2205

0.3543

0.2756

0.2205

0.0315

0.0236

0.0394

3.5°

0.0551

0.0146

0.3543

0.2756

0.3622

0.2835

0.0295

7°

0.0039

0.0630

0.0059

0.0571

0.0177

0.0079

0.3622

0.2835

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Package information STM32F301x6 STM32F301x8

Figure 50. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint

0.80

0.30

1.20

0.50

7.30

9.70

6.10

7.30

1 8

1.20

6.10

9.70

5V_FP_V2

1. Drawing is not to scale.

2. Dimensions are expressed in millimeters.

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LQFP32 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 51. LQFP32 marking example (package top view)

Product Identification

(1)

STM32F

301K8T6

Y WW

Revision code

Pin 1 indentifier

MSv47395V1

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Package information STM32F301x6 STM32F301x8

The maximum chip junction temperature (T

Table 23: General operating conditions .

max) must never exceed the values given in

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

max = T

max + (P

max x Θ

)

Where:

• T

max is the maximum ambient temperature in °C,

• Θ

is the package junction-to-ambient thermal resistance, in ° C/W,

• P

max is the sum of P

INT

max and P

I/O max (P

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Symbol

Table 80. Package thermal characteristics

Parameter Value

Thermal resistance junction-ambient

LQFP64 - 10 × 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP48 - 7 × 7 mm

Thermal resistance junction-ambient

WCSP49 - 3.4 x 3.4 mm

Thermal resistance junction-ambient

UFQFN32 - 5 x 5 mm

Thermal resistance junction-ambient

LQFP32 - 7 x 7mm / 0.8 mm pitch

Unit

°C/W

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

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7.6.2 Selecting the product temperature range

Package information

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Section 8: Ordering information .

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F301x6 STM32F301x8 at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature T

Amax

DDmax

= 50 mA, V

= 82 °C (measured according to JESD51-2),

= 3.5 V, maximum 3 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V and maximum 2 I/Os used at the same time in output at low level with I

= 20 mA, V

= 1.3 V

INTmax

= 50 mA × 3.5 V= 175 mW

IOmax

= 3 × 8 mA × 0.4 V + 2 × 20 mA × 1.3 V = 61.6 mW

This gives: P

INTmax

= 175 mW and P

IOmax

= 61.6 mW:

Dmax

= 175 + 61.6 = 236.6 mW

Thus: P

Dmax

= 236.6 mW

Using the values obtained in Table 80

Jmax

is calculated as follows:

– For LQFP64, 45°C/W

Jmax

= 82 °C + (45°C/W × 236.6 mW) = 82°C + 10.65 °C = 92.65°C

This is within the range of the suffix 6 version parts (–40 < T

< 105 °C).

In this case, parts must be ordered at least with the temperature range suffix 6 (see

Section 8: Ordering information

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Package information STM32F301x6 STM32F301x8

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature T

J specified range.

remains within the

Assuming the following application conditions:

Maximum ambient temperature T

Amax

DDmax

= 20 mA, V

= 115 °C (measured according to JESD51-2),

= 3.5 V, maximum 9 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V

INTmax

= 20 mA × 3.5 V= 70 mW

IOmax

= 9 × 8 mA × 0.4 V = 28.8 mW

This gives: P

INTmax

= 70 mW and P

IOmax

= 28.8 mW:

Dmax

= 70 + 28.8 = 98.8 mW

Thus: P

Dmax

= 98.8 mW

Using the values obtained in Table 80

Jmax

is calculated as follows:

– For LQFP100, 45°C/W

Jmax

= 115°C + (45°C/W × 98.8 mW) = 115 °C + 4.44°C = 119.44°C

This is within the range of the suffix 7 version parts (–40 < T

< 125 °C).

In this case, parts must be ordered at least with the temperature range suffix 7 (see

Section 8: Ordering information

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Table 81. Ordering information scheme

Example:

Device family

STM32 = Arm

-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

301 = STM32F301xx, 2.0 to 3.6 V operating voltage

Pin count

K = 32 pins

C = 48 or 49 pins

R = 64 pins

Flash memory size

6 = 32 Kbytes of Flash memory

8 = 64 Kbytes of Flash memory

Package

T = LQFP

Y= WLCSP

U= UFQFPN

Temperature range

6 = Industrial temperature range, –40 to 85 °C

7 = Industrial temperature range, –40 to 105 °C

Options xxx = programmed parts

TR = tape and reel

STM32 F 301 K 8 T 6 xxx

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Revision history STM32F301x6 STM32F301x8

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Date

10-Apr-2014

13-May-2014

02-Dec-2014

09-Feb-2015

Revision

Table 82. Document revision history

Changes

Initial release.

Updated Table 13: STM32F301x6/8 pin definitions .

Added the input voltage on Boot0 pin in

Table 20: Voltage characteristics .

Applied the following changes:

– added “Interconnect matrix” to

Features ,

– added the timers-related information in

Table 2: STM32F301x6/8 device features and peripheral counts ,

– updated the number of comparators for 32-pin package in

Table 2: STM32F301x6/8 device features and peripheral counts

– updated

Figure 1: STM32F301x6/8 block diagram ,

– updated

Section 3.5.1: Power supply schemes

and added

Table 3: External analog supply values for analog peripherals ,

– added a table footnote about touch sensing sensitivity for pins

PA4 and PA6 in Table 13: STM32F301x6/8 pin definitions ,

– renamed USARTx_RTS as USARTx_RTS_DE where x=1, 2 or 3,

– updated I

DD values at 48 MHz (Supply current in Run mode,

executing from RAM/External clock (HSE bypass)) in Table 29:

Typical and maximum current consumption from VDD supply at

VDD = 3.6V

– updated t

WUSTOP

wakeup timings

maximum values in Table 38: Low-power mode

– updated

Figure 19: HSI oscillator accuracy characterization results for soldered parts and Table 43: HSI oscillator characteristics

– updated the supply current in stop mode values for T

Celsius in Table 31: Typical and maximum V

Stop and Standby modes ,

=25 deg.

consumption in

– replaced all occurrences of V

DDA monitoring with V

in Section 6: Electrical characteristics ,

DDA supervisor

– added footnotes to

Figure : UFQFPN32 device marking ,

– updated the marking information (

Figure 39: WLCSP49 marking example (package top view)

Figure 42: LQFP64 marking example (package top view)

Figure 45: LQFP48 marking example (package top view)

Figure 48: UFQFPN32 marking example (package top view)

Updated:

–

Table 41: HSE oscillator characteristics

–

Table 46: Flash memory characteristics

–

Table 69: Comparator characteristics

Added:

–

Figure 35: Maximum V

REFINT down

scaler startup time from power

DS9895 Rev 8

STM32F301x6 STM32F301x8

Date

04-Jun-2015

22-Jul-2016

Revision history

Table 82. Document revision history (continued)

Revision Changes

Updated:

– AF9 value for PA1, PA3 and PA9 in Table 14: Alternate functions for Port A ,

– the structure of

Section 7: Package information

Updated notes on:

– All document tables by removing the “not tested in production” specification.

–

Table 13: STM32F301x6/8 pin definitions .

–

Table 20: Voltage characteristics .

–

Table 69: Comparator characteristics .

–

Figure 4: STM32F301x6/8 UFQFN32 pinout

–

Figure 6: STM32F301x6/8 LQFP48 pinout

–

Figure 7: STM32F301x6/8 LQFP64 pinout

–

Figure 8: STM32F301x6/8 WLCSP49 ballout .

–

Figure 25: Recommended NRST pin protection

–

Figure 46: UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline .

Updated tables:

– Updated V

REFINT

line on

Table 27: Embedded internal reference voltage .

– Updated “Conditions” column on Table 42: LSE oscillator characteristics (f

LSE

= 32.768 kHz) .

– Added CMIR and t

STAB lines on

Table 63: ADC characteristics

– Updated R

LOAD

line on Table 68: DAC characteristics .

– Updated VOH

SAT

and VOL

SAT

lines on Table 70: Operational amplifier characteristics

Updated figures:

–

Figure 2: Clock tree .

–

Figure 8: STM32F301x6/8 WLCSP49 ballout .

–

Figure 22: Five volt tolerant (FT and FTf) I/O input characteristics

- CMOS port .

–

Figure 25: Recommended NRST pin protection

Added:

– Table 39: wakeup time using USART.

Updated name of

Section 8: Ordering information

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140

Revision history

Date

06-Jun-2017

05-Apr-2018

STM32F301x6 STM32F301x8

Table 82. Document revision history (continued)

Revision Changes

– Updated

Section 7.4: UFQFPN32 package information

note 3 removed.

– Updated

Section 7: Package information

adding information about other optional marking or inset/upset marks.

– Updated note 1 below all the package device marking figures.

– Updated

Table 52: I/O current injection susceptibility note by

‘injection is not possible’.

– Removed table ‘Wakeup time using USART’.

– Updated

Figure 25: Recommended NRST pin protection note

about the 0.1uF capacitor.

Updated Arm word and added Arm logo in Section 1: Introduction .

Added LQFP32 package:

– Updated cover.

– Updated Table 2: STM32F301x6/8 device features and peripheral counts .

– Updated

Figure 4: STM32F301x6/8 UFQFN32 pinout

– Added

Figure 5: STM32F301x6/8 LQFP32 pinout .

– Updated

Figure 6: STM32F301x6/8 LQFP48 pinout .

– Updated

Table 13: STM32F301x6/8 pin definitions

and added note on LQFP32 column.

– Updated

Table 23: General operating conditions .

– Added

Section 7.5: LQFP32 package information

– Updated

Table 80: Package thermal characteristics .

140/141

DS9895 Rev 8

STM32F301x6 STM32F301x8

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DS9895 Rev 8 141/141

141

Arm

Cortex

-M4 32-bit MCU+FPU, up to 64 KB Flash,

16 KB SRAM, ADC, DAC, COMP, Op-Amp, 2.0 – 3.6 V

Features

Contents

List of tables

List of figures

1 Introduction

2 Description

3.1 Arm

®

Cortex

®

-M4 core with FPU, embedded Flash and SRAM

3.2 Memories

3.7 Clocks and startup

3.14 Ultra-fast comparators (COMP)

3.15 Timers and watchdogs

TIM2

TIM15, TIM16 and TIM 17

circuit interfaces (I

2

C)

(USART)

3.19 Serial peripheral interfaces (SPI)/inter-integrated sound interfaces (I2S)

3.20 Touch sensing controller (TSC)

4 Pinouts and pin description

6.2 Absolute maximum ratings

Typical and maximum current consumption

Typical current consumption

I/O system current consumption

On-chip peripheral current consumption

High-speed external user clock generated from an external source

Low-speed external user clock generated from an external source

High-speed external clock generated from a crystal/ceramic resonator

Low-speed external clock generated from a crystal/ceramic resonator

High-speed internal (HSI) RC oscillator

Low-speed internal (LSI) RC oscillator

Flash memory

Functional EMS (electromagnetic susceptibility)

Designing hardened software to avoid noise problems

Electromagnetic Interference (EMI)

Electrostatic discharge (ESD)

Static latch-up

Functional susceptibility to I/O current injection

General input/output characteristics

Output driving current

Output voltage levels

Input/output AC characteristics

I

C interface characteristics

SPI/I

S characteristics

General PCB design guidelines

7.1 WLCSP49 package information

WLCSP49 device marking

7.2 LQFP64 package information

LQFP64 device marking

7.3 LQFP48 package information

LQFP48 device marking

7.4 UFQFPN32 package information

UFQFPN32 device marking

7.5 LQFP32 package information

LQFP32 device marking

Example 1: High-performance application

Example 2: High-temperature application

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