STMicroelectronics STM32L100RB-A Datasheet

Figure 10: Current consumption measurement scheme

Reset temporization

POR/PDR

Power on/power down reset threshold

Brown-out reset threshold 0

Brown-out reset threshold 1

Brown-out reset threshold 2

Brown-out reset threshold 3

Brown-out reset threshold 4

Conditions

BOR detector enabled

BOR detector disabled

rising, BOR enabled

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Min Typ Max Unit

∞

1000

3.3

1.3

1.5

1.65

1.5

1.65

1.67

1.7

1.74

1.69

1.76

1.8

1.87

1.93

1.97

1.96

2.03

2.07

2.22

2.30

2.35

2.31

2.41

2.44

2.45

2.55

2.60

2.54

2.66

2.7

2.68

2.8

2.85

2.78

2.9

2.95

µs/V ms

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STM32L100x6/8/B-A Electrical characteristics

Table 15. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6

V hyst

Programmable voltage detector threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Hysteresis voltage

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

BOR0 threshold

All BOR and PVD thresholds excepting BOR0

1.8

1.85

1.88

1.94

1.99

1.98

2.04

2.09

2.08

2.14

2.18

2.20

2.24

2.28

2.34

2.38

2.39

2.44

2.48

2.47

2.54

2.58

2.57

2.64

2.69

2.68

2.74

2.79

2.77

2.83

2.88

2.87

2.94

2.99

2.97

3.05

3.09

3.08

3.15

3.20

40 -

100 -

V mV

1. Guaranteed by characterization results.

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Electrical characteristics STM32L100x6/8/B-A

The parameters given in the following table are based on characterization results, unless otherwise specified.

Table 16. Embedded internal reference voltage calibration values

Calibration value name Description Memory address

VREFINT_CAL

Raw data acquired at temperature of 30 °C ±5 °C,

DDA

= 3 V ±10 mV

0x1FF8 0078-0x1FF8 0079

Symbol

REFINT out

(1)

REFINT

VREFINT

VREF_MEAS

Table 17. Embedded internal reference voltage

Parameter

Internal reference voltage

Internal reference current consumption

Internal reference startup time

DDA

voltage during V

REFINT

factory measure

Conditions

– 40 °C < T

Min Typ Max

< +85 °C 1.202 1.224 1.242

2.99

1.4

2.3

3.01

VREF_MEAS

Coeff

(3)

Coeff

(3)

DDCoeff

(3)(4)

Accuracy of factory-measured V value

(2)

Temperature coefficient

Long-term stability

Voltage coefficient

REF

Including uncertainties due to ADC and V

DDA values

–40 °C < T

< +85 °C

1000 hours, T= 25 °C

3.0 V < V

DDA

< 3.6 V -

±5

100

1000

2000

S_vrefint

(3)

ADC_BUF

(3)

ADC sampling time when reading the internal reference voltage

Startup time of reference voltage buffer for ADC

BUF_ADC

(3)

VREF_OUT

(3)

VREF_OUT

(3)

Consumption of reference voltage buffer for ADC

VREF_OUT output current

VREF_OUT output load

(5)

13.5

LPBUF

(3)

Consumption of reference voltage buffer for VREF_OUT and COMP

730

REFINT_DIV1

(3)

REFINT_DIV2

(3)

REFINT_DIV3

(3)

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage -

1. Guaranteed by test in production.

2. The internal V

REF

value is individually measured in production and stored in dedicated EEPROM bytes.

3. Guaranteed by characterization results.

4. Shortest sampling time can be determined in the application by multiple interactions.

5. To guarantee less than 1% VREF_OUT deviation.

1200

Unit

µA ms

V mV ppm/°C ppm ppm/V

µs

µA

µA pF nA

% V

REFINT

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STM32L100x6/8/B-A

6.3.4 Supply current characteristics

Electrical characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code, unless otherwise specified.

The current consumption values are derived from the tests performed under ambient temperature T

=25°C and V

supply voltage conditions summarized in Table 14: General operating conditions

, unless otherwise specified.

The MCU is placed under the following conditions:

• All I/O pins are configured in analog input mode.

• All peripherals are disabled except when explicitly mentioned.

• The Flash memory access time, 64-bit access and prefetch is adjusted depending on f

HCLK

frequency and voltage range to provide the best CPU performance.

• When the peripherals are enabled f

APB1

= f

APB2

= f

AHB

• When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or

HSE = 16 MHz (if HSE bypass mode is used).

• The HSE user clock applied to OSC_IN input follows the characteristics specified in

Table 27: High-speed external user clock characteristics .

• For maximum current consumption V

= V

DDA

= 3.6 V is applied to all supply pins.

• For typical current consumption V

DD specified otherwise.

= V

DDA

= 3.0 V is applied to all supply pins if not

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Electrical characteristics STM32L100x6/8/B-A

Table 18. Current consumption in Run mode, code with data processing running from Flash

Symbol Parameter Conditions f

HCLK

Typ Max

(1)

Unit

DD (Run from Flash)

Supply current in

Run mode, code executed from Flash

HSI clock source (16

MHz)

Range 3, V

CORE

VOS[1:0] = 11

=1.2 V f

HSE

= f

HCLK f

HSE

= f

HCLK

16 MHz

(PLL ON) (2) up to 16 MHz, included

/2 above

Range 2, V

CORE

VOS[1:0] = 10

=1.5 V

Range 1, V

CORE

VOS[1:0] = 01

=1.8 V

Range 2, V

CORE

VOS[1:0] = 10

=1.5 V

Range 1, V

CORE

VOS[1:0] = 01

=1.8 V

1 MHz

2 MHz

215

400

4 MHz 725

4 MHz 0.915

8 MHz 1.75

16 MHz

8 MHz

3.4

2.1

16 MHz 4.2

32 MHz 8.25

16 MHz

32 MHz

3.5

8.2

285

490

1000

1.3

2.15

2.9

5.2

9.6

4.4

10.2

µA mA

MSI clock, 65 kHz

MSI clock, 524 kHz

MSI clock, 4.2 MHz

Range 3, V

CORE

VOS[1:0] = 11

=1.2 V

65 kHz 0.041

0.085

524 kHz 0.125

0.180

4.2 MHz 0.775

0.935

1. Guaranteed by characterization results, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

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STM32L100x6/8/B-A Electrical characteristics

Table 19. Current consumption in Run mode, code with data processing running from RAM

Symbol Parameter Conditions f

HCLK

Typ Max

(1)

Unit

Range 3,

CORE

=1.2 V

VOS[1:0] = 11 f

HSE

= f

HCLK up to 16 MHz, f included

HSE

= f

HCLK

/2 above

16 MHz

(PLL ON)

(2)

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

DD (Run from RAM)

Supply current in

Run mode, code executed from

RAM, Flash switched off

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

HSI clock source

(16 MHz)

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

MSI clock, 65 kHz

MSI clock, 524 kHz

Range 3,

CORE

=1.2 V

VOS[1:0] = 11

MSI clock, 4.2 MHz

1. Guaranteed by characterization results, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

1 MHz

2 MHz

4 MHz

8 MHz

16 MHz

8 MHz

16 MHz

32 MHz

16 MHz

32 MHz

65 kHz

524 kHz

4.2 MHz

185

345

645

0.755

1.5

3.0

1.8

3.6

7.15

2.95

7.15

110

690

2.2

3.6

2.9

4.3

8.5

255

435

930

1.5

3.7

8.7

115

205

870

µA mA

µA

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Electrical characteristics STM32L100x6/8/B-A

Symbol Parameter

Table 20. Current consumption in Sleep mode

Conditions f

HCLK

Typ Max

(1)

Supply current in

Sleep mode,

Flash OFF

Range 3,

CORE

=1.2 V

VOS[1:0] = 11 f

HSE

= f

HCLK

up to

16 MHz included, f

HSE

= f

HCLK

/2 above 16 MHz (PLL

ON)

(2)

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

HSI clock source

(16 MHz)

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

1 MHz 50 155

2 MHz 78.5

235

4 MHz 140 370

(3)

4 MHz 165

8 MHz 310

375

530

16 MHz 590 1000

8 MHz 350 615

16 MHz 680 1200

32 MHz 1600 2350

16 MHz 640 970

32 MHz 1600 2350

(Sleep)

Supply current in

Sleep mode,

Flash ON

MSI clock, 65 kHz

MSI clock, 524 kHz

MSI clock, 4.2 MHz

HSI clock source

(16 MHz)

Range 3,

CORE

=1.2 V

VOS[1:0] = 11

Range 3,

CORE

=1.2 V

VOS[1:0] = 11 f

HSE

= f

HCLK

up to

16 MHz included, f

HSE

= f

HCLK

/2 above 16 MHz (PLL

ON)

(2)

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

65 kHz 19

524 kHz 33

4.2 MHz 145

1 MHz 60.5

2 MHz 89.5

4 MHz 150

4 MHz 180

8 MHz 320

16 MHz 605

8 MHz 380

895

565

16 MHz 695 1070

32 MHz 1600 2200

225

360

370

490

210

145

16 MHz 650 970

32 MHz 1600 2320

MSI clock, 65 kHz

MSI clock, 524 kHz

MSI clock, 4.2 MHz

Range 3,

CORE

=1.2V

VOS[1:0] = 11

65 kHz 29.5

524 kHz 44

4.2 MHz 155

220

1. Guaranteed by characterization results, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)

3. Guaranteed by test in production.

Unit

µA

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STM32L100x6/8/B-A Electrical characteristics

Symbol Parameter

Table 21. Current consumption in Low power run mode

Conditions Typ Max

(1)

DD (LP

Run)

Supply current in

Low power run mode

All peripherals

OFF, code executed from RAM,

Flash switched

OFF, V

DD from 1.8 V to 3.6 V

All peripherals

OFF, code executed from Flash,

from

1.8 V to

3.6 V

MSI clock, 65 kHz f

HCLK f

HCLK

= 32 kHz

MSI clock, 65 kHz

= 65 kHz

MSI clock, 131 kHz

= 131 kHz

MSI clock, 65 kHz

= 32 kHz

MSI clock, 65 kHz

= 65 kHz

MSI clock, 131 kHz

= 131 kHz

= -40 °C to 25 °C

= 85 °C

= -40 °C to 25 °C

= 85 °C

= -40 °C to 25 °C

= 55 °C

= 85 °C

= -40 °C to 25 °C

= 85 °C

= -40 °C to 25 °C

= 85 °C

= -40 °C to 25 °C

= 55 °C

= 85 °C

10.9

16.5

32.5

35.5

53.5

Max

(LP

Run)

(2)

Max allowed current in

Low power run mode

from

1.8 V to

3.6 V

200

1. Guaranteed by characterization results, unless otherwise specified.

2. This limitation is related to the consumption of the CPU core and the peripherals that are powered by the regulator.

Consumption of the I/Os is not included in this limitation.

Unit

µA

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Electrical characteristics STM32L100x6/8/B-A

Table 22. Current consumption in Low power sleep mode

Symbol Parameter Conditions Typ Max (1) Unit

(LP

Sleep)

Supply current in

Low power sleep mode

MSI clock, 65 kHz f

HCLK

= 32 kHz

Flash OFF

All peripherals

OFF, V

DD from 1.8 V to 3.6 V f

MSI clock, 65 kHz

HCLK

= 32 kHz

Flash ON

MSI clock, 65 kHz f

HCLK

= 65 kHz,

Flash ON

TIM9 and

USART1 enabled,

Flash ON,

from

1.8 V to

3.6 V f f

MSI clock,

131 kHz

HCLK

= 131 kHz,

Flash ON

MSI clock, 65 kHz f

HCLK

= 32 kHz

MSI clock, 65 kHz f

HCLK

= 65 kHz

MSI clock,

131 kHz

HCLK

= 131 kHz

= -40 °C to 25 °C 5.5

= -40 °C to 25 °C

= 85 °C

= -40 °C to 25 °C

Max

(LP

Sleep)

Max allowed current in

Low power

Sleep mode

from

1.8 V to

3.6 V

1. Guaranteed by characterization results, unless otherwise specified.

= 85 °C 20.5

= -40 °C to 25 °C 18

= 55 °C 21

= 85 °C

= -40 °C to 25 °C 15

= 85 °C 20.5

= -40 °C to 25 °C 18

= 55 °C

= 85 °C

200

µA

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STM32L100x6/8/B-A Electrical characteristics

Symbol

Table 23. Typical and maximum current consumptions in Stop mode

Parameter Conditions Typ

(1)

Max

(1)(2)

DD (Stop with RTC)

DD (Stop)

DD (WU from Stop)

Supply current in

Stop mode with

RTC enabled

RTC clocked by LSI, regulator in LP mode, HSI and HSE OFF

(no independent watchdog)

RTC clocked by LSE external clock (32.768 kHz), regulator in LP mode, HSI and HSE OFF

(no independent watchdog)

RTC clocked by LSE (no independent watchdog)

(5)

LCD OFF

LCD ON

(static duty)

(3)

LCD ON

(1/8 duty)

(4)

LCD OFF

LCD ON

(static duty)

(3)

LCD ON

(1/8 duty)

(1)

LCD OFF

= -40°C to 25°C

= 1.8 V

= -40°C to 25°C

= 55°C

= 85°C

= -40°C to 25°C

= 55°C

= 85°C

= -40°C to 25°C

= 55°C

= 85°C

= -40°C to 25°C

= 55°C

= 85°C

= -40°C to 25°C

= 55°C

= 85°C

= -40°C to 25°C

= 55°C

= 85°C

= -40°C to 25°C

= 1.8 V

= -40°C to 25°C

= 3.0 V

= -40°C to 25°C

= 3.6 V

Regulator in LP mode, HSI and HSE

OFF, independent watchdog and LSI enabled

Supply current in

Stop mode (

RTC disabled)

Regulator in LP mode, LSI, HSI and

HSE OFF (no independent watchdog)

= -40°C to 25°C

= 55°C

= 85°C

RMS (root mean square) supply current during wakeup time when exiting from Stop mode

MSI = 4.2 MHz

MSI = 1.05 MHz

MSI = 65 kHz

(6)

= 3.0 V

= -40°C to 25°C

1.50

1.75

1.80

0.434

0.735

2.350

1.45

2.2

Unit

µA mA

1.13

3.65

1.60

2.05

3.75

3.90

4.55

6.35

1.38

1.70

3.30

1.50

1.80

3.45

3.80

4.30

6.10

1.50

1.90

1.23

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Electrical characteristics STM32L100x6/8/B-A

1. The typical values are given for V

= 3.0 V and max values are given for V

= 3.6 V, unless otherwise specified.

2. Guaranteed by characterization results, unless otherwise specified.

3. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected.

4. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.

5. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF loading capacitors.

6. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the remaining time of the wakeup period, the current is similar to the Run mode current.

Symbol

Table 24. Typical and maximum current consumptions in Standby mode

Parameter Conditions Typ

(1)

Max

(1)(2)

Unit

(Standby with RTC)

Supply current in Standby mode with RTC enabled

RTC clocked by LSI (no independent watchdog)

RTC clocked by LSE (no independent watchdog)

(3)

= -40 °C to 25 °C

= 1.8 V

= -40 °C to 25 °C

= 55 °C

= 85 °C

= -40 °C to 25 °C

= 1.8 V

= -40 °C to 25 °C

= 55 °C

= 85 °C

0.865

1.11

1.15

1.35

0.97

1.28

1.4

1.7

1.9

2.2

µA

Independent watchdog and LSI enabled

= -40 °C to 25 °C 1.0

1.7

(Standby)

Supply current in Standby mode with RTC disabled

Independent watchdog and LSI OFF

= -40 °C to 25 °C 0.277

0.6

= 55 °C

= 85 °C

0.31

0.52

0.9

2.75

DD (WU from

Standby)

RMS supply current during wakeup time when exiting from Standby mode

= 3.0 V

= -40 °C to 25 °C

1 -

1. The typical values are given for V

= 3.0 V and max values are given for V

= 3.6 V, unless otherwise specified.

2. Guaranteed by characterization results, unless otherwise specified.

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF loading capacitors.

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STM32L100x6/8/B-A Electrical characteristics

APB1 USART2

USART3

I2C1

I2C2

USB

PWR

DAC

COMP

TIM2

TIM3

TIM4

TIM6

TIM7

LCD

WWDG

SPI2

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions:

• all I/O pins are in input mode with a static value at V

or V

(no load)

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

Peripheral

Table 25. Peripheral current consumption

(1)

Typical consumption, V

= 3.0 V, T

= 25 °C

Range 1,

CORE

1.8 V

VOS[1:0] = 01

8.1

7.9

7.8

7.2

12.7

3.1

6.6

5.3

11.3

11.4

11.3

3.9

4.2

4.7

3.7

5.9

Range 2,

CORE

1.5 V

VOS[1:0] = 10

6.6

6.4

6.1

5.7

10.3

2.4

5.3

4.3

9.0

9.1

9.0

3.1

3.3

3.6

2.9

4.8

Range 3,

CORE

1.2 V

VOS[1:0] = 11

Low-power sleep and run

5.1

5.0

4.9

4.6

8.1

2.0

4.3

3.4

7.3

7.1

7.3

2.5

2.6

2.9

2.4

3.9

6.6

6.4

6.1

5.7

10.3

2.4

5.3

4.3

9.0

9.1

9.0

3.1

3.3

3.6

2.9

4.8

Unit

µA/MHz

HCLK

)

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Electrical characteristics STM32L100x6/8/B-A

Table 25. Peripheral current consumption (1) (continued)

Typical consumption, V

= 3.0 V, T

= 25 °C

Peripheral

Range 1,

CORE

1.8 V

VOS[1:0] = 01

Range 2,

CORE

1.5 V

VOS[1:0] = 10

Range 3,

CORE

1.2 V

VOS[1:0] = 11

Low-power sleep and run

Unit

APB2

SYSCFG & RI

TIM9

TIM10

TIM11

ADC

(2)

SPI1

USART1

GPIOA

GPIOB

GPIOC

GPIOD

GPIOH

CRC

FLASH

2.2

9.1

6.0

5.8

8.7

4.4

8.1

4.4

1.9

7.3

4.9

4.6

7.0

3.4

6.5

3.5

1.6

5.9

3.9

3.8

5.6

2.8

5.2

2.9

1.9

7.3

4.9

4.6

7.0

3.4

6.5

3.5

AHB

DMA1

All enabled

DD (RTC)

DD (LCD)

DD (ADC)

(4)

DD (DAC)

(5)

DD (COMP1)

Slow mode

DD (COMP2)

DD (PVD / BOR)

(6)

DD (IWDG)

Fast mode

3.7

3.6

3.7

0.6

12.2

12.4

160

3.0

2.8

2.9

0.4

10.2

10.1

135

0.4

3.1

1450

340

0.16

2.6

0.25

2.5

2.4

0.4

7.8

8.2

103

3.0

2.8

2.9

0.4

(3)

10.1

124.8

µA/MHz

HCLK

µA

)

1. Data based on differential I following conditions: f power run/sleep), f

HCLK

measurement between all peripherals OFF an one peripheral with clock enabled, in the

= 32 MHz (Range 1), f

= f

HCLK

, f

APB2

= f

HCLK

= 16 MHz (Range 2), f

HCLK

= 4 MHz (Range 3), f

HCLK

= 64kHz (Low-

, default prescaler value for each peripheral. The CPU is in Sleep mode in

2. HSI oscillator is OFF for this measure.

3. In low-power sleep and run mode, the Flash memory must always be in power-down mode.

4. Data based on a differential I DD measurement between ADC in reset configuration and continuous ADC conversion (HSI consumption not included).

5. Data based on a differential I

DD measurement between DAC in reset configuration and continuous DAC conversion of

/2. DAC is in buffered mode, output is left floating.

6. Including supply current of internal reference voltage.

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STM32L100x6/8/B-A Electrical characteristics

The wakeup times given in the following table are measured with the MSI RC oscillator. The clock source used to wake up the device depends on the current operating mode:

• Sleep mode: the clock source is the clock that was set before entering Sleep mode

• Stop mode: the clock source is the MSI oscillator in the range configured before entering Stop mode

• Standby mode: the clock source is the MSI oscillator running at 2.1 MHz

All timings are derived from tests performed under ambient temperature and V

DD voltage conditions summarized in

external clock signal has to respect the I/O characteristics in Section 6.3.13

supply

Symbol

Table 26. Low-power mode wakeup timings

Parameter Conditions Typ Max (1) Unit t

WUSLEEP

WUSLEEP_LP t t t

WUSTOP

WUSTDBY

Wakeup from Sleep mode f

HCLK

= 32 MHz

Wakeup from Low-power sleep mode f

HCLK

= 262 kHz f f

HCLK

= 262 kHz

Flash enabled

HCLK

= 262 kHz

Flash switched OFF

Wakeup from Stop mode, regulator in Run mode f

HCLK

= f

MSI

= 4.2 MHz

Wakeup from Stop mode, regulator in low-power mode f

HCLK

= f

MSI

= 4.2 MHz

Voltage Ranges 1 and 2 f

HCLK

= f

MSI

= 4.2 MHz

Voltage Range 3

0.4

8.2

7.7

8.2

8.9

13.1

f f f

HCLK

= f

MSI

= 2.1 MHz 10.2

13.4

HCLK

= f

MSI

= 1.05 MHz

= 524 kHz

57 66 f

HCLK

= f

MSI

= 262 kHz f

HCLK

= f

MSI

= 131 kHz f

HCLK

= MSI = 65 kHz

112

221

123

236

Wakeup from Standby mode

FWU bit = 1

Wakeup from Standby mode

FWU bit = 0 f f

HCLK

= MSI = 2.1 MHz

2.6

104

3.25

µs ms

1. Guaranteed by characterization results, unless otherwise specified

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Electrical characteristics STM32L100x6/8/B-A

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The

. However, the

Symbol f

HSE_ext

Table 27. High-speed external user clock characteristics (1)

Parameter Conditions Min Typ Max

User external clock source frequency

CSS is on or

PLL is used

CSS is off, PLL not used

8 32

HSEH

HSEL t w(HSEH) t w(HSEL) t r(HSE) t f(HSE)

C in(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

OSC_IN input capacitance

1. Guaranteed by design.

0.7V

2.6

0.3V

Unit

MHz ns pF

Figure 11. High-speed external clock source AC timing diagram

WZ+6(+

9+6(+

9+6(/

WU+6(

7+6(

WI+6( WZ+6(/

069

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STM32L100x6/8/B-A Electrical characteristics

Low-speed external user clock generated from an external source

The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions summarized in

characterization results obtained with typical external components specified in Table 29

Symbol

Table 28. Low-speed external user clock characteristics (1)

Parameter f

LSE_ext

LSEH

LSEL t w(LSEH) t w(LSEL) t r(LSE) t f(LSE)

IN(LSE)

User external clock source frequency

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

OSC32_IN input capacitance

1. Guaranteed by design.

Min

0.7V

465

Typ

32.768

0.6

Max

1000

0.3V

Unit kHz

ns pF

Figure 12. Low-speed external clock source AC timing diagram

WZ/6(+

9/6(+

9/6(/

WU/6(

7/6(

WI/6(

WZ/6(/

069

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 29. HSE oscillator characteristics (1)(2)

Parameter f

OSC_IN

Oscillator frequency

Feedback resistor

Conditions

Min Typ

200

Max

Unit

MHz k Ω

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Electrical characteristics STM32L100x6/8/B-A t

Symbol

HSE

Table 29. HSE oscillator characteristics (1)(2) (continued)

Parameter Conditions Min Typ Max

Recommended load capacitance versus equivalent serial resistance of the crystal (R

)

(3)

= 30 Ω 20 -

HSE driving current

DD(HSE)

HSE oscillator power consumption

= 3.3 V, V

= V

SS with 30 pF load

C = 20 pF f

OSC

= 16 MHz

C = 10 pF f

OSC

= 16 MHz

2.5 (startup)

0.7 (stabilized)

2.5 (startup)

0.46 (stabilized) g m

Oscillator transconductance Startup 3.5

Startup time V

is stabilized 1 -

Unit

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by characterization results.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

pF mA mA mA

/V ms

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 13

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

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STM32L100x6/8/B-A Electrical characteristics

Figure 13. HSE oscillator circuit diagram

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WRFRUH

5HVRQDWRU

26&B,1

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FRQWURO

5HVRQDWRU

670

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Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 14

Symbol

Table 30. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions Min Typ Max Unit f

LSE

Low speed external oscillator frequency

32.768

kHz

Feedback resistor 1.2

M Ω

(2)

Recommended load capacitance versus equivalent serial resistance of the crystal (R

)

(3)

LSE driving current

= 30 k Ω 8 pF

LSE

DD (LSE)

LSE oscillator current consumption

= 3.3 V, V

= V

= 1.8 V

= 3.0 V

= 3.6V

450

600

750

1.1

µA nA g m t

SU(LSE)

(4)

Oscillator transconductance

Startup time V

is stabilized

1 -

µA/V

1. Guaranteed by characterization results.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”.

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R

value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details.

4. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

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Electrical characteristics STM32L100x6/8/B-A

Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to

15 pF range selected to match the requirements of the crystal or resonator (see

Figure 14

CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.

Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF.

Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load capacitance of 12.5 pF.

Example: if the user chooses a resonator with a load capacitance of CL = 6 pF and

Cstray = 2 pF, then CL1 = CL2 = 8 pF.

Figure 14. Typical application with a 32.768 kHz crystal

5HVRQDWRUZLWK

LQWHJUDWHGFDSDFLWRUV

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UHVRQDWRU

26&B,1

)

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26&B287

/6(

670/[[

DLE

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STM32L100x6/8/B-A

6.3.7 Internal clock source characteristics

Electrical characteristics

The parameters given in the following table are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

High-speed internal (HSI) RC oscillator

Symbol

Table 31. HSI oscillator characteristics

Parameter Conditions Min Typ Max Unit f

HSI

TRIM

(1)(2)

ACC

HSI

(2)

Frequency

HSI user-trimmed resolution

= 3.0 V

Trimming code is not a multiple of 16

Trimming code is a multiple of 16

DDA

= 1.8 V to 3.6 V

= -40 to 85 °C

-10

± 0.4

0.7

MHz

± 1.5

+10 %

I t

SU(HSI)

(2)

DD(HSI)

(2)

HSI oscillator startup time

HSI oscillator power consumption

3.7

100

140

1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).

2. Guaranteed by characterization results.

µs

µA

Low-speed internal (LSI) RC oscillator

Table 32. LSI oscillator characteristics

Symbol Parameter Min Typ f

LSI

(1)

LSI frequency 26 38

LSI

(2)

LSI oscillator frequency drift

0°C ≤

85°C

LSI oscillator startup time

-10 t su(LSI)

(3)

DD(LSI)

(3)

LSI oscillator power consumption -

400

1. Guaranteed by test in production.

2. This is a deviation for an individual part, once the initial frequency has been measured.

3. Guaranteed by design.

Max

200

510

Unit kHz

µs nA

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Electrical characteristics STM32L100x6/8/B-A

Multi-speed internal (MSI) RC oscillator

Symbol f

MSI

Table 33. MSI oscillator characteristics

Parameter Condition

Frequency after factory calibration, done at

= 3.3 V and T

= 25 °C

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6

ACC

MSI

TEMP(MSI)

(1)

VOLT(MSI)

(1)

Frequency error after factory calibration

MSI oscillator frequency drift

0 °C ≤ T

≤

MSI oscillator frequency drift

1.8 V ≤ V

≤ 3.6 V, T

= 25 °C

DD(MSI)

(2) t

SU(MSI)

MSI oscillator power consumption

MSI oscillator startup time

± 10

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6,

Voltage range 1 and 2

MSI range 6,

Voltage range 3

0.75

1.5

2.5

4.5

3.5

65.5

131

262

524

1.05

2.1

4.2

± 0.5

Typ Max Unit

kHz

MHz

2.5

%/V

µA

µs

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STM32L100x6/8/B-A Electrical characteristics

Symbol

Table 33. MSI oscillator characteristics (continued)

Parameter Condition t

STAB(MSI)

Table 34 are derived from tests performed under ambient

OVER(MSI)

MSI oscillator stabilization time

MSI oscillator frequency overshoot

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6,

Voltage range 1 and 2

MSI range 3,

Voltage Range 3

Any range to range 5

Any range to range 6

1. This is a deviation for an individual part, once the initial frequency has been measured.

2. Guaranteed by characterization results.

Typ Max Unit

2.5

µs

MHz

The parameters given in

temperature and V

supply voltage conditions summarized in

Unless otherwise specified, the parameters given in Table 43

Table 34. PLL characteristics

Value

Symbol Parameter Unit

Min Typ Max

(1) f

PLL_IN

PLL input clock (2)

PLL input clock duty cycle

45 -

MHz

% t f

PLL_OUT

LOCK

PLL output clock

PLL lock time

PLL input = 16 MHz

PLL VCO = 96 MHz

115

160

MHz

µs

Jitter Cycle-to-cycle jitter ± 600 ps

DDA

(PLL)

Current consumption on V

DDA

Current consumption on V

220

120

450

150

µA

1. Guaranteed by characterization results.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

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Electrical characteristics STM32L100x6/8/B-A

The characteristics are given at T

= -40 to 85 °C unless otherwise specified.

RAM memory

Symbol

Table 35. RAM and hardware registers

Parameter Conditions Min Typ Max Unit

Data retention mode

(1)

STOP mode (or RESET) 1.8

V VRM

1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode).

Flash memory and data EEPROM

Symbol

Table 36. Flash memory and data EEPROM characteristics

Parameter Conditions t

DD prog

Operating voltage

Read / Write / Erase

Programming / erasing time for byte / word / double word / halfpage

Erasing

Programming

Average current during whole program/erase operation

Maximum current (peak) during program/erase operation

= 25 °C, V

= 3.6 V

1. Guaranteed by design.

Min

1.8

Typ Max

(1)

3.28

300

1.5

3.6

3.94

2.5

Unit

V ms

µA mA

Symbol

Table 37. Flash memory, data EEPROM endurance and data retention

Value

Parameter Conditions

Min

(1)

Typ Max

CYC

(2)

Cycling (erase / write)

Program memory

Cycling (erase / write)

EEPROM data memory

= -40°C to

85 °C t

RET

(2)

Data retention (program memory) after

1 kcycle at T

= 85 °C

Data retention (EEPROM data memory) after 100 kcycles at T

= 85 °C

RET

1. Guaranteed by characterization results.

2. Characterization is done according to JEDEC JESD22-A117.

= +85 °C

100

10 -

Unit kcycles years

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STM32L100x6/8/B-A Electrical characteristics

Susceptibility tests are performed on a sample basis during the device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

SS compliant with the IEC 61000-4-4 standard.

and

through a 100 pF capacitor, until a functional disturbance occurs. This test is

A device reset allows normal operations to be resumed.

The test results are given in

Table 38

. They are based on the EMS levels and classes defined in application note AN1709.

Table 38. EMS characteristics

Symbol

FESD

EFTB

Parameter Conditions

Level/

Class

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

SS f

= 3.3 V, LQFP100, T

= +25 °C,

HCLK

= 32 MHz conforms to IEC 61000-4-2

= 3.3 V, LQFP100, T

= +25 °C, f

HCLK

= 32 MHz conforms to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second.

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Electrical characteristics STM32L100x6/8/B-A

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

EMI

Symbol Parameter

Table 39. EMI characteristics

Max vs. frequency range

Conditions

Peak level

= 3.3 V,

= 25 °C,

LQFP100 package compliant with IEC

61967-2

Monitored frequency band

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

4 MHz voltage

Range 3

-16

-12

-11

16 MHz voltage

Range 2

-7

1.5

32 MHz voltage

Range 1

-3

Unit dBµV

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114, ANSI/ESD STM5.3.1 standard.

Symbol Ratings

Table 40. ESD absolute maximum ratings

Conditions Packages Class

Maximum value (1)

Unit

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage

(human body model)

= +25 °C, conforming to

JESD22-A114

Electrostatic discharge voltage

(charge device model)

= +25 °C, conforming to

ANSI/ESD STM5.3.1

1. Guaranteed by characterization results.

All

2000

500

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STM32L100x6/8/B-A Electrical characteristics

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol

Parameter

Table 41. Electrical sensitivities

Conditions

Static latch-up class T

= +85 °C conforming to JESD78A

Class

II level A

Note:

As a general rule, current injection to the I/O pins, due to external voltage below V

(for standard pins) should be avoided during normal product operation.

or above V

However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset occurrence, oscillator frequency deviation, LCD levels).

The test results are given in

Table 42

Symbol

INJ

Table 42. I/O current injection susceptibility

Functional susceptibility

Description

Injected current on all 5 V tolerant (FT) pins

Injected current on BOOT0

Injected current on any other pin

Negative injection

-5

-0

-5

Positive injection

(1)

1. Injection is not possible.

Unit mA

It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

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Electrical characteristics STM32L100x6/8/B-A

General input/output characteristics

are derived from tests performed under conditions summarized in

Table 14 . All I/Os are CMOS and TTL compliant.

Symbol

IH hys lkg

Parameter

Input low level voltage

Input high level voltage

I/O Schmitt trigger voltage hysteresis (2)

Input leakage current

(4)

Table 43. I/O static characteristics

Conditions

TC and FT I/O

BOOT0

TC I/O

FT I/O

BOOT0

TC and FT I/O

BOOT0

≤ V

I/Os with LCD

≤ V

I/Os with analog switches

≤ V

I/Os with analog switches and LCD

≤ V

I/Os with USB

Min

0.45 V

+0.38

(2)

0.39 V

+0.59

(2)

0.15 V

+0.56

(2)

Typ

10% V

(3)

0.01

Max

0.3 V

(1)(2)

0.14 V

(2)

±50

±250

≤ V

TC and FT I/O

FT I/O

≤ V

≤ 5V

±50

±10

Weak pull-up equivalent resistor

(5)(1)

Weak pull-down equivalent resistor

(5)

I/O pin capacitance 5 -

1. Guaranteed by test in production.

2. Guaranteed by design.

3. With a minimum of 200 mV.

4. The max. value may be exceeded if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

Unit

V nA uA k Ω k Ω pF

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STM32L100x6/8/B-A Electrical characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with the non-standard V

specifications given in Table 44 .

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

• The sum of the currents sourced by all the I/Os on V

DD, consumption of the MCU sourced on V

DD,

Σ I

VDD

(see

Table 12 ).

plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

SS consumption of the MCU sunk on V

Σ I

VSS

(see

Table 12 ).

plus the maximum Run

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in Table 44

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 14 . All I/Os are CMOS and TTL compliant.

Symbol

Table 44. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)(2)

(3)(2)

(1)(4)

(3)(4)

(1)(4)

(3)(4)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

2.7 V < V

= 8 mA

= 4 mA

1.8 V < V

= 20 mA

2.7 V < V

< 3.6 V

< 2.7 V

< 3.6 V

-0.4

-0.45

-1.3

0.4

0.45

1.3

1. The I

current sunk by the device must always respect the absolute maximum rating specified in

Table 12

and the sum of

(I/O ports and control pins) must not exceed I

VSS

2. Guaranteed by test in production.

3. The I of I

current sourced by the device must always respect the absolute maximum rating specified in

Table 12

and the sum

(I/O ports and control pins) must not exceed I

VDD

4. Guaranteed by characterization results.

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Electrical characteristics STM32L100x6/8/B-A

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 15 and

Table 45 , respectively.

Unless otherwise specified, the parameters given in Table 45

are derived from tests performed under ambient temperature and V

Unless otherwise specified, the parameters given in Table 46

supply voltage conditions summarized in

Table 45. I/O AC characteristics (1)

OSPEEDRx

[1:0] bit value (1)

Symbol Parameter Conditions Min Max

(2)

Unit

11 f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out

F max(IO)out

Maximum frequency

(3) t f(IO)out t r(IO)out

F max(IO)out

Maximum frequency

(3) t f(IO)out t r(IO)out

Maximum frequency

(3)

Output rise and fall time

Maximum frequency

(3)

Output rise and fall time

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.8 V to 2.7 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.8 V to 2.7 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.8 V to 2.7 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.8 V to 2.7 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.8 V to 2.7 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.8 V to 2.7 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.8 V to 2.7 V

= 30 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.8 V to 2.7 V kHz ns

MHz ns

MHz

EXTIpw

Pulse width of external signals detected by the

EXTI controller

8 -

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0038 reference manual for a description of

GPIO Port configuration register.

2. Guaranteed by design.

3. The maximum frequency is defined in

Figure 15

125

250

400

625

74/103

DocID025966 Rev 6

STM32L100x6/8/B-A Electrical characteristics

Figure 15. I/O AC characteristics definition

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The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see

Table 46 ).

are derived from tests performed under ambient temperature and V

Table 46 . Otherwise the reset will not be taken into account by the device.

supply voltage conditions summarized in

Symbol

IL(NRST)

(1)

IH(NRST)

(1)

Parameter

Table 46. NRST pin characteristics

Conditions Min

NRST input low level voltage

NRST input high level voltage

0.39 V

+0.59

Typ

Max

0.3 V

OL(NRST)

(1)

NRST output low level voltage

= 2 mA

2.7 V < V

< 3.6 V

= 1.5 mA

1.8 V < V

< 2.7 V

0.4

V hys(NRST)

(1)

NRST Schmitt trigger voltage hysteresis

10%V

(2)

Weak pull-up equivalent resistor

(3)

= V

25 45 65

F(NRST)

(1)

NF(NRST)

(1)

NRST input filtered pulse

NRST input not filtered pulse -

350 -

1. Guaranteed by design.

2. 200 mV minimum value.

3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is around 10%.

Unit

V mV k Ω ns ns

DocID025966 Rev 6

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Electrical characteristics STM32L100x6/8/B-A

Figure 16. Recommended NRST pin protection

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1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip.

2. The user must ensure that the level on the NRST pin can go below the V

max level specified in

The parameters given in

Table 47 are guaranteed by design.

Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 47. TIMx

(1)

characteristics

Parameter Conditions Min t t res(TIM) f

EXT

Res

TIM

COUNTER

Timer resolution time

Timer external clock frequency on CH1 to CH4

Timer resolution

16-bit counter clock period when internal clock is selected (timer’s prescaler disabled)

TIMxCLK

= 32 MHz 31.25

0 f

TIMxCLK

= 32 MHz

TIMxCLK

= 32 MHz 0.0312

MAX_COUNT

Maximum possible count

TIMxCLK

= 32 MHz -

1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.

Max

TIMxCLK

65536

2048 µs

65536 × 65536 t

TIMxCLK

134.2

Unit t

TIMxCLK ns

MHz

MHz bit t

TIMxCLK

76/103

DocID025966 Rev 6

STM32L100x6/8/B-A Electrical characteristics

I

C interface characteristics

The STM32L100x6/8/B-A product line I

C interface meets the requirements of the standard

C communication protocol with the following restrictions: SDA and SCL are not “true” open-drain I/O pins. When configured as open-drain, the PMOS connected between the I/O pin and V

DD is disabled, but is still present.

The I

C characteristics are described in

Table 48

. Refer also to

Section 6.3.12: I/O current injection characteristics

for more details on the input/output alternate function characteristics

(SDA and SCL).

Symbol Parameter

Table 48. I 2 C characteristics

Standard mode

(1)(2)

Min Max

Fast mode I

(1) (2)

Unit

Min Max t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

4.7

4.0

250

3450

(3)

1000

300

1.3

0.6

100

900

(3)

300

µs ns t t su(STA) su(STO) t w(STO:STA) t

C b

Start condition hold time

Repeated Start condition setup time

Stop condition setup time

Stop to Start condition time

(bus free)

Capacitive load for each bus line

Pulse width of spikes that are suppressed by the analog filter

4.0

4.7

4.0

4.7

400

50 (4)

0.6

0.6 -

0.6

1.3

400

(4)

µs

μ pF ns

1. Guaranteed by design.

2. f

PCLK1 must be at least 2 MHz to achieve standard mode I ² C frequencies. It must be at least 4 MHz to achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast mode clock.

3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal.

4. The minimum width of the spikes filtered by the analog filter is above t

SP(max)

. s s

DocID025966 Rev 6

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Electrical characteristics STM32L100x6/8/B-A

Figure 17. I 2 C bus AC waveforms and measurement circuit s ͺ/Ϯ s ͺ/Ϯ

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1. R

= series protection resistors

2. R

= pull-up resistors

3. V

DD_I2C

= I2C bus supply

4. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

Table 49. SCL frequency (f

PCLK1

= 32 MHz, V

= V

DD_I2C

= 3.3 V)

(1)(2)

I2C_CCR value f

SCL

(kHz)

= 4.7 k Ω

400

300

200

100

0x801B

0x8024

0x8035

0x00A0

50 0x0140

20 0x0320

1. R

= External pull-up resistance, f

SCL

= I

C speed.

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ± 5%. For other speed ranges, the tolerance on the achieved speed is ± 2%. These variations depend on the accuracy of the external components used to design the application.

78/103

DocID025966 Rev 6

STM32L100x6/8/B-A Electrical characteristics

SPI characteristics

Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, f

conditions summarized in Table 14

PCLKx frequency and V

supply voltage

Refer to Section 6.3.12: I/O current injection characteristics for more details on the

input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol Parameter

Table 50. SPI characteristics (1)

Conditions Min Max

(2)

Unit f

SCK

1/t c(SCK)

SPI clock frequency

Master mode

Slave mode

Slave transmitter t t

r(SCK)

f(SCK)

Unless otherwise specified, the parameters given in Table 55

SPI clock rise and fall time

Capacitive load: C = 30 pF

DuCy(SCK)

SPI slave input clock duty cycle

Slave mode

(3)

MHz ns

% t su(NSS) t h(NSS) t t

t su(MI)

t su(SI)

t a(SO)

(4) t

t v(MO)

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Data input hold time

Data output access time

Data output valid time

Data output hold time

Slave mode

Master mode

Slave mode

Master mode

Slave mode

Master mode

Slave mode

Master mode t

HCLK

SCK

0.5

− 5 t

SCK

HCLK

/2+3

6.5

1. The characteristics above are given for voltage Range 1.

2. Guaranteed by characterization results.

3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK)) ranging between 40 to 60%.

4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.

DocID025966 Rev 6

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Electrical characteristics STM32L100x6/8/B-A

Figure 18. SPI timing diagram - slave mode and CPHA = 0

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1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

DLE

80/103

DocID025966 Rev 6

STM32L100x6/8/B-A Electrical characteristics

Figure 20. SPI timing diagram - master mode (1)

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1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

USB characteristics

The USB interface is USB-IF certified (full speed).

Table 51. USB startup time

Symbol Parameter t

STARTUP

(1)

USB transceiver startup time

1. Guaranteed by design.

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Max

DLF

Unit

µs

DocID025966 Rev 6

81/103

Electrical characteristics STM32L100x6/8/B-A

Symbol

Table 52. USB DC electrical characteristics

Parameter Conditions Min.

(1)

Max.

(1)

Unit

Input levels

(3)

USB operating voltage

Differential input sensitivity I(USB_DP, USB_DM)

Differential common mode range Includes V

Single ended receiver threshold

Output levels

(2) -

DI range

3.0

0.2

0.8

1.3

3.6

2.5

2.0

(4)

Static output level low

Static output level high

of 1.5

k Ω to 3.6 V

of 15 k Ω to V

(5)

2.8

0.3

3.6

1. All the voltages are measured from the local ground potential.

2. To be compliant with the USB 2.0 full speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 k Ω resistor to a 3.0-to-3.6 V voltage range.

3. Guaranteed by characterization results.

4. Guaranteed by test in production.

5. R

is the load connected on the USB drivers.

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Figure 21. USB timings: definition of data signal rise and fall time

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Table 53. USB: full speed electrical characteristics

Driver characteristics

(1)

Symbol Parameter Conditions Min Max t r t f t rfm

CRS

Rise time

Fall Time

(2)

Rise/ fall time matching

Output signal crossover voltage

= 50 pF

= 50 pF t r

/t f

1.3

110

2.0

1. Guaranteed by design.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification section 7 (version 2.0).

Unit ns ns

82/103

DocID025966 Rev 6

STM32L100x6/8/B-A Electrical characteristics

are guaranteed by design.

Symbol Parameter f

ADC

ADC clock frequency

Table 54. ADC clock frequency

Conditions

Voltage

Range 1 &

2.4 V ≤

DDA

3.6 V

1.8 V ≤

DDA

2.4 V

Voltage Range 3

Min

0.480

Max Unit

MHz

Symbol

DDA

VDDA

AIN f

S t

CONV

ADC

Parameter

Table 55. ADC characteristics

Conditions Min

Power supply

Current on the V

DDA pin

input

Conversion voltage range

12-bit sampling rate

10-bit sampling rate

8-bit sampling rate

6-bit sampling rate

Sampling time

(2)

Peak

Average

Direct channels

Multiplexed channels

Direct channels

Multiplexed channels

Direct channels

Multiplexed channels

Direct channels

Multiplexed channels

Direct channels

2.4 V ≤

DDA

3.6 V

Multiplexed channels

2.4 V ≤

DDA

3.6 V

Direct channels

1.8 V ≤

DDA

2.4 V

Multiplexed channels

1.8 V ≤

DDA

2.4 V

ADC

= 16 MHz

1.8

(1)

0.25

0.56

Total conversion time

(including sampling time)

Internal sample and hold capacitor

Direct channels

Multiplexed channels

Typ

1400

384

24.75

4 to 384 (sampling phase) +12 (successive approximation)

Max

3.6

2150

1900

DDA

0.76

1.07

0.8

1.23

0.89

1.45

Unit

µA

Msps

µs

1/f

ADC

µs

1/f

ADC pF

DocID025966 Rev 6

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Electrical characteristics STM32L100x6/8/B-A

Symbol

Table 55. ADC characteristics (continued)

Parameter Conditions Min f

TRIG

External trigger frequency

Regular sequencer

12-bit conversions

6/8/10-bit conversions -

TRIG

External trigger frequency

Injected sequencer

12-bit conversions

6/8/10-bit conversions -

AIN

Signal source impedance

2. See Table 57: Maximum source impedance RAIN max for R

ADC

= 16 MHz

219 t t lat latr

Injection trigger conversion latency

Regular trigger conversion latency f

ADC

= 16 MHz

3.5

156

2.5

STAB

Power-up time -

1. V

SSA

must be tied to ground.

AIN

limitations

Typ

Max Unit

Tconv+1 1/f

ADC

Tconv 1/f

ADC

Tconv+2 1/f

ADC

Tconv+1 1/f

ADC

50 κΩ

281 ns

4.5

219

3.5

1/f

ADC ns

1/f

ADC

µs

Symbol Parameter

Table 56. ADC accuracy (1)(2)

Test conditions

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

ENOB Effective number of bits

SINAD

Signal-to-noise and distortion ratio

SNR Signal-to-noise ratio

THD Total harmonic distortion

ENOB Effective number of bits

SINAD

Signal-to-noise and distortion ratio

SNR Signal-to-noise ratio

THD Total harmonic distortion

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f f

2.4 V ≤ V

ADC

A f

ADC

A input

1.8 V ≤ V

DDA

3.6 V

= 8 MHz, R

= -40 to 85

2.4 V ≤ V

DDA

1.8 V ≤ V

DDA f

ADC

AIN

A input

ADC

DDA

≤

≤ 2.4 V

= 8 MHz or 4 MHz,

= 50 Ω

= -40 to 85

=10 kHz

° C

= 4 MHz, R

AIN

= -40 to 85 ° C

1. ADC DC accuracy values are measured after internal calibration.

= 50 Ω

≤ 3.6 V

= 16 MHz, R

AIN

= -40 to 85

=10 kHz

° C

≤ 2.4 V

= 50 Ω

Min (3)

9.5

-72

Typ

2.5

1.5

-72

1.5

Unit

LSB bits dB bits dB

LSB

-69

Max (3)

3.5

-69

1.5

2.5

84/103

DocID025966 Rev 6

STM32L100x6/8/B-A Electrical characteristics

2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

in Section 6.3.12

does not affect the ADC

3. Guaranteed by characterization results.

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Figure 22. ADC accuracy characteristics

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Figure 23. Typical connection diagram using the ADC

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1. Refer to Table 57: Maximum source impedance RAIN max for the value of R

characteristics for the value of CADC

AIN

and Table 55: ADC

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 this, f

ADC pF). A high C

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

DocID025966 Rev 6

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Electrical characteristics STM32L100x6/8/B-A

Figure 24. Maximum dynamic current consumption on V

DDA conversion

supply pin during ADC

Conversion (12 cycles)

ADC clock

DDA

1700 µA

Sampling (n cycles)

1300 µA

MS36686V1

1.5

Table 57. Maximum source impedance R

AIN

max (1)

AIN

max (kOhm)

(µs)

Multiplexed channels Direct channels

0.25

0.5625

2.4 V < V

DDA

< 3.6 V 1.8 V < V

DDA

< 2.4 V 2.4 V < V

DDA

< 3.3 V 1.8 V < V

DDA

< 2.4 V

Not allowed

0.8

Not allowed

0.7

2.0

Not allowed

1.0

Ts (cycles) f

ADC

= 16 MHz

(2)

2.0

3.0

6.8

15.0

32.0

50.0

0.8

1.8

4.0

10.0

25.0

50.0

4.0

6.0

15.0

30.0

50.0

3.0

4.5

10.0

20.0

40.0

50.0

192

384

1. Guaranteed by design.

2. Number of samples calculated for f

ADC

= 16 MHz. F or f

ADC

= 8 and 4 MHz the number of sampling cycles can be reduced with respect to the minimum sampling time Ts (us).

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 8 . The 100 nF capacitors

should be ceramic (good quality). They should be placed as close as possible to the chip.

86/103

DocID025966 Rev 6

STM32L100x6/8/B-A Electrical characteristics

Data guaranteed by design, unless otherwise specified.

Symbol

DDA

(1)

Parameter

Analog supply voltage

Current consumption on

DDA

supply

DDA

= 3.3 V

Resistive load

Capacitive load

Output impedance

Table 58. DAC characteristics

Conditions Min

No load, middle code (0x800)

No load, worst code (0xF1C)

DAC output buffer ON

Connected to V

SSA

Connected to V

DDA

DAC output buffer ON

DAC output buffer OFF

1.8

DAC output buffer ON 0.2

DAC_OUT

Voltage on DAC_OUT output

DAC output buffer OFF 0.5

Typ

330

540

Max

3.6

540

870

DDA

0.2

–

Unit

µA

V k Ω pF k Ω

DDA

1LSB

– mV

DNL

INL

Offset

Offset1

Gain

(1) dOffset/dT

≤

≥ 5 k Ω

DAC output buffer ON

Differential non linearity

(2)

No R

, C

≤ 50 pF

DAC output buffer OFF

≤

≥ 5 k Ω

DAC output buffer ON

Integral non linearity

(3)

Offset error at code 0x800

(4)

No R

, C

≤ 50 pF

DAC output buffer OFF

≤

≥ 5 k Ω

DAC output buffer ON

No R

, C

≤ 50 pF

DAC output buffer OFF

Offset error at code 0x001

Offset error temperature coefficient (code 0x800)

(5)

No R

, C

≤ 50 pF

DAC output buffer OFF

DDA

= 3.3V,T

= 0 to 50 ° C

DAC output buffer OFF

Gain error

(6)

DDA

= 3.3V, T

= 0 to 50 ° C

DAC output buffer ON

≤

≥ 5 k Ω

DAC output buffer ON

No R

, C

≤ 50 pF

DAC output buffer OFF

1.5

±10

±25

LSB

±5 ±8

-20

±1.5

±5

-10 0

+0.1 /

-0.2%

+0 / -

0.2%

+0.2 / -

0.5%

+0 / -

0.4%

µV/°C

DocID025966 Rev 6

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Electrical characteristics STM32L100x6/8/B-A

Symbol

Table 58. DAC characteristics (continued)

Parameter Conditions Min Typ Max Unit t t dGain/dT

TUE

SETTLING

Update rate

WAKEUP

PSRR+

Gain error temperature coefficient

Total unadjusted error

DDA

= 3.3V, T

= 0 to 50 ° C

DAC output buffer OFF

DDA

= 3.3V, T

= 0 to 50 ° C

DAC output buffer ON

≤

≥ 5 k Ω

DAC output buffer ON

No R

, C

≤ 50 pF

DAC output buffer OFF

Settling time (full scale: for a

12-bit code transition between the lowest and the highest input codes till

DAC_OUT reaches final value ±1LSB

≤

≥ 5 k Ω

Max frequency for a correct

DAC_OUT change (95% of final value) with 1 LSB variation in the input code

Wakeup time from off state

(setting the ENx bit in the

DAC Control register)

(7)

DDA

supply rejection ratio

(static DC measurement)

≤

≥ 5 k Ω

-10

-40

-2

-8

-60 -35

µV/°C

LSB

µs

Msps

µs dB

1. Guaranteed by characterization results.

2. Difference between two consecutive codes - 1 LSB.

3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code

4095.

4. Difference between the value measured at Code (0x800) and the ideal value = V

DDA

/2.

5. Difference between the value measured at Code (0x001) and the ideal value.

6. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (V

DDA

– 0.2) V when buffer is ON.

7. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

88/103

DocID025966 Rev 6

STM32L100x6/8/B-A Electrical characteristics

Figure 25. 12-bit buffered /non-buffered DAC

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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

6.3.19 Comparator

Symbol

Table 59. Comparator 1 characteristics

Parameter Conditions Min

(1)

Typ Max

(1)

Unit

DDA

400K

10K

Analog supply voltage

400K

value

10K

value

Comparator 1 input voltage range

1.8

0.6

400

3.6

DDA k

V t

START td

Comparator startup time

Propagation delay (2)

µs

Voffset Comparator offset ± 3 ± 10 mV d

Voffset

/dt

Comparator offset variation in worst voltage stress conditions

DDA

IN+

IN-

= 3.6 V

= 0 V

= V

REFINT

= 25 ° C

0 1.5

10 mV/1000 h

COMP1

Current consumption

(3)

160 260

1. Guaranteed by characterization results.

2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.

3. Comparator consumption only. Internal reference voltage not included.

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Electrical characteristics STM32L100x6/8/B-A

Symbol

Table 60. Comparator 2 characteristics

Parameter Conditions Min Typ Max

(1)

Unit

I t t

DDA

START t d slow

V d fast offset dThreshold/ dt

COMP2

Analog supply voltage

Comparator 2 input voltage range

Comparator startup time

Propagation delay

Propagation delay coefficient

(2)

Current consumption

in slow mode

in fast mode

Comparator offset error

Threshold voltage temperature

(3)

Fast mode

Slow mode

1.8 V ≤ V

DDA

≤

2.7 V ≤ V

DDA

≤

1.8 V ≤ V

DDA

≤

2.7 V ≤ V

DDA

≤

DDA

1/2 V

= 3.3V

= 0 to 50 ° C

V- = V

REFINT

3/4 V

REFINT

1/4 V

REFINT

Fast mode

Slow mode

1.8

2.5

0.8

1.2

3.5

0.5

3.6

DDA

3.5

µs

± 20 mV

100

1. Guaranteed by characterization results.

2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.

3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not included.

ppm

/°C

µA

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DocID025966 Rev 6

STM32L100x6/8/B-A Electrical characteristics

The STM32L100x6/8/B-A devices embed a built-in step-up converter to provide a constant

LCD reference voltage independently from the V

DD be connected to the V

LCD

voltage. An external capacitor C

pin to decouple this converter.

ext

must

Symbol

Table 61. LCD controller characteristics

Parameter Min Typ Max Unit

LCD

LCD0

LCD1

LCD2

LCD3

LCD4

LCD5

LCD6

LCD7

C ext

LCD external voltage

LCD internal reference voltage 0

LCD internal reference voltage 1

LCD internal reference voltage 2

LCD internal reference voltage 3

LCD internal reference voltage 4

LCD internal reference voltage 5

LCD internal reference voltage 6

LCD internal reference voltage 7 -

2.6

2.73

2.86

2.98

3.12

3.26

3.4

3.55

3.6

LCD

(1)

LCD

external capacitance

Supply current at V

= 2.2 V

Supply current at V

= 3.0 V

Low drive resistive network overall value

0.1

3.3

3.1

µF

µA

Htot

(2)

High drive resistive network total value

Segment/Common highest level voltage

Segment/Common 3/4 level voltage

Segment/Common 2/3 level voltage

Segment/Common 1/2 level voltage

Segment/Common 1/3 level voltage

Segment/Common 1/4 level voltage

Segment/Common lowest level voltage

5.28

192

6.6

240

3/4 V

2/3 V

1/2 V

1/3 V

1/4 V

LCD

7.92

288

LCD

M k

Δ Vxx

Updated DMIPS features in cover page and Section 2: Description

Segment/Common level voltage error

= -40 to 85 ° C

± 50 mV

1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected

2. Guaranteed by characterization results.

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Package information STM32L100x6/8/B-A

7.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK

is an ST trademark.

LQFP64 10 x 10 mm, 64-pin low-profile quad flat package information

Figure 26. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package outline

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*$8*(3/$1(

FFF &

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3,1

,'(17,),&$7,21

:B0(B9

1. Drawing is not to scale.

Table 62. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Typ Min Max

0.050

1.350

1.400

1.600

0.150

1.450

0.0020

0.0531

0.0551

0.0630

0.0059

0.0571

DocID025966 Rev 6

STM32L100x6/8/B-A Package information

Table 62. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Typ Min Max

E1 b c

0.170

0.090

0.220

12.000

10.000

7.500

12.000

10.000

0.270

0.200

E3 e

0°

0.450

7.500

0.500

3.5°

0.600

7°

0.750

0°

0.0177

L1 ccc

1.000

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0067

0.0035

0.2953

0.0197

3.5°

0.0236

0.0394

0.0087

0.4724

0.3937

0.2953

0.4724

0.3937

7°

0.0295

0.0031

0.0106

0.0079

Figure 27. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package recommended footprint

1. Dimensions are in millimeters.

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Package information STM32L100x6/8/B-A

LQFP64 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 28. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example

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1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

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STM32L100x6/8/B-A

7.2

Package information

UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information

Figure 29. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline

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ODVHUPDUNLQJDUHD

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GGG

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1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground.

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Package information STM32L100x6/8/B-A

Table 63. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

T b e ddd

0.500

0.000

6.900

5.500

0.300

0.200

0.550

0.020

7.000

5.600

0.400

0.152

0.250

0.500

0.600

0.050

7.100

5.700

0.500

0.300

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0000

0.2717

0.2165

0.0118

0.0079

0.0217

0.0008

0.2756

0.2205

0.0157

0.0060

0.0098

0.0197

0.0236

0.0020

0.2795

0.2244

0.0197

0.0118

0.0031

Figure 30. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package recommended footprint

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1. Dimensions are in millimeters.

DocID025966 Rev 6

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STM32L100x6/8/B-A Package information

UFQFPN48 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 31. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package top view example

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Package information STM32L100x6/8/B-A

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

max = T

max + (P

max × Θ

)

Where:

• T

max is the maximum ambient temperature in ° C,

• Θ

is the package junction-to-ambient thermal resistance, in ° C/W,

• P

max is the sum of P

INT

max and P

I/O max (P

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Symbol

Table 64. Thermal characteristics

Parameter

Thermal resistance junction-ambient

LQFP64 - 10 x 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

UFQFPN48 - 7 x 7 mm / 0.5 mm pitch

Value

Unit

°C/W

Figure 32. Thermal resistance

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-PD[

/4)3

8)4)31

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STM32L100x6/8/B-A Package information

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

DocID025966 Rev 6

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Ordering information STM32L100x6/8/B-A

100/103

Example:

Table 65. Ordering information scheme

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

L = Low power

STM32 L 100 R B T 6 A TR

Device subfamily

100

Pin count

C = 48 pins

R = 64 pins

Flash memory size

6 = 32 Kbytes of Flash memory

8 = 64 Kbytes of Flash memory

B = 128 Kbytes of Flash memory

Package

T = LQFP

U = UFQFPN

Temperature range

6 = Industrial temperature range, –40 to 85 °C

Options

A = Device generation A

Packing

TR = tape and reel

No character = tray or tube

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.

DocID025966 Rev 6

STM32L100x6/8/B-A Revision history

Date

25-Mar-2014

27-Oct-2014

03-Feb-2015

30-Apr-2015

25-Apr-2016

Table 66. Document revision history

Revision Changes

Initial release.

Updated current consumption in

Table 20: Current consumption in

Sleep mode

Updated

Table 25: Peripheral current consumption with new

measured values.

Updated

Table 57: Maximum source impedance RAIN max

adding note 2.

Updated

with new package device markings.

Updated

Figure 5: Memory map

Updated

Updated Table 62: LQFP64 10 x 10 mm, 64-pin low-profile quad flat package mechanical data .

structure: Paragraph titles and paragraph heading level.

Updated

Table 17: Embedded internal reference voltage

for LQFP64 and

UFQFPN48 package device markings, adding text for device orientation versus pin 1 identifier.

Updated

temperature coefficient at 100ppm/°C and table footnote 3:

“guaranteed by design” changed by “guaranteed by characterization results”.

Updated

Table 60: Comparator 2 characteristics new maximum

threshold voltage temperature coefficient at 100ppm/°C.

Updated

Table 40: ESD absolute maximum ratings CDM class.

Updated all the notes, removing ‘not tested in production’.

Updated

Table 11: Voltage characteristics

adding note about V pin.

REF-

Updated

Table 3: Functionalities depending on the operating power supply range

LSI and LSE functionalities putting “Y” in Standby mode.

Removed note 1 below

Figure 2: Clock tree

Updated

Table 58: DAC characteristics

replacing “Marking of engineering samples” by “device marking”.

Updated

resistive load.

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102

Revision history

Date

28-Aug-2017

STM32L100x6/8/B-A

Table 66. Document revision history (continued)

Revision Changes

Updated

Table 43: I/O static characteristics

pull-up and pull-down values.

Updated

Table 46: NRST pin characteristics pull-up values.

Updated