supply pin during ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 31.

12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 32.

LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 110

Figure 33.

LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 34.

LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example . . . . . . 112

Figure 35.

LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 113

Figure 36.

LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 37.

LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example . . . . . . . . . 115

Figure 38.

LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 116

Figure 39.

Figure 40.

LQFP48 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 41.

UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 42.

Figure 43.

UFQFPN48 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 44.

UFBGA100, 7 x 7 mm, 0.5 mm pitch package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 45.

UFBGA100, 7 x 7 mm, 0.5 mm pitch, package recommended footprint. . . . . . . . . . . . . . 123

DocID022799 Rev 13 7/136

List of figures STM32L151xC STM32L152xC

Figure 46.

UFBGA100, 7 x 7 mm, 0.5 mm pitch, package top view example . . . . . . . . . . . . . . . . . . 124

Figure 47.

WLCSP63, 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . . 125

Figure 48.

WLCSP63 device marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 49.

Thermal resistance suffix 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 50.

Thermal resistance suffix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

8/136 DocID022799 Rev 13

STM32L151xC STM32L152xC

1 Introduction

Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32L151xC and STM32L152xC ultra-low-power ARM ® Cortex ® -M3 based microcontroller product line with a Flash memory of 256 Kbytes.

The ultra-low-power STM32L151xC and STM32L152xC family includes devices in 6 different package types: from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

These features make the ultra-low-power STM32L151xC and STM32L152xC microcontroller family suitable for a wide range of applications:

• Medical and handheld equipment

• Application control and user interface

• PC peripherals, gaming, GPS and sport equipment

• Alarm systems, wired and wireless sensors, video intercom

• Utility metering

This STM32L151xC and STM32L152xC datasheet should be read in conjunction with the

STM32L1xxxx reference manual (RM0038). The application note “Getting started with

STM32L1xxxx hardware development” (AN3216) gives a hardware implementation overview. Both documents are available from the STMicroelectronics website www.st.com

For information on the ARM

Cortex

-M3 core please refer to the ARM

Cortex

-M3

technical reference manual, available from the www.arm.com website. Figure 1

shows the general block diagram of the device family.

DocID022799 Rev 13 9/136

Description

2 Description

STM32L151xC STM32L152xC

The ultra-low-power STM32L151xC and STM32L152xC devices incorporate the connectivity power of the universal serial bus (USB) with the high-performance ARM ®

Cortex ® -M3 32-bit RISC core operating at a frequency of 32 MHz (33.3 DMIPS), a memory protection unit (MPU), high-speed embedded memories (Flash memory up to 256 Kbytes and RAM up to 32 Kbytes) and an extensive range of enhanced I/Os and peripherals connected to two APB buses.

The STM32L151xC and STM32L152xC devices offer two operational amplifiers, one 12-bit

ADC, two DACs, two ultra-low-power comparators, one general-purpose 32-bit timer, six general-purpose 16-bit timers and two basic timers, which can be used as time bases.

Moreover, the STM32L151xC and STM32L152xC devices contain standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2S, three USARTs and an USB.

The STM32L151xC and STM32L152xC devices offer up to 23 capacitive sensing channels to simply add a touch sensing functionality to any application.

They also include a real-time clock and a set of backup registers that remain powered in

Standby mode.

Finally, the integrated LCD controller (except STM32L151xC devices) has a built-in LCD voltage generator that allows to drive up to 8 multiplexed LCDs with the contrast independent of the supply voltage.

The ultra-low-power STM32L151xC and STM32L152xC devices operate from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. They are available in the -40 to +85 °C and -40 to +105 °C temperature ranges. A comprehensive set of power-saving modes allows the design of lowpower applications.

10/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Description

Table 2. Ultra-low-power STM32L151xC and STM32L152xC device features and peripheral counts

Peripheral STM32L15xCC

STM32L15xUC

STM32L15xRC

STM32L15xVC

Flash (Kbytes)

Data EEPROM (Kbytes)

RAM (Kbytes)

Timers

32 bit

Generalpurpose

Communica tion interfaces

Basic

SPI

I 2 C

USART

USB

8(3) (1)

256

GPIOs

Operation amplifiers

12-bit synchronized ADC

Number of channels

12-bit DAC

Number of channels

LCD

(2)

COM x SEG

4x18

4x32 or 8x28

4x44 or 8x40

Comparators

Capacitive sensing channels 16 23

Max. CPU frequency 32 MHz

Operating voltage

Operating temperatures

Packages

1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option

1.65 V to 3.6 V without BOR option

Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C

Junction temperature: –40 to + 110 °C

LQFP48,

UFQFPN48

LQFP64,

WLCSP63

LQFP100,

UFBGA100

1. 5 SPIs are USART configured in synchronous mode emulating SPI master.

2. STM32L152xx devices only.

DocID022799 Rev 13 11/136

Description STM32L151xC STM32L152xC

2.2

Note:

Ultra-low-power device continuum

The ultra-low-power family offers a large choice of cores and features. From proprietary 8bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to answer the user needs, in terms of ultra-low-power features. The STM32 ultra-low-power series are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and healthcare, wearable applications. Several built-in features like LCD drivers, dual-bank memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many others will clearly allow to build very cost-optimized applications by reducing BOM.

STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible the pin-to-pin compatibility between any STM8Lxxxxx and STM32Lxxxxx devices and between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented scalability, the old applications can be upgraded to respond to the latest market features and efficiency demand.

2.2.1 Performance

All the families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM Cortex-M3 core for

STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios.

This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.

STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a very easy migration from one family to another:

• Analog peripherals: ADC, DAC and comparators

• Digital peripherals: RTC and some communication interfaces

To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and

STM32L162xx family uses a common architecture:

• Same power supply range from 1.65 V to 3.6 V

• Architecture optimized to reach ultra-low consumption both in low-power modes and

Run mode

• Fast startup strategy from low-power modes

• Flexible system clock

• Ultrasafe reset: same reset strategy including power-on reset, power-down reset, brownout reset and programmable voltage detector

2.2.4 Features

ST ultra-low-power continuum also lies in feature compatibility:

• More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm

• Memory density ranging from 2 to 512 Kbytes

12/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Functional overview

Figure 1. Ultra-low-power STM32L151xC and STM32L152xC block diagram

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DocID022799 Rev 13 13/136

Functional overview STM32L151xC STM32L152xC

The ultra-low-power STM32L151xC and STM32L152xC devices support dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the internal lowdrop regulator that supplies the logic can be adjusted according to the system’s maximum operating frequency and the external voltage supply.

There are three power consumption ranges:

• Range 1 (V

range limited to 1.71 V - 3.6 V), with the CPU running at up to 32 MHz

• Range 2 (full V

range), with a maximum CPU frequency of 16 MHz

• Range 3 (full V

range), with a maximum CPU frequency limited to 4 MHz (generated only with the multispeed internal RC oscillator clock source)

Seven low-power modes are provided to achieve the best compromise between low-power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at

16 MHz is about 1 mA with all peripherals off.

• Low-power run mode

This mode is achieved with the multispeed internal (MSI) RC oscillator set to the MSI range 0 or MSI range 1 clock range (maximum 131 kHz), execution from SRAM or

Flash memory, and internal regulator in low-power mode to minimize the regulator's operating current. In low-power run mode, the clock frequency and the number of enabled peripherals are both limited.

• Low-power sleep mode

This mode is achieved by entering Sleep mode with the internal voltage regulator in

Low-power mode to minimize the regulator’s operating current. In Low-power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz.

When wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on.

• Stop mode with RTC

Stop mode achieves the lowest power consumption while retaining the RAM and register contents and real time clock. All clocks in the V

CORE

domain are stopped, the

PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still running. The voltage regulator is in the low-power mode.

The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the

Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp event or the RTC wakeup.

14/136 DocID022799 Rev 13

STM32L151xC STM32L152xC

Note:

Functional overview

• Stop mode without RTC

Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and

HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode.

The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the

Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can also be wakened by the USB wakeup.

• Standby mode with RTC

Standby mode is used to achieve the lowest power consumption and real time clock.

The internal voltage regulator is switched off so that the entire V

CORE

domain is powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched off. The LSE or LSI is still running. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,

RTC, LSI, LSE Crystal 32K osc, RCC_CSR).

The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),

RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.

• Standby mode without RTC

Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire V

CORE

domain is powered off. The PLL, MSI

RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,

RCC_CSR).

The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising edge on one of the three WKUP pin occurs.

The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by entering Stop or Standby mode.

Table 3. Functionalities depending on the operating power supply range

Functionalities depending on the operating power supply range

(1)

Operating power supply range

DAC and ADC operation

USB

Dynamic voltage scaling range

= V

DDA

= 1.65 to 1.71 V Not functional Not functional

DDA

= 1.71 to 1.8 V

(2)

DDA

= 1.8 to 2.0 V

(2)

Not functional Not functional

Conversion time up to 500 Ksps

Not functional

Range 2 or Range 3

Range 1, Range 2 or

Range 3

Range 1, Range 2 or

Range 3

DocID022799 Rev 13 15/136

Functional overview STM32L151xC STM32L152xC

Table 3. Functionalities depending on the operating power supply range (continued)

Functionalities depending on the operating power supply range

(1)

Operating power supply range

DAC and ADC operation

USB

Dynamic voltage scaling range

DDA

= 2.0 to 2.4 V

= 2.4 to 3.6 V

Conversion time up to 500 Ksps

Conversion time up to 1 Msps

Functional

(3)

Range 1, Range 2 or

Range 3

Range 1, Range 2 or

Range 3

1. The GPIO speed also depends from VDD voltage and the user has to refer to Table 45: I/O AC characteristics for more information about I/O speed.

2. CPU frequency changes from initial to final must respect “F

CPU

initial < 4*F

CPU

final” to limit V

CORE

drop changes. For example to switch from 4.2 MHz to 32 MHz, the user can switch from 4.2 MHz to 16 MHz, wait 5 µs, then switch from 16 MHz to 32 MHz.

3. Should be USB compliant from I/O voltage standpoint, the minimum V

is 3.0 V.

Table 4. CPU frequency range depending on dynamic voltage scaling

CPU frequency range Dynamic voltage scaling range

16 MHz to 32 MHz (1ws)

32 kHz to 16 MHz (0ws)

8 MHz to 16 MHz (1ws)

32 kHz to 8 MHz (0ws)

2.1MHz to 4.2 MHz (1ws)

32 kHz to 2.1 MHz (0ws)

Range 1

Range 2

Range 3

16/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Functional overview

CPU

Flash

RAM

Backup Registers

EEPROM

Brown-out rest

(BOR)

DMA

Programmable

Voltage Detector

(PVD)

Power On Reset

(POR)

Power Down Rest

(PDR)

High Speed

Internal (HSI)

High Speed

External (HSE)

Low Speed Internal

(LSI)

Low Speed

External (LSE)

Multi-Speed

Internal (MSI)

Inter-Connect

Controller

RTC

RTC Tamper

Auto WakeUp

(AWU)

LCD

USB

USART

SPI

I2C

Table 5. Functionalities depending on the working mode (from Run/active down to standby)

Stop Standby

Ips Run/Active Sleep

Lowpower

Run

Lowpower

Sleep

Wakeup capability

(1)

DocID022799 Rev 13 17/136

Functional overview STM32L151xC STM32L152xC

Table 5. Functionalities depending on the working mode (from Run/active down to standby) (continued)

Stop Standby

Ips Run/Active Sleep

Lowpower

Run

Lowpower

Sleep

Wakeup capability

ADC

DAC

Tempsensor

OP amp

Comparators

16-bit and 32-bit

Timers

IWDG

WWDG

Touch sensing

Systic Timer

GPIOs

Wakeup time to

Run mode

0 µs

0.4 µs

3 µs

46 µs

< 8 µs

3 pins

58 µs

Consumption

=1.8 to 3.6 V

(Typ)

Down to 185

µA/MHz (from

Flash)

Down to 34.5

µA/MHz (from

Flash)

Down to

8.6 µA

Down to

4.4 µA

0.43 µA

(no RTC)

=1.8V

1.15 µA

(with RTC)

=1.8V

0.44 µA

(no RTC)

=3.0V

1.4 µA

(with RTC)

=3.0V

1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before entering run mode.

0.29 µA

(no RTC)

=1.8V

0.9 µA

(with RTC)

=1.8V

0.29 µA

(no RTC)

=3.0V

1.15 µA

(with RTC)

=3.0V

3.2 ARM

®

Cortex

®

-M3 core with MPU

The ARM ® Cortex ® -M3 processor is the industry leading processor for embedded systems.

It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM ® Cortex ® -M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

18/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Functional overview

The memory protection unit (MPU) improves system reliability by defining the memory attributes (such as read/write access permissions) for different memory regions. It provides up to eight different regions and an optional predefined background region.

Owing to its embedded ARM core, the STM32L151xC and STM32L152xC devices are compatible with all ARM tools and software.

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L151xC and STM32L152xC devices embed a nested vectored interrupt controller able to handle up to 53 maskable interrupt channels (not including the 16 interrupt lines of ARM ® Cortex ® -M3) and 16 priority levels.

• Closely coupled NVIC gives low-latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving , higher-priority interrupts

• Support for tail-chaining

• Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

3.3

3.3.1

3.3.2

Reset and supply management

Power supply schemes

• V

= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through V

pins.

• V

SSA

, V

DDA

= 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to V

DDA and V

SSA must be connected to V

DD and V

SS is 1.8 V when the ADC is used). V

, respectively.

DDA

Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR) that can be coupled with a brownout reset (BOR) circuitry.

The device exists in two versions:

• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.

• The other version without BOR operates between 1.65 V and 3.6 V.

After the V

threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the BOR permanently: in this case, the V

1.65 V (whatever the version, BOR active or not, at power-on).

min value becomes

When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the power ramp-up should guarantee that 1.65 V is reached on V

DD the POR area.

at least 1 ms after it exits

DocID022799 Rev 13 19/136

Functional overview

Note:

STM32L151xC STM32L152xC

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Stop mode, it is possible to automatically switch off the internal reference voltage (V

REFINT

) in Stop mode. The device remains in reset mode when

DD is below a specified threshold, V reset circuit.

POR/PDR or V

BOR

, without the need for any external

The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for device s with BOR inactive at power-up.

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when V

DDA

is higher than the V

PVD

DDA

drops below the V

PVD

threshold and/or when

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

The regulator has three operation modes: main (MR), low-power (LPR) and power down.

• MR is used in Run mode (nominal regulation)

• LPR is used in the Low-power run, Low-power sleep and Stop modes

• Power down is used in Standby mode. The regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,

LSI, LSE crystal 32K osc, RCC_CSR).

At startup, boot pins are used to select one of three boot options:

• Boot from Flash memory

• Boot from System memory

• Boot from embedded RAM

The boot loader is located in System memory. It is used to reprogram the Flash memory by using USART1, USART2 or USB. See Application note “STM32 microcontroller system memory boot mode” (AN2606) for details.

20/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Functional overview

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

• Clock prescaler : to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

• Safe clock switching : clock sources can be changed safely on the fly in run mode through a configuration register.

• Clock management : to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

• System clock source : three different clock sources can be used to drive the master clock SYSCLK:

– 1-24 MHz high-speed external crystal (HSE), that can supply a PLL

– 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLL

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).

When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a ±0.5% accuracy.

• Auxiliary clock source : two ultra-low-power clock sources that can be used to drive the LCD controller and the real-time clock:

– 32.768 kHz low-speed external crystal (LSE)

– 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock can be measured using the high-speed internal RC oscillator for greater precision.

• RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever the system clock.

• USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply the USB interface.

• Startup clock : after reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

• Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled.

• Clock-out capability (MCO: microcontroller clock output): it outputs one of the internal clocks for external use by the application.

Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and

APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See

Figure 2 for details on the clock tree.

DocID022799 Rev 13 21/136

Functional overview STM32L151xC STM32L152xC

Figure 2. Clock tree

3TANDBYSUPPLIEDVOLTAGEDOMAIN

ENABLE

7ATCHDOG

,3)2# ,3)TEMPO

7ATCHDOG

,3%/3# ,3%TEMPO

24#ENABLE

24#

2ADIO3LEEP4IMERENABLE

2ADIO3LEEP4IMER

-3)2#

LEVELSHIFTERS

$$#/2%

(3)2#

LEVELSHIFTERS

$$#/2%

(3%

/3#

LEVELSHIFTERS

$$#/2%

-(Z

,3 ,3 ,3 ,3

CK?LSI

CK?LSE

CK?MSI

CK?HSI

CK?HSE

CK?PLLIN

CK?PLL

0,,

-(ZCLOCK

DETECTOR

#+?53"

(3%PRESENTORNOT

LEVELSHIFTERS

$$#/2%

USBENANDNOTDEEPSLEEP

#LOCK

SOURCE

CONTROL

,#$ENABLE

#+?,#$

#+?!$#

!$#ENABLE

-#/

NOTDEEPSLEEP

3YSTEM

CLOCK

!("

PRESCALER

NOTDEEPSLEEP

NOTSLEEPOR

DEEPSLEEP

NOTSLEEPOR

DEEPSLEEP

!0" !0"

PRESCALER PRESCALER

#+?072

#+?&#,+

#+?#05

#+?4)-393

#+?4)-4'/

#+?!0"

TIMERENANDNOTDEEPSLEEP

APBPERIPHENANDNOTDEEPSLEEP

IF!0"PRESC X

ELSE X

APBPERIPHENANDNOTDEEPSLEEP

-36

22/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Functional overview

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD

(binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. The RTC provides two programmable alarms and programmable periodic interrupts with wakeup from Stop and Standby modes.

The programmable wakeup time ranges from 120 µs to 36 hours.

The RTC can be calibrated with an external 512 Hz output, and a digital compensation circuit helps reduce drift due to crystal deviation.

The RTC can also be automatically corrected with a 50/60Hz stable powerline.

The RTC calendar can be updated on the fly down to sub second precision, which enables network system synchronization.

A time stamp can record an external event occurrence, and generates an interrupt.

There are thirty-two 32-bit backup registers provided to store 128 bytes of user application data. They are cleared in case of tamper detection.

Three pins can be used to detect tamper events. A change on one of these pins can reset backup register and generate an interrupt. To prevent false tamper event, like ESD event, these three tamper inputs can be digitally filtered.

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated AFIO registers. All GPIOs are high current capable. The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to the AHB with a toggling speed of up to 16 MHz.

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event

(rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 83 GPIOs can be connected to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB, comparator events or capacitive sensing acquisition.

DocID022799 Rev 13 23/136

Functional overview STM32L151xC STM32L152xC

3.7 Memories

The STM32L151xC and STM32L152xC devices have the following features:

• 32 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses).

• The non-volatile memory is divided into three arrays:

– 256 Kbytes of embedded Flash program memory

– 8 Kbytes of data EEPROM

– Options bytes

The options bytes are used to write-protect or read-out protect the memory (with 4

Kbytes granularity) and/or readout-protect the whole memory with the following options:

– Level 0: no readout protection

– Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected

– Level 2: chip readout protection, debug features (ARM Cortex-M3 JTAG and serial wire) and boot in RAM selection disabled (JTAG fuse)

The whole non-volatile memory embeds the error correction code (ECC) feature.

The user area of the Flash memory can be protected against Dbus read access by

PCROP feature (see RM0038 for details).

3.8 DMA (direct memory access)

The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose timers,

DAC and ADC.

24/136 DocID022799 Rev 13

STM32L151xC STM32L152xC

3.9 LCD (liquid crystal display)

Functional overview

The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels.

• Internal step-up converter to guarantee functionality and contrast control irrespective of

. This converter can be deactivated, in which case the V the voltage to the LCD

LCD

pin is used to provide

• Supports static, 1/2, 1/3, 1/4 and 1/8 duty

• Supports static, 1/2, 1/3 and 1/4 bias

• Phase inversion to reduce power consumption and EMI

• Up to 8 pixels can be programmed to blink

• Unneeded segments and common pins can be used as general I/O pins

• LCD RAM can be updated at any time owing to a double-buffer

• The LCD controller can operate in Stop mode

• V

LCD

rail decoupling capability

LCDRAIL1

LCDRAIL2

LCDRAIL3

1/2

1/2 V

LCD

N/A

Table 6. V

LCD rail decoupling

Bias

1/3

2/3 V

LCD

1/3 V

LCD

N/A

1/4

1/2 V

LCD

1/4 V

LCD

3/4 V

LCD

PB2

PB12

PB0

Pin

PE11

PE12

3.10 ADC (analog-to-digital converter)

A 12-bit analog-to-digital converters is embedded into STM32L151xC and STM32L152xC devices with up to 25 external channels, performing conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs with up to 24 external channels in a group.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions and timers.

An injection mode allows high priority conversions to be done by interrupting a scan mode which runs in as a background task.

The ADC includes a specific low-power mode. The converter is able to operate at maximum speed even if the CPU is operating at a very low frequency and has an auto-shutdown function. The ADC’s runtime and analog front-end current consumption are thus minimized whatever the MCU operating mode.

DocID022799 Rev 13 25/136

Functional overview STM32L151xC STM32L152xC

The temperature sensor (TS) generates a voltage V

SENSE temperature.

that varies linearly with

The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. See

Table 61:

Temperature sensor calibration values .

3.10.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

ADC and Comparators. V

REFINT

is internally connected to the ADC_IN17 input channel. It enables accurate monitoring of the V

) provides a stable (bandgap) voltage output for the

value (when no external voltage, VREF+, is available for ADC). The precise voltage of V

REFINT

is individually measured for each part by

ST during production test and stored in the system memory area. It is accessible in read-

only mode. See Table 16: Embedded internal reference voltage calibration values

3.11 DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration.

This dual digital Interface supports the following features:

• Two DAC converters: one for each output channel

• 8-bit or 12-bit monotonic output

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Dual DAC channels, independent or simultaneous conversions

• DMA capability for each channel (including the underrun interrupt)

• External triggers for conversion

• Input reference voltage V

REF+

Eight DAC trigger inputs are used in the STM32L151xC and STM32L152xC devices. The

DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

26/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Functional overview

The STM32L151xC and STM32L152xC devices embed two operational amplifiers with external or internal follower routing capability (or even amplifier and filter capability with external components). When one operational amplifier is selected, one external ADC channel is used to enable output measurement.

The operational amplifiers feature:

• Low input bias current

• Low offset voltage

• Low-power mode

• Rail-to-rail input

3.13 Ultra-low-power comparators and reference voltage

The STM32L151xC and STM32L152xC devices embed two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external

(coming from an I/O).

• One comparator with fixed threshold

• One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of the following:

– DAC output

– External I/O

– Internal reference voltage (V

REFINT

) or a sub-multiple (1/4, 1/2, 3/4)

Both comparators can wake up from Stop mode, and be combined into a window comparator.

The internal reference voltage is available externally via a low-power / low-current output buffer (driving current capability of 1 µA typical).

The system configuration controller provides the capability to remap some alternate functions on different I/O ports.

The highly flexible routing interface allows the application firmware to control the routing of different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage

REFINT

The STM32L151xC and STM32L152xC devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 23 capacitive sensing channels distributed over 10 analog I/O groups. Both software and timer capacitive sensing acquisition modes are supported.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation

DocID022799 Rev 13 27/136

Functional overview STM32L151xC STM32L152xC introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. The capacitive sensing acquisition only requires few external components to operate. This acquisition is managed directly by the GPIOs, timers and analog I/O groups

(see Section 3.14: System configuration controller and routing interface ).

Reliable touch sensing functionality can be quickly and easily implemented using the free

STM32L1xx STMTouch touch sensing firmware library.

3.16 Timers and watchdogs

The ultra-low-power STM32L151xC and STM32L152xC devices include seven generalpurpose timers, two basic timers, and two watchdog timers.

Table 7 compares the features of the general-purpose and basic timers.

Timer

Counter resolution

Counter type

Table 7. Timer feature comparison

Prescaler factor

DMA request generation

Capture/compare channels

Complementary outputs

TIM2,

TIM3,

TIM4

16-bit

Up, down, up/down

Any integer between

1 and 65536

Yes 4 No

TIM5

TIM9

TIM10,

TIM11

TIM6,

TIM7

32-bit

16-bit

Up, down, up/down

Any integer between

1 and 65536

Any integer between

1 and 65536

Any integer between

1 and 65536

Any integer between

1 and 65536

Yes

(TIM2,

TIM11)

There are seven synchronizable general-purpose timers embedded in the STM32L151xC and STM32L152xC devices (see

Table 7

for differences).

TIM2, TIM3, TIM4, TIM5

TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input captures/output compares/PWMs on the largest packages.

TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10,

TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs.

28/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Functional overview

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

TIM10, TIM11 and TIM9

TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3,

TIM4, TIM5 full-featured general-purpose timers.

They can also be used as simple time bases and be clocked by the LSE clock source

(32.768 kHz) to provide time bases independent from the main CPU clock.

3.16.2 Basic timers (TIM6 and TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as generic

16-bit time bases.

This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit downcounter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches 0.

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode.

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes.

They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SM Bus 2.0/PM Bus.

DocID022799 Rev 13 29/136

Functional overview STM32L151xC STM32L152xC

The three USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They support IrDA SIR ENDEC and have LIN Master/Slave capability. The three USARTs provide hardware management of the CTS and RTS signals and are ISO 7816 compliant.

All USART interfaces can be served by the DMA controller.

3.17.3 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

The SPIs can be served by the DMA controller.

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can operate in master or slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

The I2Ss can be served by the DMA controller.

The STM32L151xC and STM32L152xC devices embed a USB device peripheral compatible with the USB full-speed 12 Mbit/s. The USB interface implements a full-speed

(12 Mbit/s) function interface. It has software-configurable endpoint setting and supports suspend/resume. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).

3.18 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

30/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Functional overview

The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.

The JTAG port can be permanently disabled with a JTAG fuse.

3.19.2 Embedded Trace Macrocell™

The ARM ® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32L151xC and STM32L152xC device through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

DocID022799 Rev 13 31/136

Pin descriptions STM32L151xC STM32L152xC

Figure 3. STM32L15xVC UFBGA100 ballout

)

(

3( 3( 3% %227 3' 3'

3( 3( 3%

3& 1567 9''B

3% 3%

:.83

3( 3(

26&B,1

:8.3

966B

9''B 3%

3& 9/&'

26&B287

26&B,1

966B

26&B287

9''B

966$ 3& 3&

95() 3& 3$ 3$ 3&

95() 3$

:.83

9''$ 3$ 3$

3& 3%

3% 3%

3% 3% 3$ 3$ 3$ 3$

3' 3' 3' 3& 3& 3$

3' 3' 3& 3+ 3$

3$ 3$ 3&

3& 3& 3&

966B 966B

9''B 9''B

3' 3' 3'

3' 3' 3% 3% 3%

3( 3( 3( 3% 3% 3%

3( 3( 3( 3( 3( 3(

AIF

1. This figure shows the package top view.

32/136 DocID022799 Rev 13

STM32L151xC STM32L152xC

Figure 4. STM32L15xVC LQFP100 pinout

Pin descriptions

0%7+50

,#$

0#7+50

0#/3#?).

0#/3#?/54

633?

6$$?

0(/3#?).

0(/3#?/54

.234

633!

62%&

6$$!

0!7+50

,1&0

6$$?

633?

AIC

1. This figure shows the package top view.

DocID022799 Rev 13 33/136

Pin descriptions STM32L151xC STM32L152xC

Figure 5. STM32L15xRC LQFP64 pinout

,#$

0#7+50

0#/3#?).

0#/3#?/54

0(/3#?).

0(/3#?/54

.234

633!

6$$!

0!7+50

,1&0

6$$?

633?

AIC

1. This figure shows the package top view.

34/136 DocID022799 Rev 13

STM32L151xC STM32L152xC

Figure 6. STM32L15xUC WLCSP63 ballout

Pin descriptions

(

633?

0# 0$ 0" "//4 633?

6$$?

0# 0# 0" 0" 6$$?

0" 0" 0" 6,#$

0# 0!

0" 0# 0# 0#

0# 0# 0!

0# .234

0# 0" 0" 0# 633!

0( 0(

0" 0" 0" 0!

0# 0#

6$$?

0" 0" 0!

633 0!

6$$!

633?

0" 0" 0# 0!

-36

1. This figure shows the package top view.

DocID022799 Rev 13 35/136

Pin descriptions

,#$

0#7+50

0#/3#?).

0#/3#?/54

0(/3#?).

0(/3#?/54

.234

33!

$$!

0!7+50

STM32L151xC STM32L152xC

Figure 7. STM32L15xCC UFQFPN48 pinout

5&1&0.

$$?

33?

AID

1. This figure shows the package top view.

36/136 DocID022799 Rev 13

STM32L151xC STM32L152xC

Figure 8. STM32L15xCC LQFP48 pinout

Pin descriptions

9/&'

3&:.83

3&26&B,1

3&26&B287

3+26&B,1

3+26&B287

1567

966$

9''$

3$:.83

/4)3

9''B

966B

069

1. This figure shows the package top view.

DocID022799 Rev 13 37/136

Pin descriptions STM32L151xC STM32L152xC

Name

Table 8. Legend/abbreviations used in the pinout table

Abbreviation Definition

Pin name

Pin type

I/O structure

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

Input / output pin

5 V tolerant I/O

Standard 3.3 V I/O

Dedicated BOOT0 pin

Pin functions

Notes

RST Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Alternate functions

Functions selected through GPIOx_AFR registers

Additional functions

Functions directly selected/enabled through peripheral registers

Pins

Table 9. STM32L151xC and STM32L152xC pin definitions

Pin functions

Pin name

Main function

(2)

(after reset)

Alternate functions Additional functions

B2 1 -

A1 2 -

B1 3 -

C2 4 -

D2 5 -

E2 6 1 C7 1

PE2

PE3

PE4

PE5

PE6-

WKUP3

LCD

(3)

I/O FT

S -

PE2

PE3

PE4

PE5

PE6

LCD

TIM3_ETR/LCD_SEG38

/TRACECLK

TIM3_CH1/LCD_SEG39

/TRACED0

TIM3_CH2/TRACED1

TIM9_CH1/TRACED2

TIM9_CH2/ TRACED3

38/136 DocID022799 Rev 13

WKUP3/

RTC_TAMP3

STM32L151xC STM32L152xC Pin descriptions

Pins

Table 9. STM32L151xC and STM32L152xC pin definitions (continued)

Pin functions

Pin name

Main function

(2)

(after reset)

Alternate functions Additional functions

C1 7 2 D5 2

PC13-

WKUP2

I/O FT PC13

D1 8 3 D7 3

E1 9 4 D6 4

F2 10 -

G2 11 -

F1 12 5 F6 5

G1 13 6 F7 6

H2 14 7 E7 7

PC14-

OSC32_IN

(4)

PC15-

OSC32_OUT

SS_5

DD_5

PH0-

OSC_IN

(5)

PH1-

OSC_OUT

(5)

NRST

I/O

I/O RST

PC14

PC15

SS_5

DD_5

PH0

PH1

NRST

H1 15 8 E6 PC0 I/O FT PC0

J2 16 9 E5 -

J3 17 10 G7 -

18 11 G6 -

J1 19 12 F5 8

K1 20 -

L1 21 -

M1 22 13 H7 9

PC1

PC2

PC3

SSA

REF-

REF+

DDA

I/O FT

I/O TC

PC1

PC2

PC3

SSA

REF-

REF+

DDA

L2 23 14 E4 10 PA0-WKUP1 I/O FT PA0

LCD_SEG18

LCD_SEG19

LCD_SEG20

LCD_SEG21

TIM2_CH1_ETR/

TIM5_CH1/

USART2_CTS

WKUP2/

RTC_TAMP1/

RTC_TS/RTC_OUT

OSC32_IN

OSC32_OUT

OSC_IN

OSC_OUT

ADC_IN10/

COMP1_INP

ADC_IN11/

COMP1_INP

ADC_IN12/

COMP1_INP

ADC_IN13/

COMP1_INP

WKUP1/

RTC_TAMP2/

ADC_IN0/

COMP1_INP

DocID022799 Rev 13 39/136

Pin descriptions STM32L151xC STM32L152xC

Pins

Table 9. STM32L151xC and STM32L152xC pin definitions (continued)

Pin functions

Pin name

Main function

(2)

(after reset)

Alternate functions Additional functions

M2 24 15 G5 11

K3 25 16 H6 12

L3 26 17 J7 13

E3 27 18 -

H3 28 19 -

M3 29 20 J6 14

K4 30 21 H4 15

L4 31 22 G4 16

M4 32 23 J5 17

K5 33 24 F4 -

L5 34 25 J4 -

M5 35 26 J3 18

PA1

PA2

PA3

SS_4

DD_4

PA4

PA5

PA6

PA7

PC4

PC5

PB0

I/O FT

I/O

I/O FT

I/O

PA1

PA2

PA3

SS_4

DD_4

PA4

PA5

PA6

PA7

PC4

PC5

PB0

TIM2_CH2/TIM5_CH2/

USART2_RTS/

LCD_SEG0

TIM2_CH3/TIM5_CH3/

TIM9_CH1/USART2_TX

/LCD_SEG1

TIM2_CH4/TIM5_CH4/

TIM9_CH2/USART2_RX

/LCD_SEG2

SPI1_NSS/SPI3_NSS/

I2S3_WS/

USART2_CK

TIM2_CH1_ETR/

SPI1_SCK

TIM3_CH1/TIM10_CH1/

SPI1_MISO/LCD_SEG3

TIM3_CH2/TIM11_CH1/

SPI1_MOSI/LCD_SEG4

LCD_SEG22

LCD_SEG23

TIM3_CH3/LCD_SEG5

ADC_IN1/

COMP1_INP/

OPAMP1_VINP

ADC_IN2/

COMP1_INP/

OPAMP1_VINM

ADC_IN3/

COMP1_INP/

OPAMP1_VOUT

ADC_IN4/

DAC_OUT1/

COMP1_INP

ADC_IN5/

DAC_OUT2/

COMP1_INP

ADC_IN6/

COMP1_INP/

OPAMP2_VINP

ADC_IN7/

COMP1_INP/

OPAMP2_VINM

ADC_IN14/

COMP1_INP

ADC_IN15/

COMP1_INP

ADC_IN8/

COMP1_INP/

OPAMP2_VOUT/

VLCDRAIL3/

VREF_OUT

40/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Pin descriptions

Pins

Table 9. STM32L151xC and STM32L152xC pin definitions (continued)

Pin functions

Pin name

Main function

(2)

(after reset)

Alternate functions Additional functions

M6 36 27 H3 19

L6 37 28 G3 20

M7 38 -

L7 39 -

M8 40 -

L8 41 -

M9 42 -

L9 43 -

M10 44 -

M11 45 -

M12 46 -

L10 47 29 J2 21

L11 48 30 H2 22

H5 -

F12 49 31 J1 23

G12 50 32 H1 24

PB2

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB1

PB11

SS_1

DD_1

I/O FT PB1 TIM3_CH4/LCD_SEG6

I/O TC

I/O FT

I/O TC

PB2

/BOOT1

PE7

PE8 I/O TC

TC PE9

I/O FT

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

SS_1

DD_1

BOOT1

TIM2_CH1_ETR/

TIM5_ETR

TIM2_CH2

TIM2_CH3

TIM2_CH4/SPI1_NSS

SPI1_SCK

SPI1_MISO

SPI1_MOSI

TIM2_CH3/I2C2_SCL/

USART3_TX/

LCD_SEG10

TIM2_CH4/I2C2_SDA/

USART3_RX/

LCD_SEG11

ADC_IN9/

COMP1_INP/

VREF_OUT

VLCDRAIL1/

ADCIN0b

ADC_IN22/

COMP1_INP

ADC_IN23/

COMP1_INP

ADC_IN24/

COMP1_INP

ADC_IN25/

COMP1_INP

VLCDRAIL2

VLCDRAIL3

DocID022799 Rev 13 41/136

Pin descriptions STM32L151xC STM32L152xC

Pins

Table 9. STM32L151xC and STM32L152xC pin definitions (continued)

Pin functions

Pin name

Main function

(2)

(after reset)

Alternate functions Additional functions

L12 51 33 G2 25

K12 52 34 G1 26

K11 53 35 F3 27

K10 54 36 F2 28

K9 55 -

K8 56 -

J12 57 -

J11 58 -

J10 59 -

H12 60 -

H11 61 -

H10 62 -

E12 63 37 F1 -

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PC6

PB12

PB13

PB14

PB15

I/O FT

I/O

I/O FT

PB12

PB13

PB14

PB15

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PC6

TIM10_CH1

/I2C2_SMBA/

SPI2_NSS/I2S2_WS/

USART3_CK/

LCD_SEG12

TIM9_CH1/SPI2_SCK/

I2S2_CK/

USART3_CTS/

LCD_SEG13

TIM9_CH2/SPI2_MISO/

USART3_RTS/

LCD_SEG14

TIM11_CH1/SPI2_MOSI

/I2S2_SD/LCD_SEG15

USART3_TX/

LCD_SEG28

USART3_RX/

LCD_SEG29

USART3_CK/

LCD_SEG30

USART3_CTS/

LCD_SEG31

TIM4_CH1/

USART3_RTS/

LCD_SEG32

TIM4_CH2/LCD_SEG33

TIM4_CH3/LCD_SEG34

TIM4_CH4/LCD_SEG35

TIM3_CH1/I2S2_MCK/

LCD_SEG24

ADC_IN18/

COMP1_INP/

VLCDRAIL2

ADC_IN19/

COMP1_INP

ADC_IN20/

COMP1_INP

ADC_IN21/

COMP1_INP/

RTC_REFIN

42/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Pin descriptions

Pins

Table 9. STM32L151xC and STM32L152xC pin definitions (continued)

Pin functions

Pin name

Main function

(2)

(after reset)

Alternate functions Additional functions

E11 64 38 E1 -

E10 65 39 D1 -

D12 66 40 E2 -

D11 67 41 E3 29

D10 68 42 C1 30

C12 69 43 D2 31

B12 70 44 B1 32

A12 71 45 D3 33

A11 72 46 C2 34

C11 73 -

F11 74 47 A1 35

G11 75 48 B2 36

A10 76 49 C3 37

A9 77 50 A2 38

B11 78 51 B3 -

PA11

PA12

PA13

PH2

SS_2

DD_2

PA14

PC7

PC8

PC9

PA8

PA9

PA10

PA15

PC10

I/O FT

I/O

I/O FT

I/O

I/O FT

S -

I/O FT

PC7

PC8

PC9

PA8

PA9

PA10

PA11

PA12

JTMS-

SWDIO

PH2

SS_2

DD_2

JTCK-

SWCLK

JTDI

PC10

TIM3_CH2/I2S3_MCK/

LCD_SEG25

TIM3_CH3/LCD_SEG26

TIM3_CH4/LCD_SEG27

USART1_CK/MCO/

LCD_COM0

USART1_TX/

LCD_COM1

USART1_RX/

LCD_COM2

USART1_CTS/

SPI1_MISO

USART1_RTS/

SPI1_MOSI

JTMS-SWDIO

JTCK-SWCLK

TIM2_CH1_ETR/

SPI1_NSS/

SPI3_NSS/I2S3_WS/

LCD_SEG17/JTDI

SPI3_SCK/I2S3_CK/

USART3_TX/

LCD_SEG28/

LCD_SEG40/

LCD_COM4

USB_DM

USB_DP

DocID022799 Rev 13 43/136

Pin descriptions STM32L151xC STM32L152xC

Pins

Table 9. STM32L151xC and STM32L152xC pin definitions (continued)

Pin functions

Pin name

Main function

(2)

(after reset)

Alternate functions Additional functions

C10 79 52 A3

B10 80 53 B4 -

C9 81 -

B9 82 -

C8 83 54 A4 -

B8 84 -

B7 85 -

A6 86 -

B6 87 -

A5 88 -

A8 89 55 C4 39

A7 90 56 D4 40

C5 91 57 A5 41

PD3

PD4

PD5

PD6

PD7

PB3

PC11

PC12

PD0

PD1

PD2

PB4

PB5

I/O

PD5

PD6

PD7

I/O FT NJTRST

I/O

PC11

PC12

PD0

PD1

PD2

PD3

PD4

JTDO

PB5

SPI3_MISO/

USART3_RX/

LCD_SEG29/

LCD_SEG41/

LCD_COM5

SPI3_MOSI/I2S3_SD/

USART3_CK/

LCD_SEG30/

LCD_SEG42/

LCD_COM6

TIM9_CH1/SPI2_NSS/

I2S2_WS

SPI2_SCK/I2S2_CK

TIM3_ETR/LCD_SEG31

/LCD_SEG43/

LCD_COM7

SPI2_MISO/

USART2_CTS

SPI2_MOSI/I2S2_SD/

USART2_RTS

USART2_TX

USART2_RX

TIM9_CH2/USART2_CK

TIM2_CH2/SPI1_SCK/

SPI3_SCK/I2S3_CK/

LCD_SEG7/JTDO

TIM3_CH1/SPI1_MISO/

SPI3_MISO/LCD_SEG8

/NJTRST

TIM3_CH2/I2C1_SMBA/

SPI1_MOSI/SPI3_MOSI

/I2S3_SD/LCD_SEG9

COMP2_INM

COMP2_INP

44/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Pin descriptions

Pins

Table 9. STM32L151xC and STM32L152xC pin definitions (continued)

Pin functions

Pin name

Main function

(2)

(after reset)

Alternate functions Additional functions

92 58 B5 42

93 59 C5 43

A4 94 60 A6 44

PB6

PB7

BOOT0

I/O

PB6

PB7

BOOT0

TIM4_CH1/I2C1_SCL/

USART1_TX

TIM4_CH2/I2C1_SDA/

USART1_RX

COMP2_INP

COMP2_INP/PVD_IN

95 61 B6 45

96 62 C6 46

97 -

PB8

PB9

PE0

I/O

PB8

PB9

PE0

TIM4_CH3/TIM10_CH1/

I2C1_SCL/LCD_SEG16

TIM4_CH4/TIM11_CH1/

I2C1_SDA/LCD_COM3

TIM4_ETR/TIM10_CH1/

LCD_SEG36

A2 98 PE1 I/O FT PE1

TIM11_CH1/

LCD_SEG37

D3 99 63 A7 47

C4 100 64 B7 48

SS_3

DD_3

S -

SS_3

DD_3

1. I = input, O = output, S = supply.

2. Function availability depends on the chosen device.

3. Applicable to STM32L152xC devices only. In STM32L151xC devices, this pin should be connected to V

4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is ON (by setting the

LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose

PH0/PH1 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins section in the STM32L151xx, STM32L152xx and STM32L162xx reference manual (RM0038).

5. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is ON (by setting the HSEON bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the HSE oscillator is off ( after reset, the HSE oscillator is off ). The HSE has priority over the GPIO function.

DocID022799 Rev 13 45/136

Alternate functions

BOOT0

NRST

PA0-

WKUP1

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8

PA9

PA10

PA11

PA12

PA13

PA14

PA15

Port name

AFIO0 AFIO1 AFIO2

SYSTEM TIM2 TIM3/4/5

BOOT0 -

NRST -

TIM2_CH1_ ETR TIM5_CH1

TIM2_CH2 TIM5_CH2 -

TIM9/

10/11

TIM2_CH1_ETR

MCO -

JTMS-SWDIO -

JTCK-SWCLK -

Table 10. Alternate function input/output

Digital alternate function number

AFIO3 AFIO4 AFIO5 AFIO6 AFIO7

AFIO11

AFIO14 AFIO15

Alternate function

I2C1/2

SPI1/2 SPI3 USART1/2/3 LCD CPRI SYSTEM

USART2_CTS TIMx_IC1

SPI1_NSS

SPI3_NSS

I2S3_WS

SPI1_SCK -

SPI1_MISO -

SPI1_MOSI

SPI1_MISO -

SPI1_MOSI -

I2S3_WS

USART2_TX SEG1 TIMx_IC3

USART2_RX SEG2 TIMx_IC4

USART2_CK -

SEG3

SEG4

TIMx_IC3

TIMx_IC4

USART1_TX COM1 TIMx_IC2

USART1_RX COM2 TIMx_IC3

USART1_CTS

USART1_RTS

TIMx_IC4

TIMx_IC2

TIMx_IC3

SEG17 TIMx_IC4

EVENT OUT

PB13

PB14

PB15

PC0

PC1

PC2

PC3

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PB10

PB11

PB12

Port name

Table 10. Alternate function input/output (continued)

Digital alternate function number

AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7

AFIO11

AFIO14 AFIO15

Alternate function

SYSTEM TIM2 TIM3/4/5

TIM9/

10/11

I2C1/2 SPI1/2 SPI3 USART1/2/3 LCD CPRI

BOOT1 -

TIM3_CH3 -

TIM3_CH4 -

JTDO TIM2_CH2 -

I2S3_CK

SEG5

SEG6

SEG7 -

NJTRST -

TIM3_CH2 -

TIM4_CH1 -

TIM4_CH4 TIM11_CH1 I2C1_SDA

TIM2_CH3 -

I2C1_SCL -

TIM4_CH2 I2C1_SDA -

TIM4_CH3 TIM10_CH1 I2C1_SCL -

TIM2_CH4 -

TIM9_CH1 -

TIM9_CH2

TIM11_CH1 -

I2S2_WS

SPI2_SCK

I2S2_CK

SPI2_MISO

SPI2_MOSI

I2S2_SD

I2S3_SD

USART1_TX

SEG9 -

USART1_RX -

SEG16

COM3

USART3_CK SEG12

USART3_CTS SEG13

USART3_RTS SEG14

SEG15

SEG18 TIMx_IC1

SEG19 TIMx_IC2

SEG20 TIMx_IC3

SEG21 TIMx_IC4

SYSTEM

EVENT OUT

AFIO0

Port name

PC4

PC5

PC6

PC7

PC8

PC9

PC10

PC11

PC12

PC13-

WKUP2

PC14

OSC32_IN

PC15

OSC32_

OUT

PD0

PD1

PD2

SYSTEM

TIM2

AFIO1

Table 10. Alternate function input/output (continued)

Digital alternate function number

AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7

TIM3/4/5

TIM9/

10/11

TIM3_CH1 -

TIM3_CH2 -

TIM3_CH3 -

TIM3_CH4 -

AFIO11

AFIO14 AFIO15

Alternate function

I2C1/2 SPI1/2 SPI3 USART1/2/3

I2S2_MCK

I2S3_MCK

SPI3_SCK

I2S3_CK

USART3_TX

SPI3_MISO USART3_RX

SPI3_MOSI

I2S3_SD

USART3_CK

LCD CPRI SYSTEM

SEG22 TIMx_IC1

SEG23 TIMx_IC2

SEG24 TIMx_IC3

SEG25 TIMx_IC4

SEG26 TIMx_IC1

SEG27 TIMx_IC2

COM4/

SEG28/

SEG40

TIMx_IC3

COM5/

SEG29

/SEG41

COM6/

SEG30/

SEG42

TIMx_IC4

TIMx_IC2

EVENT OUT

TIM9_CH1 -

TIM3_ETR -

SPI2_NSS

I2S2_WS

SPI2 SCK

I2S2_CK

COM7/

SEG31/

SEG43

Port name

AFIO0

PD3

PD4

PE0

PE1

PE2

PE3

PD12

PD13

PD14

PD15

PD5

PD6

PD7

PD8

PD9

PD10

PD11

PE4

PE5

PE6-

WKUP3

PE7

SYSTEM TIM2

TRACECK -

TRACED0 -

TRACED1 -

TRACED2 -

TRACED3 -

AFIO1

Table 10. Alternate function input/output (continued)

Digital alternate function number

AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7

AFIO11

AFIO14 AFIO15

Alternate function

TIM3/4/5

TIM9/

10/11

I2C1/2

TIM9_CH2 -

TIM4_CH1 -

TIM4_CH2 -

TIM4_CH3 -

TIM4_CH4 -

TIM4_ETR TIM10_CH1

TIM11_CH1 -

SPI1/2 SPI3

SPI2_MISO -

SPI2_MOSI

I2S2_SD

TIM9_CH2

USART1/2/3 LCD

USART2_CTS -

USART2_RTS -

USART2_TX -

USART2_RX -

USART2_CK -

CPRI SYSTEM

TIMx_IC4

TIMx_IC1 OUT

TIMx_IC2

USART3_RX SEG29 TIMx_IC2

USART3_CK SEG30 TIMx_IC3

SEG35 TIMx_IC4

SEG36 TIMx_IC1

TIMx_IC4 EVENT OUT

Table 10. Alternate function input/output (continued)

Digital alternate function number

AFIO4 AFIO5 AFIO6 AFIO7 AFIO0 AFIO1 AFIO2 AFIO3

Port name

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PH0OSC

_IN

PH1OSC_

OUT

PH2

SYSTEM

TIM2 TIM3/4/5

TIM2_CH1_ETR TIM5_ETR

TIM2_CH2 -

TIM2_CH3 -

TIM2_CH4 -

TIM9/

10/11

Alternate function

I2C1/2

SPI1/2

SPI1_SCK -

SPI1_MISO -

SPI1_MOSI -

SPI3

USART1/2/3

AFIO11

AFIO14 AFIO15

LCD

CPRI SYSTEM

TIMx_IC2

TIMx_IC3

EVENT OUT

TIMx_IC2

TIMx_IC4

STM32L151xC STM32L152xC Memory mapping

Figure 9. Memory map

X&&&&&&&&

# RTEX -)NTERNAL

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MEMORY

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X&&&

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X&&

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RESERVED

$ATA %%02/-

RESERVED

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MEMORYDEPENDINGON

"//4PINS

X&&

$-!

RESERVED

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2##

RESERVED

#2#

RESERVED

53!24

RESERVED

30)

RESERVED

)7$'

77$'

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,#$

RESERVED

4)-

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393#&'

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#/-02)

RESERVED

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BYTE 53"

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DocID022799 Rev 13 51/136

Electrical characteristics STM32L151xC STM32L152xC

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3 σ ).

Unless otherwise specified, typical data are based on T

= 25 °C, V

1.65 V tested.

≤ V

= 3.6 V (for the

≤ 3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 10

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 11 .

Figure 10. Pin loading conditions Figure 11. Pin input voltage

0&8SLQ 0&8SLQ

& S)

9

52/136

DLF

DocID022799 Rev 13

DLG

STM32L151xC STM32L152xC

6.1.6 Power supply scheme

Figure 12. Power supply scheme

Electrical characteristics

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DocID022799 Rev 13 53/136

109

Electrical characteristics

6.1.7 Optional LCD power supply scheme

STM32L151xC STM32L152xC

Figure 13. Optional LCD power supply scheme

2SWLRQ

(;7

/&'

1[Q)

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1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open.

2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an external capacitance is needed for correct behavior of this converter.

Figure 14. Current consumption measurement scheme

1[Q)

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54/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 11: Voltage characteristics

Table 12: Current characteristics

, and

Table 13: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 11. Voltage characteristics

Ratings Min Max Unit

–V

External main supply voltage

(including V

DDA and V

)

(1)

Input voltage on five-volt tolerant pin

(2)

Input voltage on any other pin

| Δ V

DDx

| Variations between different V

DD power pins

SSX

− V

| Variations between all different ground pins

(3)

REF+

–V

DDA

ESD(HBM)

Allowed voltage difference for V

Electrostatic discharge voltage

(human body model)

REF+

> V

DDA

–0.3

−

0.3

see

4.0

+4.0

4.0

0.4

Section 6.3.11

1. All main power (V permitted range.

, V

DDA

) and ground (V

, V

SSA

) pins must always be connected to the external power supply, in the

2. V

maximum must always be respected. Refer to Table 12 for maximum allowed injected current values.

3. Include V

REF-

pin.

V mV

Symbol

Table 12. Current characteristics

Ratings Max.

Unit

VDD( Σ )

VSS( Σ )

(2)

VDD(PIN)

VSS(PIN)

Total current into sum of all V

DD_x

power lines (source)

Total current out of sum of all V

SS_x

Maximum current out of each VSS_x ground pin (sink)

(1)

ground lines (sink)

(1)

Maximum current into each V

DD_x

power pin (source)

(1)

100

-70

INJ(PIN)

(3)

Output current sunk by any I/O and control pin 25

Σ I

IO(PIN)

Output current sourced by any I/O and control pin

Total output current sunk by sum of all IOs and control pins

(2)

Total output current sourced by sum of all IOs and control pins

(2)

Injected current on five-volt tolerant I/O

(4)

, RST and B pins

Injected current on any other pin

(5)

Total injected current (sum of all I/O and control pins) (6)

- 25

-60

-5/+0

± 5 mA

Σ I

INJ(PIN)

± 25

1. All main power (V permitted range.

, V

DDA

) and ground (V

, V

SSA

) pins must always be connected to the external power supply, in the

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.

3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.17

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Electrical characteristics STM32L151xC STM32L152xC

4. Positive current injection is not possible on these I/Os. A negative injection is induced by V exceeded. Refer to

Table 11 for maximum allowed input voltage values.

. I

INJ(PIN)

must never be

5. A positive injection is induced by V exceeded. Refer to

> V

while a negative injection is induced by V

< V

. I

INJ(PIN)

must never be

6. When several inputs are submitted to a current injection, the maximum negative injected currents (instantaneous values).

Σ I

INJ(PIN)

is the absolute sum of the positive and

Symbol

STG

Table 13. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

6.3.1 General operating conditions

Symbol f

HCLK f

PCLK1 f

PCLK2

Table 14. General operating conditions

Parameter

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

Conditions

BOR detector disabled

BOR detector enabled, at power on

BOR detector disabled, after power on

DDA

(1)

Analog operating voltage

(ADC and DAC not used)

Analog operating voltage

(ADC or DAC used)

Must be the same voltage as

(2)

I/O input voltage

Power dissipation at TA = 85 °C for suffix 6 or TA = 105 °C for suffix 7 (4)

Min

1.8

1.65

1.8

FT pins; 2.0 V ≤

-0.3

FT pins; V

< 2.0 V

BOOT0 pin

-0.3

Any other pin

LQFP48 package

LQFP100 package

-0.3

LQFP64 package

UFQFPN48 package

UFBGA100

WLCSP63 package -

1.65

3.6

5.5

(3)

5.25

(3)

5.5

+0.3

364

465

435

625

339

408

Max

3.6

Unit

MHz

V mW

56/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Symbol

T A

T J

Table 14. General operating conditions (continued)

Parameter

Junction temperature range

Conditions Min Max

Ambient temperature for 6 suffix version Maximum power dissipation

(5)

–40 85

Ambient temperature for 7 suffix version Maximum power dissipation –40 105

6 suffix version

7 suffix version

–40

105

110

Unit

°C

1. When the ADC is used, refer to

Table 56: ADC characteristics

2. It is recommended to power V

and V

DDA

from the same source. A maximum difference of 300 mV between V

can be tolerated during power-up and up to 140 mV in operation.

and

3. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.

4. If T is lower, higher P

on page 128 ).

values are allowed as long as T

does not exceed T

max (see Table 73: Thermal characteristics

5. In low-power dissipation state, T

max (see

can be extended to -40°C to 105°C temperature range as long as T

Table 73: Thermal characteristics on page 128

does not exceed T

6.3.2 Embedded reset and power control block characteristics

The parameters given in the following table are derived from the tests performed under the

conditions summarized in Table 14

Symbol

Table 15. Embedded reset and power control block characteristics

Parameter Conditions Min Typ t

VDD

(1)

RSTTEMPO

(1)

Reset temporization

POR/PDR

BOR0

BOR1

BOR2

rise time rate

fall time rate

Power on/power down reset threshold

Brown-out reset threshold 0

Brown-out reset threshold 1

Brown-out reset threshold 2

BOR detector enabled

BOR detector disabled

BOR detector enabled

BOR detector disabled

rising, BOR enabled

rising, BOR disabled

(2)

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

1.67

1.69

1.87

1.96

2.22

2.31

0.4

1.3

1.7

1.76

1.93

2.03

2.30

2.41

0.7

1.5

Max Unit

1.74

1.8

1.97

2.07

3.3

1.6

1.65

2.35

2.44

∞

1000

∞

1000

µs/V ms

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Electrical characteristics STM32L151xC STM32L152xC

Table 15. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

BOR3

BOR4

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6 hyst

Brown-out reset threshold 3

Brown-out reset threshold 4

Programmable voltage detector threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Hysteresis voltage

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

BOR0 threshold

All BOR and PVD thresholds excepting BOR0

2.45

2.54

2.68

2.78

1.8

1.88

1.98

2.08

2.20

2.28

2.39

2.47

2.57

2.68

2.77

2.87

2.97

3.08

100 -

1. Guaranteed by characterization results.

2. Valid for device version without BOR at power up. Please see option “D” in Ordering information scheme for more details.

V mV

2.24

2.34

2.44

2.54

2.64

2.74

2.83

2.94

3.05

3.15

1.85

1.94

2.04

2.14

2.55

2.66

2.8

2.9

2.28

2.38

2.48

2.58

2.69

2.79

2.88

2.99

3.09

3.20

1.88

1.99

2.09

2.18

2.6

2.7

2.85

2.95

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STM32L151xC STM32L152xC Electrical characteristics

The parameters given in

Table 17 are based on characterization results, unless otherwise

specified.

Table 16. Embedded internal reference voltage calibration values

Calibration value name Description Memory address

VREFINT_CAL

Raw data acquired at temperature of 30 °C ±5 °C

DDA

= 3 V ±10 mV

0x1FF8 00F8 - 0x1FF8 00F9

Symbol

REFINT out

(1)

REFINT

VREFINT

VREF_MEAS

Coeff

(3)

Table 17. Embedded internal reference voltage

Parameter Conditions Min Typ Max Unit

Internal reference voltage

Internal reference current consumption

Internal reference startup time

– 40 °C < T

< +110 °C 1.202 1.224

DDA

and V

REF+

REFINT

voltage during

factory measure

Accuracy of factory-measured V

REF value

(2)

Including uncertainties due to ADC and

DDA

REF+

values

2.99

1.4

1.242

2.3

3.01

±5

Temperature coefficient –40 °C < T

< +110 °C 25

µA ms

V mV

100

1000 ppm/°

C ppm

2000 ppm/V

Coeff

(3)

DDCoeff

(3)

Long-term stability

Voltage coefficient

1000 hours, T= 25 °C

3.0 V < V

DDA

< 3.6 V

(4)

ADC sampling time when reading the internal reference voltage

Startup time of reference voltage buffer for ADC

BUF_ADC

Consumption of reference voltage buffer for ADC

VREF_OUT output current

VREF_OUT output load

(5)

13.5

LPBUF

(3)

Consumption of reference voltage buffer for VREF_OUT and COMP

730

REFINT_DIV1

(3)

REFINT_DIV2

(3)

REFINT_DIV3

(3)

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage -

1. Guaranteed by test in production.

2. The internal V

REF

value is individually measured in production and stored in dedicated EEPROM bytes.

3. Guaranteed by characterization results.

4. Shortest sampling time can be determined in the application by multiple iterations.

1200

µs

µA

µA pF nA

REFIN

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109

Electrical characteristics STM32L151xC STM32L152xC

5. To guarantee less than 1% VREF_OUT deviation.

6.3.4 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 14: Current consumption measurement scheme

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to the Dhrystone 2.1 code, unless otherwise specified. The current consumption values are derived from tests performed under ambient temperature T

= 25 °C and V

supply voltage conditions summarized in

Table 14: General operating conditions , unless otherwise specified.

The MCU is placed under the following conditions:

• All I/O pins are configured in analog input mode

• All peripherals are disabled except when explicitly mentioned.

• The Flash memory access time, 64-bit access and prefetch is adjusted depending on f

HCLK

frequency and voltage range to provide the best CPU performance.

• When the peripherals are enabled f

APB1

= f

APB2

= f

AHB

• When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or

HSE = 16 MHz (if HSE bypass mode is used).

• The HSE user clock applied to OSCI_IN input follows the characteristic specified in

Table 27: High-speed external user clock characteristics .

• For maximum current consumption V

= V

DDA

= 3.6 V is applied to all supply pins.

• For typical current consumption V

DD specified otherwise.

= V

DDA

= 3.0 V is applied to all supply pins if not

60/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Table 18. Current consumption in Run mode, code with data processing running from Flash

Symbol Parameter Conditions f

HCLK

Typ Max

(1)

Unit

(Run from

Flash)

Supply current in

Run mode, code executed from Flash f

HSE

= f

HCLK

up to 16

MHz included, f

HSE f

HCLK

/2 above 16 MHz

(PLL ON)

(2)

Range 2, V

CORE

VOS[1:0] = 10

=1.5 V

HSI clock source (16

MHz)

Range 3, V

CORE

VOS[1:0] = 11

=1.2 V

Range 1, V

CORE

VOS[1:0] = 01

=1.8 V

Range 2, V

CORE

VOS[1:0] = 10

=1.5 V

Range 1, V

CORE

VOS[1:0] = 01

=1.8 V

1 MHz

2 MHz

215

400

4 MHz 725

4 MHz 0.915

8 MHz

16 MHz

8 MHz

16 MHz

32 MHz

1.75

3.4

2.1

4.2

8.25

16 MHz

32 MHz

3.5

8.2

2.1

3.9

2.8

4.9

9.4

400

600

960

1.1

9.6

µA mA

MSI clock, 65 kHz

MSI clock, 524 kHz

MSI clock, 4.2 MHz

Range 3, V

CORE

VOS[1:0] = 11

=1.2 V

65 kHz 40.5

524 kHz 125

4.2 MHz 775

110

190

900

µA

1. Guaranteed by characterization results, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

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109

Electrical characteristics STM32L151xC STM32L152xC

Table 19. Current consumption in Run mode, code with data processing running from RAM

Symbol Parameter Conditions f

HCLK

Typ Max

(1)

Unit

(Run from

RAM)

Supply current in

Run mode, code executed from

RAM, Flash switched off f

HSE

= f

HCLK up to 16 MHz, included f

HSE

= f

16 MHz

HCLK

(PLL ON)

(2)

/2 above

HSI clock source (16

MHz)

Range 3,

CORE

=1.2 V VOS[1:0]

= 11

1 MHz

2 MHz

4 MHz

Range 2,

CORE

=1.5 V VOS[1:0]

= 10

4 MHz

8 MHz

16 MHz

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

8 MHz

16 MHz

32 MHz

Range 2,

CORE

=1.5 V VOS[1:0]

= 10

16 MHz

Range 1,

CORE

=1.8 V VOS[1:0]

= 01

32 MHz

185 240

345 410

645 880

(3)

0.755

1.4

1.5

1.8

3.6

7.15

2.1

3.5

2.8

4.1

8.3

2.95

7.15

3.5

8.4

µA mA

MSI clock, 65 kHz

MSI clock, 524 kHz

MSI clock, 4.2 MHz

Range 3,

CORE

=1.2 V VOS[1:0]

= 11

65 kHz

524 kHz

4.2 MHz

38.5

110

690

160

810

µA

Guaranteed by characterization results, unless otherwise specified.

Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

3. Guaranteed by test in production.

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STM32L151xC STM32L152xC Electrical characteristics

Symbol

(Sleep)

Parameter

Supply current in Sleep mode, Flash

OFF

Table 20. Current consumption in Sleep mode

Conditions f

HCLK

Range 3,

CORE

=1.2 V

VOS[1:0] = 11 f

HSE

= f

HCLK

up to

16 MHz included, f

HSE

= f

HCLK

/2 above 16 MHz (PLL

ON)

(2)

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

1 MHz

2 MHz

4 MHz

8 MHz

16 MHz

8 MHz

16 MHz

32 MHz

HSI clock source

(16 MHz)

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

16 MHz

32 MHz

Typ

78.5

140

165

310

590

350

680

1600

640

1600

MSI clock, 65 kHz

MSI clock, 524 kHz

MSI clock, 4.2 MHz

Range 3,

CORE

=1.2 V

VOS[1:0] = 11

Range 3,

CORE

=1.2 V

VOS[1:0] = 11

Supply current in Sleep mode, Flash

ON f

HSE

= f

HCLK

up to

16 MHz included, f

HSE

= f

HCLK

/2 above 16 MHz (PLL

ON)

(2)

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

65 kHz

524 kHz

4.2 MHz

1 MHz

2 MHz

4 MHz

8 MHz

16 MHz

8 MHz

16 MHz

32 MHz

150

180

320

605

380

695

1600

145

60.5

89.5

HSI clock source

(16 MHz)

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

Supply current in Sleep mode, Flash

MSI clock, 65 kHz

MSI clock, 524 kHz

MSI clock, 4.2 MHz

Range 3,

CORE

=1.2V

VOS[1:0] = 11

1. Guaranteed by characterization results, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)

16 MHz

32 MHz

65 kHz

524 kHz

4.2 MHz

650

1600

155

2200

220

µA

2200

320

460

840

540

1000

2100

210

130

190

910

Max

(1)

440

830

550

990

2100

130

195

310

890

Unit

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109

Electrical characteristics STM32L151xC STM32L152xC

Symbol Parameter

Table 21. Current consumption in Low-power run mode

Conditions Typ

DD (LP

Run)

Supply current in

Low-power run mode

All peripherals

OFF, code executed from RAM,

Flash switched

OFF, V

DD to 3.6 V

All executed

from

1.65 V to

3.6 V from 1.65 V peripherals

OFF, code from Flash, f f f f f f

MSI clock, 65 kHz

HCLK

MSI clock, 65 kHz

HCLK

= 32 kHz

MSI clock, 65 kHz

= 65 kHz

= 131 kHz

MSI clock, 65 kHz

= 32 kHz

= 65 kHz

= 131 kHz

MSI clock, 131 kHz

max

(LP Run)

Max allowed current in

Low-power run mode

from

1.65 V to

3.6 V

1. Guaranteed by characterization results, unless otherwise specified.

= -40 °C to 25 °C

= 85 °C

= 105 °C

=-40 °C to 25 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

8.6

200

Max

(1)

110

Unit

µA

64/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Table 22. Current consumption in Low-power sleep mode

Symbol Parameter Conditions Typ

(LP Sleep)

Supply current in

Low-power sleep mode

All peripherals

OFF, V

1.65 V to 3.6 V

TIM9 and

USART1

from enabled, Flash

ON, V

from

1.65 V to 3.6 V f

MSI clock, 65 kHz

HCLK

= 32 kHz

Flash OFF

= -40 °C to 25 °C f f f f

MSI clock, 65 kHz

HCLK

Flash ON

MSI clock, 65 kHz

HCLK

= 32 kHz

= 65 kHz,

Flash ON

MSI clock, 65 kHz

= 32 kHz

MSI clock, 65 kHz

HCLK

= 65 kHz f

MSI clock, 131 kHz

HCLK

= 131 kHz,

Flash ON f

MSI clock, 131 kHz

HCLK

= 131 kHz

= -40 °C to 25 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

max

(LP Sleep)

Max allowed current in

Low-power sleep mode

from 1.65 V to 3.6 V

1. Guaranteed by characterization results, unless otherwise specified.

4.4

Max

(1)

Unit

200

µA

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Electrical characteristics STM32L151xC STM32L152xC

Symbol

(Stop with RTC)

Table 23. Typical and maximum current consumptions in Stop mode

Parameter Conditions Typ Max (1) Unit

Supply current in

Stop mode with RTC enabled

RTC clocked by LSI or LSE external clock

(32.768kHz), regulator in LP mode,

HSI and HSE OFF

(no independent watchdog)

RTC clocked by LSE external quartz

(32.768kHz), regulator in LP mode,

HSI and HSE OFF

(no independent watchdog

(4)

LCD

OFF

LCD

(static duty)

(2)

= -40°C to 25°C

= 1.8 V

= -40°C to 25°C

= 55°C

1.15

1.4

= 85°C

= 105°C

= -40°C to 25°C 1.55

= 55°C 2.15

= 85°C

= 105°C

3.4

6.35

3.55

6.3

3.9

LCD

ON (1/8 duty)

(3)

= -40°C to 25°C

= 55°C

= 85°C

= 105°C

4.65

6.25

9.1

1.5

LCD

OFF

LCD

(static duty)

(2)

= -40°C to 25°C

= 55°C

= 85°C

= 105°C

= -40°C to 25°C

= 55°C

= 85°C

= 105°C

2.15

3.7

6.75

1.6

2.3

3.8

6.85

LCD

ON (1/8 duty)

(3)

= -40°C to 25°C

= 55°C

LCD

OFF

= 85°C

= 105°C

= -40°C to 25°C

= 1.8V

= -40°C to 25°C

= 3.0V

= -40°C to 25°C

= 3.6V

4.85

6.5

9.1

1.2

1.5

1.75

µA

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STM32L151xC STM32L152xC Electrical characteristics

Table 23. Typical and maximum current consumptions in Stop mode (continued)

Symbol Parameter Conditions Typ Max (1) Unit

(Stop)

(WU from

Stop)

Regulator in LP mode, HSI and

HSE OFF, independent watchdog and LSI enabled

= -40°C to 25°C 1.8

Supply current in

Stop mode (RTC disabled)

Regulator in LP mode, LSI, HSI and HSE OFF (no independent watchdog)

= -40°C to 25°C 0.435

= 55°C

= 85°C

0.99

2.4

= 105°C 5.5

MSI = 4.2 MHz 2

Supply current during wakeup from Stop mode

MSI = 1.05 MHz

MSI = 65 kHz

(6)

= -40°C to 25°C 1.45

1.45

2.2

(5)

µA mA

1. Guaranteed by characterization results, unless otherwise specified.

2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected.

3. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.

4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

5. Guaranteed by test in production.

6. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the remaining part of the wakeup period, the current corresponds the Run mode current.

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Electrical characteristics STM32L151xC STM32L152xC

Symbol

Table 24. Typical and maximum current consumptions in Standby mode

Parameter Conditions Typ Max (1) Unit

(Standby with RTC)

(Standby)

(WU from

Standby)

Supply current in

Standby mode with RTC enabled

= -40 °C to 25 °C

= 1.8 V

RTC clocked by LSI (no independent watchdog)

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 1.8 V

RTC clocked by LSE external quartz (no independent watchdog)

(3)

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

Independent watchdog and LSI enabled

= -40 °C to 25 °C

Supply current in

Standby mode (RTC disabled)

Independent watchdog and LSI OFF

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

Supply current during wakeup time from

Standby mode

= -40 °C to 25 °C

0.905

1.15

1.5

1.75

2.1

0.98

1.3

1.7

2.05

2.45

0.29

0.345

0.575

1.45

0.6

0.9

2.75

(2)

1.9

2.2

8.3

(2)

1.7

1. Guaranteed by characterization results, unless otherwise specified.

2. Guaranteed by test in production.

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF loading capacitors.

µA mA

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions:

• all I/O pins are in input mode with a static value at V

or V

(no load)

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

68/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

APB1

Peripheral

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

LCD

WWDG

SPI2

SPI3

USART2

USART3

I2C1

I2C2

USB

PWR

DAC

COMP

Table 25. Peripheral current consumption (1)

Typical consumption, V

= 3.0 V, T

= 25 °C

Range 1,

CORE

1.8 V

VOS[1:0] =

2.9

6.5

5.9

8.8

8.4

7.3

11.2

12.9

14.4

4.0

3.8

5.8

7.9

13.3

2.8

6.1

4.8

Range 2,

CORE

1.5 V

VOS[1:0] =

2.3

5.2

4.6

7.0

6.8

5.8

8.9

9.0

10.4

11.5

3.1

3.0

4.6

6.3

10.6

2.2

4.9

3.8

Range 3,

CORE

1.2 V

VOS[1:0] =

Low-power sleep and run

1.8

4.1

3.6

5.5

5.3

4.6

9.0

2.4

2.3

3.6

7.0

7.1

8.2

5.0

8.3

1.8

3.9

3.0

2.3

5.2

4.6

7.0

6.8

5.8

8.9

9.0

10.4

11.5

3.1

3.0

4.6

6.3

10.6

2.2

4.9

3.8

Unit

µA/MHz

HCLK

)

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109

Electrical characteristics STM32L151xC STM32L152xC

Table 25. Peripheral current consumption (1) (continued)

Typical consumption, V

= 3.0 V, T

= 25 °C

Peripheral

Range 1,

CORE

1.8 V

VOS[1:0] =

Range 2,

CORE

1.5 V

VOS[1:0] =

Range 3,

CORE

1.2 V

VOS[1:0] =

Low-power sleep and run

Unit

APB2

SYSCFG &

TIM9

TIM10

TIM11

ADC

(2)

SPI1

USART1

2.6

10.5

4.3

8.8

4.3

4.0

7.9

5.9

2.0

3.3

3.5

3.2

6.4

4.7

4.6

8.3

3.4

7.1

1.6

6.6

2.8

5.6

2.6

2.8

2.5

5.0

3.8

3.7

2.0

8.3

3.4

7.1

3.3

3.5

3.2

6.4

4.7

4.6

AHB

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOH

4.1

4.2

3.7

3.3

3.4

3.0

2.5

2.7

2.3

3.3

3.4

3.0

µA/MHz

HCLK

CRC

FLASH

DMA1

0.8

11.1

15.6

0.6

9.4

12.7

0.5

0.6

(3)

12.7

All enabled

DMA2 16.3

187

13.4

154

10.5

120

13.4

144.6

DD (RTC)

DD (LCD)

DD (ADC)

(4)

DD (DAC)

(5)

DD (COMP1)

Slow mode

DD (COMP2)

Fast mode

DD (PVD / BOR)

(6)

DD (IWDG)

0.4

3.1

1450

340

0.16

2.6

0.25

µA

1. Data based on differential I

(range 3), f

HCLK

measurement between all peripherals OFF an one peripheral with clock

HCLK

= 32 MHz (range 1), f

= 64kHz (Low-power run/sleep), f

APB1

= f

HCLK

, f

HCLK

= 16 MHz (range 2), f

= f each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling.

HCLK

= 4 MHz

, default prescaler value for

2. HSI oscillator is OFF for this measure.

)

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STM32L151xC STM32L152xC Electrical characteristics

3. In Low-power sleep and run mode, the Flash memory must always be in power-down mode.

4. Data based on a differential I

DD measurement between ADC in reset configuration and continuous ADC conversion (HSI consumption not included).

5. Data based on a differential I

DD measurement between DAC in reset configuration and continuous DAC conversion of V

/2. DAC is in buffered mode, output is left floating.

6. Including supply current of internal reference voltage.

6.3.5 Wakeup time from low-power mode

The wakeup times given in the following table are measured with the MSI RC oscillator. The clock source used to wake up the device depends on the current operating mode:

• Sleep mode: the clock source is the clock that was set before entering Sleep mode

• Stop mode: the clock source is the MSI oscillator in the range configured before entering Stop mode

• Standby mode: the clock source is the MSI oscillator running at 2.1 MHz

All timings are derived from tests performed under the conditions summarized in

Table 14 .

Symbol

Table 26. Low-power mode wakeup timings

Parameter Conditions Typ Max

(1)

Unit t t

WUSLEEP

WUSLEEP_LP

Wakeup from Sleep mode

Wakeup from Low-power sleep mode, f

HCLK

= 262 kHz f

HCLK

= 32 MHz f

HCLK

= 262 kHz

Flash enabled f

HCLK

= 262 kHz

Flash switched OFF

0.4

46 -

Wakeup from Stop mode, regulator in Run mode

ULP bit = 1 and FWU bit = 1 f

HCLK

= f

MSI

= 4.2 MHz 8.2

WUSTOP

Wakeup from Stop mode, regulator in low-power mode

ULP bit = 1 and FWU bit = 1 f

HCLK

= f

MSI

= 4.2 MHz

Voltage range 1 and 2 f

HCLK

= f

MSI

= 4.2 MHz

Voltage range 3

7.7

8.2

8.9

13.1

f f

HCLK

= f

MSI

= 2.1 MHz 10.2

HCLK

= f

MSI

= 1.05 MHz 16

13.4

HCLK

= f

MSI

= 524 kHz f

HCLK

= f

MSI

= 262 kHz

66 f

HCLK

= f

MSI

= 131 kHz f

HCLK

= MSI = 65 kHz

112

221

123

236 t

WUSTDBY

Wakeup from Standby mode

ULP bit = 1 and FWU bit = 1

Wakeup from Standby mode

FWU bit = 0 f f

HCLK

1. Guaranteed by characterization, unless otherwise specified

= MSI = 2.1 MHz

2.6

104

3.25

µs ms

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109

Electrical characteristics STM32L151xC STM32L152xC

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The

external clock signal has to respect the I/O characteristics in Section 6.3.12

. However, the

Symbol f

HSE_ext

Table 27. High-speed external user clock characteristics (1)

Parameter Conditions Min Typ Max Unit

User external clock source frequency

CSS is on or

PLL is used

CSS is off, PLL not used

MHz

HSEH

HSEL t w(HSEH) t w(HSEL) t r(HSE) t f(HSE)

C in(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

OSC_IN input capacitance

1. Guaranteed by design.

0.7V

2.6

0.3V

V ns pF

Figure 15. High-speed external clock source AC timing diagram

WZ+6(+

9+6(+

9+6(/

WU+6(

7+6(

WI+6( WZ+6(/

069

72/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Low-speed external user clock generated from an external source

The characteristics given in the following table result from tests performed using a low-

speed external clock source, and under the conditions summarized in Table 14

Symbol

Table 28. Low-speed external user clock characteristics (1)

Parameter f

LSE_ext

LSEH

User external clock source frequency

OSC32_IN input pin high level voltage

LSEL

OSC32_IN input pin low level voltage t w(LSEH) t w(LSEL) t r(LSE) t f(LSE)

IN(LSE)

OSC32_IN high or low time

OSC32_IN rise or fall time

OSC32_IN input capacitance

1. Guaranteed by design.

Conditions

Min

0.7V

465

Typ

32.768

0.6

Max Unit

1000 kHz

0.3V

V ns pF

Figure 16. Low-speed external clock source AC timing diagram

WZ/6(+

9/6(+

9/6(/

WU/6(

7/6(

WI/6(

WZ/6(/

069

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 29

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

DocID022799 Rev 13 73/136

109

Electrical characteristics STM32L151xC STM32L152xC

Symbol

Table 29. HSE oscillator characteristics (1)(2)

Parameter Conditions Min Typ Max Unit f

OSC_IN

Oscillator frequency

Feedback resistor

200

MHz k Ω

Recommended load capacitance versus equivalent serial resistance of the crystal

)

(3)

= 30 Ω 20 pF

HSE

HSE driving current V

= 3.3 V,

= V

SS with 30 pF load

3 mA

C = 20 pF f

OSC

= 16 MHz

2.5 (startup)

0.7 (stabilized)

DD(HSE)

HSE oscillator power consumption

2.5 (startup)

0.46 (stabilized) mA

C = 10 pF f

OSC

= 16 MHz g m

Oscillator transconductance

Startup 3.5

mA /V t

SU(HSE)

(4)

Startup time V

is stabilized 1 ms

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by characterization results.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 17

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

74/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Figure 17. HSE oscillator circuit diagram

+6(

WRFRUH

5HVRQDWRU

26&B,1

)

&RQVXPSWLRQ

FRQWURO

5HVRQDWRU

670

26&B287

DLE

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 30

Symbol

Table 30. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions Min Typ Max Unit f

LSE

Low speed external oscillator frequency

32.768

kHz

Feedback resistor 1.2

M Ω

(2)

Recommended load capacitance versus equivalent serial resistance of the crystal (R

)

(3)

LSE driving current

= 30 k Ω 8 pF

LSE

DD (LSE)

LSE oscillator current consumption

= 3.3 V, V

= V

= 1.8 V

= 3.0 V

= 3.6V

450

600

750

1.1

µA nA g m t

SU(LSE)

(4)

Oscillator transconductance

Startup time V

is stabilized

1 -

µA/V

1. Guaranteed by characterization results.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”.

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R

value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details.

DocID022799 Rev 13 75/136

109

Electrical characteristics STM32L151xC STM32L152xC

4. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Note: For C

and C

, it is recommended to use high-quality ceramic capacitors in the 5 pF to

15 pF range selected to match the requirements of the crystal or resonator (see Figure 18 ).

and C

L2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

Load capacitance C

C stray

has the following formula: C

= C

/ ( C

+ C

) + C stray

where

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF.

Caution: To avoid exceeding the maximum value of C

L1 to use a resonator with a load capacitance C

and C

(15 pF) it is strongly recommended

≤ 7 pF. Never use a resonator with a load capacitance of 12.5 pF.

Example: if the user chooses a resonator with a load capacitance of C

= 6 pF and C stray

2 pF, then C

= C

= 8 pF.

Figure 18. Typical application with a 32.768 kHz crystal

5HVRQDWRUZLWK

LQWHJUDWHGFDSDFLWRUV

N+]

UHVRQDWRU

26&B,1

)

%LDV

FRQWUROOHG

JDLQ

26&B287

/6(

670/[[

DLE

76/136 DocID022799 Rev 13

STM32L151xC STM32L152xC

6.3.7 Internal clock source characteristics

Electrical characteristics

The parameters given in

Table 31 are derived from tests performed under the conditions

summarized in

Table 14 .

High-speed internal (HSI) RC oscillator

Symbol

Table 31. HSI oscillator characteristics

Parameter Conditions Min Typ Max Unit f

HSI

TRIM

(1)(2)

ACC

HSI

(2)

Frequency

HSI user-trimmed resolution

Accuracy of the factory-calibrated

HSI oscillator

= 3.0 V

Trimming code is not a multiple of 16

Trimming code is a multiple of 16

DDA

= 3.0 V, T

= 25 °C

DDA

= 3.0 V, T

= 0 to 55 °C

DDA

= 3.0 V, T

= -10 to 70 °C

DDA

= 3.0 V, T

= -10 to 85 °C

DDA

= 3.0 V, T

= -10 to 105 °C

DDA

= 1.65 V to 3.6 V

= -40 to 105 °C

-1

(3)

-1.5

-2

-2.5

-4

± 0.4

0.7

± 1.5

1 (3) %

1.5

MHz

I t

SU(HSI)

(2)

DD(HSI)

(2)

HSI oscillator startup time

HSI oscillator power consumption

3.7

100

140

1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).

2. Guaranteed by characterization results.

3. Guaranteed by test in production.

µs

µA

Low-speed internal (LSI) RC oscillator

Table 32. LSI oscillator characteristics

Symbol Parameter Min Typ f

LSI

(1)

LSI frequency 26 38

LSI

(2) t su(LSI)

(3)

DD(LSI)

(3)

LSI oscillator frequency drift

0°C ≤ T

≤

LSI oscillator startup time

LSI oscillator power consumption

-10

400

1. Guaranteed by test in production.

2. This is a deviation for an individual part, once the initial frequency has been measured.

3. Guaranteed by design.

Max

200

510

Unit kHz

µs nA

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109

Electrical characteristics STM32L151xC STM32L152xC

Multi-speed internal (MSI) RC oscillator

Symbol f

MSI

Table 33. MSI oscillator characteristics

Parameter Condition

Frequency after factory calibration, done at

= 3.3 V and T

= 25 °C

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6

ACC

MSI

Frequency error after factory calibration

TEMP(MSI)

(1)

VOLT(MSI)

(1)

MSI oscillator frequency drift

0 °C ≤ T

105 °C

MSI oscillator frequency drift

1.65 V ≤ V

≤ 3.6 V, T

= 25 °C

DD(MSI)

(2) t

SU(MSI)

MSI oscillator power consumption

MSI oscillator startup time

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6,

Voltage range 1 and 2

MSI range 6,

Voltage range 3

Typ

65.5

131

262

524

1.05

2.1

4.2

± 0.5

± 3

0.75

1.5

2.5

4.5

3.5

Max Unit

kHz

MHz

2.5

%/V

µA

µs

78/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Symbol

Table 33. MSI oscillator characteristics (continued)

Parameter Condition t

STAB(MSI)

(2) f

OVER(MSI)

MSI oscillator stabilization time

MSI oscillator frequency overshoot

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6,

Voltage range 1 and 2

MSI range 3,

Voltage range 3

Any range to range 5

Any range to range 6

1. This is a deviation for an individual part, once the initial frequency has been measured.

2. Guaranteed by characterization results.

Typ

Max Unit

2.5

µs

MHz

DocID022799 Rev 13 79/136

109

Electrical characteristics STM32L151xC STM32L152xC

The parameters given in

Table 34 are derived from tests performed under the conditions

summarized in

Table 14 .

Table 34. PLL characteristics

Value

Symbol Parameter Unit

Min Typ Max (1) f

PLL_IN

PLL input clock

(2)

PLL input clock duty cycle

45 -

MHz

% t f

PLL_OUT

LOCK

PLL output clock

PLL lock time

PLL input = 16 MHz

PLL VCO = 96 MHz

115

160

MHz

µs

Jitter

DDA

(PLL)

Cycle-to-cycle jitter

Current consumption on V

DDA

Current consumption on V

220

120

± 600

450

150 ps

µA

1. Guaranteed by characterization results.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

The characteristics are given at T

= -40 to 105 °C unless otherwise specified.

RAM memory

Table 35. RAM and hardware registers

Symbol Parameter

VRM Data retention mode

(1)

Conditions

STOP mode (or RESET)

Min

1.65

Typ Max Unit

1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode).

80/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Flash memory and data EEPROM

Symbol

Table 36. Flash memory and data EEPROM characteristics

Parameter Conditions t

DD prog

Operating voltage

Read / Write / Erase

Programming/ erasing time for byte / word / double word / half-page

Erasing

Programming

Average current during the whole programming / erase operation

Maximum current (peak) during the whole programming / erase operation

= 25 °C, V

= 3.6 V

1. Guaranteed by design.

Min

1.65

Typ Max

(1)

3.28

600

1.5

3.6

3.94

900

2.5

Unit

V ms

µA mA

Symbol

Table 37. Flash memory and data EEPROM endurance and retention

Value

Parameter Conditions

Min

(1)

Typ Max

CYC

(2)

Cycling (erase / write)

Program memory

Cycling (erase / write)

EEPROM data memory

= -40°C to

105 °C t

RET

(2)

Data retention (program memory) after

10 kcycles at T

= 85 °C

Data retention (EEPROM data memory) after 300 kcycles at T

= 85 °C

Data retention (program memory) after

10 kcycles at T

= 105 °C

Data retention (EEPROM data memory) after 300 kcycles at T

= 105 °C

RET

= +85 °C

RET

= +105 °C

1. Guaranteed by characterization results.

2. Characterization is done according to JEDEC JESD22-A117.

300

10 -

Unit kcycles years

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109

Electrical characteristics STM32L151xC STM32L152xC

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

SS compliant with the IEC 61000-4-4 standard.

and

through a 100 pF capacitor, until a functional disturbance occurs. This test is

A device reset allows normal operations to be resumed.

The test results are given in

Table 38

. They are based on the EMS levels and classes defined in application note AN1709.

Table 38. EMS characteristics

Symbol

FESD

EFTB

Parameter Conditions

Level/

Class

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

= 3.3 V, LQFP100, T

= +25 °C, f

HCLK

= 32 MHz conforms to IEC 61000-4-2

= 3.3 V, LQFP100, T

= +25 f

°C,

HCLK

= 32 MHz conforms to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second.

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STM32L151xC STM32L152xC Electrical characteristics

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Symbol Parameter

EMI

Table 39. EMI characteristics

Max vs. frequency range

Conditions

Monitored frequency band

4 MHz voltage range 3

16 MHz voltage range 2

32 MHz voltage range 1

Unit

Peak level

= 3.3 V,

= 25 °C,

LQFP100 package compliant with IEC

61967-2

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

2.5

-6

-5

-7

1 dBµV

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114, ANSI/ESD STM5.3.1. standard.

Symbol

Table 40. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

Electrostatic discharge voltage

(human body model)

= +25 °C, conforming to JESD22-A114

ESD(CDM)

Electrostatic discharge voltage

(charge device model)

= +25 °C, conforming to ANSI/ESD STM5.3.1.

1. Guaranteed by characterization results.

2000

500

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109

Electrical characteristics STM32L151xC STM32L152xC

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol

Parameter

Table 41. Electrical sensitivities

Conditions

Static latch-up class T

= +105 °C conforming to JESD78A

Class

II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

(for standard pins) should be avoided during normal product operation.

or above V

However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator frequency deviation, LCD levels).

The test results are given in the

Table 42

Symbol

INJ

Table 42. I/O current injection susceptibility

Functional susceptibility

Description

Injected current on all 5 V tolerant (FT) pins

Injected current on BOOT0

Injected current on any other pin

Negative injection

-5

(1)

-0

-5

(1)

Positive injection

(2)

1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

2. Injection is not possible.

Unit mA

84/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 49

are derived from tests

performed under the conditions summarized in Table 14

. All I/Os are CMOS and TTL compliant.

Symbol

IH hys lkg

Parameter

Input low level voltage

Input high level voltage hysteresis (2)

Input leakage current

(4)

Table 43. I/O static characteristics

I/O Schmitt trigger voltage

Conditions Min

TC and FT I/O

BOOT0

TC I/O

FT I/O

BOOT0

TC and FT I/O

BOOT0

≤ V

I/Os with LCD

≤ V

I/Os with analog switches

≤ V

I/Os with analog switches and LCD

≤ V

I/Os with USB

0.45 V

+0.38

(2)

0.39 V

+0.59

(2)

0.15 V

+0.56

(2)

Typ

0.01

10% V

(3)

Max

0.3 V

(1)(2)

0.14 V

(2)

±50

±250

≤ V

TC and FT I/Os

FT I/O

≤ V

≤ 5V

±50

±10

Weak pull-up equivalent resistor

(5)(1)

Weak pull-down equivalent resistor

(5)

I/O pin capacitance 5 -

1. Guaranteed by test in production.

2. Guaranteed by design.

3. With a minimum of 200 mV.

4. The max. value may be exceeded if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order).

Unit

V nA

µA k Ω k Ω pF

DocID022799 Rev 13 85/136

109

Electrical characteristics STM32L151xC STM32L152xC

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA with the non-standard V

OH specifications given in

Table 44 .

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

• The sum of the currents sourced by all the I/Os on V

DD,

I consumption of the MCU sourced on V

DD,

VDD( Σ )

(see

Table 12

). plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

I consumption of the MCU sunk on V

VSS( Σ )

(see Table 12

plus the maximum Run

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in Table 44

are derived from tests

performed under the conditions summarized in Table 14

. All I/Os are CMOS and TTL compliant.

Symbol

Table 44. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)(2)

(2)(3)

(3)(4)

(1)(4)

(3)(4)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

2.7 V < V

1.65 V < V

= 8 mA

< 3.6 V

= 4 mA

= 20 mA

2.7 V < V

< 3.6 V

-0.45

-0.4

-1.3

0.4

0.45

1.3

1. The I

current sunk by the device must always respect the absolute maximum rating specified in Table 12

and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. Guaranteed by test in production.

3. The I

current sourced by the device must always respect the absolute maximum rating specified in

Table 12

and the sum of I

(I/O ports and control pins) must not exceed I

VDD

4. Guaranteed by characterization results.

86/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 19 and

Table 45 , respectively.

Unless otherwise specified, the parameters given in Table 45

are derived from tests

performed under the conditions summarized in Table 14

Table 45. I/O AC characteristics (1)

OSPEEDRx

[1:0] bit value (1)

Symbol Parameter Conditions Min Max

(2)

Unit

11 f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out t f(IO)out t r(IO)out

Maximum frequency

(3)

Output rise and fall time

Maximum frequency

(3)

Output rise and fall time

F max(IO)out

Maximum frequency

(3)

F max(IO)out

Maximum frequency

(3) t f(IO)out t r(IO)out

Output rise and fall time

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V

= 30 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V

= 30 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V

125

250

400

625

625 kHz ns

MHz ns

MHz

EXTIpw

Pulse width of external signals detected by the

EXTI controller

8 ns

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. The maximum frequency is defined in

Figure 19

DocID022799 Rev 13 87/136

109

Electrical characteristics STM32L151xC STM32L152xC

Figure 19. I/O AC characteristics definition

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AIC

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see Table 46 )

Unless otherwise specified, the parameters given in Table 46

are derived from tests

performed under the conditions summarized in Table 14

Symbol Parameter

Table 46. NRST pin characteristics

Conditions Min Typ Max Unit

IL(NRST)

(1)

IH(NRST)

(1)

NRST input low level voltage

NRST input high level voltage

0.39V

+0.59

0.3 V

OL(NRST)

(1)

NRST output low level voltage

= 2 mA

2.7 V < V

< 3.6 V

= 1.5 mA

1.65 V < V

< 2.7 V

0.4

V hys(NRST)

F(NRST)

(1)

NF(NRST)

(3)

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(3)

NRST input filtered pulse

NRST input not filtered pulse

350

10%V

(2)

1. Guaranteed by design.

2. With a minimum of 200 mV.

3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is around 10%.

V mV

Ω ns ns

88/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Figure 20. Recommended NRST pin protection

([WHUQDOUHVHWFLUFXLW

1567

538

)LOWHU

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)

670/[[

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1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip.

2. The user must ensure that the level on the NRST pin can go below the V

Table 46 . Otherwise the reset will not be taken into account by the device.

max level specified in

The parameters given in the

Table 47 are guaranteed by design.

Refer to Section 6.3.13: I/O port characteristics for details on the input/output ction

characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 47. TIMx (1) characteristics

Parameter Conditions Min t t res(TIM) f

EXT

Res

TIM

COUNTER

Timer resolution time

TIMxCLK

= 32 MHz 31.25

Timer external clock frequency on CH1 to CH4

Timer resolution

16-bit counter clock period when internal clock is selected (timer’s prescaler disabled) f

TIMxCLK

= 32 MHz

TIMxCLK

= 32 MHz 0.0312

MAX_COUNT

Maximum possible count

TIMxCLK

= 32 MHz -

1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.

Max

TIMxCLK

65536

2048 µs

65536 × 65536 t

TIMxCLK

134.2

Unit t

TIMxCLK ns

MHz

MHz bit t

TIMxCLK

DocID022799 Rev 13 89/136

109

Electrical characteristics STM32L151xC STM32L152xC

I

C interface characteristics

The device I

C interface meets the requirements of the standard I

C communication protocol with the following restrictions: SDA and SCL are not “true” open-drain I/O pins.

When configured as open-drain, the PMOS connected between the I/O pin and V

DD is disabled, but is still present.

The I

C characteristics are described in

Table 48

. Refer also to

Section 6.3.13: I/O port characteristics for more details on the input/output ction characteristics (SDA and SCL).

Symbol Parameter

Table 48. I 2 C characteristics

Standard mode

(1) (2)

Min Max

Fast mode I

(1) (2)

Unit

Min Max t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

4.7

4.0

250

3450

(3)

1000

300

1.3

0.6

100

900

(3)

300

µs ns t t su(STA) su(STO) t w(STO:STA) t

C b

Start condition hold time

Repeated Start condition setup time

Stop condition setup time

Stop to Start condition time

(bus free)

Capacitive load for each bus line

Pulse width of spikes that are suppressed by the analog filter

4.0

4.7

4.0

4.7

400

50 (4)

0.6

0.6 -

0.6

1.3

400

(4)

µs

μ pF ns

1. Guaranteed by design.

2. f

PCLK1 must be at least 2 MHz to achieve standard mode I ² C frequencies. It must be at least 4 MHz to achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast mode clock.

3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal.

4. The minimum width of the spikes filtered by the analog filter is above t

SP(max)

. s s

90/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Figure 21. I 2 C bus AC waveforms and measurement circuit s ͺ/Ϯ s ͺ/Ϯ

Ϯ ďƵƐ

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^dZdZWd

^dZd ƚ

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^dZd

^ ƚ

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Ś;^Ϳ

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1. R

= series protection resistor.

2. R

= external pull-up resistor.

3. V

DD_I2C

is the I2C bus power supply.

4. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

Table 49. SCL frequency (f

PCLK1

= 32 MHz, V

= V

DD_I2C

= 3.3 V)

(1)(2)

I2C_CCR value f

SCL

(kHz)

= 4.7 k Ω

400

300

200

100

0x801B

0x8024

0x8035

0x00A0

0x0140

0x0320

1. R

= External pull-up resistance, f

SCL

= I 2 C speed.

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ± 5%. For other speed ranges, the tolerance on the achieved speed is ± 2%. These variations depend on the accuracy of the external components used to design the application.

DocID022799 Rev 13 91/136

109

Electrical characteristics STM32L151xC STM32L152xC

SPI characteristics

Unless otherwise specified, the parameters given in the following table are derived from tests performed under the conditions summarized in

Table 14 .

Refer to Section 6.3.12: I/O current injection characteristics for more details on the

input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol Parameter

Table 50. SPI characteristics (1)

Conditions Min Max

(2)

Unit

Master mode f

SCK

1/t c(SCK)

SPI clock frequency Slave mode

Slave transmitter t t r(SCK)

(2) f(SCK)

(2)

SPI clock rise and fall time Capacitive load: C = 30 pF

DuCy(SCK) SPI slave input clock duty cycle Slave mode

(3)

MHz ns

% t su(NSS) t h(NSS) t t w(SCKH)

(2) w(SCKL)

(2) t su(MI)

(2) t su(SI)

(2) t h(MI)

(2) t h(SI)

(2) t a(SO)

(4) t v(SO)

(2) t v(MO)

(2) t h(SO)

(2) t h(MO)

(2)

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Data input hold time

Data output access time

Data output valid time

Data output hold time

Slave mode

Master mode

Slave mode

Master mode

Slave mode

Master mode

Slave mode

Master mode t

HCLK

SCK

/2 − 5 t

SCK

0.5

HCLK

/2+3

6.5

1. The characteristics above are given for voltage range 1.

2. Guaranteed by characterization results.

3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK)) ranging between 40 to 60%.

4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.

92/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Figure 22. SPI timing diagram - slave mode and CPHA = 0

Figure 23. SPI timing diagram - slave mode and CPHA = 1 (1)

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1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

DLE

DocID022799 Rev 13 93/136

109

Electrical characteristics STM32L151xC STM32L152xC

Figure 24. SPI timing diagram - master mode (1)

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1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

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94/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

USB characteristics

The USB interface is USB-IF certified (full speed).

Symbol

Table 51. USB startup time

Parameter t

STARTUP

(1)

USB transceiver startup time

1. Guaranteed by design.

Max

Unit

µs

Symbol

Table 52. USB DC electrical characteristics

Parameter Conditions Min.

(1)

Input levels

(2)

USB operating voltage

Differential input sensitivity I(USB_DP, USB_DM)

Differential common mode range Includes V

Single ended receiver threshold

Output levels

DI range

(3)

Static output level low

Static output level high

of 1.5

k Ω to 3.6 V

of 15 k Ω to V

1. All the voltages are measured from the local ground potential.

2. Guaranteed by characterization results.

3. Guaranteed by test in production.

4. R

is the load connected on the USB drivers.

(4)

3.0

0.2

0.8

1.3

2.8

Max.

(1) Unit

3.6

2.5

2.0

0.3

3.6

'LIIHUHQWLDO

GDWDOLQHV

9 &56

Figure 25. USB timings: definition of data signal rise and fall time

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9 66

W I W U

Table 53. USB: full speed electrical characteristics

Driver characteristics

(1)

Symbol t r t f t rfm

CRS

Rise time

(2)

Fall Time (2)

Parameter

Rise/ fall time matching

Output signal crossover voltage

Conditions

= 50 pF

= 50 pF t r

/t f

Min

1.3

Max

110

2.0

DLE

Unit ns ns

DocID022799 Rev 13 95/136

109

Electrical characteristics

Note:

STM32L151xC STM32L152xC

1. Guaranteed by design.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

I2S characteristics

Symbol Parameter

Table 54. I2S characteristics

Conditions f

MCK f

I2S Main Clock Output

I2S clock frequency

Master data: 32 bits

Slave data: 32 bits

CK t r(CK) t f(CK) t v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR)

I2S clock frequency duty cycle Slave receiver, 48KHz

I2S clock rise time

I2S clock fall time

WS valid time

WS hold time

WS setup time

WS hold time

Data input setup time

Data input hold time

Capacitive load CL=30pF

Master mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver t t v(SD_ST) h(SD_ST)

Data output valid time

Data output hold time

Slave transmitter

(after enable edge)

Slave transmitter

(after enable edge) t t v(SD_MT) h(SD_MT)

Data output valid time

Data output hold time

Master transmitter

(after enable edge)

Master transmitter

(after enable edge)

1. The maximum for 256xFs is 8 MHz

Min Max

256 x 8K 256xFs

(1)

64xFs

15 -

Unit

MHz

% ns

Refer to the I2S section of the product reference manual for more details about the sampling frequency (Fs), f

MCK

, f

and D

values. These values reflect only the digital peripheral behavior, source clock precision might slightly change them. DCK depends mainly on the

ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of

(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.

96/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Figure 26. I 2 S slave timing diagram (Philips protocol) (1)

1. Measurement points are done at CMOS levels: 0.3 × V

DD and 0.7 × V

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 27. I 2 S master timing diagram (Philips protocol) (1)

1. Guaranteed by characterization results.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

DocID022799 Rev 13 97/136

109

Electrical characteristics STM32L151xC STM32L152xC f

ADC

Unless otherwise specified, the parameters given in Table 56

are guaranteed by design.

Symbol Parameter

ADC clock frequency

Voltage range 1 & 2

Table 55. ADC clock frequency

Conditions

2.4 V ≤ V

DDA

≤

1.8 V ≤ V

DDA

≤

REF+ =

DDA

REF+

< V

DDA

> 2.4 V

REF+

< V

DDA

REF+

REF+ =

DDA

REF+

< V

DDA

Voltage range 3

Min

0.480

Max

Unit

MHz

Symbol

DDA

REF+

REF-

VDDA

Parameter

Power supply

Positive reference voltage

Negative reference voltage

Current on the V

DDA

input pin

VREF

(2)

AIN f

Current on the V

REF

input pin

Conversion voltage range

(3)

12-bit sampling rate

10-bit sampling rate

8-bit sampling rate

6-bit sampling rate

Table 56. ADC characteristics

Conditions

Peak

Average

Direct channels

Multiplexed channels

Direct channels

Multiplexed channels

Direct channels

Multiplexed channels

Direct channels

Multiplexed channels

Min

1.8

(1)

(4)

Typ Max

SSA

1000

400

3.6

DDA

1450

700

450

REF+

0.76

1.07

0.8

1.23

0.89

1.45

Unit

µA

Msps

98/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Symbol Parameter

Table 56. ADC characteristics (continued)

Conditions Min Typ Max Unit t

(5)

Sampling time

Direct channels

2.4 V ≤

DDA

3.6 V

Multiplexed channels

2.4 V ≤

DDA

3.6 V

Direct channels

1.8 V ≤

DDA

2.4 V

Multiplexed channels

1.8 V ≤

DDA

2.4 V

ADC

= 16 MHz

0.25

0.56

1 -

µs t

CONV

Total conversion time

(including sampling time)

384 1/f

ADC

24.75

µs

4 to 384 (sampling phase) +12

(successive approximation)

1/f

ADC

Internal sample and hold capacitor

Direct channels

Multiplexed channels

R f f

TRIG

AIN

(6)

External trigger frequency

Regular sequencer

External trigger frequency

Injected sequencer

Signal source impedance

12-bit conversions

6/8/10-bit conversions

12-bit conversions

6/8/10-bit conversions

Tconv+1 1/f

ADC

Tconv 1/f

ADC

Tconv+2 1/f

ADC

Tconv+1 1/f

ADC

50 k Ω

281 ns t lat t latr

Injection trigger conversion latency

Regular trigger conversion latency f f

ADC

= 16 MHz

219

3.5

156

2.5

4.5

219

3.5

1/f

ADC t

STAB

Power-up time 3.5

1. The Vref+ input can be grounded if neither the ADC nor the DAC are used (this allows to shut down an external voltage reference).

2. The current consumption through VREF is composed of two parameters:

- one constant (max 300 µA)

- one variable (max 400 µA), only during sampling time + 2 first conversion pulses

So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at

1Msps

3. V can be internally connected to V

Refer to Section 4: Pin descriptions

DDA

and V

for further details.

can be internally connected to V

SSA

, depending on the package.

4. V

SSA

or V

REF-

must be tied to ground.

5. Minimum sampling time is reached for an external input impedance limited to a value as defined in

Table 58: Maximum source impedance RAIN max

6. External impedance has another high value limitation when using short sampling time as defined in Table 58: Maximum source impedance RAIN max

1/f

ADC

µs

DocID022799 Rev 13 99/136

109

Electrical characteristics STM32L151xC STM32L152xC

Symbol Parameter

Table 57. ADC accuracy (1)(2)

Test conditions Min

(3)

Typ Max

(3)

Unit

Total unadjusted error

Offset error

Gain error

Differential linearity error

EL Integral linearity error

ENOB Effective number of bits

SINAD

Signal-to-noise and distortion ratio

SNR Signal-to-noise ratio

THD Total harmonic distortion

ENOB Effective number of bits

SINAD

Signal-to-noise and distortion ratio

SNR Signal-to-noise ratio

THD Total harmonic distortion

ET Total unadjusted error

EO Offset error

Gain error

Differential linearity error

Integral linearity error

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

2.4 V ≤ V

ADC

DDA

≤ 3.6 V

REF+

≤ 3.6 V

= 8 MHz, R

AIN

= -40 to 105 ° C

2.4 V ≤ V

DDA

= f

ADC input

= 50 Ω

DDA

≤ 3.6 V

REF+

= 16 MHz, R

AIN

= -40 to 105 ° C

=10kHz

= 50 Ω f

2.4 V ≤ V

DDA

≤ 3.6 V

1.8 V ≤ V

REF+

≤ 2.4 V

= 4 MHz, R

AIN

= 50 Ω

ADC

= -40 to 105 ° C f

1.8 V ≤ V

DDA

≤ 2.4 V

1.8 V ≤ V

REF+

≤ 2.4 V

= 4 MHz, R

AIN

= 50 Ω

ADC

= -40 to 105 ° C

9.2

57.5

9.2

57.5

1.5

1.7

-70

1.5

-70

1.5

3.5

-65

LSB bits dB bits

1.8 V ≤ V

DDA

≤ 2.4 V

V f

ADC

DDA

REF+

= 8 MHz or 4 MHz, R

AIN

= -40 to 105 ° C input

=10kHz

= 50 Ω

57.5

LSB

1. ADC DC accuracy values are measured after internal calibration.

2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

Section 6.3.12

does not affect the ADC

3. Guaranteed by characterization results.

1.5

-65

6.5

100/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Figure 28. ADC accuracy characteristics

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Figure 29. Typical connection diagram using the ADC

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1. Refer to Table 58: Maximum source impedance RAIN max for the value of R

characteristics for the value of C

ADC

AIN

and Table 56: ADC

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 this, f

ADC pF). A high C

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

DocID022799 Rev 13 101/136

109

Electrical characteristics STM32L151xC STM32L152xC

Figure 30. Maximum dynamic current consumption on V

REF+ conversion

supply pin during ADC

Conversion (12 cycles )

ADC clock

I ref+

700µA

Sampling (n cycles)

300µA

MS36686V1

1.5

Table 58. Maximum source impedance R

AIN

max (1)

AIN

max (k Ω )

(µs)

Multiplexed channels Direct channels

0.25

0.5625

2.4 V < V

DDA

< 3.6 V 1.8 V < V

DDA

< 2.4 V 2.4 V < V

DDA

< 3.6 V 1.8 V < V

DDA

< 2.4 V

Not allowed

0.8

Not allowed

0.7

2.0

Not allowed

1.0

Ts (cycles) f

ADC

=16 MHz

(2)

2.0

3.0

6.8

15.0

32.0

50.0

0.8

1.8

4.0

10.0

25.0

50.0

4.0

6.0

15.0

30.0

50.0

3.0

4.5

10.0

20.0

40.0

50.0

192

384

1. Guaranteed by design.

2. Number of samples calculated for f = 16 MHz. For f with respect to the minimum sampling time Ts (µs),

ADC

= 8 and 4 MHz the number of sampling cycles can be reduced

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 12

. The applicable procedure depends on whether V

REF+

is connected to V

DDA

or not. The 100 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip.

102/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

Data guaranteed by design, unless otherwise specified.

Symbol

DDA

REF+

REF-

DDVREF+

(1)

DDA

(1)

(2)

Parameter

Table 59. DAC characteristics

Conditions

Analog supply voltage -

Reference supply voltage

Lower reference voltage

REF+

must always be below

DDA

Current consumption on

REF+

supply

= 3.3 V

Current consumption on

DDA

supply

= 3.3 V

No load, middle code (0x800)

No load, worst code (0x000)

No load, middle code (0x800)

No load, worst code (0xF1C)

Resistive load

Capacitive load

DAC output buffer ON

Connected to

SSA

Conected to

DDA

DAC output buffer ON

Output impedance DAC output buffer OFF

Min

1.8

DAC output buffer ON 0.2

DAC_OUT

Voltage on DAC_OUT output

DAC output buffer OFF 0.5

DNL

INL

(1)

Offset (1)

Offset1 (1)

Differential non linearity

0x001

(6)

(3)

Integral non linearity

(4)

Offset error at code

0x800

(5)

Offset error at code

≤

≥ 5 k Ω

DAC output buffer ON

No R

, C

≤ 50 pF

DAC output buffer OFF

≤

≥ 5 k Ω

DAC output buffer ON

No R

, C

≤ 50 pF

DAC output buffer OFF

≤

≥ 5 k Ω

DAC output buffer ON

No R

, C

≤ 50 pF

DAC output buffer OFF

No R

, C

≤ 50 pF

DAC output buffer OFF

1.5

±10

±5

±1.5

Typ

SSA

130

220

210

320

Max

3.6

Unit

220

350

320

520

µA k Ω pF k Ω

DDA

– 0.2

REF+

1LSB

– mV

±25

±8

±5

LSB

DocID022799 Rev 13 103/136

109

Electrical characteristics STM32L151xC STM32L152xC

Symbol Parameter

Table 59. DAC characteristics (continued)

Conditions t t dOffset/dT

(1)

Gain

(1) dGain/dT

TUE

(1)

SETTLING

(1)

Update rate

WAKEUP

PSRR+

Offset error temperature coefficient (code 0x800)

DDA

REF+

= 3.3V

= 3.0V

= 0 to 50 ° C

DAC output buffer OFF

DDA

REF+

= 3.3V

= 3.0V

= 0 to 50 ° C

DAC output buffer ON

Gain error

(7)

≤

≥ 5 k Ω

DAC output buffer ON

No R

, C

≤ 50 pF

DAC output buffer OFF

Gain error temperature coefficient

Total unadjusted error

DDA

REF+

= 3.3V

= 3.0V

= 0 to 50 ° C

DAC output buffer OFF

DDA

REF+

= 3.3V

= 3.0V

= 0 to 50 ° C

DAC output buffer ON

≤

≥ 5 k Ω

DAC output buffer ON

No R

, C

≤ 50 pF

DAC output buffer OFF

Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes till

DAC_OUT reaches final value ±1LSB

≤

≥ 5 k Ω

Max frequency for a correct DAC_OUT change (95% of final value) with 1 LSB variation in the input code

DDA

supply rejection ratio (static DC measurement)

Wakeup time from off state (setting the ENx bit in the DAC Control register)

(8)

≤

≥ 5 k Ω

≤

≥ 5 k Ω

1. Data based on characterization results.

2. Connected between DAC_OUT and VSSA.

3. Difference between two consecutive codes - 1 LSB.

Min

-20

-10

-40

Typ

-10

Max

+0.1 / -0.2% +0.2 / -0.5%

+0 / -0.2% +0 / -0.4%

-2

-8

-60 -35

Unit

µV/°C

LSB

µs

Msps

µs dB

104/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

5. Difference between the value measured at Code (0x800) and the ideal value = V

REF+

/2.

6. Difference between the value measured at Code (0x001) and the ideal value.

7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (V

DDA

– 0.2) V when buffer is ON.

8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

Figure 31. 12-bit buffered /non-buffered DAC

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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

Symbol

Table 60. Operational amplifier characteristics

Parameter

CMIR

OFFSET

Δ VI

OFFSET

LOAD

CMRR

Common mode input range

Input offset voltage

Maximum calibration range

After offset calibration

Input offset voltage drift

Normal mode

Low-power mode

Input current bias

Drive current

Consumption

Common mode rejection ration

Dedicated input

General purpose input

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

Condition

(1)

75 °C

No load, quiescent mode

Min

(2)

Typ

100

-85

-90

Max

(2)

± 15

Unit mV

± 1.5

± 40

± 80

500

100

220

µV/°C nA

µA

µA dB

DocID022799 Rev 13 105/136

109

Electrical characteristics STM32L151xC STM32L152xC

Symbol

Table 60. Operational amplifier characteristics (continued)

Parameter Condition (1) Min (2) Typ Max (2) Unit

PSRR

GBW

Power supply rejection ratio

Bandwidth

Normal mode

Low-power mode

Normal mode

Low-power mode

>2.4 V

Normal mode

Low-power mode

<2.4 V

Normal mode

>2.4 V

(between 0.1 V and

-0.1 V)

Low-power mode V

>2.4 V

Normal mode

Low-power mode

<2.4 V

400

150

200

-85

-90

1000

300

500

150

700

3000

800

2200

800

dB kHZ

SR Slew rate

100

300

50 -

AO Open loop gain

Normal mode

Low-power mode

100

110

VOH

SAT

VOL

SAT ϕ m

Resistive load

Capacitive load

High saturation voltage

Low saturation voltage

Phase margin

Gain margin

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

<2.4 V

LOAD

= max or

= min

100

-50 -

-12

100

OFFTRIM

Offset trim time: during calibration, minimum time needed between two steps to have 1 mV accuracy

1 t

WAKEUP

Wakeup time

Normal mode

Low-power mode

≤ 50 pf,

≥ 4 k Ω

≤ 50 pf,

≥ 20 k Ω

30 -

1. Operating conditions are limited to junction temperature (0 °C to 105 °C) when V ambient temperature range (-40 °C to 85 °C, -40 °C to 105 °C).

is below 2 V. Otherwise to the full

2. Guaranteed by characterization results.

V/ms dB k pF mV

Ω dB ms

µs

106/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

6.3.20 Temperature sensor characteristics

Table 61. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at temperature of 30 °C ± 5 °C

DDA

= 3 V ± 10 mV

TS ADC raw data acquired at temperature of 110 °C ± 5 °C

DDA

= 3 V ± 10 mV

0x1FF8 00FA - 0x1FF8 00FB

0x1FF8 00FE - 0x1FF8 00FF

Symbol

(1)

Avg_Slope

110

DDA (TEMP)

(3) t

START

(3)

S_temp

(3)

(1)

Table 62. Temperature sensor characteristics

Parameter

SENSE

linearity with temperature

Average slope

Voltage at 110°C ±5°C

(2)

Current consumption

Startup time

ADC sampling time when reading the temperature

Min

1.48

612

Typ

1.61

626.8

3.4

Max

± 2

1.75

641.5

1. Guaranteed by characterization results.

2. Measured at V

= 3 V ±10 mV. V110 ADC conversion result is stored in the TS_CAL2 byte.

3. Guaranteed by design.

6.3.21 Comparator

Symbol

Table 63. Comparator 1 characteristics

Parameter Conditions Min

(1)

DDA

400K

10K

IN t

START td

Analog supply voltage

400K

value

10K

value

Comparator 1 input voltage range

Comparator startup time

Propagation delay

(2)

Voffset Comparator offset

Voffset

/dt

COMP1

Comparator offset variation in worst voltage stress conditions

Current consumption

(3)

DDA

IN+

IN-

= 3.6 V

= 0 V

= V

REFINT

= 25 ° C

1.65

0.6

Typ

400

± 3

1.5

160

Max

(1)

3.6

DDA

± 10

260

µs

Unit

V k Ω

Unit

°C mV/°C mV

µA

µs mV mV/1000 h nA

DocID022799 Rev 13 107/136

109

Electrical characteristics STM32L151xC STM32L152xC

1. Guaranteed by characterization results.

2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.

3. Comparator consumption only. Internal reference voltage not included.

Symbol

Table 64. Comparator 2 characteristics

Parameter Conditions Min Typ Max

(1)

Unit

I t t

DDA

IN t

START d slow

V d fast offset dThreshold/ dt

COMP2

Analog supply voltage

Comparator 2 input voltage range

Comparator startup time

Fast mode

Slow mode

Propagation delay

(2)

in slow mode

Propagation delay

(2)

in fast mode

1.65 V ≤ V

DDA

≤

2.7 V ≤

DDA

≤ 3.6 V

1.65 V ≤ V

DDA

≤

2.7 V ≤

DDA

≤ 3.6 V

Comparator offset error

Threshold voltage temperature coefficient

Current consumption

(3)

DDA

V- =V

3/4 V

REFINT

1/2 V

1/4 V

= 3.3V

= 0 to 50 ° C

REFINT

Fast mode

1.65

0 -

1.8

2.5

0.8

1.2

± 4

3.5

0.5

3.6

DDA

3.5

µs

± 20 mV

100

1. Guaranteed by characterization results.

2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.

3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not included.

ppm

/°C

µA

108/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Electrical characteristics

The device embeds a built-in step-up converter to provide a constant LCD reference voltage independently from the V

LCD

voltage. An external capacitor C

pin to decouple this converter.

ext

must be connected to the

Symbol

Table 65. LCD controller characteristics

Parameter Min Typ Max Unit

LCD

LCD0

LCD1

LCD2

LCD3

LCD4

LCD5

LCD6

LCD7

C ext

LCD external voltage

LCD internal reference voltage 0

LCD internal reference voltage 1

LCD internal reference voltage 2

LCD internal reference voltage 3

LCD internal reference voltage 4

LCD internal reference voltage 5

LCD internal reference voltage 6

LCD internal reference voltage 7 -

2.6

2.73

2.86

2.98

3.12

3.26

3.4

3.55

3.6

LCD

(1)

LCD

external capacitance

Supply current at V

= 2.2 V

Supply current at V

= 3.0 V

Low drive resistive network overall value

0.1

3.3

3.1

µF

µA

Htot

(2)

High drive resistive network total value

Segment/Common highest level voltage

Segment/Common 3/4 level voltage

Segment/Common 2/3 level voltage

Segment/Common 1/2 level voltage

Segment/Common 1/3 level voltage

Segment/Common 1/4 level voltage

Segment/Common lowest level voltage

5.28

192

6.6

240

3/4 V

2/3 V

1/2 V

1/3 V

1/4 V

LCD

7.92

288

LCD

M k

Δ Vxx

(3)

Segment/Common level voltage error

= -40 to 105 ° C

± 50 mV

1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected.

2. Guaranteed by design.

3. Guaranteed by characterization results.

DocID022799 Rev 13 109/136

109

Package information STM32L151xC STM32L152xC

7.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package information

Figure 32. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline

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1. Drawing is not to scale.

Table 66. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

0.050

1.350

1.400

1.600

0.150

1.450

0.0020

0.0531

0.0551

0.0630

0.0059

0.0571

DocID022799 Rev 13

STM32L151xC STM32L152xC Package information

Table 66. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max

E1 b c

0.170

0.090

15.800

13.800

15.800

13.800

0.220

16.000

14.000

12.000

16.000

14.000

0.270

0.200

16.200

14.200

16.200

14.200

E3 e

0.450

12.000

0.500

0.600

1.000

0.750

0.0177

k ccc

0.0°

3.5°

7.0°

0.080

0.0°

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0067

0.0035

0.6220

0.5433

0.6220

0.5433

0.4724

0.0197

0.0236

0.0394

3.5°

0.0087

0.6299

0.5512

0.4724

0.6299

0.5512

0.0295

7.0°

0.0031

0.0106

0.0079

0.6378

0.5591

0.6378

0.5591

Figure 33. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint

1. Dimensions are in millimeters.

DocID022799 Rev 13

069

111/136

135

Package information STM32L151xC STM32L152xC

LQFP100 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 34. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example

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1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

112/136 DocID022799 Rev 13

STM32L151xC STM32L152xC

7.2

Package information

LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package information

Figure 35. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline

6($7,1*3/$1(

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1. Drawing is not to scale.

Table 67. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

D1 b c

0.050

1.350

0.170

0.090

1.400

0.220

12.000

10.000

7.500

12.000

10.000

1.600

0.150

1.450

0.270

0.200

0.0020

0.0531

0.0067

0.0035

0.0551

0.0087

0.4724

0.3937

0.2953

0.4724

0.3937

0.0630

0.0059

0.0571

0.0106

0.0079

DocID022799 Rev 13 113/136

135

Package information STM32L151xC STM32L152xC

Table 67. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data

(continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max

L1 ccc

E3 e

0°

0.450

7.500

0.500

3.5°

0.600

1.000

7°

0.750

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0°

0.0177

0.2953

0.0197

3.5°

0.0236

0.0394

7°

0.0295

0.0031

Figure 36. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package recommended footprint

1. Dimensions are in millimeters.

114/136 DocID022799 Rev 13

AIC

STM32L151xC STM32L152xC Package information

LQFP64 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 37. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example

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5HYLVLRQFRGH

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DocID022799 Rev 13 115/136

135

Package information

7.3

STM32L151xC STM32L152xC

LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package information

Figure 38. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline

3%!4).'

0,!.%

CCC #

'!5'%0,!.%

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

"?-%?6

116/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Package information

Table 68. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max e

E3 k ccc b c

0.050

1.350

0.170

0.090

8.800

6.800

0.450

0°

- 1.600

- 0.150

1.400

1.450

0.220

9.000

7.000

- 5.500

8.800

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

0.270

0.200

9.200

7.200

9.200

7.200

0.750

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

- 0.2165

0.3465

0.3543

0.2677

0.2756

0.2165

0.0177

0°

0.0197

0.0236

0.0394

3.5°

- 0.0630

- 0.0059

0.0551

0.0571

0.0087

0.3543

0.2756

0.0106

0.0079

0.3622

0.2835

0.3622

0.2835

0.0295

7°

0.0031

Figure 39. LQFP48 recommended footprint

1. Dimensions are in millimeters.

DocID022799 Rev 13

AID

117/136

135

Package information STM32L151xC STM32L152xC

LQFP48 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 40. LQFP48 package top view example

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118/136 DocID022799 Rev 13

STM32L151xC STM32L152xC

7.4

Package information

UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information

Figure 41. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline

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1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground.

DocID022799 Rev 13 119/136

135

Package information STM32L151xC STM32L152xC

Table 69. UFQFPN48 – ultra thin fine pitch quad flat pack no-lead 7 × 7 mm,

0.5 mm pitch package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

T b e ddd

0.500

0.000

6.900

5.500

0.300

0.200

0.550

0.020

7.000

5.600

0.400

0.152

0.250

0.500

0.600

0.050

7.100

5.700

0.500

0.300

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0000

0.2717

0.2165

0.0118

0.0079

0.0217

0.0008

0.2756

0.2205

0.0157

0.0060

0.0098

0.0197

0.0236

0.0020

0.2795

0.2244

0.0197

0.0118

0.0031

Figure 42. UFQFPN48 recommended footprint

120/136

1. Dimensions are in millimeters.

DocID022799 Rev 13

!"?&0?6

STM32L151xC STM32L152xC Package information

UFQFPN48 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 43. UFQFPN48 package top view example

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DocID022799 Rev 13 121/136

135

Package information

7.5

STM32L151xC STM32L152xC

UFBGA100, 7 x 7 mm, 100-ball ultra thin, fine pitch ball grid array package information

Figure 44. UFBGA100, 7 x 7 mm, 0.5 mm pitch package outline

= 6HDWLQJSODQH

GGG =

$ $

(

)

$ $

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1. Drawing is not to scale.

Table 70. UFBGA100, 7 x 7 mm, 0.5 mm pitch package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

E1 e

F ddd

A4 b

5.450

6.950

5.450

0.700

0.460

0.050

0.400

0.080

0.270

0.200

6.950

5.500

7.000

5.500

0.500

0.750

0.530

0.080

0.450

0.130

0.320

0.250

7.000

5.550

7.050

5.550

0.800

0.100

0.600

0.110

0.500

0.180

0.370

0.300

7.050

0.2146

0.2736

0.2146

0.0276

0.0181

0.0020

0.0157

0.0031

0.0106

0.0079

0.2736

0.2165

0.2756

0.2165

0.0197

0.0295

0.0209

0.0031

0.0177

0.0051

0.0126

0.0098

0.2756

0.2185

0.2776

0.2185

0.0315

0.0039

0.0236

0.0043

0.0197

0.0071

0.0146

0.0118

0.2776

122/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Package information

Table 70. UFBGA100, 7 x 7 mm, 0.5 mm pitch package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max eee fff

0.150

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0059

0.0020

Figure 45. UFBGA100, 7 x 7 mm, 0.5 mm pitch, package recommended footprint

'SDG

'VP

$&B)3B9

Table 71. UFBGA100, 7 x 7 mm, 0.50 mm pitch, recommended PCB design rules

Dimension Recommended values

Pitch

Dpad

Dsm

Stencil opening

Stencil thickness

0.5

0.280 mm

0.370 mm typ. (depends on the soldermask registration tolerance)

0.280 mm

Between 0.100 mm and 0.125 mm

DocID022799 Rev 13 123/136

135

Package information STM32L151xC STM32L152xC

UFBGA100 device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 46. UFBGA100, 7 x 7 mm, 0.5 mm pitch, package top view example

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124/136 DocID022799 Rev 13

STM32L151xC STM32L152xC

7.6

Package information

WLCSP63, 0.400 mm pitch wafer level chip size package information

Figure 47. WLCSP63, 0.400 mm pitch wafer level chip size package outline

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1. Drawing is not to scale.

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DocID022799 Rev 13 125/136

135

Package information STM32L151xC STM32L152xC

Table 72. WLCSP63, 0.400 mm pitch wafer level chip size package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

G aaa bbb ccc ddd eee

Øb

A2 e e1 e2

0.540

0.240

3.193

4.129

0.570

0.190

0.380

0.025

0.270

3.228

4.164

0.400

2.400

3.200

0.414

0.482

0.0213

0.0094

0.1257

0.1626

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.100

0.050

0.600

0.300

3.263

4.199

0.0157

0.0945

0.1260

0.0163

0.0190

0.0224

0.0075

0.0150

0.0010

0.0106

0.1271

0.1639

0.0039

0.0020

0.0236

0.0118

0.1285

0.1653

126/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Package information

WLCSP63 device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 48. WLCSP63 device marking example

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DocID022799 Rev 13 127/136

135

Package information STM32L151xC STM32L152xC

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

max = T

max + (P

max × Θ

)

Where:

• T

max is the maximum ambient temperature in ° C,

• Θ

is the package junction-to-ambient thermal resistance, in ° C/W,

• P

max is the sum of P

INT

max and P

I/O max (P

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Table 73. Thermal characteristics

Symbol Parameter

Thermal resistance junction-ambient

UFBGA100 - 7 x 7 mm

Thermal resistance junction-ambient

LQFP100 - 14 x 14 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP64 - 10 x 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

WLCSP63 - 0.400 mm pitch

Thermal resistance junction-ambient

LQFP48 - 7 x 7 mm / 0.5 mm pitch

Thermal resistance junction-ambient

UFQFPN48 - 7 x 7 mm / 0.5 mm pitch

Value

Unit

°C/W

128/136 DocID022799 Rev 13

STM32L151xC STM32L152xC

Figure 49. Thermal resistance suffix 6

Package information

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8)4)31[PP

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JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

DocID022799 Rev 13 129/136

135

Part numbering STM32L151xC STM32L152xC

Table 74. STM32L151xC and STM32L152xC ordering information scheme

Example: STM32 L 151 R C T 6 D TR

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

L = Low-power

Device subfamily

151: Devices without LCD

152: Devices with LCD

Pin count

C = 48 pins

U = 63 pins

R = 64 pins

V = 100 pins

Flash memory size

C = 256 Kbytes of Flash memory

Package

H = BGA

T = LQFP

Y = WLCSP

U = UFQFPN

Temperature range

6 = Industrial temperature range, –40 to 85 °C

7 = Industrial temperature range, –40 to 105 °C

Options

No character = V

range: 1.8 to 3.6 V and BOR enabled

D = V

range: 1.65 to 3.6 V and BOR disabled

Packing

TR = tape and reel

No character = tray or tube

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the nearest ST sales office.

130/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Revision History

Date

21-Feb-2012

12-Oct-2012

Revision

Table 75. Document revision history

Changes

Initial release.

Added WLCSP63 package.

Updated Figure 1: Ultra-low-power STM32L162xC block diagram .

Changed maximum number of touch sensing channels to 34, and updated Table 2: Ultralow power STM32L15xxC device features and peripheral counts .

Added Table 4: Functionalities depending on the working mode (from

Run/active down to standby) , and Table 3: ange depending on dynamic voltage scaling .

Updated Section 3.10: ADC (analog-to-digital converter) to add

Section 3.10.1: Temperature sensor and Section 3.10.2: Internal voltage reference (VREFINT) .

Updated Figure 3: STM32L162VC LQFP100 pinout .

Table 10: STM32L15xxC pin definitions : updated name of reference manual in footnote 5.

Changed I2C1_SMBAI into I2C1_SMBA in Table 10: STM32L15xxC pin definitions .

Modified PB10/11/12 for AFIO4 alternate function, and replaced LBAR by NADV for AFIO12 in Table 10: Alternate function input/output .

Removed caution note below Figure 8: Power supply scheme .

Added Note 2 in Table 15: Embedded reset and power control block characteristics .

Updated Table 14: General operating conditions .

Updated Table 22: Typical and maximum current consumptions in Stop mode and added Note 6 . Updated Table 23: Typical and maximum current consumptions in Standby mode . Updated t

WUSTOP in Table : .

Updated Table 26: Peripheral current consumption .

Updated Table 60: SPI characteristics , added Note 1 and Note 3 , and applied Note 2 to t r(SCK) and t h(SI)

, t f(SCK)

, t w(SCKH)

, t w(SCKL)

, t su(MI)

, t su(SI)

, t h(MI)

Added Table 61: I2S characteristics , Figure 29: I2S slave timing diagram (Philips protocol)(1) and Figure 30: I2S master timing diagram

(Philips protocol)(1) .

Updated Table 72: Temperature sensor characteristics .

Added Figure 40: Thermal resistance .

DocID022799 Rev 13 131/136

135

Revision History STM32L151xC STM32L152xC

Date

01-Feb-2013

02-Sep-2013

Table 75. Document revision history (continued)

Revision Changes

Removed AHB1/AHB2 and corrected typo on APB1/APB2 in :Figure 1:

Ultra-low-power STM32L162xC block diagram-low-power

STM32L162xC block diagram

Updated “OP amp” line in Table 4: Functionalities depending on the working mode (from Run/active down to standby)

Added IWDG and WWDG rows in Table 4: Functionalities depending on the working mode (from Run/active down to standby)

Updated address range in Table 7: Internal voltage reference measured values

The comment "HSE = 16 MHz(2) (PLL ON for fHCLK above 16 MHz)" replaced by "fHSE = fHCLK up to 16 MHz included, fHSE = fHCLK/2 above 16 MHz (PLL ON)(2)” in table Table 27: Current consumption in

Sleep mode replaced pin names D7,C7,C6,C8,B8,A8 respectively by

D11,D10,C12,B12,A12,A11 in column UFBGA100 of Table 9:

STM32L15xxC pin definitions Added more alternate functions supported on pin K3 and M4 for UFBGA100 package in Table 9:

STM32L15xxC pin definitions

Added part number STM32L151CC in Table 1: Device summary

Updated Stop mode current to 1.5 µA in Ultra-low-power platform

Updated entire Section 7: Package information

Removed UFBGA132 and LQFP144 packages

Removed first sentence in Section : I2C interface characteristics

Added Section Table 5.: V

LCD rail decoupling

Added VRAIL functions in Table 9: STM32L15xxC pin definitions

Updated PH0-OSC_IN and PH1-OSC_OUT type in Table 9:

STM32L15xxC pin definitions .

Added Table 6.1.7: Optional LCD power supply scheme .

Updated consumption data in Table 6.3.4: Supply current characteristics

Updated Table 7: Pin loading conditions

Updated Table 8: Pin input voltage Updated Table 15: Typical application with a 32.768 kHz crystal

Updated Table 25: Recommended NRST pin protection

Table 26: I

C bus AC waveforms and measurement circuit Updated

Table 35: Typical connection diagram using the ADC and definition of symbol “RAIN” in Table 77: ADC characteristics

Updated dThreshold/dt conditions in Table 85: Comparator 2 characteristics .

Updated

Table 49: Thermal resistance suffix 6

Added D2 and E2 in Table 69: UFQFPN48 – ultra thin fine pitch quad flat pack no-lead 7 × 7 mm, 0.5 mm pitch package mechanical data

Fixed columns inversion in

Table 67: LQFP64, 10 x 10 mm 64-pin lowprofile quad flat package mechanical data

and Table 70: UFBGA100, 7 x 7 mm, 0.5 mm pitch package mechanical data

132/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Revision History

Date

12-Nov-2013

Table 75. Document revision history (continued)

Revision Changes

Updated Section 3.15: Touch sensing .

Added V

= 1.71 to 1.8 V operating power supply range in Table 4:

Functionalities depending on the working mode (from Run/active down to standby)

Renamed "I/O Level" to "I/O structure" in Table 9: STM32L15xxC pin definitions , added the I/O structure for PC14, PC15, PC3, PH0, PH1,

PA3, PA4, PA5, PB0, PE7, PE8, PE9, PE10, NRST and BOOT0

Updated Table 10: Voltage characteristics added row

Updated Table 11: Current characteristics replaced with the one inside

STM32L15xxBxxA datasheet.

Updated Table 13: General operating conditions , footnote and added row.

Updated Table 15: Embedded internal reference voltage calibration values and moved inside Section 6.3.3: Embedded internal reference voltage

Updated Section 6.3.4: Supply current characteristics .

Updated Table 19: Current consumption in Run mode, code with data processing running from Flash .

Updated Table 22: Current consumption in Run mode, code with data processing running from RAM .

Created Section 6.3.5: Wakeup time from low-power mode ..

Updated Table 38: High-speed external user clock characteristics .

Moved Figure 12: High-speed external clock source AC timing diagram after Table 38: High-speed external user clock characteristics .

Updated Table 40: HSE oscillator characteristics .

Updated Section 6.3.12: Electrical sensitivity characteristics (title).

Updated Section 6.3.13: I/O current injection characteristics .

Updated Table 61: I/O current injection susceptibility and added footnote.

Updated Table 63: I/O static characteristics

Updated Section 6.3.15: NRST pin characteristics .

Updated Table 77: ADC characteristics .

Added footnote

(5)

and

(6)

in Table 77: ADC characteristics

Updated THD values and added 4 more rows ENOB, SINAD, SNR,

THD in Table 78: ADC accuracy

Updated “SDA data hold time” and “SDA and SCL rise time” values and added “Pulse width of spikes that are suppressed by the analog filter” row in Table 68: I

C characteristics

Updated direct channels VDDA range in Table 79: R

AIN

16 MHz

max for f

ADC

Moved Table 82: Temperature sensor calibration values and moved inside Section 6.3.23: Temperature sensor characteristics

Updated I

(WU from Standby) unit in Table 31: Typical and maximum current consumptions in Standby mode .

Updated

Table 67: LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data

Updated

Chapter 8: Part numbering (title).

DocID022799 Rev 13 133/136

135

Revision History STM32L151xC STM32L152xC

Date

09-Dec-2013

13-Mar-2014

16-May-2014

13-Oct-2014

06-Mar-2015

Table 75. Document revision history (continued)

Revision Changes

Apply footnote 1 also to VDD= 1.8 to 2.0 V in Table 2: Functionalities depending on the operating power supply range .

Updated I inj

pin in Table 11: Current characteristics .

Added Input Voltage in Table 13: General operating conditions .

Updated Input leakage current conditions in Table 63: I/O static characteristics

Removed minimum value for f

S in Table 77: ADC characteristics .

Removed Fi nput accuracy .

for ENOB,SINAD,SNR,THD in Table 78: ADC

Added tolerance for TS_CAL1 and TS_CAL2 in Table 82: Temperature sensor calibration values .

Updated

Section 3.7: Memories ,

Table 33: Peripheral current consumption : updated Flash value, Table 61: I/O current injection susceptibility , Table 63: I/O static characteristics :added BOOT0 pin

Table 66: NRST pin characteristics , Chapter 2.2: Ultra-low-power device continuum . removed figures “Power supply and reference decoupling (V

REF+

not connected to V

DDA

) and “Power supply and reference decoupling(V

REF+

connected to V

DDA

). Updated Table 19:

Current consumption in Run mode, code with data processing running from Flash

Updated Section 6.3.1: General operating conditions .

Updated Table 80: DAC characteristics

Added marking for LQFP48/UFQFPN48 packages

Updated Table 66: NRST pin characteristics

Updated Table 63: I/O static characteristics

Updated I

Table 12: Current characteristics

Updated conditions in Table 44: Output voltage characteristics

Removed note 4 in

Table 62: Temperature sensor characteristics

Updated the conditions in Table 26: Low-power mode wakeup timings

Removed ambiguity of “ambient temperature” in the electrical characteristics description.

Updated

Section 3.17: Communication interfaces putting I2S

characteristics inside.

Updated DMIPS features in cover page and Section 2: Description

Updated max temperature at 105°C instead of 85°C in the whole datasheet.

Updated current consumption in

Table 20: Current consumption in

Sleep mode .

Updated Table 25: Peripheral current consumption with new measured

current values.

Updated

Table 58: Maximum source impedance RAIN max adding

note 2.

Updated

Section 7: Package information

with new package device marking.

Updated

Figure 9: Memory map

134/136 DocID022799 Rev 13

STM32L151xC STM32L152xC Revision History

Date

20-Aug-2015

10-Mar-2016

25-Aug-2017

Table 75. Document revision history (continued)

Revision Changes

Updated

Table 17: Embedded internal reference voltage

temperature coefficient at 100ppm/°C and table footnote 3: “guaranteed by design” changed by “guaranteed by characterization results”.

Updated

Table 64: Comparator 2 characteristics new maximum

threshold voltage temperature coefficient at 100ppm/°C.

Updated cover page putting eight SPIs in the peripheral communication interface list.

Updated

Table 2: Ultra-low-power STM32L151xC and STM32L152xC device features and peripheral counts SPI and I2S lines.

Updated

Table 40: ESD absolute maximum ratings

CDM class.

Updated all the notes, removing ‘not tested in production’.

Updated thermal resistance for UFQFPN48 to value of 33 °C/W.

Updated Table 11: Voltage characteristics adding note about V

REF-

pin.

Updated Table 5: Functionalities depending on the working mode (from

Run/active down to standby) LSI and LSE functionalities putting “Y” in

Standby mode.

Removed note 1 below

Figure 2: Clock tree

Updated

Table 43: I/O static characteristics

pull-up and pull-down values.

Updated

Table 46: NRST pin characteristics pull-up values.

Updated

Section 7: Package information

adding information about other optional marking or inset/upset marks.

Updated note 1 below all the package device marking figures.

Updated

Section 7: Package information

replacing “Marking of engineering samples” by “device marking”.

Updated

Nested vectored interrupt controller (NVIC)

in Section 3.2:

ARM® Cortex®-M3 core with MPU about process state automatically

saved.

Updated

Table 3: Functionalities depending on the operating power supply range

removing I/O operation column and adding note about

GPIO speed.

Updated

Table 42: I/O current injection susceptibility

note by ‘injection is not possible’.

Updated

Figure 20: Recommended NRST pin protection note about

the 0.1uF capacitor.

Updated

Table 59: DAC characteristics

resistive load.

Updated

Section 3.1: Low-power modes Low-power run mode (MSI)

RC oscillator clock.

Updated

Table 5: Functionalities depending on the working mode

(from Run/active down to standby) disabling I2C functionality in Low-

power Run and Low-power Sleep modes.

DocID022799 Rev 13 135/136

135

STM32L151xC STM32L152xC

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

136/136 DocID022799 Rev 13