supply pin during ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 29.

Power supply and reference decoupling (V

REF+

Figure 30.

Power supply and reference decoupling (V

REF+ not connected to V

DDA connected to V

DDA

). . . . . . . . . . . . . . 97

). . . . . . . . . . . . . . . . . 97

Figure 31.

12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 32.

LQFP100 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 105

Figure 33.

Figure 34.

LQFP64 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 108

Figure 35.

Figure 36.

LQFP48 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 110

Figure 37.

Figure 38.

UFQFPN48 7 x 7 mm 0.5 mm pitch, ultra thin fine-pitch quad flat no-lead package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 39.

Figure 40.

UFBGA100 7 x 7 x 0.6 mm 0.5 mm pitch, ultra thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 41.

TFBGA64 - 5.0x5.0x1.2 mm, 0.5 mm pitch, thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 42.

Figure 43.

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

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Introduction

1 Introduction

STM32L151x6/8/B, STM32L152x6/8/B

This datasheet provides the ordering information and mechanical device characteristics of the STM32L151x6/8/B and STM32L152x6/8/B ultralow power ARM ® Cortex ® -M3 based microcontrollers product line.

The ultralow power STM32L15xx6/8/B family includes devices in 3 different package types: from 48 to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

These features make the ultralow power STM32L15xx6/8/B microcontroller family suitable for a wide range of applications:

• Medical and handheld equipment

• Application control and user interface

• PC peripherals, gaming, GPS and sport equipment

• Alarm systems, Wired and wireless sensors, Video intercom

• Utility metering

This STM32L151x6/8/B and STM32L152x6/8/B datasheet should be read in conjunction with the STM32L1xxxx reference manual (RM0038).

The document "Getting started with STM32L1xxx hardware development” AN3216 gives a hardware implementation overview. Both documents are available from the

STMicroelectronics website www.st.com.

For information on the Cortex

-M3 core please refer to the Cortex

-M3 Technical Reference

Manual, available from the www.arm.com

website.

Figure 1 shows the general block diagram of the device family.

Caution: This datasheet does not apply to STM32L15xx6/8/B-A covered by a separate datasheet.

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STM32L151x6/8/B, STM32L152x6/8/B

2 Description

Description

The ultralow power STM32L15xx6/8/B incorporates the connectivity power of the universal serial bus (USB) with the high-performance ARM ® Cortex ® -M3 32-bit RISC core operating at 32 MHz frequency (33.3 DMIPS), a memory protection unit (MPU), high-speed embedded memories (Flash memory up to 128 Kbytes and RAM up to 16 Kbytes) and an extensive range of enhanced I/Os and peripherals connected to two APB buses.

All devices offer a 12-bit ADC, 2 DACs and 2 ultralow power comparators, six generalpurpose 16-bit timers and two basic timers, which can be used as time bases.

Moreover, the STM32L15xx6/8/B devices contain standard and advanced communication interfaces: up to two I 2 Cs and SPIs, three USARTs and a USB.The STM32L15xx6/8/B devices offer up to 20 capacitive sensing channels to simply add touch sensing functionality to any application.

They also include a real-time clock and a set of backup registers that remain powered in

Standby mode.

Finally, the integrated LCD controller has a built-in LCD voltage generator that allows you to drive up to 8 multiplexed LCDs with contrast independent of the supply voltage.

The ultralow power STM32L15xx6/8/B operates from a 1.8 to 3.6 V power supply (down to

1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option.

It is available in the -40 to +85 °C temperature range, extended to 105°C in low power dissipation state. A comprehensive set of power-saving modes allows the design of lowpower applications.

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Description STM32L151x6/8/B, STM32L152x6/8/B

Table 2. Ultralow power STM32L15xx6/8/B device features and peripheral counts

Peripheral STM32L15xCx STM32L15xRx STM32L15xVx

32 64 128 32 128 64 128 Flash (Kbytes)

Data EEPROM (Kbytes)

RAM (Kbytes)

Timers

Generalpurpose

Basic

SPI

Communication interfaces

USART

USB

GPIOs

12-bit synchronized ADC

Number of channels

12-bit DAC

Number of channels

LCD (STM32L152xx Only)

COM x SEG

Comparator

Capacitive sensing channels

Max. CPU frequency

Operating voltage

Operating temperatures

Packages

10 10 16 10

16 10 16

14 channels

20 channels

4x32

8x28

24 channels

4x18

4x44

8x40

13 20

32 MHz

1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option

1.65 V to 3.6 V without BOR option

Ambient temperatures: –40 to +85 °C

Junction temperature: –40 to + 105 °C

LQFP48, UFQFPN48 LQFP64, BGA64 LQFP100, BGA100

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STM32L151x6/8/B, STM32L152x6/8/B Description

2.2

Note:

Ultralow power device continuum

The ultralow power STM32L151x6/8/B and STM32L152x6/8/B are fully pin-to-pin and software compatible.

Besides the full compatibility within the family, the devices are part of

STMicroelectronics microcontrollers ultralow power strategy which also includes

STM8L101xx and STM8L15xx devices. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture and features.

They are all based on STMicroelectronics ultralow leakage process.

The ultralow power STM32L and general-purpose STM32Fxxxx families are pin-to-pin compatible. The STM8L15xxx devices are pin-to-pin compatible with the STM8L101xx devices. Please refer to the STM32F and STM8L documentation for more information on these devices.

2.2.1 Performance

All families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM ® Cortex ® -M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios.

This allows the ultralow power performance to range from 5 up to 33.3 DMIPs.

STM8L15xxx and STM32L1xxxx share identical peripherals which ensure a very easy migration from one family to another:

• Analog peripherals: ADC, DAC and comparators

• Digital peripherals: RTC and some communication interfaces

To offer flexibility and optimize performance, the STM8L15xx and STM32L1xxxx families use a common architecture:

• Same power supply range from 1.65 V to 3.6 V, (1.65 V at power down only for

STM8L15xx devices)

• Architecture optimized to reach ultralow consumption both in low power modes and

Run mode

• Fast startup strategy from low power modes

• Flexible system clock

• Ultrasafe reset: same reset strategy including power-on reset, power-down reset, brownout reset and programmable voltage detector.

2.2.4 Features

ST ultralow power continuum also lies in feature compatibility:

• More than 10 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm

• Memory density ranging from 4 to 384 Kbytes

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Functional overview STM32L151x6/8/B, STM32L152x6/8/B

12/129

Figure 1 shows the block diagrams.

Figure 1. Ultralow power STM32L15xx6/8/B block diagram

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1. AF = alternate function on I/O port pin.

DocID17659 Rev 10

STM32L151x6/8/B, STM32L152x6/8/B

3.1 Low power modes

Functional overview

The ultralow power STM32L15xx6/8/B supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system’s maximum operating frequency and the external voltage supply:

• In Range 1 (V

range limited to 1.71-3.6 V), the CPU runs at up to 32 MHz (refer to

Table 17 for consumption).

• In Range 2 (full V

DD consumption)

range), the CPU runs at up to 16 MHz (refer to

Table 17 for

• In Range 3 (full V

range), the CPU runs at up to 4 MHz (generated only with the

multispeed internal RC oscillator clock source). Refer to Table 17

for consumption.

Seven low power modes are provided to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

Sleep mode power consumption: refer to

Table 19 .

• Low power run mode

This mode is achieved with the multispeed internal (MSI) RC oscillator set to the minimum clock (65 kHz), execution from SRAM or Flash memory, and internal regulator in low power mode to minimize the regulator's operating current. In the Low power run mode, the clock frequency and the number of enabled peripherals are both limited.

Low power run mode consumption: refer to Table 20: Current consumption in Low power run mode

• Low power sleep mode

This mode is achieved by entering the Sleep mode with the internal voltage regulator in

Low power mode to minimize the regulator’s operating current. In the Low power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz.

When wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on.

Low power sleep mode consumption: refer to Table 21: Current consumption in Low power sleep mode

• Stop mode with RTC

Stop mode achieves the lowest power consumption while retaining the RAM and register contents and real time clock. All clocks in the V

CORE

domain are stopped, the

PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still running. The voltage regulator is in the low power mode.

The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the

Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp event or the RTC wakeup.

• Stop mode without RTC

Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and

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Functional overview

Note:

STM32L151x6/8/B, STM32L152x6/8/B

HSE crystal oscillators are disabled. The voltage regulator is in the low power mode.

The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the

Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can also be wakened by the USB wakeup.

Stop mode consumption: refer to

Table 22: Typical and maximum current consumptions in Stop mode

• Standby mode with RTC

Standby mode is used to achieve the lowest power consumption and real time clock.

The internal voltage regulator is switched off so that the entire V

CORE

domain is powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched off. The LSE or LSI is still running. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,

RTC, LSI, LSE Crystal 32K osc, RCC_CSR).

The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),

RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.

• Standby mode without RTC

Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire V

CORE

domain is powered off. The PLL, MSI,

RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,

RCC_CSR).

The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising edge on one of the three WKUP pin occurs.

Standby mode consumption: refer to

Table 23 .

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering the

Stop or Standby mode.

Table 3. Functionalities depending on the operating power supply range

Functionalities depending on the operating power supply range

Operating power supply range DAC and ADC operation

USB

Dynamic voltage scaling range

I/O operation

= 1.65 to 1.71 V

= 1.71 to 1.8 V

(1)

Not functional

= 1.8 to 2.0 V

(1)

Conversion time up to 500 Ksps

Not functional

Range 2 or

Range 3

Range 1,

Range 2 or

Range 3

Range 1,

Range 2 or

Range 3

Degraded speed performance

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STM32L151x6/8/B, STM32L152x6/8/B Functional overview

Table 3. Functionalities depending on the operating power supply range (continued)

Functionalities depending on the operating power supply range

Operating power supply range DAC and ADC operation

USB

Dynamic voltage scaling range

I/O operation

= 2.0 to 2.4 V

= 2.4 to 3.6 V

Conversion time up to 500 Ksps

Conversion time up to 1 Msps

Functional

(2)

Range 1,

Range 2 or

Range 3

Range 1,

Range 2 or

Range 3

Full speed operation

1. The CPU frequency changes from initial to final must respect "F

CPU

initial < 4*F

CPU

final" to limit V

CORE two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2 MHz to 16 MHz, wait 5 µs, then switch from 16 MHz to 32 MHz.

drop due to current consumption peak when frequency increases. It must also respect 5 µs delay between

2. Should be USB compliant from I/O voltage standpoint, the minimum V

is 3.0 V.

Table 4. CPU frequency range depending on dynamic voltage scaling

CPU frequency range Dynamic voltage scaling range

16 MHz to 32 MHz (1ws)

32 kHz to 16 MHz (0ws)

8 MHz to 16 MHz (1ws)

32 kHz to 8 MHz (0ws)

2.1 MHz to 4.2 MHz (1ws)

32 kHz to 2.1 MHz (0ws)

Range 1

Range 2

Range 3

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Functional overview STM32L151x6/8/B, STM32L152x6/8/B

Table 5. Working mode-dependent functionalities ( from Run/active down to stand by)

Stop Standby

Ips Run/Active Sleep

Lowpower

Run

Lowpower

Sleep

Wakeup capability

CPU

Flash

RAM

Backup Registers

EEPROM

Brown-out rest

(BOR)

DMA

Programmable

Voltage Detector

(PVD)

Power On Reset

(POR)

Power Down Rest

(PDR)

High Speed

Internal (HSI)

High Speed

External (HSE)

Low Speed Internal

(LSI)

Low Speed

External (LSE)

Multi-Speed

Internal (MSI)

Inter-Connect

Controller

RTC

RTC Tamper

Auto Wakeup

(AWU)

LCD

USB

USART

SPI

I2C

ADC

(1)

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STM32L151x6/8/B, STM32L152x6/8/B Functional overview

Table 5. Working mode-dependent functionalities ( from Run/active down to stand by) (continued)

Stop Standby

Ips Run/Active Sleep

Lowpower

Run

Lowpower

Sleep

Wakeup capability

DAC

Temperature sensor

Comparators

16-bit and 32-bit

Timers

IWDG

WWDG

Touch sensing

Systick Timer

GPIOs

3 Pins

Wakeup time to

Run mode

0 µs 0.36 µs 3 µs 32 µs < 8 µs 50 µs

Consumption

=1.8V to 3.6V

(Typ)

Down to

214 µA/MHz

(from Flash)

Down to

50 µA/MHz

(from Flash)

Down to

9 µA

Down to

4.4 µA

0.5 µA (No

RTC) V

=1.8V

1.4 µA (with

RTC) V

=1.8V

0.5 µA (No

RTC) V

=3.0V

1.6 µA (with

RTC) V

=3.0V

0.3 µA (No RTC)

=1.8V

1 µA (with RTC)

=1.8V

0.3 µA (No RTC)

=3.0V

1.3 µA (with

RTC) V

1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before entering run mode.

=3.0V

3.2 ARM

®

Cortex

®

-M3 core with MPU

The ARM

Cortex

-M3 processor is the industry leading processor for embedded systems.

It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM

Cortex

-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The memory protection unit (MPU) improves system reliability by defining the memory attributes (such as read/write access permissions) for different memory regions. It provides up to eight different regions and an optional predefined background region.

Owing to its embedded ARM core, the STM32L15xx6/8/B is compatible with all ARM tools and software.

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Functional overview STM32L151x6/8/B, STM32L152x6/8/B

Nested vectored interrupt controller (NVIC)

The ultralow power STM32L15xx6/8/B embeds a nested vectored interrupt controller able to handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of Cortex ® -

M3) and 16 priority levels.

• Closely coupled NVIC gives low-latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving , higher-priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

3.3

3.3.1

3.3.2

Reset and supply management

Power supply schemes

• V

= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through V

pins.

• V

SSA

, V

DDA

and V

= 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to V

DDA

SSA must be connected to V

DD and V is 1.8 V when the ADC is used).

, respectively.

Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR) that can be coupled with a brownout reset (BOR) circuitry.

The device exists in two versions:

• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.

• The other version without BOR operates between 1.65 V and 3.6 V.

After the V

threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the BOR permanently: in this case, the V

1.65 V (whatever the version, BOR active or not, at power-on).

min value becomes

When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the power ramp-up should guarantee that 1.65 V is reached on V

DD the POR area.

at least 1 ms after it exits

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STM32L151x6/8/B, STM32L152x6/8/B

Note:

Functional overview

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Stop mode, it is possible to automatically switch off the internal reference voltage (V

REFINT

) in Stop mode. The device remains in reset mode when

DD is below a specified threshold, V reset circuit.

POR/PDR or V

BOR

, without the need for any external

The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive at power-up.

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when V

DDA

is higher than the V

PVD

DDA

drops below the V

PVD

threshold and/or when

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

The regulator has three operation modes: main (MR), low power (LPR) and power down.

• MR is used in Run mode (nominal regulation)

• LPR is used in the Low-power run, Low-power sleep and Stop modes

• Power down is used in Standby mode. The regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and RAM are lost are lost except for the standby circuitry (wakeup logic,

IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR).

At startup, boot pins are used to select one of three boot options:

• Boot from Flash memory

• Boot from System Memory

• Boot from embedded RAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1 or USART2. See STM32™ microcontroller system memory boot mode

AN2606 for details.

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Functional overview STM32L151x6/8/B, STM32L152x6/8/B

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. It features:

• Clock prescaler : to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

• Safe clock switching : clock sources can be changed safely on the fly in run mode through a configuration register.

• Clock management : to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

• Master clock source : three different clock sources can be used to drive the master clock:

– 1-24 MHz high-speed external crystal (HSE), that can supply a PLL

– 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLL

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz) with a consumption proportional to speed, down to 750 nA typical. When a

32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a ±0.5% accuracy.

• Auxiliary clock source : two ultralow power clock sources that can be used to drive the LCD controller and the real-time clock:

– 32.768 kHz low-speed external crystal (LSE)

– 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock can be measured using the high-speed internal RC oscillator for greater precision.

• RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever the system clock.

• USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply the USB interface.

• Startup clock : after reset, the microcontroller restarts by default with an internal

2.1 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

• Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled.

• Clock-out capability (MCO: microcontroller clock output): it outputs one of the internal clocks for external use by the application.

Several prescalers allow the configuration of the AHB frequency, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See

Figure 2 for details on the clock tree.

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STM32L151x6/8/B, STM32L152x6/8/B Functional overview

Figure 2. Clock tree

/3#?/54

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-3)2#

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-#/3%,

AIC

1. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either

24 MHz or 32 MHz.

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Functional overview

3.5

STM32L151x6/8/B, STM32L152x6/8/B

Low power real-time clock and backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes.

• The programmable wakeup time ranges from 120 µs to 36 hours

• Stop mode consumption with LSI and Auto-wakeup: 1.2 µA (at 1.8 V) and 1.4 µA (at

3.0 V)

• Stop mode consumption with LSE, calendar and Auto-wakeup: 1.3 µA (at 1.8V), 1.6 µA

(at 3.0 V)

The RTC can be calibrated with an external 512 Hz output, and a digital compensation circuit helps reduce drift due to crystal deviation.

There are twenty 32-bit backup registers provided to store 80 bytes of user application data.

They are cleared in case of tamper detection.

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated AFIO registers. All GPIOs are high current capable. The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to the AHB with a toggling speed of up to 16 MHz.

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event

(rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 83 GPIOs can be connected to the 16 external interrupt lines. The 7 other lines are connected to RTC, PVD, USB or

Comparator events.

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3.7 Memories

The STM32L15xx6/8/B devices have the following features:

• Up to 16 Kbyte of embedded RAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses).

• The non-volatile memory is divided into three arrays:

– 32, 64 or 128 Kbyte of embedded Flash program memory

– 4 Kbyte of data EEPROM

– Options bytes

The options bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options:

– Level 0: no readout protection

– Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected

– Level 2: chip readout protection, debug features (Cortex ® -M3 JTAG and serial wire) and boot in RAM selection disabled (JTAG fuse)

The whole non-volatile memory embeds the error correction code (ECC) feature.

3.8 DMA (direct memory access)

The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I 2 C, USART, general-purpose timers and ADC.

3.9 LCD (liquid crystal display)

The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels.

• Internal step-up converter to guarantee functionality and contrast control irrespective of

. This converter can be deactivated, in which case the V the voltage to the LCD

LCD

pin is used to provide

• Supports static, 1/2, 1/3, 1/4 and 1/8 duty

• Supports static, 1/2, 1/3 and 1/4 bias

• Phase inversion to reduce power consumption and EMI

• Up to 8 pixels can be programmed to blink

• Unneeded segments and common pins can be used as general I/O pins

• LCD RAM can be updated at any time owing to a double-buffer

• The LCD controller can operate in Stop mode

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Functional overview STM32L151x6/8/B, STM32L152x6/8/B

3.10 ADC (analog-to-digital converter)

A 12-bit analog-to-digital converters is embedded into STM32L15xx6/8/B devices with up to

24 external channels, performing conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start trigger and injection trigger, to allow the application to synchronize A/D conversions and timers. An injection mode allows high priority conversions to be done by interrupting a scan mode which runs in as a background task.

The ADC includes a specific low power mode. The converter is able to operate at maximum speed even if the CPU is operating at a very low frequency and has an auto-shutdown function. The ADC’s runtime and analog front-end current consumption are thus minimized whatever the MCU operating mode.

The temperature sensor (TS) generates a voltage V

SENSE temperature.

that varies linearly with

The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode, see

Table 58:

Temperature sensor calibration values .

3.10.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

ADC and Comparators. V

REFINT

is internally connected to the ADC_IN17 input channel. It enables accurate monitoring of the V

) provides a stable (bandgap) voltage output for the

value (when no external voltage, VREF+, is available for ADC). The precise voltage of V

REFINT

is individually measured for each part by

ST during production test and stored in the system memory area. It is accessible in readonly mode see

Table 16: Embedded internal reference voltage .

3.11 DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration.

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STM32L151x6/8/B, STM32L152x6/8/B Functional overview

This dual digital Interface supports the following features:

• two DAC converters: one for each output channel

• left or right data alignment in 12-bit mode

• synchronized update capability

• noise-wave generation

• triangular-wave generation

• dual DAC channels’ independent or simultaneous conversions

• DMA capability for each channel (including the underrun interrupt)

• external triggers for conversion

• input reference voltage V

REF+

Eight DAC trigger inputs are used in the STM32L15xx6/8/B. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

3.12 Ultralow power comparators and reference voltage

The STM32L15xx6/8/B embeds two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O).

• one comparator with fixed threshold

• one comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of the following:

– DAC output

– External I/O

– Internal reference voltage (V

REFINT

) or V

REFINT

submultiple (1/4, 1/2, 3/4)

Both comparators can wake up from Stop mode, and be combined into a window comparator.

The internal reference voltage is available externally via a low power / low current output buffer (driving current capability of 1 µA typical).

This interface controls the internal routing of I/Os to TIM2, TIM3, TIM4 and to the comparator and reference voltage output.

The STM32L15xx6/8/B devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 20 capacitive sensing channels distributed over 10 analog I/O groups. Only software capacitive sensing acquisition mode is supported.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of

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Functional overview STM32L151x6/8/B, STM32L152x6/8/B charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. The capacitive sensing acquisition only requires few external components to operate.

Reliable touch sensing functionality can be quickly and easily implemented using the free

STM32L1xx STMTouch touch sensing firmware library.

3.15 Timers and watchdogs

The ultralow power STM32L15xx6/8/B devices include six general-purpose timers, two basic timers and two watchdog timers.

Table 6 compares the features of the general-purpose and basic timers.

Timer

TIM2,

TIM3,

TIM4

TIM9

TIM10,

TIM11

TIM6,

TIM7

Counter resolution

Table 6. Timer feature comparison

Counter type

Prescaler factor

DMA request generation

Capture/compare channels

Complementary outputs

16-bit

Up, down, up/down

Any integer between 1 and 65536

Yes

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STM32L151x6/8/B, STM32L152x6/8/B Functional overview

There are six synchronizable general-purpose timers embedded in the STM32L15xx6/8/B

devices (see Table 6 for differences).

TIM2, TIM3, TIM4

These timers are based on a 16-bit auto-reload up/down-counter and a 16-bit prescaler.

They feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.

The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM10, TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4 all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

TIM10, TIM11 and TIM9

These timers are based on a 16-bit auto-reload up-counter and a 16-bit prescaler. They include a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas

TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4 full-featured generalpurpose timers.

They can also be used as simple time bases and be clocked by the LSE clock source

(32.768 kHz) to provide time bases independent from the main CPU clock.

3.15.2 Basic timers (TIM6 and TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as generic

16-bit time bases.

This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit down-counter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches 0.

The independent watchdog is based on a 12-bit down-counter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode.

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Functional overview STM32L151x6/8/B, STM32L152x6/8/B

The window watchdog is based on a 7-bit down-counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes.

They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SM Bus 2.0/PM Bus.

All USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They provide hardware management of the CTS and RTS signals. They support IrDA SIR ENDEC, are

ISO 7816 compliant and have LIN Master/Slave capability.

All USART interfaces can be served by the DMA controller.

3.16.3 Serial peripheral interface (SPI)

Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

Both SPIs can be served by the DMA controller.

The STM32L15xx6/8/B embeds a USB device peripheral compatible with the USB full speed 12 Mbit/s. The USB interface implements a full speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and supports suspend/resume. The dedicated

48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).

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STM32L151x6/8/B, STM32L152x6/8/B Functional overview

3.17 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.

The JTAG port can be permanently disabled with a JTAG fuse.

Embedded Trace Macrocell™

The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32L15xx6/8/B through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

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Pin descriptions STM32L151x6/8/B, STM32L152x6/8/B

Figure 3. STM32L15xVx UFBGA100 ballout

)

(

3( 3( 3% %227 3'

3( 3( 3% 3% 3%

:.83

3( 3(

26&B,1

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966B

9''B 3%

3& 9/&'

26&B287

26&B,1

966B

26&B287

9''B

3& 1567 9''B

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:.83

9''$ 3$ 3$

3% 3% 3$ 3$ 3$

3' 3' 3' 3& 3& 3$

3' 3' 3& 3+ 3$

3$ 3$ 3&

3& 3& 3&

966B 966B

9''B 9''B

3' 3' 3'

3' 3' 3%

3% 3%

3( 3( 3( 3% 3% 3%

3( 3( 3( 3( 3( 3(

AIF

1. This figure shows the package top view.

30/129

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STM32L151x6/8/B, STM32L152x6/8/B

Figure 4. STM32L15xVx LQFP100 pinout

Pin descriptions

PE2

PE3

PE4

PE5

PE6-WKUP3

LCD

PC13-WKUP2

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

VDD_5

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PA0-WKUP1

PA1

PA2

LQFP100

VDD_2

VSS_2

PH2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

67 ai15692c

1. This figure shows the package top view.

DocID17659 Rev 10

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Pin descriptions STM32L151x6/8/B, STM32L152x6/8/B

Figure 5. STM32L15xRx TFBGA64 ballout

3 4 5 6 7 8 1

PC14-

O S C 3 2_IN

PC1 3 -

WKUP2

PB9 PB4 PB 3 PA15 PA14 PA1 3

PC15-

O S C 3 2_OUT

VLCD

PH0-

O S C_IN V

SS _4

PB 8

PB7

BOOT0 PD2

PB5 PC12

PC11

PA10

PC10

PA9

PA12

PA11

PH1-

O S C_OUT VDD_4 PB6 V

SS _ 3

SS _2

SS _1

PA 8 PC9

E NR S T PC1 PC0 VDD_

VDD_2 VDD_1 PC7 PC 8

SS A

PC2 PA2 PA5 PB0 PC6 PB15 PB14

VREF+

PA0-WKUP1 PA 3 PA6 PB1 PB2 PB10 PB1 3

H VDDA PA1 PA4 PA7 PC4 PC5 PB11 PB12

AI16090c

1. This figure shows the package top view.

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STM32L151x6/8/B, STM32L152x6/8/B

Figure 6. STM32L15xRx LQFP64 pinout

Pin descriptions

LCD

PC13-WKUP2

PC14-OSC32_IN

PC15-OSC32_OUT

PH0 -OSC_IN

PH1- OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VDDA

PA0-WKUP1

PA1

PA2

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

2 47

3 46

LQFP64

17 18 19 20 21 22 23 24

25 26 27 28

29 30 31 32

VDD_2

VSS_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

1. This figure shows the package top view.

Figure 7. STM32L15xCx LQFP48 pinout ai15693c

LCD

PC13-WKUP2

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA

VDDA

PA0 -WKUP1

PA1

PA2

48 47 46 45 44 43 42 41 40 39 38 37

5 32

6 LQFP48 31

7 30

8 29

13 14 15 16 17 18 19 20 21 22 23 24

VDD_2

VSS_2

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12 ai15694 c

1. This figure shows the package top view.

DocID17659 Rev 10

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Pin descriptions

,#$

0#7+50

0#/3#?).

0#/3#?/54

0(/3#?).

0(/3#?/54

.234

33!

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0!7+50

STM32L151x6/8/B, STM32L152x6/8/B

Figure 8. STM32L15xCx UFQFPN48 pinout

5&1&0.

$$?

33?

AID

1. This figure shows the package top view.

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STM32L151x6/8/B, STM32L152x6/8/B Pin descriptions

Name

Table 7. Legend/abbreviations used in the pinout table

Abbreviation Definition

Pin name

Pin type

I/O structure

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

Input / output pin

5 V tolerant I/O

Standard 3.3 V I/O

Dedicated BOOT0 pin

Notes

RST Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Alternate functions

Functions selected through GPIOx_AFR registers

Pin functions

Additional functions

Functions directly selected/enabled through peripheral registers

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Pin descriptions

Pins

STM32L151x6/8/B, STM32L152x6/8/B

Table 8. STM32L15xx6/8/B pin definitions

Pin name

Main function (2)

(after reset)

Alternate functions

1 B2 -

2 A1 -

3 B1 -

PE2

PE3

PE4

I/O FT

4 C2 PE5 I/O FT

5 D2 PE6-WKUP3 I/O FT

6 1 B2 E2 1 V

LCD

(3)

7 2 A2 C1 2

PC13-

WKUP2

I/O FT

3 A1

4 B1

PC14-

OSC32_IN

(4)

PC15-

OSC32_OUT

(4)

I/O

5 C1

6 D1

14 7 E1 H2 7

15 8 E3 H1 -

16 9 E2 J2 -

17 10 F2 J3 -

18 11 -

(6)

19 12 F1 J1 8

20 K1 -

21 -

(6)

L1 -

SS_5

DD_5

PH0-

OSC_IN

(5)

PH1-

OSC_OUT

NRST

PC0

PC1

PC2

PC3

SSA

REF-

I/O

22 13 H1 M1 9

REF+

DDA

S -

23 14 G2 L2 10 PA0-WKUP1 I/O FT

I/O RST

I/O FT

I/O TC

S -

PC15

SS_5

DD_5

PH0

PH1

NRST

PC0

PC1

PC2

PC3

SSA

REF-

REF+

DDA

PA0

PE2

PE3

PE4

PE5

PE6

LCD

PC13

PC14

TRACECLK/LCD_SEG38/TIM3_ETR

TRACED0/LCD_SEG39/TIM3_CH1

TRACED1/TIM3_CH2

TRACED2/TIM9_CH1

TRACED3/WKUP3/TIM9_CH2

RTC_TAMP1/RTC_TS/RTC_OUT/WKUP2

OSC32_IN

OSC32_OUT

OSC_IN

OSC_OUT

ADC_IN10/LCD_SEG18/COMP1_INP

ADC_IN11/LCD_SEG19/COMP1_INP

ADC_IN12/LCD_SEG20/COMP1_INP

ADC_IN13/LCD_SEG21/COMP1_INP

WKUP1/USART2_CTS/ADC_IN0/

TIM2_CH1_ETR/COMP1_INP

36/129

DocID17659 Rev 10

STM32L151x6/8/B, STM32L152x6/8/B

Table 8. STM32L15xx6/8/B pin definitions (continued)

Pins

Pin descriptions

Pin name

Main function

(2)

(after reset)

Alternate functions

24 15 H2 M2 11

25 16 F3 K3 12

26 17 G3 L3 13

27 18 C2 E3 -

28 19 D2 H3 -

29 20 H3 M3 14

30 21 F4 K4 15

31 22 G4 L4 16

32 23 H4 M4 17

33 24 H5 K5 -

34 25 H6 L5 -

35 26 F5 M5 18

36 27 G5 M6 19

37 28 G6 L6 20

38 M7 -

39 L7 -

40 M8 -

41 L8 -

42 M9 -

43 L9 -

44 M10 -

45 M11 -

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PA1

PA2

PA3

SS_4

DD_4

PA4

I/O

I/O TC

I/O

I/O FT

I/O TC

PA1

PA2

PA3

SS_4

DD_4

PA4

PA5

PA6

PA7

PC4

PC5

PB0

I/O FT PB1

I/O FT PB2/BOOT1

I/O TC

PE7

PE8

I/O TC

I/O FT

PE9

PE10

PE11

PE12

PE13

PE14

USART2_RTS/ADC_IN1/TIM2_CH2/

LCD_SEG0/COMP1_INP

USART2_TX/ADC_IN2/TIM2_CH3/

TIM9_CH1/LCD_SEG1/COMP1_INP

USART2_RX/ADC_IN3/TIM2_CH4/

TIM9_CH2/LCD_SEG2/COMP1_INP

SPI1_NSS/USART2_CK/

ADC_IN4/DAC_OUT1/COMP1_INP

SPI1_SCK/ADC_IN5/

DAC_OUT2/TIM2_CH1_ETR/COMP1_INP

SPI1_MISO/ADC_IN6/TIM3_CH1/

LCD_SEG3/TIM10_CH1/COMP1_INP

SPI1_MOSI/ADC_IN7/TIM3_CH2/

LCD_SEG4/TIM11_CH1/COMP1_INP

ADC_IN14/LCD_SEG22/COMP1_INP

ADC_IN15/LCD_SEG23/COMP1_INP

ADC_IN8/TIM3_CH3/LCD_SEG5/

COMP1_INP/VREF_OUT

ADC_IN9/TIM3_CH4/LCD_SEG6/

COMP1_INP/VREF_OUT

ADC_IN22/COMP1_INP

ADC_IN23/COMP1_INP

ADC_IN24/TIM2_CH1_ETR/COMP1_INP

ADC_IN25/TIM2_CH2/COMP1_INP

TIM2_CH3

TIM2_CH4/SPI1_NSS

SPI1_SCK

SPI1_MISO

DocID17659 Rev 10

37/129

Pin descriptions STM32L151x6/8/B, STM32L152x6/8/B

Table 8. STM32L15xx6/8/B pin definitions (continued)

Pins

Pin name

Main function

(2)

(after reset)

Alternate functions

46 M12 -

47 29 G7 L10 21

48 30 H7 L11 22

49 31 D6 F12 23

50 32 E6 G12 24

51 33 H8 L12 25

52 34 G8 K12 26

53 35 F8 K11 27

54 36 F7 K10 28

55 K9 -

56 K8 -

57 J12 -

58 J11 -

59 J10 -

60 H12 -

61 H11 -

62 H10 -

63 37 F6 E12 -

64 38 E7 E11 -

65 39 E8 E10 -

66 40 D8 D12 -

67 41 D7 D11 29

68 42 C7 D10 30

PE15

PB10

PB11

SS_1

DD_1

PB12

PB13

PB14

I/O FT

I/O

PB15

PC6

PC7

PC8

PC9

PA8

PA9

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

I/O FT

PB15

PC6

PC7

PC8

PC9

PA8

PA9

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PE15

PB10

PB11

SS_1

DD_1

PB12

PB13

PB14

SPI1_MOSI

I2C2_SCL/USART3_TX/TIM2_CH3/

LCD_SEG10

I2C2_SDA/USART3_RX/TIM2_CH4/LCD_SE

G11

SPI2_NSS/I2C2_SMBA/USART3_CK/

LCD_SEG12/ADC_IN18/COMP1_INP/

TIM10_CH1

SPI2_SCK/USART3_CTS/LCD_SEG13/

ADC_IN19/COMP1_INP/TIM9_CH1

SPI2_MISO/USART3_RTS/LCD_SEG14/

ADC_IN20/COMP1_INP/TIM9_CH2

SPI2_MOSI/LCD_SEG15/

ADC_IN21/COMP1_INP/TIM11_CH1/

RTC_REFIN

USART3_TX/LCD_SEG28

USART3_RX/LCD_SEG29

USART3_CK/LCD_SEG30

USART3_CTS/LCD_SEG31

TIM4_CH1/USART3_RTS/LCD_SEG32

TIM4_CH2/LCD_SEG33

TIM4_CH3/LCD_SEG34

TIM4_CH4/LCD_SEG35

TIM3_CH1/LCD_SEG24

TIM3_CH2/LCD_SEG25

TIM3_CH3/LCD_SEG26

TIM3_CH4/LCD_SEG27

USART1_CK/MCO/LCD_COM0

USART1_TX/LCD_COM1

38/129

DocID17659 Rev 10

STM32L151x6/8/B, STM32L152x6/8/B

Table 8. STM32L15xx6/8/B pin definitions (continued)

Pins

Pin descriptions

Pin name

Main function

(2)

(after reset)

Alternate functions

69 43 C6 C12 31

70 44 C8 B12 32

71 45 B8 A12 33

72 46 A8 A11 34

73 C11 -

74 47 D5 F11 35

75 48 E5 G11 36

76 49 A7 A10 37

77 50 A6 A9 38

78 51 B7 B11 -

79 52 B6 C10 -

80 53 C5 B10 -

81 C9 -

82 B9 -

83 54 B5 C8 -

84 B8 -

85 B7 -

86 A6 -

87 B6 -

88 A5 -

89 55 A5 A8 39

90 56 A4 A7 40

PA10

PA11

PA12

JTMS/

SWDAT

PH2

SS_2

DD_2

JTCK

/SWCLK

JTDI

PC10

PC11

PC12

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

JTDO

NJTRST

I/O FT

S -

I/O FT

PA10

PA11

PA12

PA13

PH2

SS_2

DD_2

PA14

PA15

PC10

PC11

PC12

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PB3

PB4

USART1_RX/LCD_COM2

USART1_CTS/USB_DM/SPI1_MISO

USART1_RTS/USB_DP/SPI1_MOSI

TIM2_CH1_ETR/PA15/SPI1_NSS/

LCD_SEG17

USART3_TX/LCD_SEG28/LCD_SEG40/

LCD_COM4

USART3_RX/LCD_SEG29/LCD_SEG41/

LCD_COM5

USART3_CK/LCD_SEG30/LCD_SEG42/

LCD_COM6

SPI2_NSS/TIM9_CH1

SPI2_SCK

TIM3_ETR/LCD_SEG31/LCD_SEG43/

LCD_COM7

USART2_CTS/SPI2_MISO

USART2_RTS/SPI2_MOSI

USART2_TX

USART2_RX

USART2_CK/TIM9_CH2

TIM2_CH2/PB3/SPI1_SCK/COMP2_INM/

LCD_SEG7

TIM3_CH1/PB4/SPI1_MISO/COMP2_INP/

LCD_SEG8

DocID17659 Rev 10

39/129

Pin descriptions STM32L151x6/8/B, STM32L152x6/8/B

Table 8. STM32L15xx6/8/B pin definitions (continued)

Pins

Pin name

Main function

(2)

(after reset)

Alternate functions

91 57 C4 C5 41

92 58 D3 B5 42

93 59 C3 B4 43

94 60 B4 A4 44

PB5

PB6

PB7

BOOT0

I/O FT

I B

PB5

PB6

PB7

BOOT0

I2C1_SMBA/TIM3_CH2/SPI1_MOSI/

COMP2_INP/LCD_SEG9

I2C1_SCL/TIM4_CH1/USART1_TX

I2C1_SDA/TIM4_CH2/USART1_RX/PVD_IN

95 61 B3

96 62 A3

PB8

PB9

I/O

PB8

PB9

TIM4_CH3/I2C1_SCL/LCD_SEG16/

TIM10_CH1

TIM4_CH4/I2C1_SDA/LCD_COM3/

TIM11_CH1

97 C3 -

98 A2 -

PE0

PE1

I/O

PE0

PE1

TIM4_ETR/LCD_SEG36/TIM10_CH1

LCD_SEG37/TIM11_CH1

99 63 D4

100 64 E4

SS_3

DD_3

S -

SS_3

DD_3

1. I = input, O = output, S = supply.

2. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1

and USART1 & USART2, respectively. Refer to Table 2 on page 10

3. Applicable to STM32L152xx devices only. In STM32L151xx devices, this pin should be connected to V

4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is on (by setting the

LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose

PC14/PC15 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins section in the STM32L1xxxx reference manual (RM0038).

5. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is on (by setting the HSEON bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the HSE oscillator is off (after reset, the HSE oscillator is off). The HSE has priority over the GPIO function.

6. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The V

REF+

functionality is provided instead.

40/129

DocID17659 Rev 10

PA5

PA6

PA7

PA8

Port name

BOOT0

NRST

PA0-

WKUP1

PA1

PA2

PA3

PA4

PA9

PA10

PA11

PA12

PA13

AFIO0

SYSTEM

AFIO2

TIM3/4

BOOT0 -

NRST -

WKUP1

TIM2_CH1

_ETR

TIM2_CH2 -

MCO

JTMS-

SWDAT

AFIO1

TIM2

TIM2_CH3 -

TIM2_CH4 -

TIM9_CH1 -

TIM9_CH2 -

TIM2_CH1

_ETR

TIM3_CH1 TIM10_CH1

TIM3_CH2 TIM11_CH1

AFIO3

TIM9/10/11

Table 9. Alternate function input/output

Digital alternate function number

AFIO4

I2C1/2

AFIO5 AFOI6 AFIO7

AFI

AFIO10 AFIO11

AFIO

AFIO14

SPI1/2

Alternate function

N/A

SPI1_SCK -

SPI1_MISO

SPI1_MOSI

SPI1_NSS -

SPI1_MISO -

SPI1_MOSI -

USART1_

CTS

USART1_

RTS

USART

1/2/3

USART2_

CTS

USART2_

RTS

USART2_

N/A N/A

USB

LCD

[SEG3]

[SEG4]

DM -

DP -

N/A

[SEG0] -

[SEG1] -

[SEG2] -

[COM0] -

[COM1] -

[COM2] -

N/A

AFIO15

SYSTEM

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

PB7

PB8

PB9

PB10

PA15

PB0

PB1

PB2

PB3

PB4

PB5

Port name

PA14

PB6

PB11

PB12

PB13

PB14

PB15

AFIO0

SYSTEM

AFIO1

TIM2

AFIO2

TIM3/4

JTCK-

SWCLK

JTDI

BOOT1

TIM2_CH1

_ETR

TIM3_CH3 -

TIM3_CH4 -

JTRST -

TIM3_CH2 -

RTC_REFIN

TIM4_CH1 -

TIM4_CH2 -

TIM4_CH3 TIM10_CH1* I2C1_SCL

TIM4_CH4 TIM11_CH1* I2C1_SDA

TIM2_CH3 -

I2C1_SDA -

I2C2_SCL -

TIM2_CH4 -

Table 9. Alternate function input/output (continued)

Digital alternate function number

AFIO3

TIM9/10/11

AFIO4

I2C1/2

AFIO5

SPI1/2

AFOI6 AFIO7

AFI

AFIO10

Alternate function

N/A

USART

1/2/3

N/A N/A USB

I2C1_

SMBA

SPI1_NSS -

SPI1_MOSI -

I2C1_SCL -

I2C2_SDA -

TIM10_CH1

I2C2_

SMBA

SPI2_NSS -

TIM9_CH1 -

TIM9_CH2 -

TIM11_CH1 -

USART1_

USART3_

CTS

USART3_

RTS

AFIO11

AFIO

AFIO14

LCD

N/A

SEG17 -

[SEG5] -

[SEG6] -

[SEG9] -

SEG16

[COM3]

SEG10 -

SEG11 -

SEG12 -

SEG13 -

SEG14 -

N/A

AFIO15

SYSTEM

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

EVENTOUT

Port name

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PC8

PC9

PC10

PC11

PC12

AFIO0

SYSTEM

PC13-

WKUP2

RTC_TAMP1/

RTC_TS/

RTC_OUT /

WKUP2

PC14-

OSC32_IN

PC15-

OSC32_O

OSC32_IN -

OSC32_OUT -

TIM2

AFIO1

AFIO2

TIM3/4

TIM3_CH1 -

TIM3_CH2 -

TIM3_CH3 -

TIM3_CH4 -

Table 9. Alternate function input/output (continued)

Digital alternate function number

AFIO3

TIM9/10/11

AFIO4

I2C1/2

AFIO5

SPI1/2

AFOI6 AFIO7

AFI

AFIO10

Alternate function

N/A

USART

1/2/3

USART3_

N/A N/A

USB

USART3_

AFIO11

LCD

AFIO

N/A

SEG18 -

SEG19 -

SEG20 -

SEG21 -

SEG22 -

SEG23 -

SEG24 -

SEG25 -

SEG26 -

SEG27 -

COM4 /

SEG28 /

SEG40

COM5 /

SEG29 /

SEG41

COM6 /

SEG30 /

SEG42

AFIO

N/A

AFIO14

AFIO15

SYSTEM

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PE0

Port name

AFIO0

SYSTEM

AFIO1

TIM2

AFIO2

TIM3/4

TIM3_ETR -

Table 9. Alternate function input/output (continued)

Digital alternate function number

AFIO3

TIM9/10/11

AFIO4

I2C1/2

TIM9_CH1 -

TIM9_CH2 -

TIM4_CH1 -

TIM4_CH2 -

TIM4_CH3 -

TIM4_CH4 -

TIM4_ETR TIM10_CH1 -

AFIO5 AFOI6 AFIO7

AFI

AFIO10

SPI1/2

Alternate function

N/A

SPI2_SCK -

USART

1/2/3

N/A N/A

USB

SPI2_MISO -

AFIO11

LCD

COM7 /

SEG31 /

SEG43

SPI2_MOSI -

USART3_

CTS

USART3_

RTS

USART2_

CTS

USART2_

RTS

USART2_

USART3_

AFIO

AFIO14

N/A

AFIO15

SYSTEM

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

TIMx_IC1 EVENTOUT

Port name

AFIO0

SYSTEM

AFIO1

TIM2

PE1

PE2

PE3

PE4

PE5

PE6

PE7

PE8

PE9

TRACECK -

TRACED0 -

TRACED1 -

TRACED2 -

TRACED3 /

WKUP3

TIM2_CH1

_ETR

PE10

PE11

PE12

PE13

PE14

PE15

PH0-

OSC_IN

PH1-

OSC_OUT

PH2

OSC_IN

OSC_OUT -

TIM2_CH2 -

TIM2_CH3 -

TIM2_CH4 -

AFIO2

TIM3/4

Table 9. Alternate function input/output (continued)

Digital alternate function number

AFIO3

TIM9/10/11

AFIO4

I2C1/2

TIM11_CH1 -

TIM9_CH2* -

AFIO5

SPI1/2

SPI1_NSS -

SPI1_SCK -

SPI1_MISO -

SPI1_MOSI -

AFOI6 AFIO7

AFI

AFIO10

Alternate function

N/A

USART

1/2/3

N/A N/A

USB

AFIO11

AFIO

AFIO14

LCD

N/A

AFIO15

N/A

RI SYSTEM

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

TIMx_IC1 EVENTOUT

TIMx_IC2 EVENTOUT

TIMx_IC3 EVENTOUT

TIMx_IC4 EVENTOUT

Memory mapping STM32L151x6/8/B, STM32L152x6/8/B

46/129

The memory map is shown in the following figure.

Figure 9. Memory map

0xFFFF FFFF

0xE010 0000

0xE000 0000

Cortex- M3 Internal

Peripherals

0xC000 0000

0xA000 0000

0x8000 0000

0x6000 0000

0x4000 0000

Peripherals

0x2000 0000

SRAM

0x0000 0000

Reserved

0x1FF8 001F

0x1FF8 0000

0x1FF0 0FFF

Option Bytes rese rved rese rved

System memory

0x1FF0 0000 rese rved

0x0808 0FFF

0x0808 0000

Data EEPROM rese rved

0x0801 FFFF

Flash memory

0x0800 0000

0x0000 0000

Aliased to Flash or system memory depending on

BOOT pins

0x4000 7C00

0x4000 7800

0x4000 7400

0x4000 7000

0x4000 6200

0x4000 6000

0x4000 5C00

0x4000 5800

0x4000 5400

0x4000 4C00

0x4000 4800

0x4000 4400

0x4000 3C00

0x4000 3800

0x4000 3400

0x4000 3000

0x4000 2C00

0x4000 2800

0x4000 2400

0x4000 1C00

0x4000 1400

0x4000 1000

0x4000 0C00

0x4000 0800

0x4000 0400

0x4000 0000

COMP + RI reserved

DAC1 & 2

PWR reserved

512 byte

USB

USB Reg isters

RTC

LCD reserved

TIM7

TIM6 reserved

TIM4

I2C2

I2C1 reserved

USART3

USART2 reserved

SPI2 reserved

IWDG

WWDG

TIM3

TIM2

APB memory space

0xFFFF FFFF reserved

0xE010 0000 reserved

0x6000 0000 reserved

0x4002 6400

DMA

0x4002 6000 reserved

0x4002 4000

Flash Interf ace

0x4002 3C00

RCC

0x4002 3800 reserved

0x4002 3400

CRC

0x4002 3000 reserved

0x4002 1800

Port H

0x4002 1400

Port E

0x4002 1000

Port D

0x4002 0C00

Port C

0x4002 0800

0x4002 0400

Port B

0x4002 0000

Port A reserved

0x4001 3C00

USART1

0x4001 3800 reserved

0x4001 3400

SPI1

0x4001 3000 reserved

0x4001 2800

ADC

0x4001 2400 rese rve d

0x4001 1400

TIM11

0x4001 1000

TIM10

0x4001 0C00

TIM9

0x4001 0800

EXTI

0x4001 0400

SYSCFG

0x4001 0000 reserved ai18200b

DocID17659 Rev 10

STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 σ ).

Please refer to device ErrataSheet for possible latest changes of electrical characteristics.

Unless otherwise specified, typical data are based on T

1.65 V tested.

≤ V

= 25 °C, V

= 3.6 V (for the

≤ 3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 σ ).

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 10

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 11 .

DocID17659 Rev 10

47/129

103

Electrical characteristics

Figure 10. Pin loading conditions

STM32L151x6/8/B, STM32L152x6/8/B

Figure 11. Pin input voltage

0&8SLQ

& S)

9,1

6.1.6

069

Power supply scheme

Figure 12. Power supply scheme

6WDQGE\SRZHUFLUFXLWU\

26&.57&

:DNHXSORJLF

57&EDFNXSUHJLVWHUV

069

287

/RJLF *3,2V

)

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48/129

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STM32L151x6/8/B, STM32L152x6/8/B

6.1.7 Optional LCD power supply scheme

Electrical characteristics

Figure 13. Optional LCD power supply scheme

VSEL

N x 100 nF

+ 1 x 10 μF

DD1/2/.../N

Step-up

Converter

Option 1 V

LCD

100 nF

LCD

Option 2

EXT

SS1/2/.../N

MS32462V1

1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open.

2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an external capacitance is needed for correct behavior of this converter.

Figure 14. Current consumption measurement scheme

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DocID17659 Rev 10

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103

Electrical characteristics

6.2 Absolute maximum ratings

STM32L151x6/8/B, STM32L152x6/8/B

Stresses above the absolute maximum ratings listed in

Table 10: Voltage characteristics

Table 11: Current characteristics

, and

Table 12: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 10. Voltage characteristics

Ratings Min Max Unit

–V

External main supply voltage

(including V

DDA and V

)

(1)

Input voltage on five-volt tolerant pin

(2)

Input voltage on any other pin

| Δ V

DDx

| Variations between different V

DD power pins

SSX

− V

| Variations between all different ground pins

REF+

− V

DDA

ESD(HBM)

Allowed voltage difference for V

Electrostatic discharge voltage

(human body model)

REF+

> V

DDA

V see

–0.3

− 0.3

4.0

Section 6.3.11

+4.0

4.0

0.4

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

2. V

IN maximum must always be respected. Refer to

Table 11 for maximum allowed injected current values.

Symbol

Table 11. Current characteristics

Ratings Max.

Unit

VDD Σ

VSS Σ

Total current into V

DDA power lines (source)

(1)

Total current out of V

SS ground lines (sink) (1)

Output current sunk by any I/O and control pin

INJ(PIN)

(2)

Output current sourced by any I/O and control pin

Injected current on five-volt tolerant I/O

(3)

Injected current on any other pin

(4)

Total injected current (sum of all I/O and control pins)

(5)

- 25

-5/+0

± 5

Σ I

INJ(PIN)

± 25 mA

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

2. Negative injection disturbs the analog performance of the device. See note in

Section 6.3.17

3. Positive current injection is not possible on these I/Os. A negative injection is induced by V must never be exceeded. Refer to

Table 10

for maximum allowed input voltage values.

. I

INJ(PIN)

4. A positive injection is induced by V

< V

. I must never be exceeded. Refer to

Table 10: Voltage characteristics

for the maximum allowed input voltage values.

> V

while a negative injection is induced by V

INJ(PIN)

5. When several inputs are submitted to a current injection, the maximum Σ I positive and negative injected currents (instantaneous values).

INJ(PIN)

is the absolute sum of the

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Symbol

STG

Electrical characteristics

Table 12. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

6.3.1 General operating conditions

Symbol

Table 13. General operating conditions

Parameter Conditions Min Max Unit f

HCLK f

PCLK1 f

PCLK2

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

MHz

Standard operating voltage

BOR detector disabled

BOR detector enabled, at power on

1.65

1.8

3.6

BOR detector disabled, after power on

1.65

3.6

DDA

(1)

Analog operating voltage

(ADC and DAC not used)

Analog operating voltage

(ADC or DAC used)

Input voltage on FT pins

(3)

Must be the same voltage as

(2)

1.65

1.8

3.6

Input voltage on BOOT0 pin

Input voltage on any other pin

Power dissipation at

= 85 °C

(4)

2.0 V ≤ V

≤ 3.6 V

1.65 V ≤ V

≤ 2.0 V

BGA100 package

–0.3

5.5

5.25

5.5

+0.3

339

V mW

T A Temperature range

Maximum power dissipation

Low power dissipation (5)

–40 85

–40 105

°C

Junction temperature range -40 °C ≤

≤ 105°C –40 105 °C

1. When the ADC is used, refer to

Table 54: ADC characteristics

2. It is recommended to power V

DDA

and V from the same source. A maximum difference of 300 mV between V

can be tolerated during power-up and operation.

and

3. To sustain a voltage higher than V

+0.3 V, the internal pull-up/pull-down resistors must be disabled.

4. If T is lower, higher P

on page 51

values are allowed as long as T

does not exceed T

max (see Table 12: Thermal characteristics

5. In low power dissipation state, T can be extended to this range as long as T

Thermal characteristics on page 51 ).

does not exceed T

max (see Table 12:

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

6.3.2 Embedded reset and power control block characteristics

The parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in the following table.

Symbol t

VDD

(1)

RSTTEMPO

(1)

Reset temporization

POR/PDR

BOR0

BOR1

BOR2

BOR3

BOR4

Table 14. Embedded reset and power control block characteristics

Parameter

rise time rate

fall time rate

Power on/power down reset threshold

Brown-out reset threshold 0

Brown-out reset threshold 1

Brown-out reset threshold 2

Brown-out reset threshold 3

Brown-out reset threshold 4

Conditions

BOR detector enabled

BOR detector disabled

BOR detector enabled

BOR detector disabled

rising, BOR enabled

rising, BOR disabled

(2)

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Min Typ Max Unit

0.4

20 -

∞

1000

∞

1000

3.3

0.7

1.6

1.5

1.65

1.3

1.5

1.65

1.67

1.7

1.74

1.69

1.76

1.8

1.87

1.93

1.97

1.96

2.03

2.07

2.22

2.30

2.35

2.31

2.41

2.44

2.45

2.55

2.60

2.54

2.66

2.7

2.68

2.8

2.85

2.78

2.9

2.95

µs/V ms

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Table 14. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6 hyst

Programmable voltage detector threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Hysteresis voltage

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

BOR0 threshold

All BOR and PVD thresholds excepting BOR0

1.8

1.88

1.98

2.08

2.20

2.28

2.39

2.47

2.57

2.68

2.77

2.87

2.97

3.08

1.85

1.94

2.04

2.14

2.24

2.34

2.44

2.54

2.64

2.74

2.83

2.94

3.05

3.15

100

1.88

1.99

2.09

2.18

2.28

2.38

2.48

2.58

2.69

2.79

2.88

2.99

3.09

3.20

1. Guaranteed by characterization, not tested in production.

2. Valid for device version without BOR at power up. Please see option "T" in Ordering information scheme for more details.

V mV

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

The parameters given in the following table are based on characterization results, unless otherwise specified.

Table 15. Embedded internal reference voltage calibration values

Calibration value name Description Memory address

VREFINT_CAL

Raw data acquired at temperature of 30 °C, V

DDA

= 3 V

0x1FF8 0078-0x1FF8 0079

REFINT out

(1)

VREF_MEAS

Symbol

REFINT

VREFINT

Coeff

(3)

Coeff

(3)

DDCoeff

(3)

S_vrefint

(3)(4)

Table 16. Embedded internal reference voltage

Parameter Conditions Min Typ Max

Internal reference voltage

Internal reference current consumption

Internal reference startup time

DDA

and V

REF+ voltage during V

REFINT factory measure

– 40 °C < T

< +105 °C 1.202 1.224 1.242

1.4

2.3

2 3

2.99

3 3.01

Accuracy of factory-measured V value

(2)

Temperature coefficient

Long-term stability

Voltage coefficient

REF

ADC sampling time when reading the internal reference voltage

Including uncertainties due to ADC and

DDA

REF+

values

–40 °C < T

< +105 °C

0 °C < T

< +50 °C

1000 hours, T= 25 °C

3.0 V < V

DDA

< 3.6 V

±5

1000

2000

ADC_BUF

(3)

Startup time of reference voltage buffer for ADC

BUF_ADC

(3)

Consumption of reference voltage buffer for ADC

VREF_OUT output current (5)

13.5

VREF_OUT

(3)

VREF_OUT

(3)

VREF_OUT output load -

LPBUF

(3)

Consumption of reference voltage buffer for VREF_OUT and COMP

730

REFINT_DIV1

(3)

REFINT_DIV2

(3)

REFINT_DIV3

(3)

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage -

1. Tested in production.

2. The internal V

REF

value is individually measured in production and stored in dedicated EEPROM bytes.

3. Guaranteed by design, not tested in production.

4. Shortest sampling time can be determined in the application by multiple iterations.

5. To guarantee less than 1% VREF_OUT deviation.

1200

Unit

µA ms

V mV ppm/°C ppm ppm/V

µs

µA

µA pF nA

% V

REFINT

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6.3.4 Supply current characteristics

Electrical characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in

Figure 14: Current consumption measurement scheme

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

The current consumption values are derived from the tests performed under ambient temperature T A =25°C and V DD supply voltage conditions summarized in

Table 13: General operating conditions

, unless otherwise specified. The MCU is placed under the following conditions:

The MCU is placed under the following conditions:

• V

= 3.6 V

• All I/O pins are configured in analog input mode.

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time, 64-bit access and prefetch is adjusted depending on f HCLK frequency and voltage range to provide the best CPU performance.

• When the peripherals are enabled f

APB1

= f

APB2

= f

AHB

• When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or

HSE = 16 MHz (if HSE bypass mode is used).

• The HSE user clock applied to OSC_IN input follows the characteristics specified in

Table 26: High-speed external user clock characteristics .

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Table 17. Current consumption in Run mode, code with data processing running from Flash

Max

(1)

Symbol Parameter Conditions f

HCLK

Typ Unit

55 °C 85 °C 105 °C

DD (Run from

Flash)

Supply current in

Run mode, code executed from Flash f

HSE

= f

HCLK up to 16 MHz, f included

HSE

= f

HCLK

(PLL ON)

(2)

/2 above 16 MHz

HSI clock source

(16 MHz)

Range 3,

CORE

=1.2 V

VOS[1:0] = 11

Range 2,

=1.5 V

VOS[1:0] = 10

Range 1,

=1.8 V

VOS[1:0] = 01

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

1 MHz 270 400 400 400

2 MHz 470 600 600 600

4 MHz 890 1025 1025 1025

4 MHz

8 MHz

16 MHz

32 MHz

16 MHz 3.9

8 MHz 2.16

16 MHz 4.8

32 MHz 9.6

9.4

1.3

2.5

5.5

1.3

2.5

5.5

MSI clock, 65 kHz

MSI clock, 524 kHz

MSI clock, 4.2 MHz

Range 3,

CORE

=1.2 V

VOS[1:0] = 11

65 kHz

4.2 MHz

1. Based on characterization, not tested in production, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

0.05 0.085

524 kHz 0.15 0.185

0.9

0.09

0.19

1.3

2.5

5.5

0.1

0.2

µA mA

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Table 18. Current consumption in Run mode, code with data processing running from RAM

Max

(1)

Symbol Parameter Conditions f

HCLK

Typ Unit

55 °C 85 °C 105 °C

DD (Run from

RAM)

Supply current in Run mode, code executed from RAM,

Flash switched off f

HSE

= f

HCLK up to 16 MHz, f included

HSE

= f

HCLK

/2 above 16 MHz

(PLL ON)

(2)

HSI clock source

(16 MHz)

MSI clock, 65 kHz

MSI clock, 524 kHz

MSI clock, 4.2 MHz

Range 3,

CORE

=1.2 V

VOS[1:0] = 11

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

=1.8 V

VOS[1:0] = 01

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

Range 3,

=1.2 V

VOS[1:0] = 11

1 MHz

2 MHz

4 MHz

16 MHz

32 MHz

200 300 300

380 500 500 500

720 860 860 860

(3)

4 MHz 0.9

8 MHz 1.65

3.3

7.8

16 MHz 3.2

3.7

8 MHz 2 2.5

4.5

32 MHz 7.7

8.5

3.8

9.2

3.7

2.5

4.5

8.5

3.8

9.2

300

3.7

2.5

4.5

8.5

3.8

9.2

65 kHz 40 60 60

524 kHz 110 140 140

160

4.2 MHz 700 800 800 820

1. Based on characterization, not tested in production, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

3. Tested in production.

µA mA

µA

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

(Sleep)

Symbol Parameter

Table 19. Current consumption in Sleep mode

Conditions

Range 3,

CORE

=1.2 V

VOS[1:0] = 11

Supply current in

Sleep mode, code executed from RAM,

Flash switched

OFF f

HSE

= f

HCLK

up to

16 MHz included, f

HSE

= f

HCLK

/2 above 16 MHz (PLL

ON) (2)

HSI clock source

(16 MHz)

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

MSI clock, 65 kHz

MSI clock, 524 kHz

MSI clock, 4.2 MHz

Range 3,

CORE

=1.2 V

VOS[1:0] = 11

Max

(1) f

HCLK

Typ

55 °C 85 °C 105 °C

1 MHz 80 140 140 140

2 MHz 150 210 210 210

4 MHz 280 330 330 330

(3)

4 MHz 280 400 400

8 MHz 450 550 550

400

550

16 MHz 900 1050 1050 1050

8 MHz 550 650 650 650

16 MHz 1050 1200 1200 1200

32 MHz 2300 2500 2500 2500

16 MHz 1000 1100 1100 1100

32 MHz 2300 2500 2500 2500

Supply current in

Sleep mode, code executed from Flash

Range 3,

CORE

=1.2 V

VOS[1:0] = 11 f

HSE

= f

HCLK

up to

16 MHz included, f

HSE

= f

HCLK

/2 above 16 MHz (PLL

ON) (2)

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

HSI clock source

(16 MHz)

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

65 kHz 30

524 kHz 50

4.2 MHz 200 240 240

1 MHz 80 140 140

2 MHz 150 210 210

4 MHz 290 350 350

4 MHz 300 400 400

8 MHz 500 600 600

350

400

600

16 MHz 1000 1100 1100 1100

8 MHz 550 650 650 650

250

140

210

16 MHz 1050 1200 1200 1200

32 MHz 2300 2500 2500 2500

16 MHz 1000 1100 1100 1100

32 MHz 2300 2500 2500 2500

Unit

µA

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Symbol Parameter

Table 19. Current consumption in Sleep mode (continued)

Max (1)

Conditions f

HCLK

Typ

55 °C 85 °C 105 °C

(Sleep)

Supply current in

Sleep mode, code executed from Flash

MSI clock, 65 kHz

MSI clock, 524 kHz

MSI clock, 4.2 MHz

Range 3,

CORE

=1.2V

VOS[1:0] = 11

65 kHz

524 kHz

4.2 MHz 210

1. Based on characterization, not tested in production, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)

3. Tested in production

250

100

260

Unit

µA

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Table 20. Current consumption in Low power run mode

Symbol Parameter Conditions Typ

Max

(1)

DD (LP

Run)

Supply current in

Low power run mode

All peripherals

OFF, code executed from RAM,

Flash switched

OFF, V

DD from 1.65 V to 3.6 V

All peripherals

OFF, code executed from Flash,

from

1.65 V to

3.6 V f

MSI clock, 65 kHz

HCLK f

HCLK

MSI clock, 65 kHz f

HCLK f

HCLK

= 32 kHz

MSI clock, 65 kHz f

HCLK

= 65 kHz

MSI clock, 131 kHz f

HCLK

= 131 kHz

MSI clock, 65 kHz

= 32 kHz

= 65 kHz

MSI clock, 131 kHz

= 131 kHz

= -40 °C to 25 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

17.5

Max

(LP

Run)

(2)

Max allowed current in

Low power run mode

from

1.65 V to

3.6 V

200

1. Based on characterization, not tested in production, unless otherwise specified.

2. This limitation is related to the consumption of the CPU core and the peripherals that are powered by the regulator.

Consumption of the I/Os is not included in this limitation.

Unit

µA

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Table 21. Current consumption in Low power sleep mode

Symbol Parameter Conditions Typ

Max

(1)

Unit

(LP

Sleep)

Max

(LP Sleep)

MSI clock, 65 kHz f

HCLK

= 32 kHz

Flash OFF

= -40 °C to 25 °C 4.4

Supply current in

Low power sleep mode

All peripherals

OFF, V

DD from 1.65 V to 3.6 V

TIM9 and

USART1 enabled,

Flash ON,

from

1.65 V to

3.6 V

MSI clock, 65 kHz f

HCLK

= 32 kHz

Flash ON

MSI clock, 65 kHz f

HCLK

= 65 kHz,

Flash ON

MSI clock, 131 kHz f

HCLK

= 131 kHz,

Flash ON

MSI clock, 65 kHz f

HCLK

= 32 kHz

MSI clock, 65 kHz f

HCLK

= 65 kHz

MSI clock, 131 kHz f

HCLK

= 131 kHz

= -40 °C to 25 °C 17.5

= 85 °C 22 27

= 105 °C 31

= -40 °C to 25 °C 18

28 T

= 85 °C

= 105 °C

= -40 °C to 25 °C 22

= 55 °C 24

= 85 °C

= 105 °C

= -40 °C to 25 °C 17.5

= 85 °C 22 27

39 T

= 105 °C 31

= -40 °C to 25 °C 18

= 85 °C

= 105 °C

30 T

= -40 °C to 25 °C 22

= 55 °C 24

= 85 °C

= 105 °C

Max allowed current in

Low power

Sleep mode

from

1.65 V to

3.6 V

200

1. Based on characterization, not tested in production, unless otherwise specified.

µA

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Table 22. Typical and maximum current consumptions in Stop mode

Symbol Parameter Conditions

Typ

(1)

Max

(1)(2)

Unit

DD (Stop with RTC)

Supply current in Stop mode with RTC enabled

RTC clocked by LSI, regulator in LP mode,

HSI and HSE OFF

(no independent watchdog)

RTC clocked by LSE external clock (32.768 kHz), regulator in LP mode, HSI and HSE

OFF (no independent watchdog)

RTC clocked by LSE

(no independent watchdog)

(5)

LCD

OFF

LCD ON

(static duty)

(3)

= -40°C to 25°C

= 1.8 V

1.2

= -40°C to 25°C 1.4

2.75

= 55°C

= 85°C

= 105°C 10.2

= -40°C to 25°C 3.3

= 55°C

= 85°C

2.6

4.8

4.5

6.6

LCD ON

(1/8 duty)

(4)

= 105°C 13.6

= -40°C to 25°C 7.7

= 55°C

= 85°C

8.6

10.7

LCD

OFF

= 105°C 19.8

= -40°C to 25°C 1.6

= 55°C

= 85°C

2.7

4.8

LCD ON

(static duty)

(3)

= 105°C 10.3

= -40°C to 25°C 3.6

= 55°C

= 85°C

4.6

6.7

LCD ON

(1/8 duty)

(4)

= 105°C 10.9

= -40°C to 25°C 7.6

= 55°C

= 85°C

8.6

10.7

LCD

OFF

= 105°C

= -40°C to 25°C

= 1.8 V

= -40°C to 25°C

= 3.0 V

= -40°C to 25°C

= 3.6 V

19.8

1.45

1.9

2.2

µA

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Table 22. Typical and maximum current consumptions in Stop mode (continued)

Symbol Parameter Conditions

Typ

(1)

Max

(1)(2)

Unit

DD (Stop)

Supply current in Stop mode

(RTC disabled)

Regulator in LP mode, HSI and

HSE OFF, independent watchdog and LSI enabled

Regulator in LP mode, LSI, HSI and HSE OFF (no independent watchdog)

DD (WU from Stop)

RMS (root mean square) supply current during wakeup time when exiting from

Stop mode

MSI = 4.2 MHz

MSI = 1.05 MHz

MSI = 65 kHz

(7)

= -40°C to 25°C 1.1

2.2

= -40°C to 25°C 0.5

0.9

= 55°C 1.9

= 85°C

= 105°C

3.7

8.9

(6)

2 -

1.45

= 3.0 V

= -40°C to 25°C

1.45

µA mA

1. The typical values are given for V specified.

= 3.0 V and max values are given for V

= 3.6 V, unless otherwise

2. Based on characterization, not tested in production, unless otherwise specified

3. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected

4. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.

5. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF loading capacitors.

6. Tested in production

7. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the remaining time of the wakeup period, the current is similar to the Run mode current.

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Symbol

Table 23. Typical and maximum current consumptions in Standby mode

Parameter Conditions Typ

(1)

Max

(1)(2)

Unit

(Standby with RTC)

Supply current in Standby mode with RTC enabled

RTC clocked by LSI (no independent watchdog)

RTC clocked by LSE (no independent watchdog)

(3)

= -40 °C to 25 °C

= 1.8 V

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

= -40 °C to 25 °C

= 1.8 V

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

0.9

1.1

1.42

1.87

2.78

1.33

1.59

2.01

3.27

1.8

2.5

2.9

3.4

4.3

6.3

Independent watchdog and LSI enabled

= -40 °C to 25 °C 1.1

1.6

(Standby)

Supply current in Standby mode with RTC disabled

Independent watchdog and LSI OFF

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

0.3

0.5

2.5

0.55

0.8

1.7

(4)

DD (WU from

Standby)

RMS supply current during wakeup time when exiting from Standby mode

= 3.0 V

= -40 °C to 25 °C

1 -

1. The typical values are given for V

= 3.0 V and max values are given for V

= 3.6 V, unless otherwise specified.

2. Based on characterization, not tested in production, unless otherwise specified.

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF loading capacitors.

4. Tested in production.

µA

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions:

• all I/O pins are in input mode with a static value at V

or V

(no load)

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

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APB1

APB2

Table 24. Peripheral current consumption (1)

Typical consumption, V

= 3.0 V, T

= 25 °C

Peripheral

TIM2

TIM3

TIM4

TIM6

TIM7

LCD

WWDG

SPI2

USART2

USART3

I2C1

I2C2

USB

PWR

DAC

COMP

SYSCFG & RI

TIM9

TIM10

TIM11

ADC (2)

SPI1

USART1

10.5

4.5

3.5

2.5

7.5

5.5

9.5

7.5

4.5

7.5

Range 1,

CORE

=1.8 V

VOS[1:0] = 01

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 3,

CORE

=1.2 V

VOS[1:0] = 11

Low power sleep and run

5.5

10.5

8.5

12.5

5.5

4.5

6.5

11.5

5.5

6.5

3.5

2.5

4.5

3.5

8.5

7.5

6.5

10.5

4.5

3.5

2.5

5.5

3.5

4.5

7.5

Unit

µA/MHz

HCLK

)

µA/MHz

HCLK

)

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Table 24. Peripheral current consumption (1) (continued)

Typical consumption, V

= 3.0 V, T

= 25 °C

Peripheral Range 1,

CORE

=1.8 V

VOS[1:0] = 01

Range 2,

CORE

=1.5 V

VOS[1:0] = 10

Range 3,

CORE

=1.2 V

VOS[1:0] = 11

Low power sleep and run

Unit

AHB

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOH

CRC

4.5

0.5

3.5

0.5

4.5

3.5

0.5

µA/MHz

HCLK

)

FLASH

DMA1

11.5

18.5

10.5

All enabled 166 138 106 130

DD (RTC)

DD (LCD)

DD (ADC)

(3)

DD (DAC)

(4)

DD (COMP1)

Slow mode

DD (COMP2)

DD (PVD / BOR)

(5)

DD (IWDG)

Fast mode

0.47

3.1

1450

340

0.16

2.6

0.25

µA

1. Data based on differential I following conditions: f

HCLK

measurement between all peripherals OFF an one peripheral with clock enabled, in the

= 32 MHz (Range 1), f

= f

HCLK

, f

APB2

HCLK

= 16 MHz (Range 2), f

= f

HCLK

= 4 MHz (Range 3), f

HCLK

= 64kHz

(Low power run/sleep), f

APB1

, default prescaler value for each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.

2. HSI oscillator is OFF for this measure.

3. Data based on a differential I

DD measurement between ADC in reset configuration and continuous ADC conversion (HSI consumption not included).

4. Data based on a differential I

DD measurement between DAC in reset configuration and continuous DAC conversion of

/2. DAC is in buffered mode, output is left floating.

5. Including supply current of internal reference voltage.

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6.3.5 Wakeup time from Low power mode

Electrical characteristics

The wakeup times given in the following table are measured with the MSI RC oscillator. The clock source used to wake up the device depends on the current operating mode:

• Sleep mode: the clock source is the clock that was set before entering Sleep mode

• Stop mode: the clock source is the MSI oscillator in the range configured before entering Stop mode

• Standby mode: the clock source is the MSI oscillator running at 2.1 MHz

All timings are derived from tests performed under ambient temperature and V

DD voltage conditions summarized in

Table 13 .

supply

Symbol

Table 25. Low-power mode wakeup timings

Parameter Conditions Typ Max

(1)

Unit t

WUSLEEP

WUSLEEP_LP t t t

WUSTOP

WUSTDBY

Wakeup from Sleep mode f

HCLK

= 32 MHz

Wakeup from Low power sleep mode f

HCLK

= 262 kHz f f

HCLK

= 262 kHz

Flash enabled

HCLK

= 262 kHz

Flash switched OFF

Wakeup from Stop mode, regulator in Run mode f

HCLK

= f

MSI

= 4.2 MHz

Wakeup from Stop mode, regulator in low power mode

0.36

8.2

HCLK

= f

MSI

= 4.2 MHz

Voltage Range 1 and 2 f

HCLK

= f

MSI

= 4.2 MHz

Voltage Range 3

8.2

7.8

9.3

11.2

f f

HCLK

= f

MSI

= 2.1 MHz 10 f f

HCLK

= f

MSI

= 1.05 MHz 15.5

HCLK

= f

MSI

= 524 kHz 29

HCLK

= f

MSI

= 262 kHz f

HCLK

= f

MSI

= 131 kHz

105

118 f

HCLK

= MSI = 65 kHz 210 237

Wakeup from Standby mode

FWU bit = 1

Wakeup from Standby mode

FWU bit = 0 f f

HCLK

= MSI = 2.1 MHz

2.5

103

3.2

1. Based on characterization, not tested in production, unless otherwise specified

µs ms

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The

external clock signal has to respect the I/O characteristics in Section 6.3.13

. However, the

Symbol

Table 26. High-speed external user clock characteristics (1)

Parameter Conditions Min f

HSE_ext

User external clock source frequency

CSS is on or

PLL is used

CSS is off, PLL not used

HSEH

HSEL t w(HSEH) t w(HSEL) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

OSC_IN input capacitance

Duty cycle

OSC_IN Input leakage current

1. Guaranteed by design, not tested in production.

≤ V

0.7V

Typ

2.6

Max

0.3V

±1

Unit

MHz

V ns pF

µA

Figure 15. High-speed external clock source AC timing diagram

WZ+6(+

9+6(+

9+6(/

WU+6(

7+6(

WI+6( WZ+6(/

069

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Low-speed external user clock generated from an external source

The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions summarized in

Table 13 .

Symbol

Table 27. Low-speed external user clock characteristics (1)

Parameter Conditions f

LSE_ext

LSEH

User external clock source frequency

OSC32_IN input pin high level voltage

LSEL

OSC32_IN input pin low level voltage

t w(LSEH) t w(LSEL) t r(LSE) t f(LSE)

IN(LSE)

DuCy

(LSE)

OSC32_IN high or low time

OSC32_IN rise or fall time

OSC32_IN input capacitance

Duty cycle

OSC32_IN Input leakage current V

≤ V

1. Guaranteed by design, not tested in production

Min

0.7V

465

Typ

32.768

0.6

Max Unit

1000 kHz

0.3V

±1

V ns pF

µA

Figure 16. Low-speed external clock source AC timing diagram

WZ/6(+

9/6(+

9/6(/

WU/6(

7/6(

WI/6(

WZ/6(/

069

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 28

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Symbol

Table 28. HSE oscillator characteristics (1)(2)

Parameter f

OSC_IN

Oscillator frequency

Feedback resistor

Recommended load capacitance versus equivalent serial resistance of the crystal (R

)

(3)

Conditions

= 30 Ω

Min Typ

200

HSE

HSE driving current

DD(HSE)

HSE oscillator power consumption

= 3.3 V, V

= V

SS with 30 pF load

C = 20 pF f

OSC

= 16 MHz

C = 10 pF f

OSC

= 16 MHz

Max

2.5 (startup)

0.7 (stabilized)

2.5 (startup)

0.46 (stabilized) g m

Oscillator transconductance Startup 3.5

Startup time V

is stabilized 1 -

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization results, not tested in production.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Unit

MHz k Ω pF mA mA mA

/V ms

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 17

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

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Figure 17. HSE oscillator circuit diagram

(3%

TOCORE

2ESONATOR

/3#?).

#ONSUMPTION

CONTROL

2ESONATOR

34-

/3#?/54

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 29

Symbol

Table 29. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions Min Typ Max Unit f

LSE

Low speed external oscillator frequency

32.768

kHz

Feedback resistor 1.2

M Ω

(2)

Recommended load capacitance versus equivalent serial resistance of the crystal (R

)

(3)

LSE driving current

= 30 k Ω 8 pF

LSE

DD (LSE)

LSE oscillator current consumption

= 3.3 V, V

= V

= 1.8 V

= 3.0 V

= 3.6V

450

600

750

1.1

µA nA g m t

SU(LSE)

(4)

Oscillator transconductance

Startup time V

is stabilized

1 -

µA/V

1. Based on characterization, not tested in production.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”.

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R

value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details.

4. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to

15 pF range selected to match the requirements of the crystal or resonator (see

Figure 18

CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.

Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF.

Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load capacitance of 12.5 pF.

Example: if you choose a resonator with a load capacitance of CL = 6 pF and Cstray = 2 pF, then CL1 = CL2 = 8 pF.

Figure 18. Typical application with a 32.768 kHz crystal

2ESONATORWITH

INTEGRATEDCAPACITORS

K( Z

RESONATOR

/3#?).

"IAS

CONTROLLED

GAIN

/3#?/5 4

F,3%

34-,XX

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6.3.7 Internal clock source characteristics

Electrical characteristics

The parameters given in the following table are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 13 .

High-speed internal (HSI) RC oscillator

Symbol

Table 30. HSI oscillator characteristics

Parameter Conditions Min Typ Max Unit f

HSI

TRIM

(1)(2)

ACC

HSI

(2)

Frequency

HSI user-trimmed resolution

Accuracy of the factory-calibrated

HSI oscillator

= 3.0 V

Trimming code is not a multiple of 16

Trimming code is a multiple of 16

DDA

= 3.0 V, T

= 25 °C

DDA

= 3.0 V, T

= 0 to 55 °C

DDA

= 3.0 V, T

= -10 to 70 °C

DDA

= 3.0 V, T

= -10 to 85 °C

DDA

= 3.0 V, T

= -10 to 105 °C

DDA

= 1.65 V to 3.6 V

= -40 to 105 °C

-1

(3)

-1.5

-2

-2.5

-4

± 0.4

0.7

1.5

MHz

± 1.5

1 (3) %

3 %

I t

SU(HSI)

(2)

DD(HSI)

(2)

HSI oscillator startup time

HSI oscillator power consumption

3.7

100

140

1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).

2. Based on characterization, not tested in production.

3. Tested in production.

µs

µA

Low-speed internal (LSI) RC oscillator

Table 31. LSI oscillator characteristics

Symbol Parameter Min Typ f

LSI

(1)

LSI frequency 26 38

LSI

(2)

LSI oscillator frequency drift

0°C ≤

85°C

LSI oscillator startup time

-10 t su(LSI)

(3)

DD(LSI)

(3)

LSI oscillator power consumption -

400

1. Tested in production.

2. This is a deviation for an individual part, once the initial frequency has been measured.

3. Guaranteed by design, not tested in production.

Max

200

510

Unit kHz

µs nA

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Multi-speed internal (MSI) RC oscillator

Symbol f

MSI

Table 32. MSI oscillator characteristics

Parameter Condition

Frequency after factory calibration, done at

= 3.3 V and T

= 25 °C

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6

ACC

MSI

TEMP(MSI)

(1)

VOLT(MSI)

(1)

Frequency error after factory calibration

MSI oscillator frequency drift

0 °C ≤ T

≤

MSI oscillator frequency drift

1.65 V ≤ V

≤

= 25 °C

DD(MSI)

(2) t

SU(MSI)

MSI oscillator power consumption

MSI oscillator startup time

± 3

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6,

Voltage range 1 and 2

MSI range 6,

Voltage range 3

0.75

1.5

2.5

4.5

3.5

65.5

131

262

524

1.05

2.1

4.2

± 0.5

Typ Max Unit

kHz

MHz

2.5

%/V

µA

µs

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Symbol

Table 32. MSI oscillator characteristics (continued)

Parameter Condition t

STAB(MSI)

(2) f

OVER(MSI)

MSI oscillator stabilization time

MSI oscillator frequency overshoot

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6,

Voltage range 1 and 2

MSI range 3,

Voltage Range 3

Any range to range 5

Any range to range 6

1. This is a deviation for an individual part, once the initial frequency has been measured.

2. Based on characterization, not tested in production.

Typ Max Unit

2.5

µs

MHz

The parameters given in

Table 33 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Table 13 .

Table 33. PLL characteristics

Value

Symbol Parameter Unit

Min Typ Max

(1) f

PLL_IN

PLL input clock (2)

PLL input clock duty cycle

45 -

MHz

% t f

PLL_OUT

LOCK

PLL output clock

Worst case PLL lock time

PLL input = 2 MHz

PLL VCO = 96 MHz

100

130

MHz

µs

Jitter Cycle-to-cycle jitter ± 600 ps

DDA

(PLL)

Current consumption on V

DDA

Current consumption on V

220

120

450

150

µA

1. Based on characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

The characteristics are given at T

= -40 to 105 °C unless otherwise specified.

RAM memory

Symbol

Table 34. RAM and hardware registers

Parameter Conditions Min Typ Max Unit

Data retention mode

(1)

STOP mode (or RESET) 1.65

V VRM

1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode).

Flash memory and data EEPROM

Symbol

Table 35. Flash memory and data EEPROM characteristics

Parameter Conditions t

DD prog

Operating voltage

Read / Write / Erase

Programming time for word or half-page

Erasing

Programming

Average current during whole program/erase operation

Maximum current (peak) during program/erase operation

= 25 °C, V

= 3.6 V

1. Guaranteed by design, not tested in production.

Min

1.65

Typ Max

(1)

3.28

300

1.5

3.6

3.94

2.5

Unit

V ms

µA mA

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Symbol

Table 36. Flash memory, data EEPROM endurance and data retention

Value

Parameter Conditions

Min

(1)

Typ Max

NCYC

(2)

Cycling (erase / write)

Program memory

Cycling (erase / write)

EEPROM data memory

= -40°C to

105 °C t

RET

(2)

Data retention (program memory) after

10 kcycles at T

= 85 °C

Data retention (EEPROM data memory) after 300 kcycles at T

= 85 °C

Data retention (program memory) after

10 kcycles at T

= 105 °C

Data retention (EEPROM data memory) after 300 kcycles at T

= 105 °C

TRET = +85 °C

TRET = +105 °C

1. Based on characterization not tested in production.

2. Characterization is done according to JEDEC JESD22-A117.

300

10 -

Unit kcycles years

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

SS compliant with the IEC 61000-4-4 standard.

and

through a 100 pF capacitor, until a functional disturbance occurs. This test is

A device reset allows normal operations to be resumed.

The test results are given in

Table 37

. They are based on the EMS levels and classes defined in application note AN1709.

Table 37. EMS characteristics

Symbol

FESD

EFTB

Parameter Conditions

Level/

Class

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

= 3.3 V, LQFP100, T

= +25 °C, f

HCLK

= 32 MHz conforms to IEC 61000-4-2

= 3.3 V, LQFP100, T

= +25 f

°C,

HCLK

= 32 MHz conforms to IEC 61000-4-4

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Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

EMI

Symbol Parameter

Table 38. EMI characteristics

Conditions

Peak level

= 3.3 V,

= 25 °C,

LQFP100 package compliant with IEC

61967-2

Monitored frequency band

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

Max vs. frequency range

4 MHz voltage

Range 3

2.5

16 MHz voltage

Range 2

-6

32 MHz voltage

Range 1

-5

-7

Unit dBµV

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Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Symbol

Table 39. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

Electrostatic discharge voltage (human body model)

= +25 °C, conforming to

JESD22-A114

ESD(CDM)

Electrostatic discharge voltage (charge device model)

= +25 °C, conforming to

ANSI/ESD STM5.3.1

1. Based on characterization results, not tested in production.

2000

500

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol

Parameter

Table 40. Electrical sensitivities

Conditions

Static latch-up class T

= +105 °C conforming to JESD78A

Class

II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

(for standard pins) should be avoided during normal product operation.

or above V

However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

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Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error, out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation, LCD levels, etc.).

The test results are given in

Table 41

Symbol

INJ

Table 41. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

Injected current on all 5 V tolerant (FT) pins

Injected current on any other pin

-5

Unit mA

Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

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General input/output characteristics

Unless otherwise specified, the parameters given in Table 42

are derived from tests performed under conditions summarized in

Table 13 . All I/Os are CMOS and TTL compliant.

Symbol

V hys hysteresis

(2)

Parameter

Input low level voltage

Input high level voltage

I/O Schmitt trigger voltage

Table 42. I/O static characteristics

Conditions

Standard I/O

FT I/O

Standard I/O

FT I/O

≤ V

I/Os with LCD

≤ V

I/Os with analog switches

Min

0.7 V

Typ

10% V

5% V

(3)

(4)

Max

0.3V

(1)

±50

I lkg

Input leakage current

(5)

≤ V

I/Os with analog switches and LCD

≤ V

I/Os with USB

±50

TBD

FT I/O

≤ V

≤ 5V

≤ V

Standard I/Os

TBD

±50

Weak pull-up equivalent resistor

Weak pull-down equivalent resistor

I/O pin capacitance

(6)(1)

(6)

= V

1. Tested in production

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

3. With a minimum of 200 mV. Based on characterization, not tested in production.

4. With a minimum of 100 mV. Based on characterization, not tested in production.

5. The max. value may be exceeded if negative current is injected on adjacent pins.

6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order).

Unit

V nA k Ω k Ω pF

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Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with the non-standard V

specifications given in Table 43 .

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

• The sum of the currents sourced by all the I/Os on V

DD,

I consumption of the MCU sourced on V

DD,

VDD Σ

(see Table 11

). plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

I consumption of the MCU sunk on V

VSS Σ

(see Table 11 ).

plus the maximum Run

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in Table 43

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 13 . All I/Os are CMOS and TTL compliant.

Symbol

Table 43. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)(2)

(3)(2)

(1)(4)

(3)(4)

(1)(4)

(3)(4)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

1.65 V < V

= +8 mA

2.7 V < V

< 3.6 V

=+ 4 mA

< 2.7 V

= +20 mA

< 3.6 V

2.4

-0.45

-1.3

0.4

0.45

1.3

1. The I

current sunk by the device must always respect the absolute maximum rating specified in

Table 11

and the sum of

(I/O ports and control pins) must not exceed I

VSS

2. Tested in production.

3. The I of I

current sourced by the device must always respect the absolute maximum rating specified in

Table 11

and the sum

(I/O ports and control pins) must not exceed I

VDD

4. Based on characterization data, not tested in production.

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Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 19 and

Table 44 , respectively.

Unless otherwise specified, the parameters given in Table 44

are derived from tests performed under ambient temperature and V

Table 13 .

supply voltage conditions summarized in

Table 44. I/O AC characteristics (1)

OSPEEDRx

[1:0] bit value (1)

Symbol Parameter Conditions Min Max

(2)

f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out

F max(IO)out t f(IO)out t r(IO)out

F max(IO)out t f(IO)out t r(IO)out t

EXTIpw

Maximum frequency

(3)

Output rise and fall time

Maximum frequency

(3)

Output rise and fall time

Maximum frequency

(3)

Output rise and fall time

Maximum frequency

(3)

Output rise and fall time

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V -

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V -

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V -

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V -

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V -

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V -

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V -

= 30 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 1.65 V to 2.7 V -

Pulse width of external signals detected by the

EXTI controller

8 -

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L15xx6/8/B reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design. Not tested in production.

3. The maximum frequency is defined in

Figure 19 .

125

250

400

625

Unit kHz ns

MHz ns

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Figure 19. I/O AC characteristics definition

%XTERNAL

/UTPUT

ONP&

TR )/ OUT TF)/ OUT

-AXIMUMFREQUENCYISACHIEVEDIFT

F a 4ANDIFTHEDUTYCYCLEIS

WHENLOADEDBYP&

AIB

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see

Table 45 ).

Unless otherwise specified, the parameters given in Table 45

are derived from tests performed under ambient temperature and V

Table 13 .

supply voltage conditions summarized in

Symbol

IL(NRST)

(1)

IH(NRST)

(1)

OL(NRST)

(1) voltage

Table 45. NRST pin characteristics

Parameter

NRST input low level voltage

NRST input high level voltage

NRST output low level

Conditions

= 2 mA

2.7 V < V

< 3.6 V

= 1.5 mA

1.65 V < V

< 2.7 V

Min

1.4

Typ

Max Unit

0.8

0.4

V hys(NRST)

(1)

NRST Schmitt trigger voltage hysteresis

10%V

(2) mV

Weak pull-up equivalent resistor

(3)

= V

30 45 60 k Ω

F(NRST)

(1)

NF(NRST)

(1)

NRST input filtered pulse

NRST input not filtered pulse -

350 -

1. Guaranteed by design, not tested in production.

2. 200 mV minimum value

3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is around 10%.

ns ns

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Figure 20. Recommended NRST pin protection

%XTERNAL

RESETCIRCUIT

.234

6$$

205

&ILTER

)NTERNALRESET

34-,XX

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 45 . Otherwise the reset will not be taken into account by the device.

max level specified in

The parameters given in

Table 46 are guaranteed by design.

Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 46. TIMx (1) characteristics

Parameter Conditions Min t t res(TIM) f

EXT

Res

TIM

COUNTER

Timer resolution time

Timer external clock frequency on CH1 to CH4

Timer resolution

16-bit counter clock period when internal clock is selected (timer’s prescaler disabled)

TIMxCLK

= 32 MHz 31.25

0 f

TIMxCLK

= 32 MHz

TIMxCLK

= 32 MHz 0.0312

MAX_COUNT

Maximum possible count

TIMxCLK

= 32 MHz -

1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.

Max

TIMxCLK

65536

2048 µs

65536 × 65536 t

TIMxCLK

134.2

Unit t

TIMxCLK ns

MHz

MHz bit t

TIMxCLK

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

I

C interface characteristics

The STM32L15xx6/8/B product line I

C interface meets the requirements of the standard

C communication protocol with the following restrictions: SDA and SCL are not “true” open-drain I/O pins. When configured as open-drain, the PMOS connected between the I/O pin and V

DD is disabled, but is still present.

The I

C characteristics are described in

Table 47

. Refer also to

Section 6.3.12: I/O current injection characteristics

for more details on the input/output alternate function characteristics

(SDA and SCL).

Symbol Parameter

Table 47. I 2 C characteristics

Standard mode I

(1)

Min Max

Fast mode I

(1) (2)

Unit

Min Max t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

4.7

4.0

250

1000

300

1.3

0.6

100

20 + 0.1C

900

(3)

300

µs ns t t su(STA) su(STO) t w(STO:STA)

C b

Start condition hold time

Repeated Start condition setup time

Stop condition setup time

Stop to Start condition time

(bus free)

Capacitive load for each bus line

4.0

4.7

4.0

4.7

400

0.6

0.6 -

0.6

1.3

400

µs

μ pF

1. Guaranteed by design, not tested in production.

2. f

PCLK1 must be at least 2 MHz to achieve standard mode I ² C frequencies. It must be at least 4 MHz to achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast mode clock.

3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal.

s s

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Figure 21. I 2 C bus AC waveforms and measurement circuit s ͺ/Ϯ s ͺ/Ϯ

Ϯ ďƵƐ

^dDϯϮ>ϭǆǆ

^dZdZWd

^dZd ƚ

ƐƵ;^dͿ

^dZd

^ ƚ

Ĩ;^Ϳ ƚ ƌ;^Ϳ ƚ

ƐƵ;^Ϳ ƚ

Ś;^Ϳ

^dKW ƚ

ƐƵ;^d͗^dKͿ ƚ

Ś;^dͿ ƚ

ǁ;^<>Ϳ

^> ƚ

ǁ;^<,Ϳ ƚ ƌ;^<Ϳ ƚ

Ĩ;^<Ϳ ƚ

ƐƵ;^dKͿ

ĂŝϭϳϴϱϱĐ

1. R

= series protection resistors

2. R

= pull-up resistors

3. V

DD_I2C

= I2C bus supply

4. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

Table 48. SCL frequency (f

PCLK1

= 32 MHz, V

= V

DD_I2C

= 3.3 V)

(1)(2)

I2C_CCR value f

SCL

(kHz)

= 4.7 k Ω

400

300

200

100

0x801B

0x8024

0x8035

0x00A0

50 0x0140

20 0x0320

1. R

= External pull-up resistance, f

SCL

= I

C speed.

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ± 5%. For other speed ranges, the tolerance on the achieved speed is ± 2%. These variations depend on the accuracy of the external components used to design the application.

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

SPI characteristics

Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, f

conditions summarized in Table 13

PCLKx frequency and V

supply voltage

Refer to Section 6.3.12: I/O current injection characteristics for more details on the

input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol

Table 49. SPI characteristics (1)

Parameter Conditions Min Max

(2)

Unit

1/t f

SCK c(SCK)

SPI clock frequency

Master mode

Slave mode

Slave transmitter

(3)

MHz t t r(SCK)

(2) f(SCK)

(2)

SPI clock rise and fall time

Capacitive load: C = 30 pF 6 ns

DuCy(SCK)

SPI slave input clock duty cycle

Slave mode 30 70 % t su(NSS) t h(NSS) t t w(SCKH)

(2) w(SCKL)

(2) t su(MI)

(2) t su(SI)

(2) t h(MI)

(2) t h(SI)

(2) t a(SO)

(4) t v(SO)

(2) t v(MO)

(2) t h(SO)

(2) t h(MO)

(2)

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Data input hold time

Data output access time

Data output valid time

Data output hold time

Slave mode

Master mode

Slave mode

Master mode

Slave mode

Master mode

Slave mode

Master mode

HCLK

HCLK t

SCK

/2 −

0.5

SCK

HCLK

/2+

6.5

1. The characteristics above are given for voltage Range 1.

2. Based on characterization, not tested in production.

3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK)) ranging between 40 to 60%.

4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.

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Figure 22. SPI timing diagram - slave mode and CPHA = 0

NSS input tc(SCK) tSU(NSS)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tw(SCKH) tw(SCKL) ta(SO)

MISO

OUT P UT tsu(SI)

MOSI

I NPUT tv(SO)

MS B O UT

M SB IN th(SI) th(SO)

BI T6 OUT

B I T1 IN tr(SCK) tf(SCK)

LSB OUT tdis(SO)

LSB IN th(NSS)

Figure 23. SPI timing diagram - slave mode and CPHA = 1

(1) ai14134c

NSS input tSU(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 tw(SCKH) tw(SCKL)

MISO

OUT P UT ta(SO) tsu(SI)

MOSI

I NPUT tc(SCK) tv(SO)

MS B O UT th(SI)

M SB IN B I T1 IN th(SO)

BI T6 OUT th(NSS) tr(SCK) tf(SCK) tdis(SO)

LSB OUT

LSB IN

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

ai14135

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Figure 24. SPI timing diagram - master mode (1)

NSS input

High

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tc(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MS BIN th(MI)

M SB OUT tv(MO)

BI T6 IN

B I T1 OUT th(MO) tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

USB characteristics

The USB interface is USB-IF certified (full speed).

Symbol

Table 50. USB startup time

Parameter t

STARTUP

(1) USB transceiver startup time

1. Guaranteed by design, not tested in production.

Max

Unit

µs

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Symbol

Table 51. USB DC electrical characteristics

Parameter Conditions Min.

(1)

Max.

(1)

Unit

Input levels

(3)

USB operating voltage

Differential input sensitivity I(USB_DP, USB_DM)

Differential common mode range Includes V

Single ended receiver threshold

Output levels

(2) -

DI range

3.0

0.2

0.8

1.3

3.6

2.5

2.0

(4)

Static output level low

Static output level high

of 1.5

k Ω to 3.6 V

of 15 k Ω to V

(5)

2.8

0.3

3.6

1. All the voltages are measured from the local ground potential.

2. To be compliant with the USB 2.0 full speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 k Ω resistor to a 3.0-to-3.6 V voltage range.

3. Guaranteed by characterization, not tested in production.

4. Tested in production.

5. R

is the load connected on the USB drivers.

Figure 25. USB timings: definition of data signal rise and fall time

Crossover points

Differen tial

Data L ines

VCRS

VS S tf tr ai14137

Table 52. USB: full speed electrical characteristics

Driver characteristics

(1)

Symbol Parameter Conditions Min Max t r t f t rfm

CRS

Rise time

Fall Time

(2)

Rise/ fall time matching

Output signal crossover voltage

= 50 pF

= 50 pF t r

/t f

1.3

110

2.0

1. Guaranteed by design, not tested in production.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

Unit ns ns

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Unless otherwise specified, the parameters given in Table 54

are guaranteed by design.

Symbol Parameter f

ADC

ADC clock frequency

Table 53. ADC clock frequency

Voltage

Range 1 &

Conditions

2.4 V ≤

DDA

3.6 V

1.8 V ≤

DDA

2.4 V

Min

REF+ =

DDA

REF+

< V

DDA

> 2.4 V

REF+

< V

DDA

REF+

REF+ =

DDA

REF+

< V

DDA

0.480

Voltage Range 3

Max Unit

MHz

Symbol

DDA

REF+

REF-

VDDA

VREF

(2)

AIN f

Parameter

Table 54. ADC characteristics

Conditions Min

Power supply

Positive reference voltage

2.4 V ≤

DDA

3.6 V

REF+

must be below or equal to V

DDA

1.8

(1)

Negative reference voltage

Current on the V

DDA pin

input

Current on the V

REF pin

input

Conversion voltage range

(3)

12-bit sampling rate

10-bit sampling rate

8-bit sampling rate

6-bit sampling rate

Peak

Average

(4)

Direct channels 0.03

Multiplexed channels 0.03

Direct channels 0.03

Multiplexed channels 0.03

Direct channels 0.03

Multiplexed channels 0.03

Direct channels 0.03

Multiplexed channels 0.03

SSA

1000

400

Typ

Max

3.6

DDA

1450

0.8

1.23

0.89

1.45

700

450

REF+

0.76

1.07

Unit

Msps

µA

Msps

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Symbol

Table 54. ADC characteristics (continued)

Parameter Conditions Min Typ Max Unit t

Sampling time

(5)

Direct channels

2.4 V ≤

DDA

3.6 V

Multiplexed channels

2.4 V ≤

DDA

3.6 V

Direct channels

1.8 V ≤

DDA

2.4 V

Multiplexed channels

1.8 V ≤

DDA

2.4 V

ADC

= 16 MHz

0.25

0.56

384

24.75

1/f

µs

ADC

µs t

CONV

ADC

Total conversion time

(including sampling time)

Internal sample and hold capacitor

Direct channels

4 to 384 (sampling phase) +12 (successive approximation)

1/f

ADC pF

Multiplexed channels f f

TRIG

AIN

External trigger frequency

Regular sequencer

External trigger frequency

Injected sequencer

Signal source impedance

(5)

Injection trigger conversion latency

12-bit conversions

6/8/10-bit conversions

12-bit conversions

6/8/10-bit conversions

ADC

= 16 MHz

ADC

= 16 MHz

219

Tconv+1 1/f

ADC

Tconv 1/f

ADC

Tconv+2 1/f

ADC

Tconv+1 1/f

ADC

50 κΩ

281 ns t lat t latr t

STAB

Regular trigger conversion latency

Power-up time -

3.5

156

2.5

4.5

219

3.5

1/f

ADC ns

1/f

ADC

µs

1. The V

REF+

input can be grounded iif neither the ADC nor the DAC are used (this allows to shut down an external voltage reference).

2. The current consumption through V

REF

is composed of two parameters:

- one constant (max 300 µA)

- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.

So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400

= 450 µA at 1Msps

3. V can be internally connected to V the package. Refer to

DDA

and V

Section 4: Pin descriptions

REF-

can be internally connected to V

for further details.

SSA

, depending on

4. V

SSA

must be tied to ground.

5. See

Figure 56: R

AIN

max for f

ADC

= 16 MHz

for R

AIN limitation.

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Symbol Parameter

Table 55. ADC accuracy (1)(2)

Test conditions Min

(3)

Typ Max

(3)

Unit

Total unadjusted error

Offset error

Gain error

Differential linearity error

EL Integral linearity error

ENOB Effective number of bits

SINAD

Signal-to-noise and distortion ratio

SNR Signal-to-noise ratio

THD Total harmonic distortion

ET Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

2.4 V ≤ V f

ADC

DDA

2.4 V ≤ V

REF+

≤ 3.6 V

= 8 MHz, R

AIN

= -40 to 105 ° C

= 50 Ω

9.2

1.5

1.7

1.5

-75

3.5

LSB f

2.4 V ≤ V

DDA

≤ 3.6 V

DDA =

REF+ f

ADC

= 16 MHz, R

AIN

= 50 Ω

1.8 V ≤ V

ADC

= -40 to 105

1 kHz

2.4 V ≤

≤ F

V input

DDA

REF+

≤

3.6 V

1.8 V ≤ V

REF+

≤ 2.4 V f

ADC

= 4 MHz, R

AIN

= 50 Ω

= -40 to 105 ° C

≤ 2.4 V

= 4 MHz, R

= -40 to 105

100 kHz

2.4 V

AIN

= 50 Ω

57.5

-74

62 bits dB

LSB

1. ADC DC accuracy values are measured after internal calibration.

2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

in Section 6.3.12

does not affect the ADC

3. Based on characterization, not tested in production.

1.5

6.5

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STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics

Figure 26. ADC accuracy characteristics

4095

4094

4093

[1LSB

IDEAL

REF+

4096

(or depending on package)]

4096

(2)

(3)

1 LSB

IDEAL

(1)

SSA

1 2 3 4 5 6 7 4093 4094 4095 4096

DDA

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

=Offset Error: deviation between the first actual transition and the first ideal one.

=Gain Error: deviation between the last ideal transition and the last actual one.

=Differential Linearity Error: maximum deviation between actual steps and the ideal one.

=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

ai14395b s

;ϭͿ

Figure 27. Typical connection diagram using the ADC s

/Eǆ

ƉĂƌĂƐŝƚŝĐ

/>цϱϬŶ

^dDϯϮ>ǆǆ

^ĂŵƉůĞĂŶĚŚŽůĚ

ĐŽŶǀĞƌƚĞƌ

;ϭͿ ϭϮͲďŝƚ

ĐŽŶǀĞƌƚĞƌ

;ϭͿ

Ăŝϭϳϴϱϲď

1. Refer to Table 56: R

the value of CADC

AIN

max for f

ADC

= 16 MHz

for the value of R

AIN

and

Table 54: ADC characteristics

for

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 this, f

ADC pF). A high C

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

DocID17659 Rev 10

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103

Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Figure 28. Maximum dynamic current consumption on V

REF+ conversion

supply pin during ADC

Conversion (12 cycles)

ADC clock

I ref+

700µA

Sampling (n cycles)

300µA

Table 56. R

AIN

max for f

ADC

= 16 MHz (1)

AIN

max (kOhm)

(cycles)

(µs)

Multiplexed channels Direct channels

192

384

0.25

0.5625

1.5

2.4 V < V

DDA

< 3.6 V 1.8 V < V

DDA

< 2.4 V 2.4 V < V

DDA

< 3.3 V 1.8 V < V

DDA

< 2.4 V

Not allowed

0.8

Not allowed

0.7

2.0

Not allowed

1.0

2.0

3.0

6.8

15.0

32.0

50.0

0.8

1.8

4.0

10.0

25.0

50.0

4.0

6.0

15.0

30.0

50.0

3.0

4.5

10.0

20.0

40.0

50.0

1. Guaranteed by design, not tested in production.

General PCB design guidelines

Power supply decoupling should be performed as shown in The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip.

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STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics

Figure 29. Power supply and reference decoupling (V

REF+ not connected to V

DDA

)

670/[[

95()

VHHQRWH

)Q) 9''$

)Q)

966$ 95()±

VHHQRWH

DLE

1. V

REF+

and V

REF–

inputs are available only on 100-pin packages.

Figure 30. Power supply and reference decoupling (V

REF+ connected to V

DDA

)

34-,XX

6

$$!

&N&

1. V

REF+

and V

REF–

inputs are available only on 100-pin packages.

6

33!

AIB

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103

Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Data guaranteed by design, not tested in production, unless otherwise specified.

Symbol

DDA

REF+

REF-

DDVREF+

(1)

DDA

(1)

(2)

Parameter

Table 57. DAC characteristics

Conditions

Analog supply voltage -

Reference supply voltage

Lower reference voltage

REF+

must always be below

DDA

No load, middle code (0x800) Current consumption on

REF+

supply

REF+

= 3.3 V

Current consumption on

DDA

supply

DDA

= 3.3 V

Resistive load

No load, worst code (0x000)

No load, middle code (0x800)

No load, worst code (0xF1C)

DAC output buffer ON

Capacitive load

Output impedance DAC output buffer OFF

Min

1.8

Typ

130

SSA

220

210

320

Max

3.6

220

350

320

520

DAC output buffer ON 0.2 V

DDA

– 0.2

DAC_OUT

Voltage on DAC_OUT output

DAC output buffer OFF 0.5

REF+

1LSB

–

Unit

µA

µA k Ω pF k Ω

V mV

DNL

(1)

INL

(1)

Offset

(1)

Offset1 (1)

Differential non linearity

(3)

Integral non linearity

(4)

Offset error at code

0x800

(5)

Offset error at code

0x001

(6)

≤

≥ 5 k Ω

DAC output buffer ON

No R

LOAD

, C

≤

DAC output buffer OFF

≤

≥ 5 k Ω

DAC output buffer ON

No R

LOAD

, C

≤

DAC output buffer OFF

≤

≥ 5 k Ω

DAC output buffer ON

No R

LOAD

, C

≤

DAC output buffer OFF

No R

LOAD

, C

≤

DAC output buffer OFF

1.5

±10

±5

±1.5

±25

±8

±5

LSB

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STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics

Symbol Parameter

Table 57. DAC characteristics (continued)

Conditions Min Typ Max Unit t t dOffset/dT

(1)

Gain

(1) dGain/dT

TUE

(1)

SETTLING

(1)

Update rate

WAKEUP

PSRR+

Offset error temperature coefficient (code 0x800)

Gain error

Gain error temperature coefficient

(7)

Total unadjusted error

DDA

= 3.3V, T

= 0 to 50 ° C

DAC output buffer OFF

DDA

= 3.3V, T

= 0 to 50 ° C

DAC output buffer ON

≤

≥ 5 k Ω

DAC output buffer ON

No R

LOAD

, C

≤

DAC output buffer OFF

DDA

= 3.3V, T

= 0 to 50 ° C

DAC output buffer OFF

DDA

= 3.3V, T

= 0 to 50 ° C

DAC output buffer ON

≤

≥ 5 k Ω

DAC output buffer ON

No R

LOAD

, C

≤

DAC output buffer OFF

Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes till

DAC_OUT reaches final value ±1LSB

Max frequency for a correct DAC_OUT change (95% of final value) with 1 LSB variation in the input code

Wakeup time from off state (setting the ENx bit in the DAC Control register)

(8)

DDA

supply rejection ratio (static DC measurement)

≤

≥ 5 k Ω

≤

≥ 5 k Ω

≤

≥ 5 k Ω

≤

≥ 5 k Ω

-20

-10

-40

-10

+0.1 /

-0.2%

+0 / -0.2%

-2

-8

+0.2 / -0.5%

+0 / -0.4%

-60 -35

µV/°C

LSB

µs

Msps

µs dB

1. Data based on characterization results.

2. Connected between DAC_OUT and V

SSA

3. Difference between two consecutive codes - 1 LSB.

4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

5. Difference between the value measured at Code (0x800) and the ideal value = V/2.

6. Difference between the value measured at Code (0x001) and the ideal value.

7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (V

DDA

– 0.2) V when buffer is ON.

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103

Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

Figure 31. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)

12-bit digital to analog converter

DAC_OUTx

L ai17157V2

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

6.3.19 Temperature sensor characteristics

Table 58. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at temperature of 30 °C,

DDA

= 3 V

TS ADC raw data acquired at temperature of 110 °C

DDA

= 3 V

0x1FF8 007A-0x1FF8 007B

0x1FF8 007E-0x1FF8 007F

Symbol

(1)

Avg_Slope

110

(1)

DDA(TEMP)

(3) t

START

(3)

S_temp

(4)(3)

Table 59. Temperature sensor characteristics

Parameter

SENSE

linearity with temperature

Average slope

Voltage at 110°C ±5°C

(2)

Current consumption

Startup time

ADC sampling time when reading the temperature

Min

1.48

612

Typ

1.61

626.8

3.4

Max

± 2

1.75

641.5

1. Guaranteed by characterization, not tested in production.

2. Measured at V

= 3 V ±10 mV. V110 ADC conversion result is stored in the TS_CAL2 byte.

3. Guaranteed by design, not tested in production.

4. Shortest sampling time can be determined in the application by multiple iterations.

Unit

°C mV/°C mV

µA

µs

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STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics

6.3.20 Comparator

Symbol

Table 60. Comparator 1 characteristics

Parameter Conditions Min

(1)

Typ Max

(1)

Unit

DDA

400K

10K

Analog supply voltage

400K

value

10K

value

Comparator 1 input voltage range

Comparator startup time

Propagation delay

(2)

1.65

0.6

400

3.6

DDA k

V t

START td

µs

Voffset Comparator offset ± 3 ± 10 mV d

Voffset

/dt

Comparator offset variation in worst voltage stress conditions

DDA

IN+

IN-

= 3.6 V

= 0 V

= V

REFINT

= 25 ° C

0 1.5

10 mV/1000 h

COMP1

Current consumption

(3)

160 260

1. Based on characterization, not tested in production.

2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.

3. Comparator consumption only. Internal reference voltage not included.

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Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B

Symbol

Table 61. Comparator 2 characteristics

Parameter Conditions Min Typ Max

(1)

Unit

I t t

DDA

START t d slow

V d fast offset dThreshold/ dt

COMP2

Analog supply voltage

Comparator 2 input voltage range

Comparator startup time

Propagation delay

Propagation delay coefficient

(2)

Current consumption

in slow mode

in fast mode

Comparator offset error

Threshold voltage temperature

(3)

Fast mode

Slow mode

1. V ≤

DDA

≤ 2.7 V

2.7 V ≤ V

DDA

≤

1. V ≤

DDA

≤ 2.7 V

2.7 V ≤ V

DDA

≤

DDA

1/2 V

= 3.3V

= 0 to 50 ° C

V- = V

REFINT

3/4 V

REFINT

1/4 V

REFINT

Fast mode

Slow mode

1.8

2.5

0.8

1.2

3.5

0.5

3.6

DDA

3.5

µs

± 20 mV

1. Based on characterization, not tested in production.

2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.

3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not included.

ppm

/°C

µA

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STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics

The embeds a built-in step-up converter to provide a constant LCD reference voltage independently from the V

LCD

voltage. An external capacitor C

pin to decouple this converter.

ext

must be connected to the

Symbol

Table 62. LCD controller characteristics

Parameter Min Typ Max Unit

LCD

LCD0

LCD1

LCD2

LCD3

LCD4

LCD5

LCD6

LCD7

C ext

LCD external voltage

LCD internal reference voltage 0

LCD internal reference voltage 1

LCD internal reference voltage 2

LCD internal reference voltage 3

LCD internal reference voltage 4

LCD internal reference voltage 5

LCD internal reference voltage 6

LCD internal reference voltage 7 -

2.6

2.73

2.86

2.98

3.12

3.26

3.4

3.55

3.6

LCD

(1)

LCD

external capacitance

Supply current at V

= 2.2 V

Supply current at V

= 3.0 V

Low drive resistive network overall value

0.1

3.3

3.1

µF

µA

Htot

(2)

High drive resistive network total value

Segment/Common highest level voltage

Segment/Common 3/4 level voltage

Segment/Common 2/3 level voltage

Segment/Common 1/2 level voltage

Segment/Common 1/3 level voltage

Segment/Common 1/4 level voltage

Segment/Common lowest level voltage

5.28

192

6.6

240

3/4 V

2/3 V

1/2 V

1/3 V

1/4 V

LCD

7.92

288

LCD

M k

Δ Vxx

(3)

Segment/Common level voltage error

= -40 to 85 ° C

± 50 mV

1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected

2. Guaranteed by design, not tested in production.

3. Based on characterization, not tested in production.

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Package characteristics STM32L151x6/8/B, STM32L152x6/8/B

7.1 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

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STM32L151x6/8/B, STM32L152x6/8/B Package characteristics

Figure 32. LQFP100 14 x 14 mm, 100-pin low-profile quad flat package outline

3%!4).'

0,!.%

CCC #

'!5'%0,!.%

, +

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

,?-%?6

DocID17659 Rev 10

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128

Package characteristics STM32L151x6/8/B, STM32L152x6/8/B

Table 63. LQPF100 14 x 14 mm, 100-pin low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max e

E3 k ccc b c

0.050

1.350

0.170

0.090

15.800

13.800

15.800

13.800

0.450

0.0°

1.400

0.220

16.000

14.000

12.000

16.000

14.000

12.000

0.500

0.600

1.000

3.5°

1.600

0.150

1.450

0.270

0.200

16.200

14.200

16.200

14.200

0.750

7.0°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.6220

0.5433

0.0177

0.0°

0.0020

0.0531

0.0067

0.0035

0.6220

0.5433

0.4724

0.6299

0.5512

0.4724

0.0197

0.0236

0.0394

3.5°

0.0551

0.0087

0.6299

0.5512

0.6378

0.5591

0.0295

7.0°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

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STM32L151x6/8/B, STM32L152x6/8/B

Figure 33. Recommended footprint

Package characteristics

AIC

1. Dimensions are in millimeters.

DocID17659 Rev 10

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128

Package characteristics STM32L151x6/8/B, STM32L152x6/8/B

Figure 34. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package outline

3%!4).'

0,!.%

'!5'%0,!.%

CCC #

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

7?-%?6

108/129

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STM32L151x6/8/B, STM32L152x6/8/B Package characteristics

Table 64. LQFP64 10 x 10 mm 64-pin low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Typ Min Max e

E3 ccc

D1 b c

0.050

1.350

0.170

0.090

11.800

9.800

11.800

9.800

0.450

0.0

1.400

0.220

12.000

10.000

7.500

12.000

10.000

7.500

0.500

0.600

1.000

3.5

1.600

0.150

1.450

0.270

0.200

12.200

10.200

12.200

10.200

0.750

0.080

7.0

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.4646

0.3858

0.0177

0.0

0.0020

0.0531

0.0067

0.0035

0.4646

0.3858

0.2953

0.4724

0.3937

0.2953

0.0197

0.0236

0.0394

3.5

0.0551

0.0087

0.4724

0.3937

0.4803

0.4016

0.0295

0.0031

7.0

0.0630

0.0059

0.0571

0.0106

0.0079

0.4803

0.4016

Figure 35. Recommended footprint

48 33

0.3

49 0.5

12.7

10.3

64 17

1.2

1 16

7.8

12.7

ai14909

1. Dimensions are in millimeters.

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128

Package characteristics STM32L151x6/8/B, STM32L152x6/8/B

Figure 36. LQFP48 7 x 7 mm, 48-pin low-profile quad flat package outline

3%!4).'

0,!.%

CCC #

'!5'%0,!.%

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

"?-%?6

110/129

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STM32L151x6/8/B, STM32L152x6/8/B Package characteristics

Table 65. LQFP48 7 x 7 mm, 48-pin low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max e

E3 k ccc b c

0.050

1.350

0.170

0.090

8.800

6.800

8.800

6.800

0.450

0°

1.400

0.220

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

1.600

0.150

1.450

0.270

0.200

9.200

7.200

9.200

7.200

0.750

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.3465

0.2677

0.0177

0°

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

0.0551

0.0087

0.3543

0.2756

0.3622

0.2835

0.0295

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

Figure 37. Recommended footprint

0.50

1.20

36 25

0.20

7.30

9.70

5.80

0.30

7.30

1 12

1.20

5.80

9.70

ai14911b

1. Dimensions are in millimeters.

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128

Package characteristics STM32L151x6/8/B, STM32L152x6/8/B

Figure 38. UFQFPN48 7 x 7 mm 0.5 mm pitch, ultra thin fine-pitch quad flat no-lead package outline

3LQLGHQWLILHU

ODVHUPDUNLQJDUHD

( (

H E

'HWDLO<

GGG

6HDWLQJ

SODQH

([SRVHGSDG

DUHD

SLQFRUQHU

'HWDLO=

5W\S

(

$%B0(B9

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground.

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STM32L151x6/8/B, STM32L152x6/8/B Package characteristics

Table 66. UFQFPN48 7 x 7 mm, 0.5 mm pitch, ultra thin fine-pitch quad flat no-lead package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

T b e ddd

0.500

0.000

6.900

5.500

0.300

0.200

0.550

0.020

7.000

5.600

0.400

0.152

0.250

0.500

0.600

0.050

7.100

5.700

0.500

0.300

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0000

0.2717

0.2165

0.0118

0.0079

0.0217

0.0008

0.2756

0.2205

0.0157

0.0060

0.0098

0.0197

0.0236

0.0020

0.2795

0.2244

0.0197

0.0118

0.0031

Figure 39. Recommended footprint

7.30

48 37

1 36

6.20

0.20

7.30

6.20

5.60

5.80

5.60

0.30

0.55

1. Dimensions are in millimeters.

5.80

0.50

0.75

ai15697

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128

Package characteristics STM32L151x6/8/B, STM32L152x6/8/B

Figure 40. UFBGA100 7 x 7 x 0.6 mm 0.5 mm pitch, ultra thin fine-pitch ball grid array package outline

= 6HDWLQJSODQH

GGG =

$ $

(

)

$ $

$EDOO

LGHQWLILHU

$EDOO

LQGH[DUHD

;

(

)

' '

%277209,(:

EEDOOV

HHH 0 = < ;

III 0 =

7239,(:

$&B0(B9

1. Drawing is not to scale.

Table 67. UFBGA100 7 x 7 x 0.6 mm 0.5 mm pitch, ultra thin fine-pitch ball grid array package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

E1 e

F ddd

A4 b

5.45

6.95

5.45

0.7

0.05

0.4

0.08

0.27

0.2

6.95

5.5

0.5

0.75

0.08

0.45

0.13

0.32

0.25

5.55

7.05

5.55

0.8

0.1

0.6

0.11

0.5

0.18

0.37

0.3

7.05

0.2146

0.2736

0.2146

0.0276

0.002

0.0157

0.0031

0.0106

0.0079

0.2736

0.2165

0.2756

0.2165

0.0197

0.0295

0.0031

0.0177

0.0051

0.0126

0.0098

0.2756

0.2185

0.2776

0.2185

0.0315

0.0039

0.0236

0.0043

0.0197

0.0071

0.0146

0.0118

0.2776

114/129

DocID17659 Rev 10

STM32L151x6/8/B, STM32L152x6/8/B Package characteristics

Table 67. UFBGA100 7 x 7 x 0.6 mm 0.5 mm pitch, ultra thin fine-pitch ball grid array package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max eee fff

0.15

0.05

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0059

0.002

DocID17659 Rev 10

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128

Package characteristics STM32L151x6/8/B, STM32L152x6/8/B

Figure 41. TFBGA64 - 5.0x5.0x1.2 mm, 0.5 mm pitch, thin fine-pitch ball grid array package outline

= 6HDWLQJSODQH

GGG =

(

)

$ $

$EDOO

LGHQWLILHU

$EDOO

LQGH[DUHD

;

(

1. Drawing is not to scale.

%277209,(:

)

EEDOOV

HHH

III

= < ;

7239,(:

5B0(B9

Table 68. TFBGA64 5.0x5.0x1.2 mm, 0.5 mm pitch thin fine-pitch ball grid array package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

A4 b

A2 e

E1 ddd

4.850

- -

0.150

0.200

0.250

4.850

0.300

5.000

3.500

5.000

3.500

0.500

0.750

1.200

0.600

0.350

5.150

0.080

0.0059

0.0098

0.1909

0.0079

0.0118

0.1969

0.1378

0.1969

0.1378

0.0197

0.0295

0.0472

0.0236

0.0138

0.2028

0.0031

116/129

DocID17659 Rev 10

STM32L151x6/8/B, STM32L152x6/8/B Package characteristics

Table 68. TFBGA64 5.0x5.0x1.2 mm, 0.5 mm pitch thin fine-pitch ball grid array package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max eee fff

0.15

0.05

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0059

0.002

DocID17659 Rev 10

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128

Package characteristics STM32L151x6/8/B, STM32L152x6/8/B

Figure 42. Recommended PCB design rules for pads (0.5 mm pitch BGA)

Dpad

Dsm

1. Non solder mask defined (NSMD) pads are recommended

2. 4 to 6 mils solder paste screen printing process

Pitch

D pad

0.5 mm

0.27 mm

Dsm 0.35 mm typ (depends on the soldermask registration tolerance)

Solder paste 0.27 mm aperture diameter ai15495

118/129

DocID17659 Rev 10

STM32L151x6/8/B, STM32L152x6/8/B Package characteristics

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

max = T

max + (P

max × Θ

)

Where:

• T

max is the maximum ambient temperature in ° C,

• Θ

is the package junction-to-ambient thermal resistance, in ° C/W,

• P

max is the sum of P

INT

max and P

I/O max (P

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Table 69. Thermal characteristics

Symbol Parameter

Thermal resistance junction-ambient

BGA100 - 7 x 7 mm

Thermal resistance junction-ambient

LQFP100 - 14 x 14 mm / 0.5 mm pitch

Thermal resistance junction-ambient

TFBGA64 - 5 x 5 mm

Thermal resistance junction-ambient

LQFP64 - 10 x 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP48 - 7 x 7 mm / 0.5 mm pitch

Thermal resistance junction-ambient

UFQFPN48 - 7 x 7 mm / 0.5 mm pitch

Value

Unit

°C/W

DocID17659 Rev 10

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128

Package characteristics

)RUELGGHQDUHD

7-!7-PD[

STM32L151x6/8/B, STM32L152x6/8/B

Figure 43. Thermal resistance

3'P:

84)3[PP

/4)3[PP

8)%*$[PP

7HPSHUDWXUH Σ

069

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

120/129

DocID17659 Rev 10

STM32L151x6/8/B, STM32L152x6/8/B Part numbering

Table 70. Ordering information scheme

Example: STM32 L 151 C 8 T 6 T xxx

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

L = Low power

Device subfamily

151: Devices without LCD

152: Devices with LCD

Pin count

C = 48 pins

R = 64 pins

V = 100 pins

Flash memory size

6 = 32 Kbytes of Flash memory

8 = 64 Kbytes of Flash memory

B = 128 Kbytes of Flash memory

Package

H = BGA

T = LQFP

U = UFQFPN

Temperature range

6 = Industrial temperature range, –40 to 85 °C

Options

No character = V

range: 1.8 to 3.6 V and BOR enabled

T = V

range: 1.65 to 3.6 V and BOR disabled

Packing

TR = tape and reel

No character = tray or tube

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.

DocID17659 Rev 10

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128

Revision history STM32L151x6/8/B, STM32L152x6/8/B

Date

02-Jul-2010

01-Oct-2010

16-Dec-2010

Table 71. Document revision history

Revision Changes

Initial release.

Removed 5 V tolerance (FT) from PA3, PB0 and PC3 in Table 8:

STM32L15xx6/8/B pin definitions

Updated

Table 14: Embedded reset and power control block characteristics

Updated

Table 16: Embedded internal reference voltage

Added

Table 53: ADC clock frequency

Updated

Table 54: ADC characteristics

Modified consumptions on page 1 and in

Section 3.1: Low power modes

LED_SEG8 removed on PB6.

Updated

Section 6: Electrical characteristics

VFQFPN48 replaced by UFQFPN48

122/129

DocID17659 Rev 10

STM32L151x6/8/B, STM32L152x6/8/B

Date

25-Feb-2011

Revision history

Table 71. Document revision history (continued)

Revision Changes

Features

: updated value of Low-power sleep.

Section 3.3.2: Power supply supervisor

: updated note.

Table 8: STM32L15xx6/8/B pin definitions:

modified main function

(after reset) and alternate function for OSC_IN and OSC_OUT pins; modified footnote 5; added footnote to OSC32_IN and OSC32_OUT pins; C1 and D1 removed on PD0 and PD1 pins (TFBGA64 column).

Section 3.11: DAC (digital-to-analog converter)

: updated bullet list.

Table 10: Voltage characteristics on page 50 : updated footnote 3

regarding I

INJ(PIN)

Table 11: Current characteristics on page 50 : updated footnote 4

regarding positive and negative injection.

Table 14: Embedded reset and power control block characteristics on page 52

: updated typ and max values for T

RSTTEMPO

DD rising, BOR enabled).

Table 17: Current consumption in Run mode, code with data processing running from Flash on page 56 : removed values for HSI

clock source (16 MHz), Range 3.

Table 18: Current consumption in Run mode, code with data processing running from RAM on page 57

: removed values for HSI clock source (16 MHz), Range 3.

Table 19: Current consumption in Sleep mode on page 58 removed

values for HSI clock source (16 MHz), Range 3 for both RAM and

Flash; changed units.

Table 20: Current consumption in Low power run mode on page 60

: updated parameter and max value of I

Max (LP Run).

Table 21: Current consumption in Low power sleep mode on page 61 : updated symbol, parameter, and max value of I

Sleep).

Max (LP

Table 22: Typical and maximum current consumptions in Stop mode on page 62

updated values for I

DD (Stop with RTC)

- RTC clocked by

LSE external clock (32.768 kHz), regulator in LP mode, HSI and

HSE OFF (no independent watchdog).

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128

Revision history STM32L151x6/8/B, STM32L152x6/8/B

Date

25-Feb-2011

Table 71. Document revision history (continued)

Revision Changes

(continued)

Updated

Table 23: Typical and maximum current consumptions in

Standby mode on page 64

(WU from Stop).

(WU from Standby) instead of (I

Table 25: Low-power mode wakeup timings on page 67 : updated

condition for Wakeup from Stop mode, regulator in Run mode; updated max values for Wakeup from Stop mode, regulator in low power mode; updated max values for t

WUSTDBY

Table 24: Peripheral current consumption on page 65

: updated values for column Low power sleep and run; updated Flash values; renamed ADC1 to ADC; updated I

DD (LCD) added values for I

DD (RTC) and I

DD (IWDG) added foot note 2 concerning ADC.

value; updated units;

; updated footnote 1 and 3;

Table 26: High-speed external user clock characteristics on page 68 : added min value for t

w(HSE) time; added max value for t r(HSE) updated I

for typ and max values.

/t w(HSE) f(HSE)

OSC_IN high or low

OSC_IN rise or fall time;

Table 27: Low-speed external user clock characteristics on page 69 :

updated max value for I

Table 28: HSE oscillator characteristics on page 70

: renamed i

HSE

and updated max value; updated max values for I

DD(HSE)

Table 29: LSE oscillator characteristics (f

LSE page 71 : updated max value for I

LSE

= 32.768 kHz) on

Table 30: HSI oscillator characteristics on page 73

: updated some min and max values for ACC

HSI

Table 32: MSI oscillator characteristics on page 74 : updated

parameter, typ, and max values for D

VOLT(MSI)

Table 35: Flash memory and data EEPROM characteristics on page 76 : updated typ values for t

prog

Table 44: I/O AC characteristics on page 83

: updated some max values for 01, 10, and 11; updated min value; updated footnotes.

Table 55: ADC accuracy on page 94

: updated typ values and some of the test conditions for ENOB, SINAD, SNR, and THD.

Table 57: DAC characteristics on page 98

: updated footnote 7 and added footnote 8.

Updated leakage value in

Figure 27: Typical connection diagram using the ADC

Added Figure 28: Maximum dynamic current consumption on V

REF+ supply pin during ADC conversion

Added

Table 56: R

AIN

max for f

ADC

= 16 MHz on page 96

Figure 29: Power supply and reference decoupling (V connected to V

capacitors.

DDA

REF+ not

)

: replaced all 10 nF capacitors with 100 nF

Figure 30: Power supply and reference decoupling (V connected to V

capacitor.

DDA

REF+

)

: replaced 10 nF capacitor with 100 nF

124/129

DocID17659 Rev 10

STM32L151x6/8/B, STM32L152x6/8/B Revision history

Date

17-June-2011

25-Jan-2012

Table 71. Document revision history (continued)

Revision Changes

Modified 1st page (low power features)

Added STM32L15xC6 and STM32L15xR6 devices (32 Kbytes of

Flash memory).

Modified

Section 3.6: GPIOs (general-purpose inputs/outputs) on page 22

Modified

Section 6.3: Operating conditions on page 51

Modified

Table 55: ADC accuracy on page 94 ,

Table 57: DAC characteristics on page 98

and Table 60: Comparator 1 characteristics on page 101

Features

: updated internal multispeed low power RC.

Table 2: Ultralow power STM32L15xx6/8/B device features and peripheral counts

: LCD 4x44 and 8x40 available for both 64- and

128-Kbyte devices; two comparators available for all devices.

Table 3: Functionalities depending on the operating power supply range : added footnote

1 .

Figure 8: STM32L15xCx UFQFPN48 pinout

: replaced VFQPN48 by

UFQFPN48 as name of package.

Table 8: STM32L15xx6/8/B pin definitions

: replaced PH0/PH1 by

PC14/PC15.

Table 9: Alternate function input/output : removed EVENT OUT from

PH2 port, AFIO15 column.

Table 19: Current consumption in Sleep mode : updated MSI

conditions and f

HCLK

Table 20: Current consumption in Low power run mode : updated

some temperature conditions; added footnote 2.

Table 21: Current consumption in Low power sleep mode : updated

some temperature conditions and one of the MSI clock conditions.

Table 22: Typical and maximum current consumptions in Stop mode : updated I

(WU from Stop) parameter.

Table 23: Typical and maximum current consumptions in Standby mode : updated I

(WU from Standby) parameter.

Table 25: Low-power mode wakeup timings : updated f

HCLK for t

WUSLEEP_LP

Stop mode, regulator in Run mode”.

value

; updated typical value of parameter “Wakeup from

Table 24: Peripheral current consumption

: replaced GPIOF by

GPIOH.

Table 33: PLL characteristics : updated “PLL output clock”

Table 35: Flash memory and data EEPROM characteristics

: updated all information for I

Figure 19: I/O AC characteristics definition : replaced the falling

edge “t r(IO)out

Table 47: I

” by “t f(IO)out

”.

C characteristics

: amended footnote 2.

Table 54: ADC characteristics

: updated f

S channels, 6-bit sampling rate.

max value for direct

Table 55: ADC accuracy : Updated the first, third and fourth f

ADC condition.

test

Table 59: Temperature sensor characteristics : updated typ, min,

and max values of the T

S_temp parameter.

DocID17659 Rev 10

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128

Revision history

Date

26-Oct-2012

07-Feb-2013

STM32L151x6/8/B, STM32L152x6/8/B

Table 71. Document revision history (continued)

Revision Changes

Updated cover page.

Updated

Section 3.10: ADC (analog-to-digital converter)

Updated

Table 3: Functionalities depending on the operating power supply range

, added Table 4: CPU frequency range depending on dynamic voltage scaling

and

Table 5: Working mode-dependent functionalities (from Run/active down to standby) .

Updated

Table 27: Low-speed external user clock characteristics

Added footnote 2.

Table 14: Embedded reset and power control block characteristics

Updated

Table 22: Typical and maximum current consumptions in

Stop mode

and Table 23: Typical and maximum current consumptions in Standby mode

Updated footnote 4.

Table 22: Typical and maximum current consumptions in Stop mode

Updated

Table 44: I/O AC characteristics

Updated

Table 47: I 2 C characteristics

Updated

Table 49: SPI characteristics

Updated

Section 6.3.9: Memory characteristics

Updated “non-robust”

Table 54: ADC characteristics

Removed the note “position of 4.7 µf capacitor” in Section 6.1.6:

Power supply scheme

Updated

Table 66: UFQFPN48 7 x 7 mm, 0.5 mm pitch, ultra thin fine-pitch quad flat no-lead package mechanical data

Updated

Table 65: LQFP48 7 x 7 mm, 48-pin low-profile quad flat package mechanical data

Added the resistance of TFBGA in

Table 69: Thermal characteristics

Added

Figure 43: Thermal resistance

Removed AHB1/AHB2 in

Figure 1: Ultralow power

STM32L15xx6/8/B block diagram

Added IWDG and WWDG rows in Table 5: Working modedependent functionalities (from Run/active down to standby)

Updated I

(Supply current during wakeup time from Standby

mode) in Table 23: Typical and maximum current consumptions in

Standby mode

The comment "HSE = 16 MHz(2) (PLL ON for fHCLK above 16

MHz)" replaced by "fHSE = fHCLK up to 16 MHz included, fHSE =

fHCLK/2 above 16 MHz (PLL ON)(2)” in Table 19: Current consumption in Sleep mode

Updated Stop mode current to 1.2 µA in Ultra-low-power platform

Updated entire Section 7: Package characteristics

Removed alternate function “I2C2_SMBA” for GPIO pin “PH2” in

Table 8: STM32L15xx6/8/B pin definitions

Updated

Table 27: Low-speed external user clock characteristics

and definition of symbol “R

AIN

” in Table 54: ADC characteristics

Removed first sentence in

I2C interface characteristics

126/129

DocID17659 Rev 10

STM32L151x6/8/B, STM32L152x6/8/B

Date

12-Nov-2013

Revision history

Table 71. Document revision history (continued)

Revision Changes

Changed voltage Range 1 minimum to 1.71 V and updated dynamic

voltage scaling range in Table 3: Functionalities depending on the operating power supply range

Updated LCD and ADC features in

Table 2: Ultralow power

STM32L15xx6/8/B device features and peripheral counts

Updated

Table 3: Functionalities depending on the operating power supply range

Updated

Table 5: Working mode-dependent functionalities (from

Run/active down to standby)

Updated

Figure 3: STM32L15xVx UFBGA100 ballout

Added

Table 7: Legend/abbreviations used in the pinout table .

Updated

Table 8: STM32L15xx6/8/B pin definitions

Updated

Figure 10: Pin loading conditions and Figure 11: Pin input voltage

. Updated

Figure 12: Power supply scheme .

Replaced “ Σ ” by “ σ

” in Section 6.1.1

and Section 6.1.2

Updated

Table 10: Voltage characteristics

Updated

Table 13: General operating conditions .

Added

Section 6.1.7: Optional LCD power supply scheme

Updated

Table 16: Embedded internal reference voltage

Added this Note

in Section : High-speed external clock generated from a crystal/ceramic resonator

Updated

Section : Functional susceptibility to I/O current injection

This Section 6.3.5: Wakeup time from Low power mode

was previously a paragraph in

Section 6.3.4: Supply current characteristics

Updated f

HSE

conditions in Table 17: Current consumption in Run mode, code with data processing running from Flash

and Table 18:

Current consumption in Run mode, code with data processing running from RAM

. Fixed IDD unit in Table 23: Typical and maximum current consumptions in Standby mode

This Figure 15: High-speed external clock source AC timing diagram

was moved up (was previously after Figure 16: Low-speed external clock source AC timing diagram

Updated first sentence in

Section 6.3.14: NRST pin characteristics

Updated

Table 25: Low-power mode wakeup timings title.

Updated

Table 26: High-speed external user clock characteristics

Updated Table 28: HSE oscillator characteristics and

Table 29: LSE oscillator characteristics (f

LSE

= 32.768 kHz) .

Updated

Section 6.3.11: Electrical sensitivity characteristics

title.

Updated

Table 39: ESD absolute maximum ratings

Updated

Table 41: I/O current injection susceptibility and

Table 42:

I/O static characteristics

Updated

Figure 21: I

C bus AC waveforms and measurement circuit

Removed any occurrence of “when 8 pins are sourced at same

time” in Table 43: Output voltage characteristics

Updated section link in second paragraph of

Section 6.3.15: TIM timer characteristics .

DocID17659 Rev 10

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128

Revision history STM32L151x6/8/B, STM32L152x6/8/B

Date

12-Nov-2013

22-Jul-2014

Table 71. Document revision history (continued)

Revision Changes

(continued)

Updated

Table 54: ADC characteristics and

Figure 27: Typical connection diagram using the ADC

Table 58: Temperature sensor calibration values was previously in

Section 3.10.1: Temperature sensor

. Updated Table 59:

Temperature sensor characteristics

In Table 61: Comparator 2 characteristics

, parameter dThreshold/dt, replaced any occurrence of “VREF+” by “V

REFINT

”Updated

Table 63: LQPF100 14 x 14 mm, 100-pin low-profile quad flat package mechanical data

Table 64: LQFP64 10 x 10 mm 64-pin low-profile quad flat package mechanical data ,

Table 65: LQFP48 7 x 7 mm, 48-pin low-profile quad flat package mechanical data

and

Table 66: UFQFPN48 7 x 7 mm, 0.5 mm pitch, ultra thin fine-pitch quad flat no-lead package mechanical data .

Updated

Figure 33: Recommended footprint

Updated

Figure 41: TFBGA64 - 5.0x5.0x1.2 mm, 0.5 mm pitch, thin fine-pitch ball grid array package outline

title.

Remove minimum and typical values of A dimension in

Table 67:

UFBGA100 7 x 7 x 0.6 mm 0.5 mm pitch, ultra thin fine-pitch ball grid array package mechanical data

Deleted second footnote in Figure 39: Recommended footprint .

Updated

Section 8: Part numbering title and added first sentence.

Changed BOR disabled option identifier in

Table 70: Ordering information scheme .

Updated

Figure 14 ,

Figure 15

;

Updated

Table 5 ;

Updated

Figure 6.3.4

Udded note

inside

Table 54

Updated Ro value inside

Table 54

128/129

DocID17659 Rev 10

STM32L151x6/8/B, STM32L152x6/8/B

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

DocID17659 Rev 10 129/129

129

Ultra-low-power 32-bit MCU ARM-based Cortex

®

-M3,

128KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC

-

Features

Contents

List of tables

List of figures

1 Introduction

2 Description

2.2

Ultralow power device continuum

3.1 Low power modes

3.2 ARM

®

Cortex

®

-M3 core with MPU

Nested vectored interrupt controller (NVIC)

3.3

Reset and supply management

3.5

Low power real-time clock and backup registers

External interrupt/event controller (EXTI)

3.7 Memories

3.8 DMA (direct memory access)

3.9 LCD (liquid crystal display)

3.10 ADC (analog-to-digital converter)

3.11 DAC (digital-to-analog converter)

3.12 Ultralow power comparators and reference voltage

3.15 Timers and watchdogs

TIM2, TIM3, TIM4

TIM10, TIM11 and TIM9

3.17 CRC (cyclic redundancy check) calculation unit

Serial wire JTAG debug port (SWJ-DP)

Embedded Trace Macrocell™

6.2 Absolute maximum ratings

On-chip peripheral current consumption

High-speed external user clock generated from an external source

Low-speed external user clock generated from an external source

High-speed external clock generated from a crystal/ceramic resonator

Low-speed external clock generated from a crystal/ceramic resonator

High-speed internal (HSI) RC oscillator

Low-speed internal (LSI) RC oscillator

Multi-speed internal (MSI) RC oscillator

RAM memory

Flash memory and data EEPROM

Functional EMS (electromagnetic susceptibility)

Designing hardened software to avoid noise problems

Electromagnetic Interference (EMI)

Electrostatic discharge (ESD)

Static latch-up

Functional susceptibility to I/O current injection

General input/output characteristics

Output driving current

Output voltage levels

Input/output AC characteristics

I

C interface characteristics

SPI characteristics

USB characteristics

General PCB design guidelines

34-,XX

6

&N&

6

7.1 Package mechanical data

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